Fix build on ARM

Author: Byron

crates/core_arch/src/acle/crypto.rs

@@ -191,6 +191,7 @@ pub unsafe fn vsha256su1q_u32(
 
 #[cfg(test)]
 mod tests {
+    use super::*;
     use crate::core_arch::{arm::*, simd::*};
     use std::mem;
     use stdarch_test::simd_test;

crates/core_arch/src/acle/mod.rs

@@ -68,19 +68,17 @@ mod ex;
 
 pub use self::ex::*;
 
-#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+#[cfg(any(target_feature = "v7", doc))]
 mod crc;
-#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+#[cfg(any(target_feature = "v7", doc))]
 pub use crc::*;
 
-#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+#[cfg(any(target_feature = "v7", doc))]
 mod crypto;
-#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
+#[cfg(any(arget_feature = "v7", doc))]
 pub use self::crypto::*;
 
-#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
 pub(crate) mod neon;
-#[cfg(any(target_arch = "aarch64", target_feature = "v7", doc))]
 pub use self::neon::*;
 
 mod sealed {

crates/core_arch/src/acle/neon/mod.rs

@@ -646,8 +646,13 @@ pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t {
 #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ldr))]
 pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t {
     #[cfg(target_arch = "aarch64")]
-    use crate::core_arch::aarch64::vld1_s64;
-    vld1_s64(ptr)
+    {
+        crate::core_arch::aarch64::vld1_s64(ptr)
+    }
+    #[cfg(target_arch = "arm")]
+    {
+        crate::core_arch::arm::vld1_s64(ptr)
+    }
 }
 
 /// Load one single-element structure and Replicate to all lanes (of one register).
@@ -735,8 +740,13 @@ pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t {
 #[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ldr))]
 pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t {
     #[cfg(target_arch = "aarch64")]
-    use crate::core_arch::aarch64::vld1_u64;
-    vld1_u64(ptr)
+    {
+        crate::core_arch::aarch64::vld1_u64(ptr)
+    }
+    #[cfg(target_arch = "arm")]
+    {
+        crate::core_arch::arm::vld1_u64(ptr)
+    }
 }
 
 /// Load one single-element structure and Replicate to all lanes (of one register).
@@ -4065,7 +4075,7 @@ pub unsafe fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t {
 pub unsafe fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
     #[cfg(target_arch = "arm")]
     {
-        vpadal_s8_(a, b)
+        crate::core_arch::arm::neon::vpadal_s8_(a, b)
     }
     #[cfg(target_arch = "aarch64")]
     {
@@ -4082,7 +4092,7 @@ pub unsafe fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
 pub unsafe fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
     #[cfg(target_arch = "arm")]
     {
-        vpadal_s16_(a, b)
+        crate::core_arch::arm::neon::vpadal_s16_(a, b)
     }
     #[cfg(target_arch = "aarch64")]
     {
@@ -4099,7 +4109,7 @@ pub unsafe fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
 pub unsafe fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
     #[cfg(target_arch = "arm")]
     {
-        vpadal_s32_(a, b)
+        crate::core_arch::arm::neon::vpadal_s32_(a, b)
     }
     #[cfg(target_arch = "aarch64")]
     {
@@ -4116,7 +4126,7 @@ pub unsafe fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
 pub unsafe fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
     #[cfg(target_arch = "arm")]
     {
-        vpadalq_s8_(a, b)
+        crate::core_arch::arm::neon::vpadalq_s8_(a, b)
     }
     #[cfg(target_arch = "aarch64")]
     {
@@ -4133,7 +4143,7 @@ pub unsafe fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 pub unsafe fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
     #[cfg(target_arch = "arm")]
     {
-        vpadalq_s16_(a, b)
+        crate::core_arch::arm::neon::vpadalq_s16_(a, b)
     }
     #[cfg(target_arch = "aarch64")]
     {
@@ -4150,7 +4160,7 @@ pub unsafe fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 pub unsafe fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
     #[cfg(target_arch = "arm")]
     {
-        vpadalq_s32_(a, b)
+        crate::core_arch::arm::neon::vpadalq_s32_(a, b)
     }
     #[cfg(target_arch = "aarch64")]
     {
@@ -4167,7 +4177,7 @@ pub unsafe fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 pub unsafe fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
     #[cfg(target_arch = "arm")]
     {
-        vpadal_u8_(a, b)
+        crate::core_arch::arm::neon::vpadal_u8_(a, b)
     }
     #[cfg(target_arch = "aarch64")]
     {
@@ -4184,7 +4194,7 @@ pub unsafe fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
 pub unsafe fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
     #[cfg(target_arch = "arm")]
     {
-        vpadal_u16_(a, b)
+        crate::core_arch::arm::neon::vpadal_u16_(a, b)
     }
     #[cfg(target_arch = "aarch64")]
     {
@@ -4201,7 +4211,7 @@ pub unsafe fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
 pub unsafe fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
     #[cfg(target_arch = "arm")]
     {
-        vpadal_u32_(a, b)
+        crate::core_arch::arm::neon::vpadal_u32_(a, b)
     }
     #[cfg(target_arch = "aarch64")]
     {
@@ -4218,7 +4228,7 @@ pub unsafe fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
 pub unsafe fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
     #[cfg(target_arch = "arm")]
     {
-        vpadalq_u8_(a, b)
+        crate::core_arch::arm::neon::vpadalq_u8_(a, b)
     }
     #[cfg(target_arch = "aarch64")]
     {
@@ -4235,7 +4245,7 @@ pub unsafe fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 pub unsafe fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
     #[cfg(target_arch = "arm")]
     {
-        vpadalq_u16_(a, b)
+        crate::core_arch::arm::neon::vpadalq_u16_(a, b)
     }
     #[cfg(target_arch = "aarch64")]
     {
@@ -4252,7 +4262,7 @@ pub unsafe fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 pub unsafe fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
     #[cfg(target_arch = "arm")]
     {
-        vpadalq_u32_(a, b)
+        crate::core_arch::arm::neon::vpadalq_u32_(a, b)
     }
     #[cfg(target_arch = "aarch64")]
     {
@@ -4264,7 +4274,11 @@ pub unsafe fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
 mod tests {
     use super::*;
     use crate::core_arch::arm::test_support::*;
-    use crate::core_arch::{arm::*, simd::*};
+    use crate::core_arch::simd::*;
+    #[cfg(target_arch = "arm")]
+    use crate::core_arch::arm::*;
+    #[cfg(target_arch = "aarch64")]
+    use crate::core_arch::aarch64::*;
     use std::{i16, i32, i8, mem::transmute, u16, u32, u8, vec::Vec};
     use stdarch_test::simd_test;
 

crates/core_arch/src/arm/mod.rs

@@ -80,7 +80,7 @@ pub use crate::core_arch::acle::*;
 #[cfg(test)]
 use stdarch_test::assert_instr;
 
-mod neon;
+pub(crate) mod neon;
 pub use neon::*;
 
 /// Generates the trap instruction `UDF`
@@ -92,5 +92,4 @@ pub unsafe fn udf() -> ! {
 }
 
 #[cfg(test)]
-#[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
 pub(crate) mod test_support;

crates/core_arch/src/arm/neon.rs

@@ -26,30 +26,30 @@ extern "C" {
     #[link_name = "llvm.arm.neon.vbsl.v16i8"]
     fn vbslq_s8_(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t;
     #[link_name = "llvm.arm.neon.vpadals.v4i16.v8i8"]
-    fn vpadal_s8_(a: int16x4_t, b: int8x8_t) -> int16x4_t;
+    pub(crate) fn vpadal_s8_(a: int16x4_t, b: int8x8_t) -> int16x4_t;
     #[link_name = "llvm.arm.neon.vpadals.v2i32.v4i16"]
-    fn vpadal_s16_(a: int32x2_t, b: int16x4_t) -> int32x2_t;
+    pub(crate) fn vpadal_s16_(a: int32x2_t, b: int16x4_t) -> int32x2_t;
     #[link_name = "llvm.arm.neon.vpadals.v1i64.v2i32"]
-    fn vpadal_s32_(a: int64x1_t, b: int32x2_t) -> int64x1_t;
+    pub(crate) fn vpadal_s32_(a: int64x1_t, b: int32x2_t) -> int64x1_t;
     #[link_name = "llvm.arm.neon.vpadals.v8i16.v16i8"]
-    fn vpadalq_s8_(a: int16x8_t, b: int8x16_t) -> int16x8_t;
+    pub(crate) fn vpadalq_s8_(a: int16x8_t, b: int8x16_t) -> int16x8_t;
     #[link_name = "llvm.arm.neon.vpadals.v4i32.v8i16"]
-    fn vpadalq_s16_(a: int32x4_t, b: int16x8_t) -> int32x4_t;
+    pub(crate) fn vpadalq_s16_(a: int32x4_t, b: int16x8_t) -> int32x4_t;
     #[link_name = "llvm.arm.neon.vpadals.v2i64.v4i32"]
-    fn vpadalq_s32_(a: int64x2_t, b: int32x4_t) -> int64x2_t;
+    pub(crate) fn vpadalq_s32_(a: int64x2_t, b: int32x4_t) -> int64x2_t;
 
     #[link_name = "llvm.arm.neon.vpadalu.v4i16.v8i8"]
-    fn vpadal_u8_(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t;
+    pub(crate) fn vpadal_u8_(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t;
     #[link_name = "llvm.arm.neon.vpadalu.v2i32.v4i16"]
-    fn vpadal_u16_(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t;
+    pub(crate) fn vpadal_u16_(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t;
     #[link_name = "llvm.arm.neon.vpadalu.v1i64.v2i32"]
-    fn vpadal_u32_(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t;
+    pub(crate) fn vpadal_u32_(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t;
     #[link_name = "llvm.arm.neon.vpadalu.v8i16.v16i8"]
-    fn vpadalq_u8_(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t;
+    pub(crate) fn vpadalq_u8_(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t;
     #[link_name = "llvm.arm.neon.vpadalu.v4i32.v8i16"]
-    fn vpadalq_u16_(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t;
+    pub(crate) fn vpadalq_u16_(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t;
     #[link_name = "llvm.arm.neon.vpadalu.v2i64.v4i32"]
-    fn vpadalq_u32_(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t;
+    pub(crate) fn vpadalq_u32_(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t;
 
     #[link_name = "llvm.arm.neon.vtbl1"]
     fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t;
@@ -1162,6 +1162,11 @@ pub unsafe fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x
 
 #[cfg(test)]
 mod tests {
+    use super::*;
+    use crate::core_arch::{arm::*, simd::*};
+    use stdarch_test::simd_test;
+    use crate::mem::transmute;
+
     #[cfg(target_arch = "arm")]
     #[simd_test(enable = "neon")]
     unsafe fn test_vcvtq_s32_f32() {