diff --git a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/arm_math.h b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/arm_math.h index ea9dd26..eb37f82 100644 --- a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/arm_math.h +++ b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/arm_math.h @@ -1,11 +1,11 @@ /****************************************************************************** * @file arm_math.h - * @brief Public header file for CMSIS DSP LibraryU - * @version V1.5.3 - * @date 10. January 2018 + * @brief Public header file for CMSIS DSP Library + * @version V1.6.0 + * @date 18. March 2019 ******************************************************************************/ /* - * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -37,7 +37,7 @@ * - Complex math functions * - Filters * - Matrix functions - * - Transforms + * - Transform functions * - Motor control functions * - Statistical functions * - Support functions @@ -73,11 +73,7 @@ * The library functions are declared in the public file arm_math.h which is placed in the Include folder. * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. - * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. - * + * * * Examples * -------- @@ -93,7 +89,7 @@ * Building the Library * ------------ * - * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP\\Projects\\ARM folder. * - arm_cortexM_math.uvprojx * * @@ -104,10 +100,6 @@ * * Each library project have different preprocessor macros. * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * * - ARM_MATH_BIG_ENDIAN: * * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. @@ -120,46 +112,41 @@ * * Define macro ARM_MATH_ROUNDING for rounding on support functions * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. + * - ARM_MATH_LOOPUNROLL: * - * - ARM_MATH_ARMV8MxL: + * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions * - * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library - * on Armv8-M Mainline target. + * - ARM_MATH_NEON: * - * - __FPU_PRESENT: + * Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions. + * It is not enabled by default when Neon is available because performances are + * dependent on the compiler and target architecture. * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * - ARM_MATH_NEON_EXPERIMENTAL: * - * - __DSP_PRESENT: - * - * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of + * of some DSP functions. Experimental Neon versions currently do not have better + * performances than the scalar versions. * *
* CMSIS-DSP in ARM::CMSIS Pack * ----------------------------- * * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * |File/Folder |Content | + * |---------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP\\DSP_Lib_TestSuite | DSP_Lib test suite | + * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP\\Include | DSP_Lib include files | + * |\b CMSIS\\DSP\\Lib | DSP_Lib binaries | + * |\b CMSIS\\DSP\\Projects | Projects to rebuild DSP_Lib binaries | + * |\b CMSIS\\DSP\\Source | DSP_Lib source files | * *
* Revision History of CMSIS-DSP * ------------ * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 Arm Limited. All rights reserved. */ @@ -220,8 +207,8 @@ * There is an associated initialization function for each type of matrix * data structure. * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15() + * for floating-point, Q31 and Q15 types, respectively. * * \par * Use of the initialization function is optional. However, if initialization function is used @@ -272,6 +259,7 @@ /** * @defgroup groupStats Statistics Functions */ + /** * @defgroup groupSupport Support Functions */ @@ -286,6 +274,8 @@ /** * @defgroup groupExamples Examples */ + + #ifndef _ARM_MATH_H #define _ARM_MATH_H @@ -295,10 +285,10 @@ #elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) #elif defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wunused-parameter" #elif defined ( __ICCARM__ ) @@ -308,42 +298,40 @@ #elif defined ( __TASKING__ ) +#elif defined ( _MSC_VER ) + #else #error Unknown compiler #endif -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" - #define ARM_MATH_DSP -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" - #define ARM_MATH_DSP -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) - #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MBL) - #include "core_armv8mbl.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MML) - #include "core_armv8mml.h" - #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) - #define ARM_MATH_DSP - #endif +/* Included for instrinsics definitions */ +#if !defined ( _MSC_VER ) +#include "cmsis_compiler.h" #else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#include +#define __STATIC_FORCEINLINE static __forceinline +#define __ALIGNED(x) __declspec(align(x)) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT #endif -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ #include "string.h" #include "math.h" +#include "float.h" + +/* evaluate ARM DSP feature */ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define ARM_MATH_DSP 1 +#endif + +#if defined(__ARM_NEON) +#include +#endif + + #ifdef __cplusplus extern "C" { @@ -379,18 +367,6 @@ extern "C" /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ #define INPUT_SPACING 0xB60B61 - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ /** * @brief Error status returned by some functions in the library. @@ -398,13 +374,13 @@ extern "C" typedef enum { - ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_SUCCESS = 0, /**< No error */ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ } arm_status; /** @@ -437,87 +413,261 @@ extern "C" */ typedef double float64_t; - /** - * @brief definition to read/write two 16 bit values. - */ + +/** + @brief definition to read/write two 16 bit values. + @deprecated + */ #if defined ( __CC_ARM ) #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - #elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - #elif defined ( __GNUC__ ) #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - #elif defined ( __ICCARM__ ) #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED - #define CMSIS_INLINE - #elif defined ( __TI_ARM__ ) #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE - #elif defined ( __CSMC__ ) #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED - #define CMSIS_INLINE - #elif defined ( __TASKING__ ) - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED - #define CMSIS_INLINE - + #define __SIMD32_TYPE __un(aligned) int32_t +#elif defined(_MSC_VER ) + #define __SIMD32_TYPE int32_t #else #error Unknown compiler #endif #define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) +#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) +#define __SIMD64(addr) (*( int64_t **) & (addr)) -#if !defined (ARM_MATH_DSP) +/* SIMD replacement */ + + +/** + @brief Read 2 Q15 from Q15 pointer. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2 ( + q15_t * pQ15) +{ + q31_t val; + + memcpy (&val, pQ15, 4); + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_ia ( + q15_t ** pQ15) +{ + q31_t val; + + memcpy (&val, *pQ15, 4); + *pQ15 += 2; + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_da ( + q15_t ** pQ15) +{ + q31_t val; + + memcpy (&val, *pQ15, 4); + *pQ15 -= 2; + + return (val); +} + +/** + @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2_ia ( + q15_t ** pQ15, + q31_t value) +{ + q31_t val = value; + + memcpy (*pQ15, &val, 4); + *pQ15 += 2; +} + +/** + @brief Write 2 Q15 to Q15 pointer. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2 ( + q15_t * pQ15, + q31_t value) +{ + q31_t val = value; + + memcpy (pQ15, &val, 4); +} + + +/** + @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_ia ( + q7_t ** pQ7) +{ + q31_t val; + + memcpy (&val, *pQ7, 4); + *pQ7 += 4; + + return (val); +} + +/** + @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_da ( + q7_t ** pQ7) +{ + q31_t val; + + memcpy (&val, *pQ7, 4); + *pQ7 -= 4; + + return (val); +} + +/** + @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x4_ia ( + q7_t ** pQ7, + q31_t value) +{ + q31_t val = value; + + memcpy (*pQ7, &val, 4); + *pQ7 += 4; +} + +/* + +Normally those kind of definitions are in a compiler file +in Core or Core_A. + +But for MSVC compiler it is a bit special. The goal is very specific +to CMSIS-DSP and only to allow the use of this library from other +systems like Python or Matlab. + +MSVC is not going to be used to cross-compile to ARM. So, having a MSVC +compiler file in Core or Core_A would not make sense. + +*/ +#if defined ( _MSC_VER ) + __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#ifndef ARM_MATH_DSP /** * @brief definition to pack two 16 bit values. */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif /* !defined (ARM_MATH_DSP) */ + #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) +#endif /** * @brief definition to pack four 8 bit values. */ #ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) #else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) #endif /** * @brief Clips Q63 to Q31 values. */ - CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + __STATIC_FORCEINLINE q31_t clip_q63_to_q31( q63_t x) { return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? @@ -527,7 +677,7 @@ extern "C" /** * @brief Clips Q63 to Q15 values. */ - CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + __STATIC_FORCEINLINE q15_t clip_q63_to_q15( q63_t x) { return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? @@ -537,7 +687,7 @@ extern "C" /** * @brief Clips Q31 to Q7 values. */ - CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + __STATIC_FORCEINLINE q7_t clip_q31_to_q7( q31_t x) { return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? @@ -547,7 +697,7 @@ extern "C" /** * @brief Clips Q31 to Q15 values. */ - CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + __STATIC_FORCEINLINE q15_t clip_q31_to_q15( q31_t x) { return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? @@ -557,23 +707,21 @@ extern "C" /** * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. */ - - CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + __STATIC_FORCEINLINE q63_t mult32x64( q63_t x, q31_t y) { return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); + (((q63_t) (x >> 32) * y) ) ); } /** * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. */ - - CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) + __STATIC_FORCEINLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + const q31_t * pRecipTable) { q31_t out; uint32_t tempVal; @@ -621,10 +769,10 @@ extern "C" /** * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. */ - CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) + __STATIC_FORCEINLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + const q15_t * pRecipTable) { q15_t out = 0; uint32_t tempVal = 0; @@ -668,16 +816,55 @@ extern "C" return (signBits + 1); } +#if defined(ARM_MATH_NEON) + +static inline float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) +{ + float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN)); + float32x4_t e = vrsqrteq_f32(x1); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + return vmulq_f32(x, e); +} + +static inline int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec) +{ + float32x4_t tempF; + int32x4_t tempHI,tempLO; + + tempLO = vmovl_s16(vget_low_s16(vec)); + tempF = vcvtq_n_f32_s32(tempLO,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempLO = vcvtq_n_s32_f32(tempF,15); + + tempHI = vmovl_s16(vget_high_s16(vec)); + tempF = vcvtq_n_f32_s32(tempHI,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempHI = vcvtq_n_s32_f32(tempF,15); + + return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI))); +} + +static inline int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec) +{ + float32x4_t temp; + + temp = vcvtq_n_f32_s32(vec,31); + temp = __arm_vec_sqrt_f32_neon(temp); + return(vcvtq_n_s32_f32(temp,31)); +} + +#endif /* - * @brief C custom defined intrinsic function for M3 and M0 processors + * @brief C custom defined intrinsic functions */ #if !defined (ARM_MATH_DSP) /* - * @brief C custom defined QADD8 for M3 and M0 processors + * @brief C custom defined QADD8 */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + __STATIC_FORCEINLINE uint32_t __QADD8( uint32_t x, uint32_t y) { @@ -693,9 +880,9 @@ extern "C" /* - * @brief C custom defined QSUB8 for M3 and M0 processors + * @brief C custom defined QSUB8 */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + __STATIC_FORCEINLINE uint32_t __QSUB8( uint32_t x, uint32_t y) { @@ -711,9 +898,9 @@ extern "C" /* - * @brief C custom defined QADD16 for M3 and M0 processors + * @brief C custom defined QADD16 */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + __STATIC_FORCEINLINE uint32_t __QADD16( uint32_t x, uint32_t y) { @@ -728,9 +915,9 @@ extern "C" /* - * @brief C custom defined SHADD16 for M3 and M0 processors + * @brief C custom defined SHADD16 */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + __STATIC_FORCEINLINE uint32_t __SHADD16( uint32_t x, uint32_t y) { @@ -744,9 +931,9 @@ extern "C" /* - * @brief C custom defined QSUB16 for M3 and M0 processors + * @brief C custom defined QSUB16 */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + __STATIC_FORCEINLINE uint32_t __QSUB16( uint32_t x, uint32_t y) { @@ -760,9 +947,9 @@ extern "C" /* - * @brief C custom defined SHSUB16 for M3 and M0 processors + * @brief C custom defined SHSUB16 */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + __STATIC_FORCEINLINE uint32_t __SHSUB16( uint32_t x, uint32_t y) { @@ -776,9 +963,9 @@ extern "C" /* - * @brief C custom defined QASX for M3 and M0 processors + * @brief C custom defined QASX */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + __STATIC_FORCEINLINE uint32_t __QASX( uint32_t x, uint32_t y) { @@ -792,9 +979,9 @@ extern "C" /* - * @brief C custom defined SHASX for M3 and M0 processors + * @brief C custom defined SHASX */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + __STATIC_FORCEINLINE uint32_t __SHASX( uint32_t x, uint32_t y) { @@ -808,9 +995,9 @@ extern "C" /* - * @brief C custom defined QSAX for M3 and M0 processors + * @brief C custom defined QSAX */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + __STATIC_FORCEINLINE uint32_t __QSAX( uint32_t x, uint32_t y) { @@ -824,9 +1011,9 @@ extern "C" /* - * @brief C custom defined SHSAX for M3 and M0 processors + * @brief C custom defined SHSAX */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + __STATIC_FORCEINLINE uint32_t __SHSAX( uint32_t x, uint32_t y) { @@ -840,9 +1027,9 @@ extern "C" /* - * @brief C custom defined SMUSDX for M3 and M0 processors + * @brief C custom defined SMUSDX */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + __STATIC_FORCEINLINE uint32_t __SMUSDX( uint32_t x, uint32_t y) { @@ -851,9 +1038,9 @@ extern "C" } /* - * @brief C custom defined SMUADX for M3 and M0 processors + * @brief C custom defined SMUADX */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + __STATIC_FORCEINLINE uint32_t __SMUADX( uint32_t x, uint32_t y) { @@ -863,9 +1050,9 @@ extern "C" /* - * @brief C custom defined QADD for M3 and M0 processors + * @brief C custom defined QADD */ - CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + __STATIC_FORCEINLINE int32_t __QADD( int32_t x, int32_t y) { @@ -874,9 +1061,9 @@ extern "C" /* - * @brief C custom defined QSUB for M3 and M0 processors + * @brief C custom defined QSUB */ - CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + __STATIC_FORCEINLINE int32_t __QSUB( int32_t x, int32_t y) { @@ -885,9 +1072,9 @@ extern "C" /* - * @brief C custom defined SMLAD for M3 and M0 processors + * @brief C custom defined SMLAD */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + __STATIC_FORCEINLINE uint32_t __SMLAD( uint32_t x, uint32_t y, uint32_t sum) @@ -899,9 +1086,9 @@ extern "C" /* - * @brief C custom defined SMLADX for M3 and M0 processors + * @brief C custom defined SMLADX */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + __STATIC_FORCEINLINE uint32_t __SMLADX( uint32_t x, uint32_t y, uint32_t sum) @@ -913,9 +1100,9 @@ extern "C" /* - * @brief C custom defined SMLSDX for M3 and M0 processors + * @brief C custom defined SMLSDX */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + __STATIC_FORCEINLINE uint32_t __SMLSDX( uint32_t x, uint32_t y, uint32_t sum) @@ -927,9 +1114,9 @@ extern "C" /* - * @brief C custom defined SMLALD for M3 and M0 processors + * @brief C custom defined SMLALD */ - CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + __STATIC_FORCEINLINE uint64_t __SMLALD( uint32_t x, uint32_t y, uint64_t sum) @@ -942,9 +1129,9 @@ extern "C" /* - * @brief C custom defined SMLALDX for M3 and M0 processors + * @brief C custom defined SMLALDX */ - CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + __STATIC_FORCEINLINE uint64_t __SMLALDX( uint32_t x, uint32_t y, uint64_t sum) @@ -957,9 +1144,9 @@ extern "C" /* - * @brief C custom defined SMUAD for M3 and M0 processors + * @brief C custom defined SMUAD */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + __STATIC_FORCEINLINE uint32_t __SMUAD( uint32_t x, uint32_t y) { @@ -969,9 +1156,9 @@ extern "C" /* - * @brief C custom defined SMUSD for M3 and M0 processors + * @brief C custom defined SMUSD */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + __STATIC_FORCEINLINE uint32_t __SMUSD( uint32_t x, uint32_t y) { @@ -981,9 +1168,9 @@ extern "C" /* - * @brief C custom defined SXTB16 for M3 and M0 processors + * @brief C custom defined SXTB16 */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + __STATIC_FORCEINLINE uint32_t __SXTB16( uint32_t x) { return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | @@ -991,9 +1178,9 @@ extern "C" } /* - * @brief C custom defined SMMLA for M3 and M0 processors + * @brief C custom defined SMMLA */ - CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + __STATIC_FORCEINLINE int32_t __SMMLA( int32_t x, int32_t y, int32_t sum) @@ -1009,9 +1196,9 @@ extern "C" */ typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ } arm_fir_instance_q7; /** @@ -1019,9 +1206,9 @@ extern "C" */ typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ } arm_fir_instance_q15; /** @@ -1029,9 +1216,9 @@ extern "C" */ typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ } arm_fir_instance_q31; /** @@ -1039,12 +1226,11 @@ extern "C" */ typedef struct { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ } arm_fir_instance_f32; - /** * @brief Processing function for the Q7 FIR filter. * @param[in] S points to an instance of the Q7 FIR filter structure. @@ -1054,10 +1240,9 @@ extern "C" */ void arm_fir_q7( const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); /** * @brief Initialization function for the Q7 FIR filter. @@ -1068,12 +1253,11 @@ extern "C" * @param[in] blockSize number of samples that are processed. */ void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); /** * @brief Processing function for the Q15 FIR filter. @@ -1084,13 +1268,12 @@ extern "C" */ void arm_fir_q15( const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @brief Processing function for the fast Q15 FIR filter (fast version). * @param[in] S points to an instance of the Q15 FIR filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. @@ -1098,10 +1281,9 @@ extern "C" */ void arm_fir_fast_q15( const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR filter. @@ -1110,16 +1292,16 @@ extern "C" * @param[in] pCoeffs points to the filter coefficients. * @param[in] pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. + * @return The function returns either + * ARM_MATH_SUCCESS if initialization was successful or + * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value. */ arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); /** * @brief Processing function for the Q31 FIR filter. @@ -1130,24 +1312,22 @@ extern "C" */ void arm_fir_q31( const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. + * @brief Processing function for the fast Q31 FIR filter (fast version). + * @param[in] S points to an instance of the Q31 FIR filter structure. * @param[in] pSrc points to the block of input data. * @param[out] pDst points to the block of output data. * @param[in] blockSize number of samples to process. */ void arm_fir_fast_q31( const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR filter. @@ -1158,12 +1338,11 @@ extern "C" * @param[in] blockSize number of samples that are processed at a time. */ void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); /** * @brief Processing function for the floating-point FIR filter. @@ -1174,10 +1353,9 @@ extern "C" */ void arm_fir_f32( const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR filter. @@ -1188,22 +1366,21 @@ extern "C" * @param[in] blockSize number of samples that are processed at a time. */ void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); /** * @brief Instance structure for the Q15 Biquad cascade filter. */ typedef struct { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ } arm_biquad_casd_df1_inst_q15; /** @@ -1211,10 +1388,10 @@ extern "C" */ typedef struct { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ } arm_biquad_casd_df1_inst_q31; /** @@ -1222,12 +1399,11 @@ extern "C" */ typedef struct { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_casd_df1_inst_f32; - /** * @brief Processing function for the Q15 Biquad cascade filter. * @param[in] S points to an instance of the Q15 Biquad cascade structure. @@ -1237,10 +1413,9 @@ extern "C" */ void arm_biquad_cascade_df1_q15( const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); /** * @brief Initialization function for the Q15 Biquad cascade filter. @@ -1251,12 +1426,11 @@ extern "C" * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format */ void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); /** * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. @@ -1267,10 +1441,9 @@ extern "C" */ void arm_biquad_cascade_df1_fast_q15( const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); /** * @brief Processing function for the Q31 Biquad cascade filter @@ -1281,10 +1454,9 @@ extern "C" */ void arm_biquad_cascade_df1_q31( const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); /** * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. @@ -1295,10 +1467,9 @@ extern "C" */ void arm_biquad_cascade_df1_fast_q31( const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); /** * @brief Initialization function for the Q31 Biquad cascade filter. @@ -1309,12 +1480,11 @@ extern "C" * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format */ void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); /** * @brief Processing function for the floating-point Biquad cascade filter. @@ -1325,10 +1495,9 @@ extern "C" */ void arm_biquad_cascade_df1_f32( const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); /** * @brief Initialization function for the floating-point Biquad cascade filter. @@ -1338,11 +1507,10 @@ extern "C" * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); /** * @brief Instance structure for the floating-point matrix structure. @@ -1385,7 +1553,6 @@ extern "C" q31_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_q31; - /** * @brief Floating-point matrix addition. * @param[in] pSrcA points to the first input matrix structure @@ -1394,11 +1561,10 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_add_f32( +arm_status arm_mat_add_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - + arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix addition. @@ -1408,11 +1574,10 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_add_q15( +arm_status arm_mat_add_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - + arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix addition. @@ -1422,11 +1587,10 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_add_q31( +arm_status arm_mat_add_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - + arm_matrix_instance_q31 * pDst); /** * @brief Floating-point, complex, matrix multiplication. @@ -1436,11 +1600,10 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_cmplx_mult_f32( +arm_status arm_mat_cmplx_mult_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - + arm_matrix_instance_f32 * pDst); /** * @brief Q15, complex, matrix multiplication. @@ -1450,12 +1613,11 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_cmplx_mult_q15( +arm_status arm_mat_cmplx_mult_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); /** * @brief Q31, complex, matrix multiplication. @@ -1465,11 +1627,10 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_cmplx_mult_q31( +arm_status arm_mat_cmplx_mult_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - + arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix transpose. @@ -1478,10 +1639,9 @@ extern "C" * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_trans_f32( +arm_status arm_mat_trans_f32( const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - + arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix transpose. @@ -1490,10 +1650,9 @@ extern "C" * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_trans_q15( +arm_status arm_mat_trans_q15( const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - + arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix transpose. @@ -1502,10 +1661,9 @@ extern "C" * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_trans_q31( +arm_status arm_mat_trans_q31( const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - + arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix multiplication @@ -1515,11 +1673,10 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_mult_f32( +arm_status arm_mat_mult_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - + arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix multiplication @@ -1530,12 +1687,11 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_mult_q15( +arm_status arm_mat_mult_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - + arm_matrix_instance_q15 * pDst, + q15_t * pState); /** * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 @@ -1546,12 +1702,11 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_mult_fast_q15( +arm_status arm_mat_mult_fast_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - + arm_matrix_instance_q15 * pDst, + q15_t * pState); /** * @brief Q31 matrix multiplication @@ -1561,11 +1716,10 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_mult_q31( +arm_status arm_mat_mult_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - + arm_matrix_instance_q31 * pDst); /** * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 @@ -1575,11 +1729,10 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_mult_fast_q31( +arm_status arm_mat_mult_fast_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - + arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix subtraction @@ -1589,11 +1742,10 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_sub_f32( +arm_status arm_mat_sub_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - + arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix subtraction @@ -1603,11 +1755,10 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_sub_q15( +arm_status arm_mat_sub_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - + arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix subtraction @@ -1617,11 +1768,10 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_sub_q31( +arm_status arm_mat_sub_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - + arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix scaling. @@ -1631,11 +1781,10 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_scale_f32( +arm_status arm_mat_scale_f32( const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - + float32_t scale, + arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix scaling. @@ -1646,12 +1795,11 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_scale_q15( +arm_status arm_mat_scale_q15( const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix scaling. @@ -1662,12 +1810,11 @@ extern "C" * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ - arm_status arm_mat_scale_q31( +arm_status arm_mat_scale_q31( const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); /** * @brief Q31 matrix initialization. @@ -1676,12 +1823,11 @@ extern "C" * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); /** * @brief Q15 matrix initialization. @@ -1690,12 +1836,11 @@ extern "C" * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); /** * @brief Floating-point matrix initialization. @@ -1704,12 +1849,11 @@ extern "C" * @param[in] nColumns number of columns in the matrix. * @param[in] pData points to the matrix data array. */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); /** @@ -1717,17 +1861,17 @@ extern "C" */ typedef struct { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ #if !defined (ARM_MATH_DSP) - q15_t A1; - q15_t A2; + q15_t A1; + q15_t A2; #else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ #endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ } arm_pid_instance_q15; /** @@ -1735,13 +1879,13 @@ extern "C" */ typedef struct { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ } arm_pid_instance_q31; /** @@ -1749,13 +1893,13 @@ extern "C" */ typedef struct { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ } arm_pid_instance_f32; @@ -1766,8 +1910,8 @@ extern "C" * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. */ void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); + arm_pid_instance_f32 * S, + int32_t resetStateFlag); /** @@ -1775,7 +1919,7 @@ extern "C" * @param[in,out] S is an instance of the floating-point PID Control structure */ void arm_pid_reset_f32( - arm_pid_instance_f32 * S); + arm_pid_instance_f32 * S); /** @@ -1784,8 +1928,8 @@ extern "C" * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. */ void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); + arm_pid_instance_q31 * S, + int32_t resetStateFlag); /** @@ -1794,7 +1938,7 @@ extern "C" */ void arm_pid_reset_q31( - arm_pid_instance_q31 * S); + arm_pid_instance_q31 * S); /** @@ -1803,8 +1947,8 @@ extern "C" * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. */ void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); + arm_pid_instance_q15 * S, + int32_t resetStateFlag); /** @@ -1812,7 +1956,7 @@ extern "C" * @param[in,out] S points to an instance of the q15 PID Control structure */ void arm_pid_reset_q15( - arm_pid_instance_q15 * S); + arm_pid_instance_q15 * S); /** @@ -1820,10 +1964,10 @@ extern "C" */ typedef struct { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ } arm_linear_interp_instance_f32; /** @@ -1831,9 +1975,9 @@ extern "C" */ typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_f32; /** @@ -1841,9 +1985,9 @@ extern "C" */ typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q31; /** @@ -1851,9 +1995,9 @@ extern "C" */ typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q15; /** @@ -1861,9 +2005,9 @@ extern "C" */ typedef struct { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q7; @@ -1875,10 +2019,10 @@ extern "C" * @param[in] blockSize number of samples in each vector */ void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); /** @@ -1889,10 +2033,10 @@ extern "C" * @param[in] blockSize number of samples in each vector */ void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); /** @@ -1903,10 +2047,10 @@ extern "C" * @param[in] blockSize number of samples in each vector */ void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); /** @@ -1917,10 +2061,10 @@ extern "C" * @param[in] blockSize number of samples in each vector */ void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); /** @@ -1928,26 +2072,26 @@ extern "C" */ typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix2_instance_q15; /* Deprecated */ arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix2_q15( const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); + q15_t * pSrc); /** @@ -1955,292 +2099,309 @@ extern "C" */ typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix4_instance_q15; /* Deprecated */ arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix4_q15( const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); + q15_t * pSrc); /** * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. */ typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix2_instance_q31; /* Deprecated */ arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix2_q31( const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); + q31_t * pSrc); /** * @brief Instance structure for the Q31 CFFT/CIFFT function. */ typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix4_instance_q31; /* Deprecated */ void arm_cfft_radix4_q31( const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); + q31_t * pSrc); /* Deprecated */ arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ } arm_cfft_radix2_instance_f32; /* Deprecated */ arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix2_f32( const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); + float32_t * pSrc); /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ } arm_cfft_radix4_instance_f32; /* Deprecated */ arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix4_f32( const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); + float32_t * pSrc); /** * @brief Instance structure for the fixed-point CFFT/CIFFT function. */ typedef struct { - uint16_t fftLen; /**< length of the FFT. */ + uint16_t fftLen; /**< length of the FFT. */ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ + uint16_t bitRevLength; /**< bit reversal table length. */ } arm_cfft_instance_q15; void arm_cfft_q15( const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); /** * @brief Instance structure for the fixed-point CFFT/CIFFT function. */ typedef struct { - uint16_t fftLen; /**< length of the FFT. */ + uint16_t fftLen; /**< length of the FFT. */ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ + uint16_t bitRevLength; /**< bit reversal table length. */ } arm_cfft_instance_q31; void arm_cfft_q31( const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { - uint16_t fftLen; /**< length of the FFT. */ + uint16_t fftLen; /**< length of the FFT. */ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ + uint16_t bitRevLength; /**< bit reversal table length. */ } arm_cfft_instance_f32; void arm_cfft_f32( const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); /** * @brief Instance structure for the Q15 RFFT/RIFFT function. */ typedef struct { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_q15; arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); void arm_rfft_q15( const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); + q15_t * pSrc, + q15_t * pDst); /** * @brief Instance structure for the Q31 RFFT/RIFFT function. */ typedef struct { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_q31; arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); void arm_rfft_q31( const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); + q31_t * pSrc, + q31_t * pDst); /** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ typedef struct { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_f32; arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); void arm_rfft_f32( const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); + float32_t * pSrc, + float32_t * pDst); /** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ typedef struct { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ } arm_rfft_fast_instance_f32 ; arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +arm_status arm_rfft_32_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_64_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_128_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_256_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_512_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_1024_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_2048_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_4096_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); + + void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); /** * @brief Instance structure for the floating-point DCT4/IDCT4 function. */ typedef struct { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + const float32_t *pTwiddle; /**< points to the twiddle factor table. */ + const float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_f32; @@ -2255,12 +2416,12 @@ void arm_rfft_fast_f32( * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. */ arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); /** @@ -2271,8 +2432,8 @@ void arm_rfft_fast_f32( */ void arm_dct4_f32( const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); + float32_t * pState, + float32_t * pInlineBuffer); /** @@ -2280,13 +2441,13 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_q31; @@ -2301,12 +2462,12 @@ void arm_rfft_fast_f32( * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. */ arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); /** @@ -2317,8 +2478,8 @@ void arm_rfft_fast_f32( */ void arm_dct4_q31( const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); + q31_t * pState, + q31_t * pInlineBuffer); /** @@ -2326,13 +2487,13 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_q15; @@ -2347,12 +2508,12 @@ void arm_rfft_fast_f32( * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. */ arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); /** @@ -2363,8 +2524,8 @@ void arm_rfft_fast_f32( */ void arm_dct4_q15( const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); + q15_t * pState, + q15_t * pInlineBuffer); /** @@ -2375,10 +2536,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in each vector */ void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); /** @@ -2389,10 +2550,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in each vector */ void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); /** @@ -2403,10 +2564,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in each vector */ void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); /** @@ -2417,10 +2578,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in each vector */ void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); /** @@ -2431,10 +2592,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in each vector */ void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); /** @@ -2445,10 +2606,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in each vector */ void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); /** @@ -2459,10 +2620,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in each vector */ void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); /** @@ -2473,10 +2634,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in each vector */ void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); /** @@ -2487,10 +2648,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in the vector */ void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); /** @@ -2502,11 +2663,11 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in the vector */ void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); /** @@ -2518,11 +2679,11 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in the vector */ void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); /** @@ -2534,11 +2695,11 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in the vector */ void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); /** @@ -2548,9 +2709,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in each vector */ void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); /** @@ -2560,9 +2721,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in each vector */ void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); /** @@ -2572,9 +2733,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in each vector */ void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); /** @@ -2584,9 +2745,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in each vector */ void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); /** @@ -2597,10 +2758,10 @@ void arm_rfft_fast_f32( * @param[out] result output result returned here */ void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); /** @@ -2611,10 +2772,10 @@ void arm_rfft_fast_f32( * @param[out] result output result returned here */ void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); /** @@ -2625,10 +2786,10 @@ void arm_rfft_fast_f32( * @param[out] result output result returned here */ void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); /** @@ -2639,10 +2800,10 @@ void arm_rfft_fast_f32( * @param[out] result output result returned here */ void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); /** @@ -2653,10 +2814,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in the vector */ void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); /** @@ -2667,10 +2828,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in the vector */ void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); /** @@ -2681,10 +2842,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in the vector */ void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); /** @@ -2695,10 +2856,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in the vector */ void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); /** @@ -2709,10 +2870,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in the vector */ void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); /** @@ -2723,10 +2884,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in the vector */ void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); /** @@ -2737,10 +2898,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in the vector */ void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); /** @@ -2750,9 +2911,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in the vector */ void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); /** @@ -2762,9 +2923,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in the vector */ void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); /** @@ -2774,9 +2935,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in the vector */ void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); /** @@ -2786,9 +2947,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples in the vector */ void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); /** @@ -2798,9 +2959,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process */ void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); /** @@ -2810,9 +2971,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process */ void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); /** @@ -2822,9 +2983,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process */ void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); /** @@ -2834,9 +2995,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process */ void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); /** @@ -2846,9 +3007,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process */ void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); + float32_t value, + float32_t * pDst, + uint32_t blockSize); /** @@ -2858,9 +3019,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process */ void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); + q7_t value, + q7_t * pDst, + uint32_t blockSize); /** @@ -2870,9 +3031,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process */ void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); + q15_t value, + q15_t * pDst, + uint32_t blockSize); /** @@ -2882,9 +3043,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process */ void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); + q31_t value, + q31_t * pDst, + uint32_t blockSize); /** @@ -2896,11 +3057,11 @@ void arm_rfft_fast_f32( * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. */ void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); /** @@ -2914,13 +3075,13 @@ void arm_rfft_fast_f32( * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). */ void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); /** @@ -2932,11 +3093,11 @@ void arm_rfft_fast_f32( * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. */ void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); /** @@ -2948,11 +3109,11 @@ void arm_rfft_fast_f32( * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); /** @@ -2966,13 +3127,13 @@ void arm_rfft_fast_f32( * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). */ void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); /** @@ -2984,11 +3145,11 @@ void arm_rfft_fast_f32( * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); /** @@ -3000,11 +3161,11 @@ void arm_rfft_fast_f32( * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); /** @@ -3018,13 +3179,13 @@ void arm_rfft_fast_f32( * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). */ void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); /** @@ -3036,11 +3197,11 @@ void arm_rfft_fast_f32( * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. */ void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); /** @@ -3055,13 +3216,13 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); /** @@ -3078,15 +3239,15 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); /** @@ -3101,13 +3262,13 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); /** @@ -3122,13 +3283,13 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); /** @@ -3145,15 +3306,15 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); /** @@ -3168,13 +3329,13 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); /** @@ -3189,13 +3350,13 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); /** @@ -3212,15 +3373,15 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); /** @@ -3235,13 +3396,13 @@ void arm_rfft_fast_f32( * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); /** @@ -3249,10 +3410,10 @@ void arm_rfft_fast_f32( */ typedef struct { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_q15; /** @@ -3260,56 +3421,57 @@ void arm_rfft_fast_f32( */ typedef struct { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_q31; - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct +/** + @brief Instance structure for floating-point FIR decimator. + */ +typedef struct { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_f32; - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_f32( +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + */ +void arm_fir_decimate_f32( const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + */ +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); /** @@ -3321,9 +3483,9 @@ void arm_rfft_fast_f32( */ void arm_fir_decimate_q15( const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); /** @@ -3335,9 +3497,9 @@ void arm_rfft_fast_f32( */ void arm_fir_decimate_fast_q15( const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); /** @@ -3352,12 +3514,12 @@ void arm_rfft_fast_f32( * blockSize is not a multiple of M. */ arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); /** @@ -3369,9 +3531,9 @@ void arm_rfft_fast_f32( */ void arm_fir_decimate_q31( const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); /** * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. @@ -3381,10 +3543,10 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of input samples to process per call. */ void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); /** @@ -3399,12 +3561,12 @@ void arm_rfft_fast_f32( * blockSize is not a multiple of M. */ arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); /** @@ -3412,10 +3574,10 @@ void arm_rfft_fast_f32( */ typedef struct { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ } arm_fir_interpolate_instance_q15; /** @@ -3423,10 +3585,10 @@ void arm_rfft_fast_f32( */ typedef struct { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ } arm_fir_interpolate_instance_q31; /** @@ -3434,10 +3596,10 @@ void arm_rfft_fast_f32( */ typedef struct { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ } arm_fir_interpolate_instance_f32; @@ -3450,9 +3612,9 @@ void arm_rfft_fast_f32( */ void arm_fir_interpolate_q15( const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); /** @@ -3467,12 +3629,12 @@ void arm_rfft_fast_f32( * the filter length numTaps is not a multiple of the interpolation factor L. */ arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); /** @@ -3484,9 +3646,9 @@ void arm_rfft_fast_f32( */ void arm_fir_interpolate_q31( const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); /** @@ -3501,12 +3663,12 @@ void arm_rfft_fast_f32( * the filter length numTaps is not a multiple of the interpolation factor L. */ arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); /** @@ -3518,9 +3680,9 @@ void arm_rfft_fast_f32( */ void arm_fir_interpolate_f32( const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); /** @@ -3535,12 +3697,12 @@ void arm_rfft_fast_f32( * the filter length numTaps is not a multiple of the interpolation factor L. */ arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); /** @@ -3548,10 +3710,10 @@ void arm_rfft_fast_f32( */ typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ } arm_biquad_cas_df1_32x64_ins_q31; @@ -3563,9 +3725,9 @@ void arm_rfft_fast_f32( */ void arm_biquad_cas_df1_32x64_q31( const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); /** @@ -3576,11 +3738,11 @@ void arm_rfft_fast_f32( * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format */ void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); /** @@ -3588,9 +3750,9 @@ void arm_rfft_fast_f32( */ typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_cascade_df2T_instance_f32; /** @@ -3598,9 +3760,9 @@ void arm_rfft_fast_f32( */ typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_cascade_stereo_df2T_instance_f32; /** @@ -3608,9 +3770,9 @@ void arm_rfft_fast_f32( */ typedef struct { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_cascade_df2T_instance_f64; @@ -3623,9 +3785,9 @@ void arm_rfft_fast_f32( */ void arm_biquad_cascade_df2T_f32( const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); /** @@ -3637,9 +3799,9 @@ void arm_rfft_fast_f32( */ void arm_biquad_cascade_stereo_df2T_f32( const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); /** @@ -3651,11 +3813,17 @@ void arm_rfft_fast_f32( */ void arm_biquad_cascade_df2T_f64( const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); +#if defined(ARM_MATH_NEON) +void arm_biquad_cascade_df2T_compute_coefs_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs); +#endif /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] S points to an instance of the filter data structure. @@ -3664,10 +3832,10 @@ void arm_rfft_fast_f32( * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); /** @@ -3678,10 +3846,10 @@ void arm_rfft_fast_f32( * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); /** @@ -3692,10 +3860,10 @@ void arm_rfft_fast_f32( * @param[in] pState points to the state buffer. */ void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); /** @@ -3703,9 +3871,9 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_q15; /** @@ -3713,9 +3881,9 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_q31; /** @@ -3723,9 +3891,9 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_f32; @@ -3737,10 +3905,10 @@ void arm_rfft_fast_f32( * @param[in] pState points to the state buffer. The array is of length numStages. */ void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState); /** @@ -3752,9 +3920,9 @@ void arm_rfft_fast_f32( */ void arm_fir_lattice_q15( const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); /** @@ -3765,10 +3933,10 @@ void arm_rfft_fast_f32( * @param[in] pState points to the state buffer. The array is of length numStages. */ void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState); /** @@ -3780,9 +3948,9 @@ void arm_rfft_fast_f32( */ void arm_fir_lattice_q31( const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); /** @@ -3793,10 +3961,10 @@ void arm_rfft_fast_f32( * @param[in] pState points to the state buffer. The array is of length numStages. */ void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState); /** @@ -3808,9 +3976,9 @@ void arm_rfft_fast_f32( */ void arm_fir_lattice_f32( const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); /** @@ -3818,10 +3986,10 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_q15; /** @@ -3829,10 +3997,10 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_q31; /** @@ -3840,10 +4008,10 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_f32; @@ -3856,9 +4024,9 @@ void arm_rfft_fast_f32( */ void arm_iir_lattice_f32( const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); /** @@ -3871,12 +4039,12 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); /** @@ -3888,9 +4056,9 @@ void arm_rfft_fast_f32( */ void arm_iir_lattice_q31( const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); /** @@ -3903,12 +4071,12 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process. */ void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); /** @@ -3920,9 +4088,9 @@ void arm_rfft_fast_f32( */ void arm_iir_lattice_q15( const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); /** @@ -3935,12 +4103,12 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process per call. */ void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); /** @@ -3948,10 +4116,10 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ } arm_lms_instance_f32; @@ -3966,11 +4134,11 @@ void arm_rfft_fast_f32( */ void arm_lms_f32( const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); /** @@ -3983,12 +4151,12 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process. */ void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); /** @@ -3996,11 +4164,11 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ } arm_lms_instance_q15; @@ -4015,13 +4183,13 @@ void arm_rfft_fast_f32( * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); /** @@ -4035,11 +4203,11 @@ void arm_rfft_fast_f32( */ void arm_lms_q15( const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); /** @@ -4047,11 +4215,11 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ } arm_lms_instance_q31; @@ -4066,11 +4234,11 @@ void arm_rfft_fast_f32( */ void arm_lms_q31( const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); /** @@ -4084,13 +4252,13 @@ void arm_rfft_fast_f32( * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); /** @@ -4098,12 +4266,12 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_f32; @@ -4117,12 +4285,12 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process. */ void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); /** @@ -4135,12 +4303,12 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process. */ void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); /** @@ -4148,14 +4316,14 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_q31; @@ -4169,12 +4337,12 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process. */ void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); /** @@ -4188,13 +4356,13 @@ void arm_rfft_fast_f32( * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); /** @@ -4202,14 +4370,14 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_q15; @@ -4223,12 +4391,12 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples to process. */ void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); /** @@ -4242,13 +4410,13 @@ void arm_rfft_fast_f32( * @param[in] postShift bit shift applied to coefficients. */ void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); /** @@ -4260,81 +4428,80 @@ void arm_rfft_fast_f32( * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); - /** - * @brief Correlation of Q15 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - +/** + @brief Correlation of Q15 sequences + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); - /** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); /** @@ -4346,27 +4513,27 @@ void arm_rfft_fast_f32( * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); /** @@ -4380,13 +4547,13 @@ void arm_rfft_fast_f32( * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). */ void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); /** @@ -4398,11 +4565,11 @@ void arm_rfft_fast_f32( * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. */ void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); /** @@ -4410,12 +4577,12 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_f32; /** @@ -4423,12 +4590,12 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q31; /** @@ -4436,12 +4603,12 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q15; /** @@ -4449,12 +4616,12 @@ void arm_rfft_fast_f32( */ typedef struct { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q7; @@ -4467,11 +4634,11 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); /** @@ -4485,13 +4652,13 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); /** @@ -4503,11 +4670,11 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); /** @@ -4521,13 +4688,13 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); /** @@ -4540,12 +4707,12 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); /** @@ -4559,13 +4726,13 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); /** @@ -4578,12 +4745,12 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of input samples to process per call. */ void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); /** @@ -4597,13 +4764,13 @@ void arm_rfft_fast_f32( * @param[in] blockSize number of samples that will be processed per block. */ void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); /** @@ -4613,9 +4780,9 @@ void arm_rfft_fast_f32( * @param[out] pCosVal points to the processed cos output. */ void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); /** @@ -4625,9 +4792,9 @@ void arm_rfft_fast_f32( * @param[out] pCosVal points to the processed cosine output. */ void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); /** @@ -4637,9 +4804,9 @@ void arm_rfft_fast_f32( * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); /** * @brief Q31 complex conjugate. @@ -4648,9 +4815,9 @@ void arm_rfft_fast_f32( * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); /** @@ -4660,9 +4827,9 @@ void arm_rfft_fast_f32( * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); /** @@ -4672,9 +4839,9 @@ void arm_rfft_fast_f32( * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); /** @@ -4684,9 +4851,9 @@ void arm_rfft_fast_f32( * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); /** @@ -4696,9 +4863,9 @@ void arm_rfft_fast_f32( * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); /** @@ -4723,7 +4890,8 @@ void arm_rfft_fast_f32( * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] * A0 = Kp + Ki + Kd * A1 = (-Kp ) - (2 * Kd ) - * A2 = Kd + * A2 = Kd + * * * \par * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant @@ -4768,12 +4936,12 @@ void arm_rfft_fast_f32( */ /** - * @brief Process function for the floating-point PID Control. + * @brief Process function for the floating-point PID Control. * @param[in,out] S is an instance of the floating-point PID Control structure * @param[in] in input sample to process - * @return out processed output sample. + * @return processed output sample. */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + __STATIC_FORCEINLINE float32_t arm_pid_f32( arm_pid_instance_f32 * S, float32_t in) { @@ -4793,21 +4961,20 @@ void arm_rfft_fast_f32( } - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( +/** + @brief Process function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +__STATIC_FORCEINLINE q31_t arm_pid_q31( arm_pid_instance_q31 * S, q31_t in) { @@ -4839,22 +5006,21 @@ void arm_rfft_fast_f32( } - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( +/** + @brief Process function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +__STATIC_FORCEINLINE q15_t arm_pid_q15( arm_pid_instance_q15 * S, q15_t in) { @@ -4862,16 +5028,13 @@ void arm_rfft_fast_f32( q15_t out; #if defined (ARM_MATH_DSP) - __SIMD32_TYPE *vstate; - /* Implementation of PID controller */ /* acc = A0 * x[n] */ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); #else /* acc = A0 * x[n] */ acc = ((q31_t) S->A0) * in; @@ -4964,8 +5127,9 @@ void arm_rfft_fast_f32( * @param[in] Ib input three-phase coordinate b * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @return none */ - CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + __STATIC_FORCEINLINE void arm_clarke_f32( float32_t Ia, float32_t Ib, float32_t * pIalpha, @@ -4979,20 +5143,20 @@ void arm_rfft_fast_f32( } - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( +/** + @brief Clarke transform for Q31 version + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_clarke_q31( q31_t Ia, q31_t Ib, q31_t * pIalpha, @@ -5017,18 +5181,6 @@ void arm_rfft_fast_f32( * @} end of clarke group */ - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** * @ingroup groupController @@ -5061,8 +5213,9 @@ void arm_rfft_fast_f32( * @param[in] Ibeta input two-phase orthogonal vector axis beta * @param[out] pIa points to output three-phase coordinate a * @param[out] pIb points to output three-phase coordinate b + * @return none */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + __STATIC_FORCEINLINE void arm_inv_clarke_f32( float32_t Ialpha, float32_t Ibeta, float32_t * pIa, @@ -5076,20 +5229,20 @@ void arm_rfft_fast_f32( } - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( +/** + @brief Inverse Clarke transform for Q31 version + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] pIa points to output three-phase coordinate a + @param[out] pIb points to output three-phase coordinate b + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_clarke_q31( q31_t Ialpha, q31_t Ibeta, q31_t * pIa, @@ -5114,17 +5267,6 @@ void arm_rfft_fast_f32( * @} end of inv_clarke group */ - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - /** @@ -5168,11 +5310,12 @@ void arm_rfft_fast_f32( * @param[out] pIq points to output rotor reference frame q * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta + * @return none * * The function implements the forward Park transform. * */ - CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + __STATIC_FORCEINLINE void arm_park_f32( float32_t Ialpha, float32_t Ibeta, float32_t * pId, @@ -5188,22 +5331,22 @@ void arm_rfft_fast_f32( } - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_park_q31( +/** + @brief Park transform for Q31 version + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] pId points to output rotor reference frame d + @param[out] pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_park_q31( q31_t Ialpha, q31_t Ibeta, q31_t * pId, @@ -5238,17 +5381,6 @@ void arm_rfft_fast_f32( * @} end of park group */ - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - /** * @ingroup groupController @@ -5284,8 +5416,9 @@ void arm_rfft_fast_f32( * @param[out] pIbeta points to output two-phase orthogonal vector axis beta * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta + * @return none */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + __STATIC_FORCEINLINE void arm_inv_park_f32( float32_t Id, float32_t Iq, float32_t * pIalpha, @@ -5301,22 +5434,22 @@ void arm_rfft_fast_f32( } - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( +/** + @brief Inverse Park transform for Q31 version + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_park_q31( q31_t Id, q31_t Iq, q31_t * pIalpha, @@ -5352,17 +5485,6 @@ void arm_rfft_fast_f32( */ - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - /** * @ingroup groupInterpolation */ @@ -5411,7 +5533,7 @@ void arm_rfft_fast_f32( * @return y processed output sample. * */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + __STATIC_FORCEINLINE float32_t arm_linear_interp_f32( arm_linear_interp_instance_f32 * S, float32_t x) { @@ -5468,7 +5590,7 @@ void arm_rfft_fast_f32( * This function can support maximum of table size 2^12. * */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + __STATIC_FORCEINLINE q31_t arm_linear_interp_q31( q31_t * pYData, q31_t x, uint32_t nValues) @@ -5526,7 +5648,7 @@ void arm_rfft_fast_f32( * This function can support maximum of table size 2^12. * */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + __STATIC_FORCEINLINE q15_t arm_linear_interp_q15( q15_t * pYData, q31_t x, uint32_t nValues) @@ -5583,7 +5705,7 @@ void arm_rfft_fast_f32( * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. */ - CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + __STATIC_FORCEINLINE q7_t arm_linear_interp_q7( q7_t * pYData, q31_t x, uint32_t nValues) @@ -5716,28 +5838,34 @@ void arm_rfft_fast_f32( * @{ */ - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE arm_status arm_sqrt_f32( float32_t in, float32_t * pOut) { if (in >= 0.0f) { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + #else + *pOut = sqrtf(in); + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); + #else + *pOut = sqrtf(in); + #endif + #else *pOut = sqrtf(in); #endif @@ -5752,28 +5880,53 @@ void arm_rfft_fast_f32( } - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q31( q31_t in, q31_t * pOut); +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. + * @brief Vector Floating-point square root function. + * @param[in] pIn input vector. + * @param[out] pOut vector of square roots of input elements. + * @param[in] len length of input vector. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * in is negative value and returns zero output for negative values. */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); + void arm_vsqrt_f32( + float32_t * pIn, + float32_t * pOut, + uint16_t len); + + void arm_vsqrt_q31( + q31_t * pIn, + q31_t * pOut, + uint16_t len); + + void arm_vsqrt_q15( + q15_t * pIn, + q15_t * pOut, + uint16_t len); /** * @} end of SQRT group @@ -5783,7 +5936,7 @@ void arm_rfft_fast_f32( /** * @brief floating-point Circular write function. */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + __STATIC_FORCEINLINE void arm_circularWrite_f32( int32_t * circBuffer, int32_t L, uint16_t * writeOffset, @@ -5828,7 +5981,7 @@ void arm_rfft_fast_f32( /** * @brief floating-point Circular Read function. */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + __STATIC_FORCEINLINE void arm_circularRead_f32( int32_t * circBuffer, int32_t L, int32_t * readOffset, @@ -5840,12 +5993,13 @@ void arm_rfft_fast_f32( uint32_t blockSize) { uint32_t i = 0U; - int32_t rOffset, dst_end; + int32_t rOffset; + int32_t* dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); + dst_end = dst_base + dst_length; /* Loop over the blockSize */ i = blockSize; @@ -5858,7 +6012,7 @@ void arm_rfft_fast_f32( /* Update the input pointer */ dst += dstInc; - if (dst == (int32_t *) dst_end) + if (dst == dst_end) { dst = dst_base; } @@ -5883,7 +6037,7 @@ void arm_rfft_fast_f32( /** * @brief Q15 Circular write function. */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + __STATIC_FORCEINLINE void arm_circularWrite_q15( q15_t * circBuffer, int32_t L, uint16_t * writeOffset, @@ -5927,7 +6081,7 @@ void arm_rfft_fast_f32( /** * @brief Q15 Circular Read function. */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + __STATIC_FORCEINLINE void arm_circularRead_q15( q15_t * circBuffer, int32_t L, int32_t * readOffset, @@ -5939,13 +6093,14 @@ void arm_rfft_fast_f32( uint32_t blockSize) { uint32_t i = 0; - int32_t rOffset, dst_end; + int32_t rOffset; + q15_t* dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); + dst_end = dst_base + dst_length; /* Loop over the blockSize */ i = blockSize; @@ -5958,7 +6113,7 @@ void arm_rfft_fast_f32( /* Update the input pointer */ dst += dstInc; - if (dst == (q15_t *) dst_end) + if (dst == dst_end) { dst = dst_base; } @@ -5983,7 +6138,7 @@ void arm_rfft_fast_f32( /** * @brief Q7 Circular write function. */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + __STATIC_FORCEINLINE void arm_circularWrite_q7( q7_t * circBuffer, int32_t L, uint16_t * writeOffset, @@ -6027,7 +6182,7 @@ void arm_rfft_fast_f32( /** * @brief Q7 Circular Read function. */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + __STATIC_FORCEINLINE void arm_circularRead_q7( q7_t * circBuffer, int32_t L, int32_t * readOffset, @@ -6039,13 +6194,14 @@ void arm_rfft_fast_f32( uint32_t blockSize) { uint32_t i = 0; - int32_t rOffset, dst_end; + int32_t rOffset; + q7_t* dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); + dst_end = dst_base + dst_length; /* Loop over the blockSize */ i = blockSize; @@ -6058,7 +6214,7 @@ void arm_rfft_fast_f32( /* Update the input pointer */ dst += dstInc; - if (dst == (q7_t *) dst_end) + if (dst == dst_end) { dst = dst_base; } @@ -6087,9 +6243,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); /** @@ -6099,9 +6255,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); /** @@ -6111,9 +6267,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); /** @@ -6123,9 +6279,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); /** @@ -6135,9 +6291,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); /** @@ -6147,9 +6303,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); /** @@ -6159,9 +6315,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); /** @@ -6171,9 +6327,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); /** @@ -6183,9 +6339,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); /** @@ -6195,9 +6351,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); /** @@ -6207,9 +6363,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); /** @@ -6219,9 +6375,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); /** @@ -6231,9 +6387,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); /** @@ -6243,9 +6399,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); /** @@ -6255,9 +6411,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); /** @@ -6267,9 +6423,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); /** @@ -6279,9 +6435,9 @@ void arm_rfft_fast_f32( * @param[out] pResult is output value. */ void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); /** @@ -6291,9 +6447,9 @@ void arm_rfft_fast_f32( * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); /** @@ -6303,9 +6459,9 @@ void arm_rfft_fast_f32( * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); /** @@ -6315,9 +6471,9 @@ void arm_rfft_fast_f32( * @param[in] numSamples number of complex samples in the input vector */ void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); /** @@ -6329,11 +6485,11 @@ void arm_rfft_fast_f32( * @param[out] imagResult imaginary part of the result returned here */ void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); /** @@ -6345,11 +6501,11 @@ void arm_rfft_fast_f32( * @param[out] imagResult imaginary part of the result returned here */ void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); /** @@ -6361,11 +6517,11 @@ void arm_rfft_fast_f32( * @param[out] imagResult imaginary part of the result returned here */ void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); /** @@ -6376,10 +6532,10 @@ void arm_rfft_fast_f32( * @param[in] numSamples number of samples in each vector */ void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); /** @@ -6390,10 +6546,10 @@ void arm_rfft_fast_f32( * @param[in] numSamples number of samples in each vector */ void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); /** @@ -6404,10 +6560,10 @@ void arm_rfft_fast_f32( * @param[in] numSamples number of samples in each vector */ void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); /** @@ -6418,10 +6574,10 @@ void arm_rfft_fast_f32( * @param[in] index is the array index of the minimum value in the input buffer. */ void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); /** @@ -6432,10 +6588,10 @@ void arm_rfft_fast_f32( * @param[in] pIndex is the array index of the minimum value in the input buffer. */ void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); /** @@ -6446,10 +6602,10 @@ void arm_rfft_fast_f32( * @param[out] pIndex is the array index of the minimum value in the input buffer. */ void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); /** @@ -6460,10 +6616,10 @@ void arm_rfft_fast_f32( * @param[out] pIndex is the array index of the minimum value in the input buffer. */ void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); /** @@ -6474,10 +6630,10 @@ void arm_rfft_fast_f32( * @param[out] pIndex index of maximum value returned here */ void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); /** @@ -6488,10 +6644,10 @@ void arm_rfft_fast_f32( * @param[out] pIndex index of maximum value returned here */ void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); /** @@ -6502,10 +6658,10 @@ void arm_rfft_fast_f32( * @param[out] pIndex index of maximum value returned here */ void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); /** @@ -6516,10 +6672,10 @@ void arm_rfft_fast_f32( * @param[out] pIndex index of maximum value returned here */ void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); /** @@ -6530,10 +6686,10 @@ void arm_rfft_fast_f32( * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); /** @@ -6544,10 +6700,10 @@ void arm_rfft_fast_f32( * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); /** @@ -6558,10 +6714,10 @@ void arm_rfft_fast_f32( * @param[in] numSamples number of complex samples in each vector */ void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); /** @@ -6571,9 +6727,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize length of the input vector */ void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); /** @@ -6583,9 +6739,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize length of the input vector */ void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); /** @@ -6595,9 +6751,21 @@ void arm_rfft_fast_f32( * @param[in] blockSize length of the input vector */ void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); /** @@ -6607,9 +6775,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize is the number of samples to process */ void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); /** @@ -6619,9 +6787,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize is the number of samples to process */ void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); /** @@ -6631,9 +6799,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize is the number of samples to process */ void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); /** @@ -6643,9 +6811,9 @@ void arm_rfft_fast_f32( * @param[in] blockSize is the number of samples to process */ void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); /** @@ -6655,9 +6823,45 @@ void arm_rfft_fast_f32( * @param[in] blockSize is the number of samples to process */ void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); /** @@ -6716,21 +6920,20 @@ void arm_rfft_fast_f32( * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. */ + /** * @addtogroup BilinearInterpolate * @{ */ - /** - * * @brief Floating-point bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate. * @param[in] Y interpolation coordinate. * @return out interpolated value. */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32( const arm_bilinear_interp_instance_f32 * S, float32_t X, float32_t Y) @@ -6789,14 +6992,13 @@ void arm_rfft_fast_f32( /** - * * @brief Q31 bilinear interpolation. * @param[in,out] S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31( arm_bilinear_interp_instance_q31 * S, q31_t X, q31_t Y) @@ -6870,7 +7072,7 @@ void arm_rfft_fast_f32( * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15( arm_bilinear_interp_instance_q15 * S, q31_t X, q31_t Y) @@ -6948,7 +7150,7 @@ void arm_rfft_fast_f32( * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ - CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7( arm_bilinear_interp_instance_q7 * S, q31_t X, q31_t Y) @@ -7046,7 +7248,7 @@ void arm_rfft_fast_f32( #if defined ( __CC_ARM ) /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #if defined( __ARM_ARCH_7EM__ ) #define LOW_OPTIMIZATION_ENTER \ _Pragma ("push") \ _Pragma ("O1") @@ -7055,7 +7257,7 @@ void arm_rfft_fast_f32( #endif /* Exit low optimization region - place directly after end of function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #if defined ( __ARM_ARCH_7EM__ ) #define LOW_OPTIMIZATION_EXIT \ _Pragma ("pop") #else @@ -7083,7 +7285,7 @@ void arm_rfft_fast_f32( #elif defined ( __ICCARM__ ) /* Enter low optimization region - place directly above function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #if defined ( __ARM_ARCH_7EM__ ) #define LOW_OPTIMIZATION_ENTER \ _Pragma ("optimize=low") #else @@ -7094,7 +7296,7 @@ void arm_rfft_fast_f32( #define LOW_OPTIMIZATION_EXIT /* Enter low optimization region - place directly above function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #if defined ( __ARM_ARCH_7EM__ ) #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ _Pragma ("optimize=low") #else @@ -7145,6 +7347,8 @@ void arm_rfft_fast_f32( #elif defined ( __TASKING__ ) +#elif defined ( _MSC_VER ) + #else #error Unknown compiler #endif diff --git a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_armcc.h b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_armcc.h index 093d35b..59f173a 100644 --- a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_armcc.h +++ b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_armcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armcc.h * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V5.0.4 - * @date 10. January 2018 + * @version V5.1.0 + * @date 08. May 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -47,6 +47,10 @@ /* __ARM_ARCH_8M_BASE__ not applicable */ /* __ARM_ARCH_8M_MAIN__ not applicable */ +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif /* CMSIS compiler specific defines */ #ifndef __ASM @@ -100,6 +104,31 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface @@ -337,8 +366,6 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. @@ -372,9 +399,6 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) #endif } -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - /*@} end of CMSIS_Core_RegAccFunctions */ diff --git a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_armclang.h b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_armclang.h index 5c4c20e..e917f35 100644 --- a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_armclang.h +++ b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_armclang.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.0.4 - * @date 10. January 2018 + * @version V5.2.0 + * @date 08. May 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -43,9 +43,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif @@ -110,7 +110,31 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface @@ -237,7 +261,7 @@ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); @@ -252,7 +276,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSP(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); @@ -291,7 +315,7 @@ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); @@ -306,7 +330,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSP(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); @@ -346,7 +370,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); @@ -581,7 +605,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif @@ -603,7 +627,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif @@ -669,7 +693,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif @@ -691,7 +715,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif @@ -742,10 +766,6 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. @@ -770,10 +790,6 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) #define __set_FPSCR(x) ((void)(x)) #endif -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - /*@} end of CMSIS_Core_RegAccFunctions */ @@ -789,9 +805,11 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif @@ -829,14 +847,14 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -#define __ISB() __builtin_arm_isb(0xF); +#define __ISB() __builtin_arm_isb(0xF) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -#define __DSB() __builtin_arm_dsb(0xF); +#define __DSB() __builtin_arm_dsb(0xF) /** @@ -844,7 +862,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -#define __DMB() __builtin_arm_dmb(0xF); +#define __DMB() __builtin_arm_dmb(0xF) /** @@ -916,7 +934,23 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -#define __CLZ (uint8_t)__builtin_clz +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ @@ -1329,532 +1363,65 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) diff --git a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_compiler.h b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_compiler.h index 94212eb..adbf296 100644 --- a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_compiler.h +++ b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_compiler.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_compiler.h * @brief CMSIS compiler generic header file - * @version V5.0.4 - * @date 10. January 2018 + * @version V5.1.0 + * @date 09. October 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -35,9 +35,15 @@ /* - * Arm Compiler 6 (armclang) + * Arm Compiler 6.6 LTM (armclang) */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) #include "cmsis_armclang.h" @@ -115,8 +121,11 @@ #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 #endif @@ -187,6 +196,10 @@ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif /* @@ -255,6 +268,10 @@ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif #else diff --git a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_gcc.h b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_gcc.h index 5d0f07e..3ddcc58 100644 --- a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_gcc.h +++ b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_gcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file - * @version V5.0.3 - * @date 16. January 2018 + * @version V5.2.0 + * @date 08. May 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -113,7 +113,74 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface @@ -246,7 +313,7 @@ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); @@ -261,7 +328,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSP(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); @@ -300,7 +367,7 @@ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); @@ -315,7 +382,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSP(void) */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); @@ -355,7 +422,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); @@ -596,7 +663,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif @@ -617,7 +684,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif @@ -683,7 +750,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif @@ -705,7 +772,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else - register uint32_t result; + uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif @@ -758,9 +825,6 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. @@ -770,7 +834,9 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ return __builtin_arm_get_fpscr(); #else @@ -794,7 +860,9 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ __builtin_arm_set_fpscr(fpscr); #else @@ -805,10 +873,6 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) #endif } -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - /*@} end of CMSIS_Core_RegAccFunctions */ @@ -1011,7 +1075,23 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -#define __CLZ (uint8_t)__builtin_clz +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ diff --git a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_iccarm.h b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_iccarm.h index edcaee3..12d68fd 100644 --- a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_iccarm.h +++ b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_iccarm.h @@ -1,13 +1,14 @@ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.0.5 - * @date 10. January 2018 + * @version V5.1.0 + * @date 08. May 2019 ******************************************************************************/ //------------------------------------------------------------------------------ // -// Copyright (c) 2017-2018 IAR Systems +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. @@ -110,6 +111,10 @@ #define __ASM __asm #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + #ifndef __INLINE #define __INLINE inline #endif @@ -150,7 +155,12 @@ #endif #ifndef __RESTRICT - #define __RESTRICT restrict + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif #endif #ifndef __STATIC_INLINE @@ -234,6 +244,25 @@ __packed struct __iar_u32 { uint32_t v; }; #endif #endif +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif #ifndef __ICCARM_INTRINSICS_VERSION__ #define __ICCARM_INTRINSICS_VERSION__ 0 @@ -340,8 +369,17 @@ __packed struct __iar_u32 { uint32_t v; }; #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) - #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) - #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) @@ -716,12 +754,25 @@ __packed struct __iar_u32 { uint32_t v; }; __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) { uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif return res; } + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif } __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) @@ -826,78 +877,78 @@ __packed struct __iar_u32 { uint32_t v; }; __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t res; - __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t res; - __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) { uint32_t res; - __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return res; } __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) { - __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) { - __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) { - __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t res; - __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t res; - __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t res; - __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return res; } __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t res; - __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t res; - __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t res; - __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } diff --git a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_version.h b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_version.h index 660f612..f2e2746 100644 --- a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_version.h +++ b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/cmsis_version.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_version.h * @brief CMSIS Core(M) Version definitions - * @version V5.0.2 - * @date 19. April 2017 + * @version V5.0.3 + * @date 24. June 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -33,7 +33,7 @@ /* CMSIS Version definitions */ #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ #endif diff --git a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/core_cm4.h b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/core_cm4.h index a11a381..12c023b 100644 --- a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/core_cm4.h +++ b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/core_cm4.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 08. January 2018 + * @version V5.1.0 + * @date 13. March 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM4 definitions */ #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ @@ -86,7 +86,7 @@ #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP + #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else @@ -408,7 +408,7 @@ typedef struct __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; + uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ @@ -822,10 +822,7 @@ typedef struct __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ @@ -876,18 +873,6 @@ typedef struct #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ @@ -1060,7 +1045,7 @@ typedef struct */ typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ @@ -1071,7 +1056,7 @@ typedef struct __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; @@ -1087,11 +1072,8 @@ typedef struct } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -1123,13 +1105,13 @@ typedef struct /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ @@ -1144,18 +1126,21 @@ typedef struct #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ @@ -1170,12 +1155,15 @@ typedef struct #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ @@ -1197,12 +1185,12 @@ typedef struct #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1321,6 +1309,7 @@ typedef struct __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ @@ -1406,6 +1395,11 @@ typedef struct #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + /*@} end of group CMSIS_FPU */ @@ -1622,7 +1616,7 @@ typedef struct #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else @@ -1633,6 +1627,14 @@ typedef struct #define NVIC_USER_IRQ_OFFSET 16 +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + /** \brief Set Priority Grouping @@ -1678,7 +1680,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -1901,8 +1905,9 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ } @@ -1916,8 +1921,8 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } @@ -1925,7 +1930,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void __NVIC_SystemReset(void) +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ @@ -1942,6 +1947,7 @@ __STATIC_INLINE void __NVIC_SystemReset(void) /*@} end of CMSIS_Core_NVICFunctions */ + /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) diff --git a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/mpu_armv7.h b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/mpu_armv7.h index aa180c9..66ef59b 100644 --- a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/mpu_armv7.h +++ b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Include/mpu_armv7.h @@ -1,11 +1,11 @@ /****************************************************************************** * @file mpu_armv7.h * @brief CMSIS MPU API for Armv7-M MPU - * @version V5.0.4 - * @date 10. January 2018 + * @version V5.1.0 + * @date 08. March 2019 ******************************************************************************/ /* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -31,41 +31,41 @@ #ifndef ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H -#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) -#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) -#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) -#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) -#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) -#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) -#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) -#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) -#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) -#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) -#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) -#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) -#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) -#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) -#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) -#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) -#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) -#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) -#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) -#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) -#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) -#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) -#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) -#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) -#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) -#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) -#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) -#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) - -#define ARM_MPU_AP_NONE 0U -#define ARM_MPU_AP_PRIV 1U -#define ARM_MPU_AP_URO 2U -#define ARM_MPU_AP_FULL 3U -#define ARM_MPU_AP_PRO 5U -#define ARM_MPU_AP_RO 6U +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access /** MPU Region Base Address Register Value * @@ -77,6 +77,37 @@ ((Region) & MPU_RBAR_REGION_Msk) | \ (MPU_RBAR_VALID_Msk)) +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + /** * MPU Region Attribute and Size Register Value * @@ -90,15 +121,60 @@ * \param Size Region size of the region to be configured, for example 4K, 8K. */ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ - ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ - (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ - (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ - (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ - (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ - (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ - (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ - (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ - (MPU_RASR_ENABLE_Msk)) + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U /** @@ -114,20 +190,19 @@ typedef struct { */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { - __DSB(); - __ISB(); MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif + __DSB(); + __ISB(); } /** Disable the MPU. */ __STATIC_INLINE void ARM_MPU_Disable(void) { - __DSB(); - __ISB(); + __DMB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif @@ -170,7 +245,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r * \param src Source data is copied from. * \param len Amount of data words to be copied. */ -__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; for (i = 0U; i < len; ++i) @@ -187,11 +262,11 @@ __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; while (cnt > MPU_TYPE_RALIASES) { - orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); table += MPU_TYPE_RALIASES; cnt -= MPU_TYPE_RALIASES; } - orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); } #endif diff --git a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/arm_cortexM4l_math.lib b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/arm_cortexM4l_math.lib index 593d42f..49930a0 100644 Binary files a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/arm_cortexM4l_math.lib and b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/arm_cortexM4l_math.lib differ diff --git a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/arm_cortexM4lf_math.lib b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/arm_cortexM4lf_math.lib index 5e8d842..fc5cd80 100644 Binary files a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/arm_cortexM4lf_math.lib and b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/arm_cortexM4lf_math.lib differ diff --git a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/iar_cortexM4l_math.a b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/iar_cortexM4l_math.a index 805e7ea..8fc7b37 100644 Binary files a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/iar_cortexM4l_math.a and b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/iar_cortexM4l_math.a differ diff --git a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/iar_cortexM4lf_math.a b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/iar_cortexM4lf_math.a index 2260b2e..f3e0bb5 100644 Binary files a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/iar_cortexM4lf_math.a and b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/iar_cortexM4lf_math.a differ diff --git a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/libarm_cortexM4l_math.a b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/libarm_cortexM4l_math.a index ca10192..3084c44 100644 Binary files a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/libarm_cortexM4l_math.a and b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/libarm_cortexM4l_math.a differ diff --git a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/libarm_cortexM4lf_math.a b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/libarm_cortexM4lf_math.a index d8c3658..66efc87 100644 Binary files a/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/libarm_cortexM4lf_math.a and b/cores/arduino/am_sdk_ap3/CMSIS/ARM/Lib/ARM/libarm_cortexM4lf_math.a differ diff --git a/cores/arduino/am_sdk_ap3/CMSIS/AmbiqMicro/Include/apollo3c.h b/cores/arduino/am_sdk_ap3/CMSIS/AmbiqMicro/Include/apollo3c.h deleted file mode 100644 index 003017b..0000000 --- a/cores/arduino/am_sdk_ap3/CMSIS/AmbiqMicro/Include/apollo3c.h +++ /dev/null @@ -1,26576 +0,0 @@ -/* - * Copyright (c) 2019, Ambiq Micro - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * Third party software included in this distribution is subject to the - * additional license terms as defined in the /docs/licenses directory. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * @file apollo3c.h - * @brief CMSIS HeaderFile - * @version 1.0 - * @date 20. May 2019 - * @note Generated by SVDConv V3.3.18 on Monday, 20.05.2019 15:44:40 - * from File './apollo3c.svd', - * last modified on Monday, 20.05.2019 20:44:40 - */ - - - -/** @addtogroup Ambiq Micro - * @{ - */ - - -/** @addtogroup apollo3c - * @{ - */ - - -#ifndef APOLLO3C_H -#define APOLLO3C_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ - -typedef enum { -/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ - Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation - and No Match */ - BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ - PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ - SysTick_IRQn = -1, /*!< -1 System Tick Timer */ -/* ========================================== apollo3c Specific Interrupt Numbers ========================================== */ - BROWNOUT_IRQn = 0, /*!< 0 BROWNOUT */ - WDT_IRQn = 1, /*!< 1 WDT */ - RTC_IRQn = 2, /*!< 2 RTC */ - VCOMP_IRQn = 3, /*!< 3 VCOMP */ - IOSLAVE_IRQn = 4, /*!< 4 IOSLAVE */ - IOSLAVEACC_IRQn = 5, /*!< 5 IOSLAVEACC */ - IOMSTR0_IRQn = 6, /*!< 6 IOMSTR0 */ - IOMSTR1_IRQn = 7, /*!< 7 IOMSTR1 */ - IOMSTR2_IRQn = 8, /*!< 8 IOMSTR2 */ - IOMSTR3_IRQn = 9, /*!< 9 IOMSTR3 */ - IOMSTR4_IRQn = 10, /*!< 10 IOMSTR4 */ - IOMSTR5_IRQn = 11, /*!< 11 IOMSTR5 */ - BLE_IRQn = 12, /*!< 12 BLE */ - GPIO_IRQn = 13, /*!< 13 GPIO */ - CTIMER_IRQn = 14, /*!< 14 CTIMER */ - UART0_IRQn = 15, /*!< 15 UART0 */ - UART1_IRQn = 16, /*!< 16 UART1 */ - SCARD_IRQn = 17, /*!< 17 SCARD */ - ADC_IRQn = 18, /*!< 18 ADC */ - PDM_IRQn = 19, /*!< 19 PDM */ - MSPI0_IRQn = 20, /*!< 20 MSPI0 */ - STIMER_IRQn = 22, /*!< 22 STIMER */ - STIMER_CMPR0_IRQn = 23, /*!< 23 STIMER_CMPR0 */ - STIMER_CMPR1_IRQn = 24, /*!< 24 STIMER_CMPR1 */ - STIMER_CMPR2_IRQn = 25, /*!< 25 STIMER_CMPR2 */ - STIMER_CMPR3_IRQn = 26, /*!< 26 STIMER_CMPR3 */ - STIMER_CMPR4_IRQn = 27, /*!< 27 STIMER_CMPR4 */ - STIMER_CMPR5_IRQn = 28, /*!< 28 STIMER_CMPR5 */ - STIMER_CMPR6_IRQn = 29, /*!< 29 STIMER_CMPR6 */ - STIMER_CMPR7_IRQn = 30, /*!< 30 STIMER_CMPR7 */ - CLKGEN_IRQn = 31, /*!< 31 CLKGEN */ - MSPI1_IRQn = 32, /*!< 32 MSPI1 */ - MSPI2_IRQn = 33 /*!< 33 MSPI2 */ -} IRQn_Type; - - - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ -#define __CM4_REV 0x0100U /*!< CM4 Core Revision */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ - - -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ -#include "system_apollo3c.h" /*!< apollo3c System */ - -#ifndef __IM /*!< Fallback for older CMSIS versions */ - #define __IM __I -#endif -#ifndef __OM /*!< Fallback for older CMSIS versions */ - #define __OM __O -#endif -#ifndef __IOM /*!< Fallback for older CMSIS versions */ - #define __IOM __IO -#endif - - -/* ======================================== Start of section using anonymous unions ======================================== */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" - #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" - #pragma clang diagnostic ignored "-Wnested-anon-types" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ - - - -/* =========================================================================================================================== */ -/* ================ ADC ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Analog Digital Converter Control (ADC) - */ - -typedef struct { /*!< (@ 0x50010000) ADC Structure */ - - union { - __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ - - struct { - __IOM uint32_t ADCEN : 1; /*!< [0..0] This bit enables the ADC module. While the ADC is enabled, - the ADCCFG and SLOT Configuration regsiter settings must - remain stable and unchanged. All configuration register - settings, slot configuration settings and window comparison - settings should be written prior to setting the ADCEN bit - to '1'. */ - __IM uint32_t : 1; - __IOM uint32_t RPTEN : 1; /*!< [2..2] This bit enables Repeating Scan Mode. */ - __IOM uint32_t LPMODE : 1; /*!< [3..3] Select power mode to enter between active scans. */ - __IOM uint32_t CKMODE : 1; /*!< [4..4] Clock mode register */ - __IM uint32_t : 3; - __IOM uint32_t REFSEL : 2; /*!< [9..8] Select the ADC reference voltage. */ - __IM uint32_t : 2; - __IOM uint32_t DFIFORDEN : 1; /*!< [12..12] Destructive FIFO Read Enable. Setting this will enable - FIFO pop upon reading the FIFOPR register. */ - __IM uint32_t : 3; - __IOM uint32_t TRIGSEL : 3; /*!< [18..16] Select the ADC trigger source. */ - __IOM uint32_t TRIGPOL : 1; /*!< [19..19] This bit selects the ADC trigger polarity for external - off chip triggers. */ - __IM uint32_t : 4; - __IOM uint32_t CLKSEL : 2; /*!< [25..24] Select the source and frequency for the ADC clock. - All values not enumerated below are undefined. */ - } CFG_b; - } ; - - union { - __IOM uint32_t STAT; /*!< (@ 0x00000004) ADC Power Status */ - - struct { - __IOM uint32_t PWDSTAT : 1; /*!< [0..0] Indicates the power-status of the ADC. */ - } STAT_b; - } ; - - union { - __IOM uint32_t SWT; /*!< (@ 0x00000008) Software trigger */ - - struct { - __IOM uint32_t SWT : 8; /*!< [7..0] Writing 0x37 to this register generates a software trigger. */ - } SWT_b; - } ; - - union { - __IOM uint32_t SL0CFG; /*!< (@ 0x0000000C) Slot 0 Configuration Register */ - - struct { - __IOM uint32_t SLEN0 : 1; /*!< [0..0] This bit enables slot 0 for ADC conversions. */ - __IOM uint32_t WCEN0 : 1; /*!< [1..1] This bit enables the window compare function for slot - 0. */ - __IM uint32_t : 6; - __IOM uint32_t CHSEL0 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ - __IM uint32_t : 4; - __IOM uint32_t PRMODE0 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ - __IM uint32_t : 6; - __IOM uint32_t ADSEL0 : 3; /*!< [26..24] Select the number of measurements to average in the - accumulate divide module for this slot. */ - } SL0CFG_b; - } ; - - union { - __IOM uint32_t SL1CFG; /*!< (@ 0x00000010) Slot 1 Configuration Register */ - - struct { - __IOM uint32_t SLEN1 : 1; /*!< [0..0] This bit enables slot 1 for ADC conversions. */ - __IOM uint32_t WCEN1 : 1; /*!< [1..1] This bit enables the window compare function for slot - 1. */ - __IM uint32_t : 6; - __IOM uint32_t CHSEL1 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ - __IM uint32_t : 4; - __IOM uint32_t PRMODE1 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ - __IM uint32_t : 6; - __IOM uint32_t ADSEL1 : 3; /*!< [26..24] Select the number of measurements to average in the - accumulate divide module for this slot. */ - } SL1CFG_b; - } ; - - union { - __IOM uint32_t SL2CFG; /*!< (@ 0x00000014) Slot 2 Configuration Register */ - - struct { - __IOM uint32_t SLEN2 : 1; /*!< [0..0] This bit enables slot 2 for ADC conversions. */ - __IOM uint32_t WCEN2 : 1; /*!< [1..1] This bit enables the window compare function for slot - 2. */ - __IM uint32_t : 6; - __IOM uint32_t CHSEL2 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ - __IM uint32_t : 4; - __IOM uint32_t PRMODE2 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ - __IM uint32_t : 6; - __IOM uint32_t ADSEL2 : 3; /*!< [26..24] Select the number of measurements to average in the - accumulate divide module for this slot. */ - } SL2CFG_b; - } ; - - union { - __IOM uint32_t SL3CFG; /*!< (@ 0x00000018) Slot 3 Configuration Register */ - - struct { - __IOM uint32_t SLEN3 : 1; /*!< [0..0] This bit enables slot 3 for ADC conversions. */ - __IOM uint32_t WCEN3 : 1; /*!< [1..1] This bit enables the window compare function for slot - 3. */ - __IM uint32_t : 6; - __IOM uint32_t CHSEL3 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ - __IM uint32_t : 4; - __IOM uint32_t PRMODE3 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ - __IM uint32_t : 6; - __IOM uint32_t ADSEL3 : 3; /*!< [26..24] Select the number of measurements to average in the - accumulate divide module for this slot. */ - } SL3CFG_b; - } ; - - union { - __IOM uint32_t SL4CFG; /*!< (@ 0x0000001C) Slot 4 Configuration Register */ - - struct { - __IOM uint32_t SLEN4 : 1; /*!< [0..0] This bit enables slot 4 for ADC conversions. */ - __IOM uint32_t WCEN4 : 1; /*!< [1..1] This bit enables the window compare function for slot - 4. */ - __IM uint32_t : 6; - __IOM uint32_t CHSEL4 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ - __IM uint32_t : 4; - __IOM uint32_t PRMODE4 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ - __IM uint32_t : 6; - __IOM uint32_t ADSEL4 : 3; /*!< [26..24] Select the number of measurements to average in the - accumulate divide module for this slot. */ - } SL4CFG_b; - } ; - - union { - __IOM uint32_t SL5CFG; /*!< (@ 0x00000020) Slot 5 Configuration Register */ - - struct { - __IOM uint32_t SLEN5 : 1; /*!< [0..0] This bit enables slot 5 for ADC conversions. */ - __IOM uint32_t WCEN5 : 1; /*!< [1..1] This bit enables the window compare function for slot - 5. */ - __IM uint32_t : 6; - __IOM uint32_t CHSEL5 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ - __IM uint32_t : 4; - __IOM uint32_t PRMODE5 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ - __IM uint32_t : 6; - __IOM uint32_t ADSEL5 : 3; /*!< [26..24] Select number of measurements to average in the accumulate - divide module for this slot. */ - } SL5CFG_b; - } ; - - union { - __IOM uint32_t SL6CFG; /*!< (@ 0x00000024) Slot 6 Configuration Register */ - - struct { - __IOM uint32_t SLEN6 : 1; /*!< [0..0] This bit enables slot 6 for ADC conversions. */ - __IOM uint32_t WCEN6 : 1; /*!< [1..1] This bit enables the window compare function for slot - 6. */ - __IM uint32_t : 6; - __IOM uint32_t CHSEL6 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ - __IM uint32_t : 4; - __IOM uint32_t PRMODE6 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ - __IM uint32_t : 6; - __IOM uint32_t ADSEL6 : 3; /*!< [26..24] Select the number of measurements to average in the - accumulate divide module for this slot. */ - } SL6CFG_b; - } ; - - union { - __IOM uint32_t SL7CFG; /*!< (@ 0x00000028) Slot 7 Configuration Register */ - - struct { - __IOM uint32_t SLEN7 : 1; /*!< [0..0] This bit enables slot 7 for ADC conversions. */ - __IOM uint32_t WCEN7 : 1; /*!< [1..1] This bit enables the window compare function for slot - 7. */ - __IM uint32_t : 6; - __IOM uint32_t CHSEL7 : 4; /*!< [11..8] Select one of the 14 channel inputs for this slot. */ - __IM uint32_t : 4; - __IOM uint32_t PRMODE7 : 2; /*!< [17..16] Set the Precision Mode For Slot. */ - __IM uint32_t : 6; - __IOM uint32_t ADSEL7 : 3; /*!< [26..24] Select the number of measurements to average in the - accumulate divide module for this slot. */ - } SL7CFG_b; - } ; - - union { - __IOM uint32_t WULIM; /*!< (@ 0x0000002C) Window Comparator Upper Limits Register */ - - struct { - __IOM uint32_t ULIM : 20; /*!< [19..0] Sets the upper limit for the window comparator. */ - } WULIM_b; - } ; - - union { - __IOM uint32_t WLLIM; /*!< (@ 0x00000030) Window Comparator Lower Limits Register */ - - struct { - __IOM uint32_t LLIM : 20; /*!< [19..0] Sets the lower limit for the window comparator. */ - } WLLIM_b; - } ; - - union { - __IOM uint32_t SCWLIM; /*!< (@ 0x00000034) Scale Window Comparator Limits */ - - struct { - __IOM uint32_t SCWLIMEN : 1; /*!< [0..0] Scale the window limits compare values per precision - mode. When set to 0x0 (default), the values in the 20-bit - limits registers will compare directly with the FIFO values - regardless of the precision mode the slot is configured - to. When set to 0x1, the compare values will be divided - by the difference in precision bits while performing the - window limit comparisons. */ - } SCWLIM_b; - } ; - - union { - __IOM uint32_t FIFO; /*!< (@ 0x00000038) FIFO Data and Valid Count Register */ - - struct { - __IOM uint32_t DATA : 20; /*!< [19..0] Oldest data in the FIFO. */ - __IOM uint32_t COUNT : 8; /*!< [27..20] Number of valid entries in the ADC FIFO. */ - __IOM uint32_t SLOTNUM : 3; /*!< [30..28] Slot number associated with this FIFO data. */ - __IOM uint32_t RSVD : 1; /*!< [31..31] RESERVED. */ - } FIFO_b; - } ; - - union { - __IOM uint32_t FIFOPR; /*!< (@ 0x0000003C) FIFO Data and Valid Count Register */ - - struct { - __IOM uint32_t DATA : 20; /*!< [19..0] Oldest data in the FIFO. */ - __IOM uint32_t COUNT : 8; /*!< [27..20] Number of valid entries in the ADC FIFO. */ - __IOM uint32_t SLOTNUMPR : 3; /*!< [30..28] Slot number associated with this FIFO data. */ - __IOM uint32_t RSVDPR : 1; /*!< [31..31] RESERVED. */ - } FIFOPR_b; - } ; - __IM uint32_t RESERVED[112]; - - union { - __IOM uint32_t INTEN; /*!< (@ 0x00000200) ADC Interrupt registers: Enable */ - - struct { - __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ - __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ - __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ - __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ - __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ - __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ - __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */ - __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */ - } INTEN_b; - } ; - - union { - __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) ADC Interrupt registers: Status */ - - struct { - __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ - __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ - __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ - __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ - __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ - __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ - __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */ - __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */ - } INTSTAT_b; - } ; - - union { - __IOM uint32_t INTCLR; /*!< (@ 0x00000208) ADC Interrupt registers: Clear */ - - struct { - __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ - __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ - __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ - __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ - __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ - __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ - __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */ - __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */ - } INTCLR_b; - } ; - - union { - __IOM uint32_t INTSET; /*!< (@ 0x0000020C) ADC Interrupt registers: Set */ - - struct { - __IOM uint32_t CNVCMP : 1; /*!< [0..0] ADC conversion complete interrupt. */ - __IOM uint32_t SCNCMP : 1; /*!< [1..1] ADC scan complete interrupt. */ - __IOM uint32_t FIFOOVR1 : 1; /*!< [2..2] FIFO 75 percent full interrupt. */ - __IOM uint32_t FIFOOVR2 : 1; /*!< [3..3] FIFO 100 percent full interrupt. */ - __IOM uint32_t WCEXC : 1; /*!< [4..4] Window comparator voltage excursion interrupt. */ - __IOM uint32_t WCINC : 1; /*!< [5..5] Window comparator voltage incursion interrupt. */ - __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Transfer Complete */ - __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Condition */ - } INTSET_b; - } ; - __IM uint32_t RESERVED1[12]; - - union { - __IOM uint32_t DMATRIGEN; /*!< (@ 0x00000240) DMA Trigger Enable Register */ - - struct { - __IOM uint32_t DFIFO75 : 1; /*!< [0..0] Trigger DMA upon FIFO 75 percent Full */ - __IOM uint32_t DFIFOFULL : 1; /*!< [1..1] Trigger DMA upon FIFO 100 percent Full */ - } DMATRIGEN_b; - } ; - - union { - __IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000244) DMA Trigger Status Register */ - - struct { - __IOM uint32_t D75STAT : 1; /*!< [0..0] Triggered DMA from FIFO 75 percent Full */ - __IOM uint32_t DFULLSTAT : 1; /*!< [1..1] Triggered DMA from FIFO 100 percent Full */ - } DMATRIGSTAT_b; - } ; - __IM uint32_t RESERVED2[14]; - - union { - __IOM uint32_t DMACFG; /*!< (@ 0x00000280) DMA Configuration Register */ - - struct { - __IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable */ - __IM uint32_t : 1; - __IOM uint32_t DMADIR : 1; /*!< [2..2] Direction */ - __IM uint32_t : 5; - __IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */ - __IOM uint32_t DMADYNPRI : 1; /*!< [9..9] Enables dynamic priority based on FIFO fullness. When - FIFO is full, priority is automatically set to HIGH. Otherwise, - DMAPRI is used. */ - __IM uint32_t : 6; - __IOM uint32_t DMAHONSTAT : 1; /*!< [16..16] Halt New ADC conversions until DMA Status DMAERR and - DMACPL Cleared. */ - __IOM uint32_t DMAMSK : 1; /*!< [17..17] Mask the FIFOCNT and SLOTNUM when transferring FIFO - contents to memory */ - __IOM uint32_t DPWROFF : 1; /*!< [18..18] Power Off the ADC System upon DMACPL. */ - } DMACFG_b; - } ; - __IM uint32_t RESERVED3; - - union { - __IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000288) DMA Total Transfer Count */ - - struct { - __IM uint32_t : 2; - __IOM uint32_t TOTCOUNT : 16; /*!< [17..2] Total Transfer Count */ - } DMATOTCOUNT_b; - } ; - - union { - __IOM uint32_t DMATARGADDR; /*!< (@ 0x0000028C) DMA Target Address Register */ - - struct { - __IOM uint32_t LTARGADDR : 20; /*!< [19..0] DMA Target Address */ - __IOM uint32_t UTARGADDR : 12; /*!< [31..20] SRAM Target */ - } DMATARGADDR_b; - } ; - - union { - __IOM uint32_t DMASTAT; /*!< (@ 0x00000290) DMA Status Register */ - - struct { - __IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress */ - __IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete */ - __IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error */ - } DMASTAT_b; - } ; -} ADC_Type; /*!< Size = 660 (0x294) */ - - - -/* =========================================================================================================================== */ -/* ================ APBDMA ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief APB DMA Register Interfaces (APBDMA) - */ - -typedef struct { /*!< (@ 0x40011000) APBDMA Structure */ - - union { - __IOM uint32_t BBVALUE; /*!< (@ 0x00000000) Control Register */ - - struct { - __IOM uint32_t DATAOUT : 8; /*!< [7..0] Data Output Values */ - __IM uint32_t : 8; - __IOM uint32_t PIN : 8; /*!< [23..16] PIO values */ - } BBVALUE_b; - } ; - - union { - __IOM uint32_t BBSETCLEAR; /*!< (@ 0x00000004) Set/Clear Register */ - - struct { - __IOM uint32_t SET : 8; /*!< [7..0] Write 1 to Set PIO value (set hier priority than clear - if both bit set) */ - __IM uint32_t : 8; - __IOM uint32_t CLEAR : 8; /*!< [23..16] Write 1 to Clear PIO value */ - } BBSETCLEAR_b; - } ; - - union { - __IOM uint32_t BBINPUT; /*!< (@ 0x00000008) PIO Input Values */ - - struct { - __IOM uint32_t DATAIN : 8; /*!< [7..0] PIO values */ - } BBINPUT_b; - } ; - __IM uint32_t RESERVED[5]; - - union { - __IOM uint32_t DEBUGDATA; /*!< (@ 0x00000020) PIO Input Values */ - - struct { - __IOM uint32_t DEBUGDATA : 32; /*!< [31..0] Debug Data */ - } DEBUGDATA_b; - } ; - __IM uint32_t RESERVED1[7]; - - union { - __IOM uint32_t DEBUG; /*!< (@ 0x00000040) PIO Input Values */ - - struct { - __IOM uint32_t DEBUGEN : 4; /*!< [3..0] Debug Enable */ - } DEBUG_b; - } ; -} APBDMA_Type; /*!< Size = 68 (0x44) */ - - - -/* =========================================================================================================================== */ -/* ================ BLEIF ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief BLE Interface (BLEIF) - */ - -typedef struct { /*!< (@ 0x5000C000) BLEIF Structure */ - - union { - __IOM uint32_t FIFO; /*!< (@ 0x00000000) FIFO Access Port */ - - struct { - __IOM uint32_t FIFO : 32; /*!< [31..0] FIFO direct access. Only locations 0 - 3F will return - valid information. */ - } FIFO_b; - } ; - __IM uint32_t RESERVED[63]; - - union { - __IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) FIFO size and remaining slots open values */ - - struct { - __IOM uint32_t FIFO0SIZ : 8; /*!< [7..0] The number of valid data bytes currently in the FIFO - 0 (written by MCU, read by interface) */ - __IOM uint32_t FIFO0REM : 8; /*!< [15..8] The number of remaining data bytes slots currently in - FIFO 0 (written by MCU, read by interface) */ - __IOM uint32_t FIFO1SIZ : 8; /*!< [23..16] The number of valid data bytes currently in FIFO 1 - (written by interface, read by MCU) */ - __IOM uint32_t FIFO1REM : 8; /*!< [31..24] The number of remaining data bytes slots currently - in FIFO 1 (written by interface, read by MCU) */ - } FIFOPTR_b; - } ; - - union { - __IOM uint32_t FIFOTHR; /*!< (@ 0x00000104) FIFO Threshold Configuration */ - - struct { - __IOM uint32_t FIFORTHR : 6; /*!< [5..0] FIFO read threshold in bytes. A value of 0 will disable - the read FIFO level from activating the threshold interrupt. - If this field is non-zero, it will trigger a threshold - interrupt when the read fifo contains FIFORTHR valid bytes - of data, as indicated by the FIFO1SIZ field. This is intended - to signal when a data transfer of FIFORTHR bytes can be - done from the IOM module to the host via the read fifo - to support large IOM read operations. */ - __IM uint32_t : 2; - __IOM uint32_t FIFOWTHR : 6; /*!< [13..8] FIFO write threshold in bytes. A value of 0 will disable - the write FIFO level from activating the threshold interrupt. - If this field is non-zero, it will trigger a threshold - interrupt when the write fifo contains FIFOWTHR free bytes, - as indicated by the FIFO0REM field. This is intended to - signal when a transfer of FIFOWTHR bytes can be done from - the host to the IOM write fifo to support large IOM write - operations. */ - } FIFOTHR_b; - } ; - - union { - __IOM uint32_t FIFOPOP; /*!< (@ 0x00000108) FIFO POP register */ - - struct { - __IOM uint32_t FIFODOUT : 32; /*!< [31..0] This register will return the read data indicated by - the current read pointer on reads. If the POPWR control - bit in the FIFOCTRL register is reset (0), the fifo read - pointer will be advanced by one word as a result of the - read.If the POPWR bit is set (1), the fifo read pointer - will only be advanced after a write operation to this register. - The write data is ignored for this register.If less than - a even word multiple is available, and the command is completed, - the module will return the word containing */ - } FIFOPOP_b; - } ; - - union { - __IOM uint32_t FIFOPUSH; /*!< (@ 0x0000010C) FIFO PUSH register */ - - struct { - __IOM uint32_t FIFODIN : 32; /*!< [31..0] This register is used to write the FIFORAM in FIFO mode - and will cause a push event to occur to the next open slot - within the FIFORAM. Writing to this register will cause - the write point to increment by 1 word(4 bytes). */ - } FIFOPUSH_b; - } ; - - union { - __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000110) FIFO Control Register */ - - struct { - __IOM uint32_t POPWR : 1; /*!< [0..0] Selects the mode in which 'pop' events are done for the - fifo read operations. A value of '1' will prevent a pop - event on a read operation, and will require a write to - the FIFOPOP register to create a pop event.A value of '0' - in this register will allow a pop event to occur on the - read of the FIFOPOP register, and may cause inadvertant - fifo pops when used in a debugging mode. */ - __IOM uint32_t FIFORSTN : 1; /*!< [1..1] Active low manual reset of the fifo. Write to 0 to reset - fifo, and then write to 1 to remove the reset. */ - } FIFOCTRL_b; - } ; - - union { - __IOM uint32_t FIFOLOC; /*!< (@ 0x00000114) FIFO Pointers */ - - struct { - __IOM uint32_t FIFOWPTR : 4; /*!< [3..0] Current FIFO write pointer. Value is the index into the - outgoing FIFO (FIFO0), which is used during write operations - to external devices. */ - __IM uint32_t : 4; - __IOM uint32_t FIFORPTR : 4; /*!< [11..8] Current FIFO read pointer. Used to index into the incoming - FIFO (FIFO1), which is used to store read data returned - from external devices during a read operation. */ - } FIFOLOC_b; - } ; - __IM uint32_t RESERVED1[58]; - - union { - __IOM uint32_t CLKCFG; /*!< (@ 0x00000200) I/O Clock Configuration */ - - struct { - __IOM uint32_t IOCLKEN : 1; /*!< [0..0] Enable for the interface clock. Must be enabled prior - to executing any IO operations. */ - __IM uint32_t : 7; - __IOM uint32_t FSEL : 3; /*!< [10..8] Select the input clock frequency. */ - __IOM uint32_t CLK32KEN : 1; /*!< [11..11] Enable for the 32Khz clock to the BLE module */ - __IOM uint32_t DIV3 : 1; /*!< [12..12] Enable of the divide by 3 of the source IOCLK. */ - } CLKCFG_b; - } ; - __IM uint32_t RESERVED2[2]; - - union { - __IOM uint32_t CMD; /*!< (@ 0x0000020C) Command and offset Register */ - - struct { - __IOM uint32_t CMD : 5; /*!< [4..0] Command for submodule. */ - __IOM uint32_t OFFSETCNT : 2; /*!< [6..5] Number of offset bytes to use for the command - 0, 1, - 2, 3 are valid selections. The second (byte 1) and third - byte (byte 2) are read from the OFFSETHI register, and - the low order byte is pulled from this register in the - OFFSETLO field.Offset bytes are transmitted highest byte - first. EG if offsetcnt == 3, OFFSETHI[15:8] will be transmitted - first, then OFFSETHI[7:0] then OFFSETLO.If offsetcnt == - 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO.If - offsetcnt == 1, only OFFSETLO will be transmitted. */ - __IOM uint32_t CONT : 1; /*!< [7..7] Contine to hold the bus after the current transaction - if set to a 1 with a new command issued. */ - __IOM uint32_t TSIZE : 12; /*!< [19..8] Defines the transaction size in bytes. The offset transfer - is not included in this size. */ - __IOM uint32_t CMDSEL : 2; /*!< [21..20] Command Specific selection information */ - __IM uint32_t : 2; - __IOM uint32_t OFFSETLO : 8; /*!< [31..24] This register holds the low order byte of offset to - be used in the transaction. The number of offset bytes - to use is set with bits 1:0 of the command. Offset bytes - are transferred starting from the highest byte first. */ - } CMD_b; - } ; - - union { - __IOM uint32_t CMDRPT; /*!< (@ 0x00000210) Command Repeat Register */ - - struct { - __IOM uint32_t CMDRPT : 5; /*!< [4..0] Count of number of times to repeat the next command. */ - } CMDRPT_b; - } ; - - union { - __IOM uint32_t OFFSETHI; /*!< (@ 0x00000214) High order offset bytes */ - - struct { - __IOM uint32_t OFFSETHI : 16; /*!< [15..0] Holds the high order bytes of the 2 or 3 byte offset - phase of a transaction. */ - } OFFSETHI_b; - } ; - - union { - __IOM uint32_t CMDSTAT; /*!< (@ 0x00000218) Command status */ - - struct { - __IOM uint32_t CCMD : 5; /*!< [4..0] current command that is being executed */ - __IOM uint32_t CMDSTAT : 3; /*!< [7..5] The current status of the command execution. */ - __IOM uint32_t CTSIZE : 12; /*!< [19..8] The current number of bytes still to be transferred - with this command. This field will count down to zero. */ - } CMDSTAT_b; - } ; - __IM uint32_t RESERVED3; - - union { - __IOM uint32_t INTEN; /*!< (@ 0x00000220) IO Master Interrupts: Enable */ - - struct { - __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current - operation has completed. For repeated commands, this will - only be asserted when the final repeated command is completed. */ - __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted - when the number of free bytes in the write FIFO equals - or exceeds the WTHR field.For read operations, asserted - when the number of valid bytes in the read FIFO equals - of exceeds the value set in the RTHR field. */ - __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation - is done to a empty read FIFO. */ - __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software - tries to write to a full fifo. The current operation does - not stop. */ - __IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in - the B2M_STATE signal from the BLE Core. */ - __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is - a overflow or underflow event */ - __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is - written when an active command is in progress. */ - __IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal - from the BLE Core is asserted, indicating the availability - of read data from the BLE Core. */ - __IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS - signal from the BLE Core is asserted, indicating that SPI - writes can be done to the BLE Core.Transfers to the BLE - Core should only be done when this signal is high. */ - __IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed - and the DMA submodule is returned into the idle state */ - __IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the - DMA command. The DMA error could occur when the memory - access specified in the DMA operation is not available - or incorrectly specified. */ - __IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled - in the PAUSEEN register. The interrupt is posted when the - event is enabled within the PAUSEEN register, the mask - is active in the CQIRQMASK field and the event occurs. */ - __IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write - with the register address bit 0 set to 1. The low address - bits in the CQ address fields are unused and bit 0 can - be used to trigger an interrupt to indicate when this register - write is performed by the CQ operation. */ - __IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error - occurs, the system will stop processing and halt operations - to allow software to take recovery actions */ - __IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the - sleep state */ - __IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned - into the active state Revision B: Falling BLE Core IRQ - signal. Asserted when the BLE_IRQ signal from the BLE Core - is de-asserted (1 -> 0) */ - __IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned - into shutdown state Revision B: Falling BLE Core Status - signal. Asserted when the BLE_STATUS signal from the BLE - Core is de-asserted (1 -> 0) */ - } INTEN_b; - } ; - - union { - __IOM uint32_t INTSTAT; /*!< (@ 0x00000224) IO Master Interrupts: Status */ - - struct { - __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current - operation has completed. For repeated commands, this will - only be asserted when the final repeated command is completed. */ - __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted - when the number of free bytes in the write FIFO equals - or exceeds the WTHR field.For read operations, asserted - when the number of valid bytes in the read FIFO equals - of exceeds the value set in the RTHR field. */ - __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation - is done to a empty read FIFO. */ - __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software - tries to write to a full fifo. The current operation does - not stop. */ - __IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in - the B2M_STATE signal from the BLE Core. */ - __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is - a overflow or underflow event */ - __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is - written when an active command is in progress. */ - __IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal - from the BLE Core is asserted, indicating the availability - of read data from the BLE Core. */ - __IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS - signal from the BLE Core is asserted, indicating that SPI - writes can be done to the BLE Core.Transfers to the BLE - Core should only be done when this signal is high. */ - __IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed - and the DMA submodule is returned into the idle state */ - __IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the - DMA command. The DMA error could occur when the memory - access specified in the DMA operation is not available - or incorrectly specified. */ - __IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled - in the PAUSEEN register. The interrupt is posted when the - event is enabled within the PAUSEEN register, the mask - is active in the CQIRQMASK field and the event occurs. */ - __IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write - with the register address bit 0 set to 1. The low address - bits in the CQ address fields are unused and bit 0 can - be used to trigger an interrupt to indicate when this register - write is performed by the CQ operation. */ - __IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error - occurs, the system will stop processing and halt operations - to allow software to take recovery actions */ - __IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the - sleep state */ - __IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned - into the active state Revision B: Falling BLE Core IRQ - signal. Asserted when the BLE_IRQ signal from the BLE Core - is de-asserted (1 -> 0) */ - __IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned - into shutdown state Revision B: Falling BLE Core Status - signal. Asserted when the BLE_STATUS signal from the BLE - Core is de-asserted (1 -> 0) */ - } INTSTAT_b; - } ; - - union { - __IOM uint32_t INTCLR; /*!< (@ 0x00000228) IO Master Interrupts: Clear */ - - struct { - __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current - operation has completed. For repeated commands, this will - only be asserted when the final repeated command is completed. */ - __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted - when the number of free bytes in the write FIFO equals - or exceeds the WTHR field.For read operations, asserted - when the number of valid bytes in the read FIFO equals - of exceeds the value set in the RTHR field. */ - __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation - is done to a empty read FIFO. */ - __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software - tries to write to a full fifo. The current operation does - not stop. */ - __IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in - the B2M_STATE signal from the BLE Core. */ - __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is - a overflow or underflow event */ - __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is - written when an active command is in progress. */ - __IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal - from the BLE Core is asserted, indicating the availability - of read data from the BLE Core. */ - __IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS - signal from the BLE Core is asserted, indicating that SPI - writes can be done to the BLE Core.Transfers to the BLE - Core should only be done when this signal is high. */ - __IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed - and the DMA submodule is returned into the idle state */ - __IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the - DMA command. The DMA error could occur when the memory - access specified in the DMA operation is not available - or incorrectly specified. */ - __IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled - in the PAUSEEN register. The interrupt is posted when the - event is enabled within the PAUSEEN register, the mask - is active in the CQIRQMASK field and the event occurs. */ - __IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write - with the register address bit 0 set to 1. The low address - bits in the CQ address fields are unused and bit 0 can - be used to trigger an interrupt to indicate when this register - write is performed by the CQ operation. */ - __IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error - occurs, the system will stop processing and halt operations - to allow software to take recovery actions */ - __IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the - sleep state */ - __IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned - into the active state Revision B: Falling BLE Core IRQ - signal. Asserted when the BLE_IRQ signal from the BLE Core - is de-asserted (1 -> 0) */ - __IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned - into shutdown state Revision B: Falling BLE Core Status - signal. Asserted when the BLE_STATUS signal from the BLE - Core is de-asserted (1 -> 0) */ - } INTCLR_b; - } ; - - union { - __IOM uint32_t INTSET; /*!< (@ 0x0000022C) IO Master Interrupts: Set */ - - struct { - __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when the current - operation has completed. For repeated commands, this will - only be asserted when the final repeated command is completed. */ - __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted - when the number of free bytes in the write FIFO equals - or exceeds the WTHR field.For read operations, asserted - when the number of valid bytes in the read FIFO equals - of exceeds the value set in the RTHR field. */ - __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation - is done to a empty read FIFO. */ - __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software - tries to write to a full fifo. The current operation does - not stop. */ - __IOM uint32_t B2MST : 1; /*!< [4..4] B2M State change interrupt. Asserted on any change in - the B2M_STATE signal from the BLE Core. */ - __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is - a overflow or underflow event */ - __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is - written when an active command is in progress. */ - __IOM uint32_t BLECIRQ : 1; /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal - from the BLE Core is asserted, indicating the availability - of read data from the BLE Core. */ - __IOM uint32_t BLECSSTAT : 1; /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS - signal from the BLE Core is asserted, indicating that SPI - writes can be done to the BLE Core.Transfers to the BLE - Core should only be done when this signal is high. */ - __IOM uint32_t DCMP : 1; /*!< [9..9] DMA Complete. Processing of the DMA operation has completed - and the DMA submodule is returned into the idle state */ - __IOM uint32_t DERR : 1; /*!< [10..10] DMA Error encountered during the processing of the - DMA command. The DMA error could occur when the memory - access specified in the DMA operation is not available - or incorrectly specified. */ - __IOM uint32_t CQPAUSED : 1; /*!< [11..11] Command queue is paused due to an active event enabled - in the PAUSEEN register. The interrupt is posted when the - event is enabled within the PAUSEEN register, the mask - is active in the CQIRQMASK field and the event occurs. */ - __IOM uint32_t CQUPD : 1; /*!< [12..12] Command queue write operation executed a register write - with the register address bit 0 set to 1. The low address - bits in the CQ address fields are unused and bit 0 can - be used to trigger an interrupt to indicate when this register - write is performed by the CQ operation. */ - __IOM uint32_t CQERR : 1; /*!< [13..13] Command queue error during processing. When an error - occurs, the system will stop processing and halt operations - to allow software to take recovery actions */ - __IOM uint32_t B2MSLEEP : 1; /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the - sleep state */ - __IOM uint32_t B2MACTIVE : 1; /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned - into the active state Revision B: Falling BLE Core IRQ - signal. Asserted when the BLE_IRQ signal from the BLE Core - is de-asserted (1 -> 0) */ - __IOM uint32_t B2MSHUTDN : 1; /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned - into shutdown state Revision B: Falling BLE Core Status - signal. Asserted when the BLE_STATUS signal from the BLE - Core is de-asserted (1 -> 0) */ - } INTSET_b; - } ; - - union { - __IOM uint32_t DMATRIGEN; /*!< (@ 0x00000230) DMA Trigger Enable Register */ - - struct { - __IOM uint32_t DCMDCMPEN : 1; /*!< [0..0] Trigger DMA upon command complete. Enables the trigger - of the DMA when a command is completed. When this event - is triggered, the number of words transferred will be the - lesser of the remaining TOTCOUNT bytes, or the number of - bytes in the FIFO when the command completed. If this is - disabled, and the number of bytes in the FIFO is equal - or greater than the TOTCOUNT bytes, a transfer of TOTCOUNT - bytes will be done to ensure read data is stored when the - DMA is completed. */ - __IOM uint32_t DTHREN : 1; /*!< [1..1] Trigger DMA upon THR level reached. For M2P DMA operations - (IOM writes), the trigger will assert when the write FIFO - has (WTHR/4) number of words free in the write FIFO, and - will transfer (WTHR/4) number of wordsor, if the number - of words left to transfer is less than the WTHR value, - will transfer the remaining byte count.For P2M DMA operations, - the trigger will assert when the read FIFO has (RTHR/4) - words available in the read FIFO, and will transfer (RTHR/4) - words to SRAM. This trigger will NOT asser */ - } DMATRIGEN_b; - } ; - - union { - __IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000234) DMA Trigger Status Register */ - - struct { - __IOM uint32_t DCMDCMP : 1; /*!< [0..0] Triggered DMA from Command complete event. Bit is read - only and can be cleared by disabling the DCMDCMP trigger - enable or by disabling DMA. */ - __IOM uint32_t DTHR : 1; /*!< [1..1] Triggered DMA from THR event. Bit is read only and can - be cleared by disabling the DTHR trigger enable or by disabling - DMA. */ - __IOM uint32_t DTOTCMP : 1; /*!< [2..2] DMA triggered when DCMDCMP = 0, and the amount of data - in the FIFO was enough to complete the DMA operation (greater - than or equal to current TOTCOUNT) when the command completed. - This trigger is default active when the DCMDCMP trigger - isdisabled and there is enough data in the FIFO to complete - the DMA operation. */ - } DMATRIGSTAT_b; - } ; - - union { - __IOM uint32_t DMACFG; /*!< (@ 0x00000238) DMA Configuration Register */ - - struct { - __IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable. Setting this bit to EN will start the DMA - operation. This should be the last DMA related register - set prior to issuing the command */ - __IOM uint32_t DMADIR : 1; /*!< [1..1] Direction */ - __IM uint32_t : 6; - __IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */ - } DMACFG_b; - } ; - - union { - __IOM uint32_t DMATOTCOUNT; /*!< (@ 0x0000023C) DMA Total Transfer Count */ - - struct { - __IOM uint32_t TOTCOUNT : 12; /*!< [11..0] Triggered DMA from Command complete event occured. Bit - is read only and can be cleared by disabling the DTHR trigger - enable or by disabling DMA. */ - } DMATOTCOUNT_b; - } ; - - union { - __IOM uint32_t DMATARGADDR; /*!< (@ 0x00000240) DMA Target Address Register */ - - struct { - __IOM uint32_t TARGADDR : 21; /*!< [20..0] Bits [19:0] of the target byte address for source of - DMA (either read or write). The address can be any byte - alignment, and does not have to be word aligned. In cases - of non-word aligned addresses, the DMA logic will take - care for ensuring only the target bytes are read/written. */ - __IM uint32_t : 7; - __IOM uint32_t TARGADDR28 : 1; /*!< [28..28] Bit 28 of the target byte address for source of DMA - (either read or write). In cases of non-word aligned addresses, - the DMA logic will take care for ensuring only the target - bytes are read/written.Setting to '1' will select the SRAM. - Setting to '0' will select the flash */ - } DMATARGADDR_b; - } ; - - union { - __IOM uint32_t DMASTAT; /*!< (@ 0x00000244) DMA Status Register */ - - struct { - __IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that - a DMA transfer is active. The DMA transfer may be waiting - on data, transferring data, or waiting for priority.All - of these will be indicated with a 1. A 0 will indicate - that the DMA is fully complete and no further transactions - will be done. This bit is read only. */ - __IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA - operation. This bit can be cleared by writing to 0. */ - __IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error. This active high bit signals that an error - was encountered during the DMA operation. */ - } DMASTAT_b; - } ; - - union { - __IOM uint32_t CQCFG; /*!< (@ 0x00000248) Command Queue Configuration Register */ - - struct { - __IOM uint32_t CQEN : 1; /*!< [0..0] Command queue enable. When set, will enable the processing - of the command queue and fetches of address/data pairs - will proceed from the word address within the CQADDR register. - Can be disabledusing a CQ executed write to this bit as - well. */ - __IOM uint32_t CQPRI : 1; /*!< [1..1] Sets the Priority of the command queue dma request. */ - } CQCFG_b; - } ; - - union { - __IOM uint32_t CQADDR; /*!< (@ 0x0000024C) CQ Target Read Address Register */ - - struct { - __IM uint32_t : 2; - __IOM uint32_t CQADDR : 19; /*!< [20..2] Bits 19:2 of target byte address for source of CQ (read - only). The buffer must be aligned on a word boundary */ - __IM uint32_t : 7; - __IOM uint32_t CQADDR28 : 1; /*!< [28..28] Bit 28 of target byte address for source of CQ (read - only). Used to denote Flash (0) or SRAM (1) access */ - } CQADDR_b; - } ; - - union { - __IOM uint32_t CQSTAT; /*!< (@ 0x00000250) Command Queue Status Register */ - - struct { - __IOM uint32_t CQTIP : 1; /*!< [0..0] Command queue Transfer In Progress indicator. 1 will - indicate that a CQ transfer is active and this will remain - active even when paused waiting for external event. */ - __IOM uint32_t CQPAUSED : 1; /*!< [1..1] Command queue operation is currently paused. */ - __IOM uint32_t CQERR : 1; /*!< [2..2] Command queue processing Error. This active high bit - signals that an error was encountered during the CQ operation. */ - } CQSTAT_b; - } ; - - union { - __IOM uint32_t CQFLAGS; /*!< (@ 0x00000254) Command Queue Flag Register */ - - struct { - __IOM uint32_t CQFLAGS : 16; /*!< [15..0] Current flag status (read-only). Bits [7:0] are software - controllable and bits [15:8] are hardware status. */ - __IOM uint32_t CQIRQMASK : 16; /*!< [31..16] Provides for a per-bit mask of the flags used to invoke - an interrupt. A '1' in the bit position will enable the - pause event to trigger the interrupt, if the CQWT_int interrupt - is enabled.Bits definitions are the same as CQPAUSE */ - } CQFLAGS_b; - } ; - - union { - __IOM uint32_t CQSETCLEAR; /*!< (@ 0x00000258) Command Queue Flag Set/Clear Register */ - - struct { - __IOM uint32_t CQFSET : 8; /*!< [7..0] Set CQFlag status bits. Will set to 1 the value of any - SWFLAG with a '1' in the corresponding bit position of - this field */ - __IOM uint32_t CQFTGL : 8; /*!< [15..8] Toggle the indicated bit. Will toggle the value of any - SWFLAG with a '1' in the corresponding bit position of - this field */ - __IOM uint32_t CQFCLR : 8; /*!< [23..16] Clear CQFlag status bits. Will clear to 0 any SWFLAG - with a '1' in the corresponding bit position of this field */ - } CQSETCLEAR_b; - } ; - - union { - __IOM uint32_t CQPAUSEEN; /*!< (@ 0x0000025C) Command Queue Pause Enable Register */ - - struct { - __IOM uint32_t CQPEN : 16; /*!< [15..0] Enables the specified event to pause command processing - when active */ - } CQPAUSEEN_b; - } ; - - union { - __IOM uint32_t CQCURIDX; /*!< (@ 0x00000260) IOM Command Queue current index value . Compared - to the CQENDIDX reg contents to generate - the IDXEQ Pause event for command queue */ - - struct { - __IOM uint32_t CQCURIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQENDIX - register field. If the values match, the IDXEQ pause event - will be activated, which will cause the pausing of command - quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */ - } CQCURIDX_b; - } ; - - union { - __IOM uint32_t CQENDIDX; /*!< (@ 0x00000264) IOM Command Queue current index value . Compared - to the CQCURIDX reg contents to generate - the IDXEQ Pause event for command queue */ - - struct { - __IOM uint32_t CQENDIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQCURIX - register field. If the values match, the IDXEQ pause event - will be activated, which will cause the pausing of command - quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */ - } CQENDIDX_b; - } ; - - union { - __IOM uint32_t STATUS; /*!< (@ 0x00000268) IOM Module Status Register */ - - struct { - __IOM uint32_t ERR : 1; /*!< [0..0] Bit has been deprecated. Please refer to the other error - indicators. This will always return 0. */ - __IOM uint32_t CMDACT : 1; /*!< [1..1] Indicates if the active I/O Command is currently processing - a transaction, or command is complete, but the FIFO pointers - are still syncronizing internally. This bit will go high - atthe start of the transaction, and will go low when the - command is complete, and the data and pointers within the - FIFO have been syncronized. */ - __IOM uint32_t IDLEST : 1; /*!< [2..2] indicates if the active I/O state machine is IDLE. Note - - The state machine could be in idle state due to holdoffs - from data availability, or as the command gets propagated - into the logic from the registers. */ - } STATUS_b; - } ; - __IM uint32_t RESERVED4[37]; - - union { - __IOM uint32_t MSPICFG; /*!< (@ 0x00000300) SPI module master configuration */ - - struct { - __IOM uint32_t SPOL : 1; /*!< [0..0] This bit selects SPI polarity. */ - __IOM uint32_t SPHA : 1; /*!< [1..1] Selects the SPI phase; When 1, will shift the sampling - edge by 1/2 clock. */ - __IOM uint32_t FULLDUP : 1; /*!< [2..2] Full Duplex mode. Capture read data during writes operations */ - __IM uint32_t : 13; - __IOM uint32_t WTFC : 1; /*!< [16..16] Enables flow control of new write transactions based - on the SPI_STATUS signal from the BLE Core. */ - __IOM uint32_t RDFC : 1; /*!< [17..17] Enables flow control of new read transactions based - on the SPI_STATUS signal from the BLE Core. */ - __IM uint32_t : 3; - __IOM uint32_t WTFCPOL : 1; /*!< [21..21] Selects the write flow control signal polarity. The - transfers are halted when the selected flow control signal - is OPPOSITE polarity of this bit. (For example: WTFCPOL - = 0 will allow a SPI_STATUS=1 to pause transfers). */ - __IOM uint32_t RDFCPOL : 1; /*!< [22..22] Selects the read flow control signal polarity. When - set, the clock will be held low until the flow control - is de-asserted. */ - __IOM uint32_t SPILSB : 1; /*!< [23..23] Selects data transfer as MSB first (0) or LSB first - (1) for the data portion of the SPI transaction. The offset - bytes are always transmitted MSB first. */ - __IOM uint32_t DINDLY : 3; /*!< [26..24] Delay tap to use for the input signal (MISO). This - gives more hold time on the input data. */ - __IOM uint32_t DOUTDLY : 3; /*!< [29..27] Delay tap to use for the output signal (MOSI). This - give more hold time on the output data. */ - __IOM uint32_t MSPIRST : 1; /*!< [30..30] Bit is deprecated. setting it will have no effect. */ - } MSPICFG_b; - } ; - - union { - __IOM uint32_t BLECFG; /*!< (@ 0x00000304) BLE Core Control */ - - struct { - __IOM uint32_t PWRSMEN : 1; /*!< [0..0] Enable the power state machine for automatic sequencing - and control of power states of the BLE Core module. */ - __IOM uint32_t BLERSTN : 1; /*!< [1..1] Reset line to the BLE Core. This will reset the BLE core - when asserted ('0') and must be written to '1' prior to - performing any BTLE related operations to the core. */ - __IOM uint32_t WAKEUPCTL : 2; /*!< [3..2] WAKE signal override. Controls the source of the WAKE - signal to the BLE Core. */ - __IOM uint32_t DCDCFLGCTL : 2; /*!< [5..4] DCDCFLG signal override. The value of this field will - be sent to the BLE Core when the PWRSM is off. Otherwise, - the value is supplied from internal logic. */ - __IOM uint32_t BLEHREQCTL : 2; /*!< [7..6] BLEH power on request override. The value of this field - will be sent to the BLE Core when the PWRSM is off. Otherwise, - the value is supplied from internal logic. */ - __IOM uint32_t WT4ACTOFF : 1; /*!< [8..8] Debug control of BLEIF power state machine. Allows transition - into the active state in the BLEIF state without waiting - for dcdc req from BLE Core. */ - __IOM uint32_t MCUFRCSLP : 1; /*!< [9..9] Force power state machine to go to the sleep state. Intended - for debug only. Has no effect on the actual BLE Core state, - only the state of the BLEIF interface state machine. */ - __IOM uint32_t FRCCLK : 1; /*!< [10..10] Force the clock in the BLEIF to be always running */ - __IOM uint32_t STAYASLEEP : 1; /*!< [11..11] Set to prevent the BLE power control module from waking - up the BLE Core after going into power down. To be used - for graceful shutdown, set by software prior to powering - off and will allow assertion of reset from sleep state. */ - __IOM uint32_t PWRISOCTL : 2; /*!< [13..12] Configuration of BLEH isolation control for power related - signals. */ - __IOM uint32_t SPIISOCTL : 2; /*!< [15..14] Configuration of BLEH isolation controls for SPI related - signals. */ - } BLECFG_b; - } ; - - union { - __IOM uint32_t PWRCMD; /*!< (@ 0x00000308) BLE Power command interface */ - - struct { - __IOM uint32_t WAKEREQ : 1; /*!< [0..0] Wake request from the MCU. When asserted (1), the BLE - Interface logic will assert the wakeup request signal to - the BLE Core. Only recognized when in the sleep state */ - __IOM uint32_t RESTART : 1; /*!< [1..1] Restart the BLE Core after going into the shutdown state. - Only valid when in the shutdown state. */ - } PWRCMD_b; - } ; - - union { - __IOM uint32_t BSTATUS; /*!< (@ 0x0000030C) BLE Core status */ - - struct { - __IOM uint32_t B2MSTATE : 3; /*!< [2..0] State of the BLE Core logic. */ - __IOM uint32_t SPISTATUS : 1; /*!< [3..3] Value of the SPISTATUS signal from the BLE Core. The - signal is asserted when the BLE Core is able to accept - write data via the SPI interface. Data should be transmitted - to theBLE core only when this signal is 1. The hardware - will automatically wait for this signal prior to performing - a write operation if flow control is active. */ - __IOM uint32_t DCDCREQ : 1; /*!< [4..4] Value of the DCDCREQ signal from the BLE Core. The DCDCREQ - signal is sent from the core to the BLEIF module when the - BLE core requires BLEH power to be active. When activated, - this isindicated by DCDCFLAG going to 1. */ - __IOM uint32_t DCDCFLAG : 1; /*!< [5..5] Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG - is a signal to the BLE Core indicating that the BLEH ppower - is active. */ - __IOM uint32_t WAKEUP : 1; /*!< [6..6] Value of the WAKEUP signal to the BLE Core . The WAKEUP - signals is sent from the BLEIF to the BLECORE to request - the BLE Core transition from sleep state to active state. */ - __IOM uint32_t BLEIRQ : 1; /*!< [7..7] Status of the BLEIRQ signal from the BLE Core. A value - of 1 idicates that read data is available in the core and - a read operation needs to be performed. */ - __IOM uint32_t PWRST : 3; /*!< [10..8] Current status of the power state machine */ - __IOM uint32_t BLEHACK : 1; /*!< [11..11] Value of the BLEHACK signal from the power control - unit. If the signal is '1', the BLEH power is active and - ready for use. */ - __IOM uint32_t BLEHREQ : 1; /*!< [12..12] Value of the BLEHREQ signal to the power control unit. - The BLEHREQ signal is sent from the BLEIF module to the - power control module to request the BLEH power up. When - the BLEHACK signal is asserted,BLEH power is stable and - ready for use. */ - } BSTATUS_b; - } ; - __IM uint32_t RESERVED5[64]; - - union { - __IOM uint32_t BLEDBG; /*!< (@ 0x00000410) BLEIF Master Debug Register */ - - struct { - __IOM uint32_t DBGEN : 1; /*!< [0..0] Debug Enable. Setting this bit will enable the update - of data within this register, otherwise it is clock gated - for power savings */ - __IOM uint32_t IOCLKON : 1; /*!< [1..1] IOCLK debug clock control. Enable IO_CLK to be active - when this bit is '1'. Otherwise, the clock is controlled - with gating from the logic as needed. */ - __IOM uint32_t APBCLKON : 1; /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active - when this bit is '1'. Otherwise, the clock is controlled - with gating from the logic as needed. */ - __IOM uint32_t DBGDATA : 29; /*!< [31..3] Debug data */ - } BLEDBG_b; - } ; -} BLEIF_Type; /*!< Size = 1044 (0x414) */ - - - -/* =========================================================================================================================== */ -/* ================ CACHECTRL ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Flash Cache Controller (CACHECTRL) - */ - -typedef struct { /*!< (@ 0x40018000) CACHECTRL Structure */ - - union { - __IOM uint32_t CACHECFG; /*!< (@ 0x00000000) Flash Cache Control Register */ - - struct { - __IOM uint32_t ENABLE : 1; /*!< [0..0] Enables the flash cache controller and enables power - to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE - should be set to enable caching for each type of access. */ - __IOM uint32_t LRU : 1; /*!< [1..1] Sets the cache repleacment policy. 0=LRR (least recently - replaced), 1=LRU (least recently used). LRR minimizes writes - to the TAG SRAM. */ - __IOM uint32_t ENABLE_NC0 : 1; /*!< [2..2] Enable Non-cacheable region 0. See NCR0 registers to - define the region. */ - __IOM uint32_t ENABLE_NC1 : 1; /*!< [3..3] Enable Non-cacheable region 1. See NCR1 registers to - define the region. */ - __IOM uint32_t CONFIG : 4; /*!< [7..4] Sets the cache configuration */ - __IOM uint32_t ICACHE_ENABLE : 1; /*!< [8..8] Enable Flash Instruction Caching */ - __IOM uint32_t DCACHE_ENABLE : 1; /*!< [9..9] Enable Flash Data Caching. */ - __IOM uint32_t CACHE_CLKGATE : 1; /*!< [10..10] Enable clock gating of cache TAG RAM. Software should - enable this bit for optimal power efficiency. */ - __IOM uint32_t CACHE_LS : 1; /*!< [11..11] Enable LS (light sleep) of cache RAMs. Software should - DISABLE this bit since cache activity is too high to benefit - from LS usage. */ - __IM uint32_t : 8; - __IOM uint32_t DATA_CLKGATE : 1; /*!< [20..20] Enable aggressive clock gating of entire data array. - This bit should be set to 1 for optimal power efficiency. */ - __IM uint32_t : 3; - __IOM uint32_t ENABLE_MONITOR : 1; /*!< [24..24] Enable Cache Monitoring Stats. Cache monitoring consumes - additional power and should only be enabled when profiling - code and counters will increment when this bit is set. - Counter values will be retained when this is set to 0, - allowing software to enable/disable counting for multiple - code segments. */ - } CACHECFG_b; - } ; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t CTRL; /*!< (@ 0x00000008) Cache Control */ - - struct { - __IOM uint32_t INVALIDATE : 1; /*!< [0..0] Writing a 1 to this bitfield invalidates the flash cache - contents. */ - __IOM uint32_t RESET_STAT : 1; /*!< [1..1] Reset Cache Statistics. When written to a 1, the cache - monitor counters will be cleared. The monitor counters - can be reset only when the CACHECFG.ENABLE_MONITOR bit - is set. */ - __IOM uint32_t CACHE_READY : 1; /*!< [2..2] Cache Ready Status (enabled and not processing an invalidate - operation) */ - __IM uint32_t : 1; - __IOM uint32_t FLASH0_SLM_STATUS : 1; /*!< [4..4] Flash Sleep Mode Status. 1 indicates that flash0 is in - sleep mode, 0 indicates flash0 is in normal mode. */ - __IOM uint32_t FLASH0_SLM_DISABLE : 1; /*!< [5..5] Disable Flash Sleep Mode. Write 1 to wake flash0 from - sleep mode (reading the array will also automatically wake - it). */ - __IOM uint32_t FLASH0_SLM_ENABLE : 1; /*!< [6..6] Enable Flash Sleep Mode. Write to 1 to put flash 0 into - sleep mode. NOTE: there is a 5us latency after waking flash - until the first access will be returned. */ - __IM uint32_t : 1; - __IOM uint32_t FLASH1_SLM_STATUS : 1; /*!< [8..8] Flash Sleep Mode Status. 1 indicates that flash1 is in - sleep mode, 0 indicates flash1 is in normal mode. */ - __IOM uint32_t FLASH1_SLM_DISABLE : 1; /*!< [9..9] Disable Flash Sleep Mode. Write 1 to wake flash1 from - sleep mode (reading the array will also automatically wake - it). */ - __IOM uint32_t FLASH1_SLM_ENABLE : 1; /*!< [10..10] Enable Flash Sleep Mode. Write to 1 to put flash 1 - into sleep mode. NOTE: there is a 5us latency after waking - flash until the first access will be returned. */ - __IM uint32_t : 1; - __IOM uint32_t FLASH2_SLM_STATUS : 1; /*!< [12..12] Flash Sleep Mode Status. 1 indicates that flash1 is - in sleep mode, 0 indicates flash2 is in normal mode. */ - __IOM uint32_t FLASH2_SLM_DISABLE : 1; /*!< [13..13] Disable Flash Sleep Mode. Write 1 to wake flash2 from - sleep mode (reading the array will also automatically wake - it). */ - __IOM uint32_t FLASH2_SLM_ENABLE : 1; /*!< [14..14] Enable Flash Sleep Mode. Write to 1 to put flash 1 - into sleep mode. NOTE: there is a 5us latency after waking - flash until the first access will be returned. */ - __IM uint32_t : 1; - __IOM uint32_t FLASH3_SLM_STATUS : 1; /*!< [16..16] Flash Sleep Mode Status. 1 indicates that flash1 is - in sleep mode, 0 indicates flash1 is in normal mode. */ - __IOM uint32_t FLASH3_SLM_DISABLE : 1; /*!< [17..17] Disable Flash Sleep Mode. Write 1 to wake flash1 from - sleep mode (reading the array will also automatically wake - it). */ - __IOM uint32_t FLASH3_SLM_ENABLE : 1; /*!< [18..18] Enable Flash Sleep Mode. Write to 1 to put flash 1 - into sleep mode. NOTE: there is a 5us latency after waking - flash until the first access will be returned. */ - } CTRL_b; - } ; - __IM uint32_t RESERVED1; - - union { - __IOM uint32_t NCR0START; /*!< (@ 0x00000010) Flash Cache Noncachable Region 0 Start */ - - struct { - __IM uint32_t : 4; - __IOM uint32_t ADDR : 23; /*!< [26..4] Start address for non-cacheable region 0 */ - } NCR0START_b; - } ; - - union { - __IOM uint32_t NCR0END; /*!< (@ 0x00000014) Flash Cache Noncachable Region 0 End */ - - struct { - __IM uint32_t : 4; - __IOM uint32_t ADDR : 23; /*!< [26..4] End address for non-cacheable region 0 */ - } NCR0END_b; - } ; - - union { - __IOM uint32_t NCR1START; /*!< (@ 0x00000018) Flash Cache Noncachable Region 1 Start */ - - struct { - __IM uint32_t : 4; - __IOM uint32_t ADDR : 23; /*!< [26..4] Start address for non-cacheable region 1 */ - } NCR1START_b; - } ; - - union { - __IOM uint32_t NCR1END; /*!< (@ 0x0000001C) Flash Cache Noncachable Region 1 End */ - - struct { - __IM uint32_t : 4; - __IOM uint32_t ADDR : 23; /*!< [26..4] End address for non-cacheable region 1 */ - } NCR1END_b; - } ; - __IM uint32_t RESERVED2[8]; - - union { - __IOM uint32_t DMON0; /*!< (@ 0x00000040) Data Cache Total Accesses */ - - struct { - __IOM uint32_t DACCESS_COUNT : 32; /*!< [31..0] Total accesses to data cache. All performance metrics - should be relative to the number of accesses performed. */ - } DMON0_b; - } ; - - union { - __IOM uint32_t DMON1; /*!< (@ 0x00000044) Data Cache Tag Lookups */ - - struct { - __IOM uint32_t DLOOKUP_COUNT : 32; /*!< [31..0] Total tag lookups from data cache. */ - } DMON1_b; - } ; - - union { - __IOM uint32_t DMON2; /*!< (@ 0x00000048) Data Cache Hits */ - - struct { - __IOM uint32_t DHIT_COUNT : 32; /*!< [31..0] Cache hits from lookup operations. */ - } DMON2_b; - } ; - - union { - __IOM uint32_t DMON3; /*!< (@ 0x0000004C) Data Cache Line Hits */ - - struct { - __IOM uint32_t DLINE_COUNT : 32; /*!< [31..0] Cache hits from line cache */ - } DMON3_b; - } ; - - union { - __IOM uint32_t IMON0; /*!< (@ 0x00000050) Instruction Cache Total Accesses */ - - struct { - __IOM uint32_t IACCESS_COUNT : 32; /*!< [31..0] Total accesses to Instruction cache */ - } IMON0_b; - } ; - - union { - __IOM uint32_t IMON1; /*!< (@ 0x00000054) Instruction Cache Tag Lookups */ - - struct { - __IOM uint32_t ILOOKUP_COUNT : 32; /*!< [31..0] Total tag lookups from Instruction cache */ - } IMON1_b; - } ; - - union { - __IOM uint32_t IMON2; /*!< (@ 0x00000058) Instruction Cache Hits */ - - struct { - __IOM uint32_t IHIT_COUNT : 32; /*!< [31..0] Cache hits from lookup operations */ - } IMON2_b; - } ; - - union { - __IOM uint32_t IMON3; /*!< (@ 0x0000005C) Instruction Cache Line Hits */ - - struct { - __IOM uint32_t ILINE_COUNT : 32; /*!< [31..0] Cache hits from line cache */ - } IMON3_b; - } ; - __IM uint32_t RESERVED3[40]; - - union { - __IOM uint32_t FLASH0CFG; /*!< (@ 0x00000100) Flash 0 Control Register */ - - struct { - __IOM uint32_t RDWAIT0 : 4; /*!< [3..0] Sets read waitstates for normal (fast) operation. A value - of 1 is recommended. */ - __IOM uint32_t SEDELAY0 : 3; /*!< [6..4] Sets SE delay (flash address setup). A value of 5 is - recommended. */ - __IM uint32_t : 1; - __IOM uint32_t LPMRDWAIT0 : 4; /*!< [11..8] Sets flash waitstates when in LPM Mode 2 (RD_WAIT in - LPM mode 2 only) */ - __IOM uint32_t LPMMODE0 : 2; /*!< [13..12] Controls flash low power modes (control of LPM pin). */ - } FLASH0CFG_b; - } ; - - union { - __IOM uint32_t FLASH1CFG; /*!< (@ 0x00000104) Flash 1 Control Register */ - - struct { - __IOM uint32_t RDWAIT1 : 4; /*!< [3..0] Sets read waitstates for normal (fast) operation. A value - of 1 is recommended. */ - __IOM uint32_t SEDELAY1 : 3; /*!< [6..4] Sets SE delay (flash address setup). A value of 5 is - recommended. */ - __IM uint32_t : 1; - __IOM uint32_t LPMRDWAIT1 : 4; /*!< [11..8] Sets flash waitstates when in LPM Mode 2 (RD_WAIT in - LPM mode 2 only) */ - __IOM uint32_t LPMMODE1 : 2; /*!< [13..12] Controls flash low power modes (control of LPM pin). */ - } FLASH1CFG_b; - } ; - - union { - __IOM uint32_t FLASH2CFG; /*!< (@ 0x00000108) Flash 2 Control Register */ - - struct { - __IOM uint32_t RDWAIT2 : 4; /*!< [3..0] Sets read waitstates for normal (fast) operation. A value - of 1 is recommended. */ - __IOM uint32_t SEDELAY2 : 3; /*!< [6..4] Sets SE delay (flash address setup). A value of 5 is - recommended. */ - __IM uint32_t : 1; - __IOM uint32_t LPMRDWAIT2 : 4; /*!< [11..8] Sets flash waitstates when in LPM Mode 2 (RD_WAIT in - LPM mode 2 only) */ - __IOM uint32_t LPMMODE2 : 2; /*!< [13..12] Controls flash low power modes (control of LPM pin). */ - } FLASH2CFG_b; - } ; - - union { - __IOM uint32_t FLASH3CFG; /*!< (@ 0x0000010C) Flash 3 Control Register */ - - struct { - __IOM uint32_t RDWAIT3 : 4; /*!< [3..0] Sets read waitstates for normal (fast) operation. A value - of 1 is recommended. */ - __IOM uint32_t SEDELAY3 : 3; /*!< [6..4] Sets SE delay (flash address setup). A value of 5 is - recommended. */ - __IM uint32_t : 1; - __IOM uint32_t LPMRDWAIT3 : 4; /*!< [11..8] Sets flash waitstates when in LPM Mode 2 (RD_WAIT in - LPM mode 2 only) */ - __IOM uint32_t LPMMODE3 : 2; /*!< [13..12] Controls flash low power modes (control of LPM pin). */ - } FLASH3CFG_b; - } ; -} CACHECTRL_Type; /*!< Size = 272 (0x110) */ - - - -/* =========================================================================================================================== */ -/* ================ CLKGEN ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Clock Generator (CLKGEN) - */ - -typedef struct { /*!< (@ 0x40004000) CLKGEN Structure */ - - union { - __IOM uint32_t CALXT; /*!< (@ 0x00000000) XT Oscillator Control */ - - struct { - __IOM uint32_t CALXT : 11; /*!< [10..0] XT Oscillator calibration value. This register will - enable the hardware to increase or decrease the number - of cycles in a 16KHz clock derived from the original 32KHz - version. The most significant bit is the sign. A '1' is - a reduction, and a '0' is an addition. This calibration - value will add or reduce the number of cycles programmed - here across a 32 second interval. The maximum value that - is effective is from -1024 to 1023. */ - } CALXT_b; - } ; - - union { - __IOM uint32_t CALRC; /*!< (@ 0x00000004) RC Oscillator Control */ - - struct { - __IOM uint32_t CALRC : 18; /*!< [17..0] LFRC Oscillator calibration value. This register will - enable the hardware to increase or decrease the number - of cycles in a 512 Hz clock derived from the original 1024 - version. The most significant bit is the sign. A '1' is - a reduction, and a '0' is an addition. This calibration - value will add or reduce the number of cycles programmed - here across a 32 second interval. The range is from -131072 - (decimal) to 131071 (decimal). This register is normally - used in conjuction with ACALCTR register. The CAL */ - } CALRC_b; - } ; - - union { - __IOM uint32_t ACALCTR; /*!< (@ 0x00000008) Autocalibration Counter */ - - struct { - __IOM uint32_t ACALCTR : 24; /*!< [23..0] Autocalibration Counter result. Bits 17 down to 0 of - this is feed directly to the CALRC register if ACAL register - in OCTRL register is set to 1024SEC or 512SEC. */ - } ACALCTR_b; - } ; - - union { - __IOM uint32_t OCTRL; /*!< (@ 0x0000000C) Oscillator Control */ - - struct { - __IOM uint32_t STOPXT : 1; /*!< [0..0] Stop the XT Oscillator to the RTC */ - __IOM uint32_t STOPRC : 1; /*!< [1..1] Stop the LFRC Oscillator to the RTC */ - __IM uint32_t : 4; - __IOM uint32_t FOS : 1; /*!< [6..6] Oscillator switch on failure function. If this is set, - then LFRC clock source will switch from XT to RC. */ - __IOM uint32_t OSEL : 1; /*!< [7..7] Selects the RTC oscillator (1 => LFRC, 0 => XT) */ - __IOM uint32_t ACAL : 3; /*!< [10..8] Autocalibration control. This selects the source to - be used in the autocalibration flow. This flow can also - be used to measure an internal clock against an external - clock source, with the external clock normally used as - the reference. */ - } OCTRL_b; - } ; - - union { - __IOM uint32_t CLKOUT; /*!< (@ 0x00000010) CLKOUT Frequency Select */ - - struct { - __IOM uint32_t CKSEL : 6; /*!< [5..0] CLKOUT signal select */ - __IM uint32_t : 1; - __IOM uint32_t CKEN : 1; /*!< [7..7] Enable the CLKOUT signal */ - } CLKOUT_b; - } ; - - union { - __IOM uint32_t CLKKEY; /*!< (@ 0x00000014) Key Register for Clock Control Register */ - - struct { - __IOM uint32_t CLKKEY : 32; /*!< [31..0] Key register value. */ - } CLKKEY_b; - } ; - - union { - __IOM uint32_t CCTRL; /*!< (@ 0x00000018) HFRC Clock Control */ - - struct { - __IOM uint32_t CORESEL : 1; /*!< [0..0] Core Clock divisor */ - } CCTRL_b; - } ; - - union { - __IOM uint32_t STATUS; /*!< (@ 0x0000001C) Clock Generator Status */ - - struct { - __IOM uint32_t OMODE : 1; /*!< [0..0] Current RTC oscillator (1 => LFRC, 0 => XT). After an - RTC oscillator change, it may take up to 2 seconds for - this field to reflect the new oscillator. */ - __IOM uint32_t OSCF : 1; /*!< [1..1] XT Oscillator is enabled but not oscillating */ - } STATUS_b; - } ; - - union { - __IOM uint32_t HFADJ; /*!< (@ 0x00000020) HFRC Adjustment */ - - struct { - __IOM uint32_t HFADJEN : 1; /*!< [0..0] HFRC adjustment control */ - __IOM uint32_t HFADJCK : 3; /*!< [3..1] Repeat period for HFRC adjustment */ - __IM uint32_t : 4; - __IOM uint32_t HFXTADJ : 12; /*!< [19..8] Target HFRC adjustment value. */ - __IOM uint32_t HFWARMUP : 1; /*!< [20..20] XT warmup period for HFRC adjustment */ - __IOM uint32_t HFADJGAIN : 3; /*!< [23..21] Gain control for HFRC adjustment */ - } HFADJ_b; - } ; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t CLOCKENSTAT; /*!< (@ 0x00000028) Clock Enable Status */ - - struct { - __IOM uint32_t CLOCKENSTAT : 32; /*!< [31..0] Clock enable status */ - } CLOCKENSTAT_b; - } ; - - union { - __IOM uint32_t CLOCKEN2STAT; /*!< (@ 0x0000002C) Clock Enable Status */ - - struct { - __IOM uint32_t CLOCKEN2STAT : 32; /*!< [31..0] Clock enable status 2 */ - } CLOCKEN2STAT_b; - } ; - - union { - __IOM uint32_t CLOCKEN3STAT; /*!< (@ 0x00000030) Clock Enable Status */ - - struct { - __IOM uint32_t CLOCKEN3STAT : 32; /*!< [31..0] Clock enable status 3 */ - } CLOCKEN3STAT_b; - } ; - - union { - __IOM uint32_t FREQCTRL; /*!< (@ 0x00000034) HFRC Frequency Control register */ - - struct { - __IOM uint32_t BURSTREQ : 1; /*!< [0..0] Frequency Burst Enable Request */ - __IOM uint32_t BURSTACK : 1; /*!< [1..1] Frequency Burst Request Acknowledge. Frequency burst - requested is always acknowledged whether burst is granted - or not depending on feature enable. */ - __IOM uint32_t BURSTSTATUS : 1; /*!< [2..2] This represents frequency burst status. */ - } FREQCTRL_b; - } ; - __IM uint32_t RESERVED1; - - union { - __IOM uint32_t BLEBUCKTONADJ; /*!< (@ 0x0000003C) BLE BUCK TON ADJUST */ - - struct { - __IOM uint32_t TONLOWTHRESHOLD : 10; /*!< [9..0] TON ADJUST LOW THRESHOLD. Suggested values are #A(94KHz) - #15(47KHz) #53(12Khz) #14D(3Khz) */ - __IOM uint32_t TONHIGHTHRESHOLD : 10; /*!< [19..10] TON ADJUST HIGH THRESHOLD. Suggested values are #15(94KHz) - #2A(47Khz) #A6(12Khz) #29A(3Khz) */ - __IOM uint32_t TONADJUSTPERIOD : 2; /*!< [21..20] TON ADJUST PERIOD */ - __IOM uint32_t TONADJUSTEN : 1; /*!< [22..22] TON ADJUST ENABLE */ - __IOM uint32_t ZEROLENDETECTTRIM : 4; /*!< [26..23] BLEBUCK ZERO LENGTH DETECT TRIM */ - __IOM uint32_t ZEROLENDETECTEN : 1; /*!< [27..27] BLEBUCK ZERO LENGTH DETECT ENABLE */ - } BLEBUCKTONADJ_b; - } ; - __IM uint32_t RESERVED2[48]; - - union { - __IOM uint32_t INTRPTEN; /*!< (@ 0x00000100) CLKGEN Interrupt Register: Enable */ - - struct { - __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ - __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ - __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ - } INTRPTEN_b; - } ; - - union { - __IOM uint32_t INTRPTSTAT; /*!< (@ 0x00000104) CLKGEN Interrupt Register: Status */ - - struct { - __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ - __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ - __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ - } INTRPTSTAT_b; - } ; - - union { - __IOM uint32_t INTRPTCLR; /*!< (@ 0x00000108) CLKGEN Interrupt Register: Clear */ - - struct { - __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ - __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ - __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ - } INTRPTCLR_b; - } ; - - union { - __IOM uint32_t INTRPTSET; /*!< (@ 0x0000010C) CLKGEN Interrupt Register: Set */ - - struct { - __IOM uint32_t ACF : 1; /*!< [0..0] Autocalibration Fail interrupt */ - __IOM uint32_t ACC : 1; /*!< [1..1] Autocalibration Complete interrupt */ - __IOM uint32_t OF : 1; /*!< [2..2] XT Oscillator Fail interrupt */ - } INTRPTSET_b; - } ; -} CLKGEN_Type; /*!< Size = 272 (0x110) */ - - - -/* =========================================================================================================================== */ -/* ================ CTIMER ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Counter/Timer (CTIMER) - */ - -typedef struct { /*!< (@ 0x40008000) CTIMER Structure */ - - union { - __IOM uint32_t TMR0; /*!< (@ 0x00000000) Counter/Timer Register */ - - struct { - __IOM uint32_t CTTMRA0 : 16; /*!< [15..0] Counter/Timer A0. */ - __IOM uint32_t CTTMRB0 : 16; /*!< [31..16] Counter/Timer B0. */ - } TMR0_b; - } ; - - union { - __IOM uint32_t CMPRA0; /*!< (@ 0x00000004) Counter/Timer A0 Compare Registers */ - - struct { - __IOM uint32_t CMPR0A0 : 16; /*!< [15..0] Counter/Timer A0 Compare Register 0. Holds the lower - limit for timer half A. */ - __IOM uint32_t CMPR1A0 : 16; /*!< [31..16] Counter/Timer A0 Compare Register 1. Holds the upper - limit for timer half A. */ - } CMPRA0_b; - } ; - - union { - __IOM uint32_t CMPRB0; /*!< (@ 0x00000008) Counter/Timer B0 Compare Registers */ - - struct { - __IOM uint32_t CMPR0B0 : 16; /*!< [15..0] Counter/Timer B0 Compare Register 0. Holds the lower - limit for timer half B. */ - __IOM uint32_t CMPR1B0 : 16; /*!< [31..16] Counter/Timer B0 Compare Register 1. Holds the upper - limit for timer half B. */ - } CMPRB0_b; - } ; - - union { - __IOM uint32_t CTRL0; /*!< (@ 0x0000000C) Counter/Timer Control */ - - struct { - __IOM uint32_t TMRA0EN : 1; /*!< [0..0] Counter/Timer A0 Enable bit. */ - __IOM uint32_t TMRA0CLK : 5; /*!< [5..1] Counter/Timer A0 Clock Select. */ - __IOM uint32_t TMRA0FN : 3; /*!< [8..6] Counter/Timer A0 Function Select. */ - __IOM uint32_t TMRA0IE0 : 1; /*!< [9..9] Counter/Timer A0 Interrupt Enable bit based on COMPR0. */ - __IOM uint32_t TMRA0IE1 : 1; /*!< [10..10] Counter/Timer A0 Interrupt Enable bit based on COMPR1. */ - __IOM uint32_t TMRA0CLR : 1; /*!< [11..11] Counter/Timer A0 Clear bit. */ - __IOM uint32_t TMRA0POL : 1; /*!< [12..12] Counter/Timer A0 output polarity. */ - __IM uint32_t : 3; - __IOM uint32_t TMRB0EN : 1; /*!< [16..16] Counter/Timer B0 Enable bit. */ - __IOM uint32_t TMRB0CLK : 5; /*!< [21..17] Counter/Timer B0 Clock Select. */ - __IOM uint32_t TMRB0FN : 3; /*!< [24..22] Counter/Timer B0 Function Select. */ - __IOM uint32_t TMRB0IE0 : 1; /*!< [25..25] Counter/Timer B0 Interrupt Enable bit for COMPR0. */ - __IOM uint32_t TMRB0IE1 : 1; /*!< [26..26] Counter/Timer B0 Interrupt Enable bit for COMPR1. */ - __IOM uint32_t TMRB0CLR : 1; /*!< [27..27] Counter/Timer B0 Clear bit. */ - __IOM uint32_t TMRB0POL : 1; /*!< [28..28] Counter/Timer B0 output polarity. */ - __IM uint32_t : 2; - __IOM uint32_t CTLINK0 : 1; /*!< [31..31] Counter/Timer A0/B0 Link bit. */ - } CTRL0_b; - } ; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t CMPRAUXA0; /*!< (@ 0x00000014) Counter/Timer A0 Compare Registers */ - - struct { - __IOM uint32_t CMPR2A0 : 16; /*!< [15..0] Counter/Timer A0 Compare Register 2. Holds the lower - limit for timer half A. */ - __IOM uint32_t CMPR3A0 : 16; /*!< [31..16] Counter/Timer A0 Compare Register 3. Holds the upper - limit for timer half A. */ - } CMPRAUXA0_b; - } ; - - union { - __IOM uint32_t CMPRAUXB0; /*!< (@ 0x00000018) Counter/Timer B0 Compare Registers */ - - struct { - __IOM uint32_t CMPR2B0 : 16; /*!< [15..0] Counter/Timer B0 Compare Register 2. Holds the lower - limit for timer half B. */ - __IOM uint32_t CMPR3B0 : 16; /*!< [31..16] Counter/Timer B0 Compare Register 3. Holds the upper - limit for timer half B. */ - } CMPRAUXB0_b; - } ; - - union { - __IOM uint32_t AUX0; /*!< (@ 0x0000001C) Counter/Timer Auxiliary */ - - struct { - __IOM uint32_t TMRA0LMT : 7; /*!< [6..0] Counter/Timer A0 Pattern Limit Count. */ - __IOM uint32_t TMRA0TRIG : 4; /*!< [10..7] Counter/Timer A0 Trigger Select. */ - __IOM uint32_t TMRA0NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ - __IOM uint32_t TMRA0TINV : 1; /*!< [12..12] Counter/Timer A0 Invert on trigger. */ - __IOM uint32_t TMRA0POL23 : 1; /*!< [13..13] Counter/Timer A0 Upper output polarity */ - __IOM uint32_t TMRA0EN23 : 1; /*!< [14..14] Counter/Timer A0 Upper compare enable. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB0LMT : 6; /*!< [21..16] Counter/Timer B0 Pattern Limit Count. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB0TRIG : 4; /*!< [26..23] Counter/Timer B0 Trigger Select. */ - __IOM uint32_t TMRB0NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ - __IOM uint32_t TMRB0TINV : 1; /*!< [28..28] Counter/Timer B0 Invert on trigger. */ - __IOM uint32_t TMRB0POL23 : 1; /*!< [29..29] Upper output polarity */ - __IOM uint32_t TMRB0EN23 : 1; /*!< [30..30] Counter/Timer B0 Upper compare enable. */ - } AUX0_b; - } ; - - union { - __IOM uint32_t TMR1; /*!< (@ 0x00000020) Counter/Timer Register */ - - struct { - __IOM uint32_t CTTMRA1 : 16; /*!< [15..0] Counter/Timer A1. */ - __IOM uint32_t CTTMRB1 : 16; /*!< [31..16] Counter/Timer B1. */ - } TMR1_b; - } ; - - union { - __IOM uint32_t CMPRA1; /*!< (@ 0x00000024) Counter/Timer A1 Compare Registers */ - - struct { - __IOM uint32_t CMPR0A1 : 16; /*!< [15..0] Counter/Timer A1 Compare Register 0. */ - __IOM uint32_t CMPR1A1 : 16; /*!< [31..16] Counter/Timer A1 Compare Register 1. */ - } CMPRA1_b; - } ; - - union { - __IOM uint32_t CMPRB1; /*!< (@ 0x00000028) Counter/Timer B1 Compare Registers */ - - struct { - __IOM uint32_t CMPR0B1 : 16; /*!< [15..0] Counter/Timer B1 Compare Register 0. */ - __IOM uint32_t CMPR1B1 : 16; /*!< [31..16] Counter/Timer B1 Compare Register 1. */ - } CMPRB1_b; - } ; - - union { - __IOM uint32_t CTRL1; /*!< (@ 0x0000002C) Counter/Timer Control */ - - struct { - __IOM uint32_t TMRA1EN : 1; /*!< [0..0] Counter/Timer A1 Enable bit. */ - __IOM uint32_t TMRA1CLK : 5; /*!< [5..1] Counter/Timer A1 Clock Select. */ - __IOM uint32_t TMRA1FN : 3; /*!< [8..6] Counter/Timer A1 Function Select. */ - __IOM uint32_t TMRA1IE0 : 1; /*!< [9..9] Counter/Timer A1 Interrupt Enable bit based on COMPR0. */ - __IOM uint32_t TMRA1IE1 : 1; /*!< [10..10] Counter/Timer A1 Interrupt Enable bit based on COMPR1. */ - __IOM uint32_t TMRA1CLR : 1; /*!< [11..11] Counter/Timer A1 Clear bit. */ - __IOM uint32_t TMRA1POL : 1; /*!< [12..12] Counter/Timer A1 output polarity. */ - __IM uint32_t : 3; - __IOM uint32_t TMRB1EN : 1; /*!< [16..16] Counter/Timer B1 Enable bit. */ - __IOM uint32_t TMRB1CLK : 5; /*!< [21..17] Counter/Timer B1 Clock Select. */ - __IOM uint32_t TMRB1FN : 3; /*!< [24..22] Counter/Timer B1 Function Select. */ - __IOM uint32_t TMRB1IE0 : 1; /*!< [25..25] Counter/Timer B1 Interrupt Enable bit for COMPR0. */ - __IOM uint32_t TMRB1IE1 : 1; /*!< [26..26] Counter/Timer B1 Interrupt Enable bit for COMPR1. */ - __IOM uint32_t TMRB1CLR : 1; /*!< [27..27] Counter/Timer B1 Clear bit. */ - __IOM uint32_t TMRB1POL : 1; /*!< [28..28] Counter/Timer B1 output polarity. */ - __IM uint32_t : 2; - __IOM uint32_t CTLINK1 : 1; /*!< [31..31] Counter/Timer A1/B1 Link bit. */ - } CTRL1_b; - } ; - __IM uint32_t RESERVED1; - - union { - __IOM uint32_t CMPRAUXA1; /*!< (@ 0x00000034) Counter/Timer A1 Compare Registers */ - - struct { - __IOM uint32_t CMPR2A1 : 16; /*!< [15..0] Counter/Timer A1 Compare Register 2. Holds the lower - limit for timer half A. */ - __IOM uint32_t CMPR3A1 : 16; /*!< [31..16] Counter/Timer A1 Compare Register 3. Holds the upper - limit for timer half A. */ - } CMPRAUXA1_b; - } ; - - union { - __IOM uint32_t CMPRAUXB1; /*!< (@ 0x00000038) Counter/Timer B1 Compare Registers */ - - struct { - __IOM uint32_t CMPR2B1 : 16; /*!< [15..0] Counter/Timer B1 Compare Register 2. Holds the lower - limit for timer half B. */ - __IOM uint32_t CMPR3B1 : 16; /*!< [31..16] Counter/Timer B1 Compare Register 3. Holds the upper - limit for timer half B. */ - } CMPRAUXB1_b; - } ; - - union { - __IOM uint32_t AUX1; /*!< (@ 0x0000003C) Counter/Timer Auxiliary */ - - struct { - __IOM uint32_t TMRA1LMT : 7; /*!< [6..0] Counter/Timer A1 Pattern Limit Count. */ - __IOM uint32_t TMRA1TRIG : 4; /*!< [10..7] Counter/Timer A1 Trigger Select. */ - __IOM uint32_t TMRA1NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ - __IOM uint32_t TMRA1TINV : 1; /*!< [12..12] Counter/Timer A1 Invert on trigger. */ - __IOM uint32_t TMRA1POL23 : 1; /*!< [13..13] Counter/Timer A1 Upper output polarity */ - __IOM uint32_t TMRA1EN23 : 1; /*!< [14..14] Counter/Timer A1 Upper compare enable. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB1LMT : 6; /*!< [21..16] Counter/Timer B1 Pattern Limit Count. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB1TRIG : 4; /*!< [26..23] Counter/Timer B1 Trigger Select. */ - __IOM uint32_t TMRB1NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ - __IOM uint32_t TMRB1TINV : 1; /*!< [28..28] Counter/Timer B1 Invert on trigger. */ - __IOM uint32_t TMRB1POL23 : 1; /*!< [29..29] Upper output polarity */ - __IOM uint32_t TMRB1EN23 : 1; /*!< [30..30] Counter/Timer B1 Upper compare enable. */ - } AUX1_b; - } ; - - union { - __IOM uint32_t TMR2; /*!< (@ 0x00000040) Counter/Timer Register */ - - struct { - __IOM uint32_t CTTMRA2 : 16; /*!< [15..0] Counter/Timer A2. */ - __IOM uint32_t CTTMRB2 : 16; /*!< [31..16] Counter/Timer B2. */ - } TMR2_b; - } ; - - union { - __IOM uint32_t CMPRA2; /*!< (@ 0x00000044) Counter/Timer A2 Compare Registers */ - - struct { - __IOM uint32_t CMPR0A2 : 16; /*!< [15..0] Counter/Timer A2 Compare Register 0. */ - __IOM uint32_t CMPR1A2 : 16; /*!< [31..16] Counter/Timer A2 Compare Register 1. */ - } CMPRA2_b; - } ; - - union { - __IOM uint32_t CMPRB2; /*!< (@ 0x00000048) Counter/Timer B2 Compare Registers */ - - struct { - __IOM uint32_t CMPR0B2 : 16; /*!< [15..0] Counter/Timer B2 Compare Register 0. */ - __IOM uint32_t CMPR1B2 : 16; /*!< [31..16] Counter/Timer B2 Compare Register 1. */ - } CMPRB2_b; - } ; - - union { - __IOM uint32_t CTRL2; /*!< (@ 0x0000004C) Counter/Timer Control */ - - struct { - __IOM uint32_t TMRA2EN : 1; /*!< [0..0] Counter/Timer A2 Enable bit. */ - __IOM uint32_t TMRA2CLK : 5; /*!< [5..1] Counter/Timer A2 Clock Select. */ - __IOM uint32_t TMRA2FN : 3; /*!< [8..6] Counter/Timer A2 Function Select. */ - __IOM uint32_t TMRA2IE0 : 1; /*!< [9..9] Counter/Timer A2 Interrupt Enable bit based on COMPR0. */ - __IOM uint32_t TMRA2IE1 : 1; /*!< [10..10] Counter/Timer A2 Interrupt Enable bit based on COMPR1. */ - __IOM uint32_t TMRA2CLR : 1; /*!< [11..11] Counter/Timer A2 Clear bit. */ - __IOM uint32_t TMRA2POL : 1; /*!< [12..12] Counter/Timer A2 output polarity. */ - __IM uint32_t : 3; - __IOM uint32_t TMRB2EN : 1; /*!< [16..16] Counter/Timer B2 Enable bit. */ - __IOM uint32_t TMRB2CLK : 5; /*!< [21..17] Counter/Timer B2 Clock Select. */ - __IOM uint32_t TMRB2FN : 3; /*!< [24..22] Counter/Timer B2 Function Select. */ - __IOM uint32_t TMRB2IE0 : 1; /*!< [25..25] Counter/Timer B2 Interrupt Enable bit for COMPR0. */ - __IOM uint32_t TMRB2IE1 : 1; /*!< [26..26] Counter/Timer B2 Interrupt Enable bit for COMPR1. */ - __IOM uint32_t TMRB2CLR : 1; /*!< [27..27] Counter/Timer B2 Clear bit. */ - __IOM uint32_t TMRB2POL : 1; /*!< [28..28] Counter/Timer B2 output polarity. */ - __IM uint32_t : 2; - __IOM uint32_t CTLINK2 : 1; /*!< [31..31] Counter/Timer A2/B2 Link bit. */ - } CTRL2_b; - } ; - __IM uint32_t RESERVED2; - - union { - __IOM uint32_t CMPRAUXA2; /*!< (@ 0x00000054) Counter/Timer A2 Compare Registers */ - - struct { - __IOM uint32_t CMPR2A2 : 16; /*!< [15..0] Counter/Timer A2 Compare Register 2. Holds the lower - limit for timer half A. */ - __IOM uint32_t CMPR3A2 : 16; /*!< [31..16] Counter/Timer A2 Compare Register 3. Holds the upper - limit for timer half A. */ - } CMPRAUXA2_b; - } ; - - union { - __IOM uint32_t CMPRAUXB2; /*!< (@ 0x00000058) Counter/Timer B2 Compare Registers */ - - struct { - __IOM uint32_t CMPR2B2 : 16; /*!< [15..0] Counter/Timer B2 Compare Register 2. Holds the lower - limit for timer half B. */ - __IOM uint32_t CMPR3B2 : 16; /*!< [31..16] Counter/Timer B2 Compare Register 3. Holds the upper - limit for timer half B. */ - } CMPRAUXB2_b; - } ; - - union { - __IOM uint32_t AUX2; /*!< (@ 0x0000005C) Counter/Timer Auxiliary */ - - struct { - __IOM uint32_t TMRA2LMT : 7; /*!< [6..0] Counter/Timer A2 Pattern Limit Count. */ - __IOM uint32_t TMRA2TRIG : 4; /*!< [10..7] Counter/Timer A2 Trigger Select. */ - __IOM uint32_t TMRA2NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ - __IOM uint32_t TMRA2TINV : 1; /*!< [12..12] Counter/Timer A2 Invert on trigger. */ - __IOM uint32_t TMRA2POL23 : 1; /*!< [13..13] Counter/Timer A2 Upper output polarity */ - __IOM uint32_t TMRA2EN23 : 1; /*!< [14..14] Counter/Timer A2 Upper compare enable. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB2LMT : 6; /*!< [21..16] Counter/Timer B2 Pattern Limit Count. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB2TRIG : 4; /*!< [26..23] Counter/Timer B2 Trigger Select. */ - __IOM uint32_t TMRB2NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ - __IOM uint32_t TMRB2TINV : 1; /*!< [28..28] Counter/Timer B2 Invert on trigger. */ - __IOM uint32_t TMRB2POL23 : 1; /*!< [29..29] Upper output polarity */ - __IOM uint32_t TMRB2EN23 : 1; /*!< [30..30] Counter/Timer B2 Upper compare enable. */ - } AUX2_b; - } ; - - union { - __IOM uint32_t TMR3; /*!< (@ 0x00000060) Counter/Timer Register */ - - struct { - __IOM uint32_t CTTMRA3 : 16; /*!< [15..0] Counter/Timer A3. */ - __IOM uint32_t CTTMRB3 : 16; /*!< [31..16] Counter/Timer B3. */ - } TMR3_b; - } ; - - union { - __IOM uint32_t CMPRA3; /*!< (@ 0x00000064) Counter/Timer A3 Compare Registers */ - - struct { - __IOM uint32_t CMPR0A3 : 16; /*!< [15..0] Counter/Timer A3 Compare Register 0. */ - __IOM uint32_t CMPR1A3 : 16; /*!< [31..16] Counter/Timer A3 Compare Register 1. */ - } CMPRA3_b; - } ; - - union { - __IOM uint32_t CMPRB3; /*!< (@ 0x00000068) Counter/Timer B3 Compare Registers */ - - struct { - __IOM uint32_t CMPR0B3 : 16; /*!< [15..0] Counter/Timer B3 Compare Register 0. */ - __IOM uint32_t CMPR1B3 : 16; /*!< [31..16] Counter/Timer B3 Compare Register 1. */ - } CMPRB3_b; - } ; - - union { - __IOM uint32_t CTRL3; /*!< (@ 0x0000006C) Counter/Timer Control */ - - struct { - __IOM uint32_t TMRA3EN : 1; /*!< [0..0] Counter/Timer A3 Enable bit. */ - __IOM uint32_t TMRA3CLK : 5; /*!< [5..1] Counter/Timer A3 Clock Select. */ - __IOM uint32_t TMRA3FN : 3; /*!< [8..6] Counter/Timer A3 Function Select. */ - __IOM uint32_t TMRA3IE0 : 1; /*!< [9..9] Counter/Timer A3 Interrupt Enable bit based on COMPR0. */ - __IOM uint32_t TMRA3IE1 : 1; /*!< [10..10] Counter/Timer A3 Interrupt Enable bit based on COMPR1. */ - __IOM uint32_t TMRA3CLR : 1; /*!< [11..11] Counter/Timer A3 Clear bit. */ - __IOM uint32_t TMRA3POL : 1; /*!< [12..12] Counter/Timer A3 output polarity. */ - __IM uint32_t : 2; - __IOM uint32_t ADCEN : 1; /*!< [15..15] Special Timer A3 enable for ADC function. */ - __IOM uint32_t TMRB3EN : 1; /*!< [16..16] Counter/Timer B3 Enable bit. */ - __IOM uint32_t TMRB3CLK : 5; /*!< [21..17] Counter/Timer B3 Clock Select. */ - __IOM uint32_t TMRB3FN : 3; /*!< [24..22] Counter/Timer B3 Function Select. */ - __IOM uint32_t TMRB3IE0 : 1; /*!< [25..25] Counter/Timer B3 Interrupt Enable bit for COMPR0. */ - __IOM uint32_t TMRB3IE1 : 1; /*!< [26..26] Counter/Timer B3 Interrupt Enable bit for COMPR1. */ - __IOM uint32_t TMRB3CLR : 1; /*!< [27..27] Counter/Timer B3 Clear bit. */ - __IOM uint32_t TMRB3POL : 1; /*!< [28..28] Counter/Timer B3 output polarity. */ - __IM uint32_t : 2; - __IOM uint32_t CTLINK3 : 1; /*!< [31..31] Counter/Timer A3/B3 Link bit. */ - } CTRL3_b; - } ; - __IM uint32_t RESERVED3; - - union { - __IOM uint32_t CMPRAUXA3; /*!< (@ 0x00000074) Counter/Timer A3 Compare Registers */ - - struct { - __IOM uint32_t CMPR2A3 : 16; /*!< [15..0] Counter/Timer A3 Compare Register 2. Holds the lower - limit for timer half A. */ - __IOM uint32_t CMPR3A3 : 16; /*!< [31..16] Counter/Timer A3 Compare Register 3. Holds the upper - limit for timer half A. */ - } CMPRAUXA3_b; - } ; - - union { - __IOM uint32_t CMPRAUXB3; /*!< (@ 0x00000078) Counter/Timer B3 Compare Registers */ - - struct { - __IOM uint32_t CMPR2B3 : 16; /*!< [15..0] Counter/Timer B3 Compare Register 2. Holds the lower - limit for timer half B. */ - __IOM uint32_t CMPR3B3 : 16; /*!< [31..16] Counter/Timer B3 Compare Register 3. Holds the upper - limit for timer half B. */ - } CMPRAUXB3_b; - } ; - - union { - __IOM uint32_t AUX3; /*!< (@ 0x0000007C) Counter/Timer Auxiliary */ - - struct { - __IOM uint32_t TMRA3LMT : 7; /*!< [6..0] Counter/Timer A3 Pattern Limit Count. */ - __IOM uint32_t TMRA3TRIG : 4; /*!< [10..7] Counter/Timer A3 Trigger Select. */ - __IOM uint32_t TMRA3NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ - __IOM uint32_t TMRA3TINV : 1; /*!< [12..12] Counter/Timer A3 Invert on trigger. */ - __IOM uint32_t TMRA3POL23 : 1; /*!< [13..13] Counter/Timer A3 Upper output polarity */ - __IOM uint32_t TMRA3EN23 : 1; /*!< [14..14] Counter/Timer A3 Upper compare enable. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB3LMT : 6; /*!< [21..16] Counter/Timer B3 Pattern Limit Count. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB3TRIG : 4; /*!< [26..23] Counter/Timer B3 Trigger Select. */ - __IOM uint32_t TMRB3NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ - __IOM uint32_t TMRB3TINV : 1; /*!< [28..28] Counter/Timer B3 Invert on trigger. */ - __IOM uint32_t TMRB3POL23 : 1; /*!< [29..29] Upper output polarity */ - __IOM uint32_t TMRB3EN23 : 1; /*!< [30..30] Counter/Timer B3 Upper compare enable. */ - } AUX3_b; - } ; - - union { - __IOM uint32_t TMR4; /*!< (@ 0x00000080) Counter/Timer Register */ - - struct { - __IOM uint32_t CTTMRA4 : 16; /*!< [15..0] Counter/Timer A4. */ - __IOM uint32_t CTTMRB4 : 16; /*!< [31..16] Counter/Timer B4. */ - } TMR4_b; - } ; - - union { - __IOM uint32_t CMPRA4; /*!< (@ 0x00000084) Counter/Timer A4 Compare Registers */ - - struct { - __IOM uint32_t CMPR0A4 : 16; /*!< [15..0] Counter/Timer A4 Compare Register 0. Holds the lower - limit for timer half A. */ - __IOM uint32_t CMPR1A4 : 16; /*!< [31..16] Counter/Timer A4 Compare Register 1. Holds the upper - limit for timer half A. */ - } CMPRA4_b; - } ; - - union { - __IOM uint32_t CMPRB4; /*!< (@ 0x00000088) Counter/Timer B4 Compare Registers */ - - struct { - __IOM uint32_t CMPR0B4 : 16; /*!< [15..0] Counter/Timer B4 Compare Register 0. Holds the lower - limit for timer half B. */ - __IOM uint32_t CMPR1B4 : 16; /*!< [31..16] Counter/Timer B4 Compare Register 1. Holds the upper - limit for timer half B. */ - } CMPRB4_b; - } ; - - union { - __IOM uint32_t CTRL4; /*!< (@ 0x0000008C) Counter/Timer Control */ - - struct { - __IOM uint32_t TMRA4EN : 1; /*!< [0..0] Counter/Timer A4 Enable bit. */ - __IOM uint32_t TMRA4CLK : 5; /*!< [5..1] Counter/Timer A4 Clock Select. */ - __IOM uint32_t TMRA4FN : 3; /*!< [8..6] Counter/Timer A4 Function Select. */ - __IOM uint32_t TMRA4IE0 : 1; /*!< [9..9] Counter/Timer A4 Interrupt Enable bit based on COMPR0. */ - __IOM uint32_t TMRA4IE1 : 1; /*!< [10..10] Counter/Timer A4 Interrupt Enable bit based on COMPR1. */ - __IOM uint32_t TMRA4CLR : 1; /*!< [11..11] Counter/Timer A4 Clear bit. */ - __IOM uint32_t TMRA4POL : 1; /*!< [12..12] Counter/Timer A4 output polarity. */ - __IM uint32_t : 3; - __IOM uint32_t TMRB4EN : 1; /*!< [16..16] Counter/Timer B4 Enable bit. */ - __IOM uint32_t TMRB4CLK : 5; /*!< [21..17] Counter/Timer B4 Clock Select. */ - __IOM uint32_t TMRB4FN : 3; /*!< [24..22] Counter/Timer B4 Function Select. */ - __IOM uint32_t TMRB4IE0 : 1; /*!< [25..25] Counter/Timer B4 Interrupt Enable bit for COMPR0. */ - __IOM uint32_t TMRB4IE1 : 1; /*!< [26..26] Counter/Timer B4 Interrupt Enable bit for COMPR1. */ - __IOM uint32_t TMRB4CLR : 1; /*!< [27..27] Counter/Timer B4 Clear bit. */ - __IOM uint32_t TMRB4POL : 1; /*!< [28..28] Counter/Timer B4 output polarity. */ - __IM uint32_t : 2; - __IOM uint32_t CTLINK4 : 1; /*!< [31..31] Counter/Timer A4/B4 Link bit. */ - } CTRL4_b; - } ; - __IM uint32_t RESERVED4; - - union { - __IOM uint32_t CMPRAUXA4; /*!< (@ 0x00000094) Counter/Timer A4 Compare Registers */ - - struct { - __IOM uint32_t CMPR2A4 : 16; /*!< [15..0] Counter/Timer A4 Compare Register 2. Holds the lower - limit for timer half A. */ - __IOM uint32_t CMPR3A4 : 16; /*!< [31..16] Counter/Timer A4 Compare Register 3. Holds the upper - limit for timer half A. */ - } CMPRAUXA4_b; - } ; - - union { - __IOM uint32_t CMPRAUXB4; /*!< (@ 0x00000098) Counter/Timer B4 Compare Registers */ - - struct { - __IOM uint32_t CMPR2B4 : 16; /*!< [15..0] Counter/Timer B4 Compare Register 2. Holds the lower - limit for timer half B. */ - __IOM uint32_t CMPR3B4 : 16; /*!< [31..16] Counter/Timer B4 Compare Register 3. Holds the upper - limit for timer half B. */ - } CMPRAUXB4_b; - } ; - - union { - __IOM uint32_t AUX4; /*!< (@ 0x0000009C) Counter/Timer Auxiliary */ - - struct { - __IOM uint32_t TMRA4LMT : 7; /*!< [6..0] Counter/Timer A4 Pattern Limit Count. */ - __IOM uint32_t TMRA4TRIG : 4; /*!< [10..7] Counter/Timer A4 Trigger Select. */ - __IOM uint32_t TMRA4NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ - __IOM uint32_t TMRA4TINV : 1; /*!< [12..12] Counter/Timer A4 Invert on trigger. */ - __IOM uint32_t TMRA4POL23 : 1; /*!< [13..13] Counter/Timer A4 Upper output polarity */ - __IOM uint32_t TMRA4EN23 : 1; /*!< [14..14] Counter/Timer A4 Upper compare enable. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB4LMT : 6; /*!< [21..16] Counter/Timer B4 Pattern Limit Count. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB4TRIG : 4; /*!< [26..23] Counter/Timer B4 Trigger Select. */ - __IOM uint32_t TMRB4NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ - __IOM uint32_t TMRB4TINV : 1; /*!< [28..28] Counter/Timer B4 Invert on trigger. */ - __IOM uint32_t TMRB4POL23 : 1; /*!< [29..29] Upper output polarity */ - __IOM uint32_t TMRB4EN23 : 1; /*!< [30..30] Counter/Timer B4 Upper compare enable. */ - } AUX4_b; - } ; - - union { - __IOM uint32_t TMR5; /*!< (@ 0x000000A0) Counter/Timer Register */ - - struct { - __IOM uint32_t CTTMRA5 : 16; /*!< [15..0] Counter/Timer A5. */ - __IOM uint32_t CTTMRB5 : 16; /*!< [31..16] Counter/Timer B5. */ - } TMR5_b; - } ; - - union { - __IOM uint32_t CMPRA5; /*!< (@ 0x000000A4) Counter/Timer A5 Compare Registers */ - - struct { - __IOM uint32_t CMPR0A5 : 16; /*!< [15..0] Counter/Timer A5 Compare Register 0. */ - __IOM uint32_t CMPR1A5 : 16; /*!< [31..16] Counter/Timer A5 Compare Register 1. */ - } CMPRA5_b; - } ; - - union { - __IOM uint32_t CMPRB5; /*!< (@ 0x000000A8) Counter/Timer B5 Compare Registers */ - - struct { - __IOM uint32_t CMPR0B5 : 16; /*!< [15..0] Counter/Timer B5 Compare Register 0. */ - __IOM uint32_t CMPR1B5 : 16; /*!< [31..16] Counter/Timer B5 Compare Register 1. */ - } CMPRB5_b; - } ; - - union { - __IOM uint32_t CTRL5; /*!< (@ 0x000000AC) Counter/Timer Control */ - - struct { - __IOM uint32_t TMRA5EN : 1; /*!< [0..0] Counter/Timer A5 Enable bit. */ - __IOM uint32_t TMRA5CLK : 5; /*!< [5..1] Counter/Timer A5 Clock Select. */ - __IOM uint32_t TMRA5FN : 3; /*!< [8..6] Counter/Timer A5 Function Select. */ - __IOM uint32_t TMRA5IE0 : 1; /*!< [9..9] Counter/Timer A5 Interrupt Enable bit based on COMPR0. */ - __IOM uint32_t TMRA5IE1 : 1; /*!< [10..10] Counter/Timer A5 Interrupt Enable bit based on COMPR1. */ - __IOM uint32_t TMRA5CLR : 1; /*!< [11..11] Counter/Timer A5 Clear bit. */ - __IOM uint32_t TMRA5POL : 1; /*!< [12..12] Counter/Timer A5 output polarity. */ - __IM uint32_t : 3; - __IOM uint32_t TMRB5EN : 1; /*!< [16..16] Counter/Timer B5 Enable bit. */ - __IOM uint32_t TMRB5CLK : 5; /*!< [21..17] Counter/Timer B5 Clock Select. */ - __IOM uint32_t TMRB5FN : 3; /*!< [24..22] Counter/Timer B5 Function Select. */ - __IOM uint32_t TMRB5IE0 : 1; /*!< [25..25] Counter/Timer B5 Interrupt Enable bit for COMPR0. */ - __IOM uint32_t TMRB5IE1 : 1; /*!< [26..26] Counter/Timer B5 Interrupt Enable bit for COMPR1. */ - __IOM uint32_t TMRB5CLR : 1; /*!< [27..27] Counter/Timer B5 Clear bit. */ - __IOM uint32_t TMRB5POL : 1; /*!< [28..28] Counter/Timer B5 output polarity. */ - __IM uint32_t : 2; - __IOM uint32_t CTLINK5 : 1; /*!< [31..31] Counter/Timer A5/B5 Link bit. */ - } CTRL5_b; - } ; - __IM uint32_t RESERVED5; - - union { - __IOM uint32_t CMPRAUXA5; /*!< (@ 0x000000B4) Counter/Timer A5 Compare Registers */ - - struct { - __IOM uint32_t CMPR2A5 : 16; /*!< [15..0] Counter/Timer A5 Compare Register 2. Holds the lower - limit for timer half A. */ - __IOM uint32_t CMPR3A5 : 16; /*!< [31..16] Counter/Timer A5 Compare Register 3. Holds the upper - limit for timer half A. */ - } CMPRAUXA5_b; - } ; - - union { - __IOM uint32_t CMPRAUXB5; /*!< (@ 0x000000B8) Counter/Timer B5 Compare Registers */ - - struct { - __IOM uint32_t CMPR2B5 : 16; /*!< [15..0] Counter/Timer B5 Compare Register 2. Holds the lower - limit for timer half B. */ - __IOM uint32_t CMPR3B5 : 16; /*!< [31..16] Counter/Timer B5 Compare Register 3. Holds the upper - limit for timer half B. */ - } CMPRAUXB5_b; - } ; - - union { - __IOM uint32_t AUX5; /*!< (@ 0x000000BC) Counter/Timer Auxiliary */ - - struct { - __IOM uint32_t TMRA5LMT : 7; /*!< [6..0] Counter/Timer A5 Pattern Limit Count. */ - __IOM uint32_t TMRA5TRIG : 4; /*!< [10..7] Counter/Timer A5 Trigger Select. */ - __IOM uint32_t TMRA5NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ - __IOM uint32_t TMRA5TINV : 1; /*!< [12..12] Counter/Timer A5 Invert on trigger. */ - __IOM uint32_t TMRA5POL23 : 1; /*!< [13..13] Counter/Timer A5 Upper output polarity */ - __IOM uint32_t TMRA5EN23 : 1; /*!< [14..14] Counter/Timer A5 Upper compare enable. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB5LMT : 6; /*!< [21..16] Counter/Timer B5 Pattern Limit Count. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB5TRIG : 4; /*!< [26..23] Counter/Timer B5 Trigger Select. */ - __IOM uint32_t TMRB5NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ - __IOM uint32_t TMRB5TINV : 1; /*!< [28..28] Counter/Timer B5 Invert on trigger. */ - __IOM uint32_t TMRB5POL23 : 1; /*!< [29..29] Upper output polarity */ - __IOM uint32_t TMRB5EN23 : 1; /*!< [30..30] Counter/Timer B5 Upper compare enable. */ - } AUX5_b; - } ; - - union { - __IOM uint32_t TMR6; /*!< (@ 0x000000C0) Counter/Timer Register */ - - struct { - __IOM uint32_t CTTMRA6 : 16; /*!< [15..0] Counter/Timer A6. */ - __IOM uint32_t CTTMRB6 : 16; /*!< [31..16] Counter/Timer B6. */ - } TMR6_b; - } ; - - union { - __IOM uint32_t CMPRA6; /*!< (@ 0x000000C4) Counter/Timer A6 Compare Registers */ - - struct { - __IOM uint32_t CMPR0A6 : 16; /*!< [15..0] Counter/Timer A6 Compare Register 0. */ - __IOM uint32_t CMPR1A6 : 16; /*!< [31..16] Counter/Timer A6 Compare Register 1. */ - } CMPRA6_b; - } ; - - union { - __IOM uint32_t CMPRB6; /*!< (@ 0x000000C8) Counter/Timer B6 Compare Registers */ - - struct { - __IOM uint32_t CMPR0B6 : 16; /*!< [15..0] Counter/Timer B6 Compare Register 0. */ - __IOM uint32_t CMPR1B6 : 16; /*!< [31..16] Counter/Timer B6 Compare Register 1. */ - } CMPRB6_b; - } ; - - union { - __IOM uint32_t CTRL6; /*!< (@ 0x000000CC) Counter/Timer Control */ - - struct { - __IOM uint32_t TMRA6EN : 1; /*!< [0..0] Counter/Timer A6 Enable bit. */ - __IOM uint32_t TMRA6CLK : 5; /*!< [5..1] Counter/Timer A6 Clock Select. */ - __IOM uint32_t TMRA6FN : 3; /*!< [8..6] Counter/Timer A6 Function Select. */ - __IOM uint32_t TMRA6IE0 : 1; /*!< [9..9] Counter/Timer A6 Interrupt Enable bit based on COMPR0. */ - __IOM uint32_t TMRA6IE1 : 1; /*!< [10..10] Counter/Timer A6 Interrupt Enable bit based on COMPR1. */ - __IOM uint32_t TMRA6CLR : 1; /*!< [11..11] Counter/Timer A6 Clear bit. */ - __IOM uint32_t TMRA6POL : 1; /*!< [12..12] Counter/Timer A6 output polarity. */ - __IM uint32_t : 3; - __IOM uint32_t TMRB6EN : 1; /*!< [16..16] Counter/Timer B6 Enable bit. */ - __IOM uint32_t TMRB6CLK : 5; /*!< [21..17] Counter/Timer B6 Clock Select. */ - __IOM uint32_t TMRB6FN : 3; /*!< [24..22] Counter/Timer B6 Function Select. */ - __IOM uint32_t TMRB6IE0 : 1; /*!< [25..25] Counter/Timer B6 Interrupt Enable bit for COMPR0. */ - __IOM uint32_t TMRB6IE1 : 1; /*!< [26..26] Counter/Timer B6 Interrupt Enable bit for COMPR1. */ - __IOM uint32_t TMRB6CLR : 1; /*!< [27..27] Counter/Timer B6 Clear bit. */ - __IOM uint32_t TMRB6POL : 1; /*!< [28..28] Counter/Timer B6 output polarity. */ - __IM uint32_t : 2; - __IOM uint32_t CTLINK6 : 1; /*!< [31..31] Counter/Timer A6/B6 Link bit. */ - } CTRL6_b; - } ; - __IM uint32_t RESERVED6; - - union { - __IOM uint32_t CMPRAUXA6; /*!< (@ 0x000000D4) Counter/Timer A6 Compare Registers */ - - struct { - __IOM uint32_t CMPR2A6 : 16; /*!< [15..0] Counter/Timer A6 Compare Register 2. Holds the lower - limit for timer half A. */ - __IOM uint32_t CMPR3A6 : 16; /*!< [31..16] Counter/Timer A6 Compare Register 3. Holds the upper - limit for timer half A. */ - } CMPRAUXA6_b; - } ; - - union { - __IOM uint32_t CMPRAUXB6; /*!< (@ 0x000000D8) Counter/Timer B6 Compare Registers */ - - struct { - __IOM uint32_t CMPR2B6 : 16; /*!< [15..0] Counter/Timer B6 Compare Register 2. Holds the lower - limit for timer half B. */ - __IOM uint32_t CMPR3B6 : 16; /*!< [31..16] Counter/Timer B6 Compare Register 3. Holds the upper - limit for timer half B. */ - } CMPRAUXB6_b; - } ; - - union { - __IOM uint32_t AUX6; /*!< (@ 0x000000DC) Counter/Timer Auxiliary */ - - struct { - __IOM uint32_t TMRA6LMT : 7; /*!< [6..0] Counter/Timer A6 Pattern Limit Count. */ - __IOM uint32_t TMRA6TRIG : 4; /*!< [10..7] Counter/Timer A6 Trigger Select. */ - __IOM uint32_t TMRA6NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ - __IOM uint32_t TMRA6TINV : 1; /*!< [12..12] Counter/Timer A6 Invert on trigger. */ - __IOM uint32_t TMRA6POL23 : 1; /*!< [13..13] Counter/Timer A6 Upper output polarity */ - __IOM uint32_t TMRA6EN23 : 1; /*!< [14..14] Counter/Timer A6 Upper compare enable. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB6LMT : 6; /*!< [21..16] Counter/Timer B6 Pattern Limit Count. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB6TRIG : 4; /*!< [26..23] Counter/Timer B6 Trigger Select. */ - __IOM uint32_t TMRB6NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ - __IOM uint32_t TMRB6TINV : 1; /*!< [28..28] Counter/Timer B6 Invert on trigger. */ - __IOM uint32_t TMRB6POL23 : 1; /*!< [29..29] Upper output polarity */ - __IOM uint32_t TMRB6EN23 : 1; /*!< [30..30] Counter/Timer B6 Upper compare enable. */ - } AUX6_b; - } ; - - union { - __IOM uint32_t TMR7; /*!< (@ 0x000000E0) Counter/Timer Register */ - - struct { - __IOM uint32_t CTTMRA7 : 16; /*!< [15..0] Counter/Timer A7. */ - __IOM uint32_t CTTMRB7 : 16; /*!< [31..16] Counter/Timer B7. */ - } TMR7_b; - } ; - - union { - __IOM uint32_t CMPRA7; /*!< (@ 0x000000E4) Counter/Timer A7 Compare Registers */ - - struct { - __IOM uint32_t CMPR0A7 : 16; /*!< [15..0] Counter/Timer A7 Compare Register 0. */ - __IOM uint32_t CMPR1A7 : 16; /*!< [31..16] Counter/Timer A7 Compare Register 1. */ - } CMPRA7_b; - } ; - - union { - __IOM uint32_t CMPRB7; /*!< (@ 0x000000E8) Counter/Timer B7 Compare Registers */ - - struct { - __IOM uint32_t CMPR0B7 : 16; /*!< [15..0] Counter/Timer B3 Compare Register 0. */ - __IOM uint32_t CMPR1B7 : 16; /*!< [31..16] Counter/Timer B3 Compare Register 1. */ - } CMPRB7_b; - } ; - - union { - __IOM uint32_t CTRL7; /*!< (@ 0x000000EC) Counter/Timer Control */ - - struct { - __IOM uint32_t TMRA7EN : 1; /*!< [0..0] Counter/Timer A7 Enable bit. */ - __IOM uint32_t TMRA7CLK : 5; /*!< [5..1] Counter/Timer A7 Clock Select. */ - __IOM uint32_t TMRA7FN : 3; /*!< [8..6] Counter/Timer A7 Function Select. */ - __IOM uint32_t TMRA7IE0 : 1; /*!< [9..9] Counter/Timer A7 Interrupt Enable bit based on COMPR0. */ - __IOM uint32_t TMRA7IE1 : 1; /*!< [10..10] Counter/Timer A7 Interrupt Enable bit based on COMPR1. */ - __IOM uint32_t TMRA7CLR : 1; /*!< [11..11] Counter/Timer A7 Clear bit. */ - __IOM uint32_t TMRA7POL : 1; /*!< [12..12] Counter/Timer A7 output polarity. */ - __IM uint32_t : 3; - __IOM uint32_t TMRB7EN : 1; /*!< [16..16] Counter/Timer B7 Enable bit. */ - __IOM uint32_t TMRB7CLK : 5; /*!< [21..17] Counter/Timer B7 Clock Select. */ - __IOM uint32_t TMRB7FN : 3; /*!< [24..22] Counter/Timer B7 Function Select. */ - __IOM uint32_t TMRB7IE0 : 1; /*!< [25..25] Counter/Timer B7 Interrupt Enable bit for COMPR0. */ - __IOM uint32_t TMRB7IE1 : 1; /*!< [26..26] Counter/Timer B7 Interrupt Enable bit for COMPR1. */ - __IOM uint32_t TMRB7CLR : 1; /*!< [27..27] Counter/Timer B7 Clear bit. */ - __IOM uint32_t TMRB7POL : 1; /*!< [28..28] Counter/Timer B7 output polarity. */ - __IM uint32_t : 2; - __IOM uint32_t CTLINK7 : 1; /*!< [31..31] Counter/Timer A7/B7 Link bit. */ - } CTRL7_b; - } ; - __IM uint32_t RESERVED7; - - union { - __IOM uint32_t CMPRAUXA7; /*!< (@ 0x000000F4) Counter/Timer A7 Compare Registers */ - - struct { - __IOM uint32_t CMPR2A7 : 16; /*!< [15..0] Counter/Timer A7 Compare Register 2. Holds the lower - limit for timer half A. */ - __IOM uint32_t CMPR3A7 : 16; /*!< [31..16] Counter/Timer A7 Compare Register 3. Holds the upper - limit for timer half A. */ - } CMPRAUXA7_b; - } ; - - union { - __IOM uint32_t CMPRAUXB7; /*!< (@ 0x000000F8) Counter/Timer B7 Compare Registers */ - - struct { - __IOM uint32_t CMPR2B7 : 16; /*!< [15..0] Counter/Timer B7 Compare Register 2. Holds the lower - limit for timer half B. */ - __IOM uint32_t CMPR3B7 : 16; /*!< [31..16] Counter/Timer B7 Compare Register 3. Holds the upper - limit for timer half B. */ - } CMPRAUXB7_b; - } ; - - union { - __IOM uint32_t AUX7; /*!< (@ 0x000000FC) Counter/Timer Auxiliary */ - - struct { - __IOM uint32_t TMRA7LMT : 7; /*!< [6..0] Counter/Timer A7 Pattern Limit Count. */ - __IOM uint32_t TMRA7TRIG : 4; /*!< [10..7] Counter/Timer A7 Trigger Select. */ - __IOM uint32_t TMRA7NOSYNC : 1; /*!< [11..11] Source clock synchronization control. */ - __IOM uint32_t TMRA7TINV : 1; /*!< [12..12] Counter/Timer A7 Invert on trigger. */ - __IOM uint32_t TMRA7POL23 : 1; /*!< [13..13] Counter/Timer A7 Upper output polarity */ - __IOM uint32_t TMRA7EN23 : 1; /*!< [14..14] Counter/Timer A7 Upper compare enable. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB7LMT : 6; /*!< [21..16] Counter/Timer B7 Pattern Limit Count. */ - __IM uint32_t : 1; - __IOM uint32_t TMRB7TRIG : 4; /*!< [26..23] Counter/Timer B7 Trigger Select. */ - __IOM uint32_t TMRB7NOSYNC : 1; /*!< [27..27] Source clock synchronization control. */ - __IOM uint32_t TMRB7TINV : 1; /*!< [28..28] Counter/Timer B7 Invert on trigger. */ - __IOM uint32_t TMRB7POL23 : 1; /*!< [29..29] Upper output polarity */ - __IOM uint32_t TMRB7EN23 : 1; /*!< [30..30] Counter/Timer B7 Upper compare enable. */ - } AUX7_b; - } ; - - union { - __IOM uint32_t GLOBEN; /*!< (@ 0x00000100) Counter/Timer Global Enable */ - - struct { - __IOM uint32_t ENA0 : 1; /*!< [0..0] Alternate enable for A0 */ - __IOM uint32_t ENB0 : 1; /*!< [1..1] Alternate enable for B0 */ - __IOM uint32_t ENA1 : 1; /*!< [2..2] Alternate enable for A1 */ - __IOM uint32_t ENB1 : 1; /*!< [3..3] Alternate enable for B1 */ - __IOM uint32_t ENA2 : 1; /*!< [4..4] Alternate enable for A2 */ - __IOM uint32_t ENB2 : 1; /*!< [5..5] Alternate enable for B2 */ - __IOM uint32_t ENA3 : 1; /*!< [6..6] Alternate enable for A3 */ - __IOM uint32_t ENB3 : 1; /*!< [7..7] Alternate enable for B3. */ - __IOM uint32_t ENA4 : 1; /*!< [8..8] Alternate enable for A4 */ - __IOM uint32_t ENB4 : 1; /*!< [9..9] Alternate enable for B4 */ - __IOM uint32_t ENA5 : 1; /*!< [10..10] Alternate enable for A5 */ - __IOM uint32_t ENB5 : 1; /*!< [11..11] Alternate enable for B5 */ - __IOM uint32_t ENA6 : 1; /*!< [12..12] Alternate enable for A6 */ - __IOM uint32_t ENB6 : 1; /*!< [13..13] Alternate enable for B6 */ - __IOM uint32_t ENA7 : 1; /*!< [14..14] Alternate enable for A7 */ - __IOM uint32_t ENB7 : 1; /*!< [15..15] Alternate enable for B7. */ - } GLOBEN_b; - } ; - - union { - __IOM uint32_t OUTCFG0; /*!< (@ 0x00000104) Counter/Timer Output Config 0 */ - - struct { - __IOM uint32_t CFG0 : 3; /*!< [2..0] Pad output 0 configuration */ - __IOM uint32_t CFG1 : 3; /*!< [5..3] Pad output 1 configuration */ - __IOM uint32_t CFG2 : 3; /*!< [8..6] Pad output 2 configuration */ - __IOM uint32_t CFG3 : 3; /*!< [11..9] Pad output 3 configuration */ - __IOM uint32_t CFG4 : 3; /*!< [14..12] Pad output 4 configuration */ - __IM uint32_t : 1; - __IOM uint32_t CFG5 : 3; /*!< [18..16] Pad output 5 configuration */ - __IOM uint32_t CFG6 : 3; /*!< [21..19] Pad output 6 configuration */ - __IOM uint32_t CFG7 : 3; /*!< [24..22] Pad output 7 configuration */ - __IOM uint32_t CFG8 : 3; /*!< [27..25] Pad output 8 configuration */ - __IOM uint32_t CFG9 : 3; /*!< [30..28] Pad output 9 configuration */ - } OUTCFG0_b; - } ; - - union { - __IOM uint32_t OUTCFG1; /*!< (@ 0x00000108) Counter/Timer Output Config 1 */ - - struct { - __IOM uint32_t CFG10 : 3; /*!< [2..0] Pad output 10 configuration */ - __IOM uint32_t CFG11 : 3; /*!< [5..3] Pad output 11 configuration */ - __IOM uint32_t CFG12 : 3; /*!< [8..6] Pad output 12 configuration */ - __IOM uint32_t CFG13 : 3; /*!< [11..9] Pad output 13 configuration */ - __IOM uint32_t CFG14 : 3; /*!< [14..12] Pad output 14 configuration */ - __IM uint32_t : 1; - __IOM uint32_t CFG15 : 3; /*!< [18..16] Pad output 15 configuration */ - __IOM uint32_t CFG16 : 3; /*!< [21..19] Pad output 16 configuration */ - __IOM uint32_t CFG17 : 3; /*!< [24..22] Pad output 17 configuration */ - __IOM uint32_t CFG18 : 3; /*!< [27..25] Pad output 18 configuration */ - __IOM uint32_t CFG19 : 3; /*!< [30..28] Pad output 19 configuration */ - } OUTCFG1_b; - } ; - - union { - __IOM uint32_t OUTCFG2; /*!< (@ 0x0000010C) Counter/Timer Output Config 2 */ - - struct { - __IOM uint32_t CFG20 : 3; /*!< [2..0] Pad output 20 configuration */ - __IOM uint32_t CFG21 : 3; /*!< [5..3] Pad output 21 configuration */ - __IOM uint32_t CFG22 : 3; /*!< [8..6] Pad output 22 configuration */ - __IOM uint32_t CFG23 : 3; /*!< [11..9] Pad output 23 configuration */ - __IOM uint32_t CFG24 : 3; /*!< [14..12] Pad output 24 configuration */ - __IM uint32_t : 1; - __IOM uint32_t CFG25 : 3; /*!< [18..16] Pad output 25 configuration */ - __IOM uint32_t CFG26 : 3; /*!< [21..19] Pad output 26 configuration */ - __IOM uint32_t CFG27 : 3; /*!< [24..22] Pad output 27 configuration */ - __IOM uint32_t CFG28 : 3; /*!< [27..25] Pad output 28 configuration */ - __IOM uint32_t CFG29 : 3; /*!< [30..28] Pad output 29 configuration */ - } OUTCFG2_b; - } ; - __IM uint32_t RESERVED8; - - union { - __IOM uint32_t OUTCFG3; /*!< (@ 0x00000114) Counter/Timer Output Config 3 */ - - struct { - __IOM uint32_t CFG30 : 3; /*!< [2..0] Pad output 30 configuration */ - __IOM uint32_t CFG31 : 3; /*!< [5..3] Pad output 31 configuration */ - } OUTCFG3_b; - } ; - - union { - __IOM uint32_t INCFG; /*!< (@ 0x00000118) Counter/Timer Input Config */ - - struct { - __IOM uint32_t CFGA0 : 1; /*!< [0..0] CTIMER A0 input configuration */ - __IOM uint32_t CFGB0 : 1; /*!< [1..1] CTIMER B0 input configuration */ - __IOM uint32_t CFGA1 : 1; /*!< [2..2] CTIMER A1 input configuration */ - __IOM uint32_t CFGB1 : 1; /*!< [3..3] CTIMER B1 input configuration */ - __IOM uint32_t CFGA2 : 1; /*!< [4..4] CTIMER A2 input configuration */ - __IOM uint32_t CFGB2 : 1; /*!< [5..5] CTIMER B2 input configuration */ - __IOM uint32_t CFGA3 : 1; /*!< [6..6] CTIMER A3 input configuration */ - __IOM uint32_t CFGB3 : 1; /*!< [7..7] CTIMER B3 input configuration */ - __IOM uint32_t CFGA4 : 1; /*!< [8..8] CTIMER A4 input configuration */ - __IOM uint32_t CFGB4 : 1; /*!< [9..9] CTIMER B4 input configuration */ - __IOM uint32_t CFGA5 : 1; /*!< [10..10] CTIMER A5 input configuration */ - __IOM uint32_t CFGB5 : 1; /*!< [11..11] CTIMER B5 input configuration */ - __IOM uint32_t CFGA6 : 1; /*!< [12..12] CTIMER A6 input configuration */ - __IOM uint32_t CFGB6 : 1; /*!< [13..13] CTIMER B6 input configuration */ - __IOM uint32_t CFGA7 : 1; /*!< [14..14] CTIMER A7 input configuration */ - __IOM uint32_t CFGB7 : 1; /*!< [15..15] CTIMER B7 input configuration */ - } INCFG_b; - } ; - __IM uint32_t RESERVED9[9]; - - union { - __IOM uint32_t STCFG; /*!< (@ 0x00000140) Configuration Register */ - - struct { - __IOM uint32_t CLKSEL : 4; /*!< [3..0] Selects an appropriate clock source and divider to use - for the System Timer clock. */ - __IM uint32_t : 4; - __IOM uint32_t COMPARE_A_EN : 1; /*!< [8..8] Selects whether compare is enabled for the corresponding - SCMPR register. If compare is enabled, the interrupt status - is set once the comparision is met. */ - __IOM uint32_t COMPARE_B_EN : 1; /*!< [9..9] Selects whether compare is enabled for the corresponding - SCMPR register. If compare is enabled, the interrupt status - is set once the comparision is met. */ - __IOM uint32_t COMPARE_C_EN : 1; /*!< [10..10] Selects whether compare is enabled for the corresponding - SCMPR register. If compare is enabled, the interrupt status - is set once the comparision is met. */ - __IOM uint32_t COMPARE_D_EN : 1; /*!< [11..11] Selects whether compare is enabled for the corresponding - SCMPR register. If compare is enabled, the interrupt status - is set once the comparision is met. */ - __IOM uint32_t COMPARE_E_EN : 1; /*!< [12..12] Selects whether compare is enabled for the corresponding - SCMPR register. If compare is enabled, the interrupt status - is set once the comparision is met. */ - __IOM uint32_t COMPARE_F_EN : 1; /*!< [13..13] Selects whether compare is enabled for the corresponding - SCMPR register. If compare is enabled, the interrupt status - is set once the comparision is met. */ - __IOM uint32_t COMPARE_G_EN : 1; /*!< [14..14] Selects whether compare is enabled for the corresponding - SCMPR register. If compare is enabled, the interrupt status - is set once the comparision is met. */ - __IOM uint32_t COMPARE_H_EN : 1; /*!< [15..15] Selects whether compare is enabled for the corresponding - SCMPR register. If compare is enabled, the interrupt status - is set once the comparision is met. */ - __IM uint32_t : 14; - __IOM uint32_t CLEAR : 1; /*!< [30..30] Set this bit to one to clear the System Timer register. - If this bit is set to '1', the system timer register will - stay cleared. It needs to be set to '0' for the system - timer to start running. */ - __IOM uint32_t FREEZE : 1; /*!< [31..31] Set this bit to one to freeze the clock input to the - COUNTER register. Once frozen, the value can be safely - written from the MCU. Unfreeze to resume. */ - } STCFG_b; - } ; - - union { - __IOM uint32_t STTMR; /*!< (@ 0x00000144) System Timer Count Register (Real Time Counter) */ - - struct { - __IOM uint32_t STTMR : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ - } STTMR_b; - } ; - - union { - __IOM uint32_t CAPTURECONTROL; /*!< (@ 0x00000148) Capture Control Register */ - - struct { - __IOM uint32_t CAPTURE0 : 1; /*!< [0..0] Selects whether capture is enabled for the specified - capture register. */ - __IOM uint32_t CAPTURE1 : 1; /*!< [1..1] Selects whether capture is enabled for the specified - capture register. */ - __IOM uint32_t CAPTURE2 : 1; /*!< [2..2] Selects whether capture is enabled for the specified - capture register. */ - __IOM uint32_t CAPTURE3 : 1; /*!< [3..3] Selects whether capture is enabled for the specified - capture register. */ - } CAPTURECONTROL_b; - } ; - __IM uint32_t RESERVED10; - - union { - __IOM uint32_t SCMPR0; /*!< (@ 0x00000150) Compare Register A */ - - struct { - __IOM uint32_t SCMPR0 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register - according to the match criterion, as selected in the COMPARE_A_EN - bit in the REG_CTIMER_STCGF register. */ - } SCMPR0_b; - } ; - - union { - __IOM uint32_t SCMPR1; /*!< (@ 0x00000154) Compare Register B */ - - struct { - __IOM uint32_t SCMPR1 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register - according to the match criterion, as selected in the COMPARE_B_EN - bit in the REG_CTIMER_STCGF register. */ - } SCMPR1_b; - } ; - - union { - __IOM uint32_t SCMPR2; /*!< (@ 0x00000158) Compare Register C */ - - struct { - __IOM uint32_t SCMPR2 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register - according to the match criterion, as selected in the COMPARE_C_EN - bit in the REG_CTIMER_STCGF register. */ - } SCMPR2_b; - } ; - - union { - __IOM uint32_t SCMPR3; /*!< (@ 0x0000015C) Compare Register D */ - - struct { - __IOM uint32_t SCMPR3 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register - according to the match criterion, as selected in the COMPARE_D_EN - bit in the REG_CTIMER_STCGF register. */ - } SCMPR3_b; - } ; - - union { - __IOM uint32_t SCMPR4; /*!< (@ 0x00000160) Compare Register E */ - - struct { - __IOM uint32_t SCMPR4 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register - according to the match criterion, as selected in the COMPARE_E_EN - bit in the REG_CTIMER_STCGF register. */ - } SCMPR4_b; - } ; - - union { - __IOM uint32_t SCMPR5; /*!< (@ 0x00000164) Compare Register F */ - - struct { - __IOM uint32_t SCMPR5 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register - according to the match criterion, as selected in the COMPARE_F_EN - bit in the REG_CTIMER_STCGF register. */ - } SCMPR5_b; - } ; - - union { - __IOM uint32_t SCMPR6; /*!< (@ 0x00000168) Compare Register G */ - - struct { - __IOM uint32_t SCMPR6 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register - according to the match criterion, as selected in the COMPARE_G_EN - bit in the REG_CTIMER_STCGF register. */ - } SCMPR6_b; - } ; - - union { - __IOM uint32_t SCMPR7; /*!< (@ 0x0000016C) Compare Register H */ - - struct { - __IOM uint32_t SCMPR7 : 32; /*!< [31..0] Compare this value to the value in the COUNTER register - according to the match criterion, as selected in the COMPARE_H_EN - bit in the REG_CTIMER_STCGF register. */ - } SCMPR7_b; - } ; - __IM uint32_t RESERVED11[28]; - - union { - __IOM uint32_t SCAPT0; /*!< (@ 0x000001E0) Capture Register A */ - - struct { - __IOM uint32_t SCAPT0 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER - is copied into this register and the corresponding interrupt - status bit is set. */ - } SCAPT0_b; - } ; - - union { - __IOM uint32_t SCAPT1; /*!< (@ 0x000001E4) Capture Register B */ - - struct { - __IOM uint32_t SCAPT1 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER - is copied into this register and the corresponding interrupt - status bit is set. */ - } SCAPT1_b; - } ; - - union { - __IOM uint32_t SCAPT2; /*!< (@ 0x000001E8) Capture Register C */ - - struct { - __IOM uint32_t SCAPT2 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER - is copied into this register and the corresponding interrupt - status bit is set. */ - } SCAPT2_b; - } ; - - union { - __IOM uint32_t SCAPT3; /*!< (@ 0x000001EC) Capture Register D */ - - struct { - __IOM uint32_t SCAPT3 : 32; /*!< [31..0] Whenever the event is detected, the value in the COUNTER - is copied into this register and the corresponding interrupt - status bit is set. */ - } SCAPT3_b; - } ; - - union { - __IOM uint32_t SNVR0; /*!< (@ 0x000001F0) System Timer NVRAM_A Register */ - - struct { - __IOM uint32_t SNVR0 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ - } SNVR0_b; - } ; - - union { - __IOM uint32_t SNVR1; /*!< (@ 0x000001F4) System Timer NVRAM_B Register */ - - struct { - __IOM uint32_t SNVR1 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ - } SNVR1_b; - } ; - - union { - __IOM uint32_t SNVR2; /*!< (@ 0x000001F8) System Timer NVRAM_C Register */ - - struct { - __IOM uint32_t SNVR2 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ - } SNVR2_b; - } ; - - union { - __IOM uint32_t SNVR3; /*!< (@ 0x000001FC) System Timer NVRAM_D Register */ - - struct { - __IOM uint32_t SNVR3 : 32; /*!< [31..0] Value of the 32-bit counter as it ticks over. */ - } SNVR3_b; - } ; - - union { - __IOM uint32_t INTEN; /*!< (@ 0x00000200) Counter/Timer Interrupts: Enable */ - - struct { - __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */ - } INTEN_b; - } ; - - union { - __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Counter/Timer Interrupts: Status */ - - struct { - __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */ - } INTSTAT_b; - } ; - - union { - __IOM uint32_t INTCLR; /*!< (@ 0x00000208) Counter/Timer Interrupts: Clear */ - - struct { - __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */ - } INTCLR_b; - } ; - - union { - __IOM uint32_t INTSET; /*!< (@ 0x0000020C) Counter/Timer Interrupts: Set */ - - struct { - __IOM uint32_t CTMRA0C0INT : 1; /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB0C0INT : 1; /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA1C0INT : 1; /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB1C0INT : 1; /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA2C0INT : 1; /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB2C0INT : 1; /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA3C0INT : 1; /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB3C0INT : 1; /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA4C0INT : 1; /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB4C0INT : 1; /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA5C0INT : 1; /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB5C0INT : 1; /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA6C0INT : 1; /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB6C0INT : 1; /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA7C0INT : 1; /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0. */ - __IOM uint32_t CTMRB7C0INT : 1; /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0. */ - __IOM uint32_t CTMRA0C1INT : 1; /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB0C1INT : 1; /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA1C1INT : 1; /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB1C1INT : 1; /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA2C1INT : 1; /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB2C1INT : 1; /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA3C1INT : 1; /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB3C1INT : 1; /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA4C1INT : 1; /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB4C1INT : 1; /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA5C1INT : 1; /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB5C1INT : 1; /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA6C1INT : 1; /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB6C1INT : 1; /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1. */ - __IOM uint32_t CTMRA7C1INT : 1; /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1. */ - __IOM uint32_t CTMRB7C1INT : 1; /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1. */ - } INTSET_b; - } ; - __IM uint32_t RESERVED12[60]; - - union { - __IOM uint32_t STMINTEN; /*!< (@ 0x00000300) STIMER Interrupt registers: Enable */ - - struct { - __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register - A. */ - __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register - B. */ - __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register - C. */ - __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register - D. */ - __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register - E. */ - __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register - F. */ - __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register - G. */ - __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register - H. */ - __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ - __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ - __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ - __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ - __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ - } STMINTEN_b; - } ; - - union { - __IOM uint32_t STMINTSTAT; /*!< (@ 0x00000304) STIMER Interrupt registers: Status */ - - struct { - __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register - A. */ - __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register - B. */ - __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register - C. */ - __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register - D. */ - __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register - E. */ - __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register - F. */ - __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register - G. */ - __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register - H. */ - __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ - __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ - __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ - __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ - __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ - } STMINTSTAT_b; - } ; - - union { - __IOM uint32_t STMINTCLR; /*!< (@ 0x00000308) STIMER Interrupt registers: Clear */ - - struct { - __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register - A. */ - __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register - B. */ - __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register - C. */ - __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register - D. */ - __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register - E. */ - __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register - F. */ - __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register - G. */ - __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register - H. */ - __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ - __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ - __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ - __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ - __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ - } STMINTCLR_b; - } ; - - union { - __IOM uint32_t STMINTSET; /*!< (@ 0x0000030C) STIMER Interrupt registers: Set */ - - struct { - __IOM uint32_t COMPAREA : 1; /*!< [0..0] COUNTER is greater than or equal to COMPARE register - A. */ - __IOM uint32_t COMPAREB : 1; /*!< [1..1] COUNTER is greater than or equal to COMPARE register - B. */ - __IOM uint32_t COMPAREC : 1; /*!< [2..2] COUNTER is greater than or equal to COMPARE register - C. */ - __IOM uint32_t COMPARED : 1; /*!< [3..3] COUNTER is greater than or equal to COMPARE register - D. */ - __IOM uint32_t COMPAREE : 1; /*!< [4..4] COUNTER is greater than or equal to COMPARE register - E. */ - __IOM uint32_t COMPAREF : 1; /*!< [5..5] COUNTER is greater than or equal to COMPARE register - F. */ - __IOM uint32_t COMPAREG : 1; /*!< [6..6] COUNTER is greater than or equal to COMPARE register - G. */ - __IOM uint32_t COMPAREH : 1; /*!< [7..7] COUNTER is greater than or equal to COMPARE register - H. */ - __IOM uint32_t OVERFLOW : 1; /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. */ - __IOM uint32_t CAPTUREA : 1; /*!< [9..9] CAPTURE register A has grabbed the value in the counter */ - __IOM uint32_t CAPTUREB : 1; /*!< [10..10] CAPTURE register B has grabbed the value in the counter */ - __IOM uint32_t CAPTUREC : 1; /*!< [11..11] CAPTURE register C has grabbed the value in the counter */ - __IOM uint32_t CAPTURED : 1; /*!< [12..12] CAPTURE register D has grabbed the value in the counter */ - } STMINTSET_b; - } ; -} CTIMER_Type; /*!< Size = 784 (0x310) */ - - - -/* =========================================================================================================================== */ -/* ================ GPIO ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief General Purpose IO (GPIO) - */ - -typedef struct { /*!< (@ 0x40010000) GPIO Structure */ - - union { - __IOM uint32_t PADREGA; /*!< (@ 0x00000000) Pad Configuration Register A (Pads 0-3) */ - - struct { - __IOM uint32_t PAD0PULL : 1; /*!< [0..0] Pad 0 pullup enable */ - __IOM uint32_t PAD0INPEN : 1; /*!< [1..1] Pad 0 input enable */ - __IOM uint32_t PAD0STRNG : 1; /*!< [2..2] Pad 0 drive strength */ - __IOM uint32_t PAD0FNCSEL : 3; /*!< [5..3] Pad 0 function select */ - __IOM uint32_t PAD0RSEL : 2; /*!< [7..6] Pad 0 pullup resistor selection. */ - __IOM uint32_t PAD1PULL : 1; /*!< [8..8] Pad 1 pullup enable */ - __IOM uint32_t PAD1INPEN : 1; /*!< [9..9] Pad 1 input enable */ - __IOM uint32_t PAD1STRNG : 1; /*!< [10..10] Pad 1 drive strength */ - __IOM uint32_t PAD1FNCSEL : 3; /*!< [13..11] Pad 1 function select */ - __IOM uint32_t PAD1RSEL : 2; /*!< [15..14] Pad 1 pullup resistor selection. */ - __IOM uint32_t PAD2PULL : 1; /*!< [16..16] Pad 2 pullup enable */ - __IOM uint32_t PAD2INPEN : 1; /*!< [17..17] Pad 2 input enable */ - __IOM uint32_t PAD2STRNG : 1; /*!< [18..18] Pad 2 drive strength */ - __IOM uint32_t PAD2FNCSEL : 3; /*!< [21..19] Pad 2 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD3PULL : 1; /*!< [24..24] Pad 3 pullup enable */ - __IOM uint32_t PAD3INPEN : 1; /*!< [25..25] Pad 3 input enable. */ - __IOM uint32_t PAD3STRNG : 1; /*!< [26..26] Pad 3 drive strength. */ - __IOM uint32_t PAD3FNCSEL : 3; /*!< [29..27] Pad 3 function select */ - __IOM uint32_t PAD3PWRUP : 1; /*!< [30..30] Pad 3 VDD power switch enable */ - } PADREGA_b; - } ; - - union { - __IOM uint32_t PADREGB; /*!< (@ 0x00000004) Pad Configuration Register B (Pads 4-7) */ - - struct { - __IOM uint32_t PAD4PULL : 1; /*!< [0..0] Pad 4 pullup enable */ - __IOM uint32_t PAD4INPEN : 1; /*!< [1..1] Pad 4 input enable */ - __IOM uint32_t PAD4STRNG : 1; /*!< [2..2] Pad 4 drive strength */ - __IOM uint32_t PAD4FNCSEL : 3; /*!< [5..3] Pad 4 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD5PULL : 1; /*!< [8..8] Pad 5 pullup enable */ - __IOM uint32_t PAD5INPEN : 1; /*!< [9..9] Pad 5 input enable */ - __IOM uint32_t PAD5STRNG : 1; /*!< [10..10] Pad 5 drive strength */ - __IOM uint32_t PAD5FNCSEL : 3; /*!< [13..11] Pad 5 function select */ - __IOM uint32_t PAD5RSEL : 2; /*!< [15..14] Pad 5 pullup resistor selection. */ - __IOM uint32_t PAD6PULL : 1; /*!< [16..16] Pad 6 pullup enable */ - __IOM uint32_t PAD6INPEN : 1; /*!< [17..17] Pad 6 input enable */ - __IOM uint32_t PAD6STRNG : 1; /*!< [18..18] Pad 6 drive strength */ - __IOM uint32_t PAD6FNCSEL : 3; /*!< [21..19] Pad 6 function select */ - __IOM uint32_t PAD6RSEL : 2; /*!< [23..22] Pad 6 pullup resistor selection. */ - __IOM uint32_t PAD7PULL : 1; /*!< [24..24] Pad 7 pullup enable */ - __IOM uint32_t PAD7INPEN : 1; /*!< [25..25] Pad 7 input enable */ - __IOM uint32_t PAD7STRNG : 1; /*!< [26..26] Pad 7 drive strength */ - __IOM uint32_t PAD7FNCSEL : 3; /*!< [29..27] Pad 7 function select */ - } PADREGB_b; - } ; - - union { - __IOM uint32_t PADREGC; /*!< (@ 0x00000008) Pad Configuration Register C (Pads 8-11) */ - - struct { - __IOM uint32_t PAD8PULL : 1; /*!< [0..0] Pad 8 pullup enable */ - __IOM uint32_t PAD8INPEN : 1; /*!< [1..1] Pad 8 input enable */ - __IOM uint32_t PAD8STRNG : 1; /*!< [2..2] Pad 8 drive strength */ - __IOM uint32_t PAD8FNCSEL : 3; /*!< [5..3] Pad 8 function select */ - __IOM uint32_t PAD8RSEL : 2; /*!< [7..6] Pad 8 pullup resistor selection. */ - __IOM uint32_t PAD9PULL : 1; /*!< [8..8] Pad 9 pullup enable */ - __IOM uint32_t PAD9INPEN : 1; /*!< [9..9] Pad 9 input enable */ - __IOM uint32_t PAD9STRNG : 1; /*!< [10..10] Pad 9 drive strength */ - __IOM uint32_t PAD9FNCSEL : 3; /*!< [13..11] Pad 9 function select */ - __IOM uint32_t PAD9RSEL : 2; /*!< [15..14] Pad 9 pullup resistor selection */ - __IOM uint32_t PAD10PULL : 1; /*!< [16..16] Pad 10 pullup enable */ - __IOM uint32_t PAD10INPEN : 1; /*!< [17..17] Pad 10 input enable */ - __IOM uint32_t PAD10STRNG : 1; /*!< [18..18] Pad 10 drive strength */ - __IOM uint32_t PAD10FNCSEL : 3; /*!< [21..19] Pad 10 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD11PULL : 1; /*!< [24..24] Pad 11 pullup enable */ - __IOM uint32_t PAD11INPEN : 1; /*!< [25..25] Pad 11 input enable */ - __IOM uint32_t PAD11STRNG : 1; /*!< [26..26] Pad 11 drive strength */ - __IOM uint32_t PAD11FNCSEL : 3; /*!< [29..27] Pad 11 function select */ - } PADREGC_b; - } ; - - union { - __IOM uint32_t PADREGD; /*!< (@ 0x0000000C) Pad Configuration Register D (Pads 12-15) */ - - struct { - __IOM uint32_t PAD12PULL : 1; /*!< [0..0] Pad 12 pullup enable */ - __IOM uint32_t PAD12INPEN : 1; /*!< [1..1] Pad 12 input enable */ - __IOM uint32_t PAD12STRNG : 1; /*!< [2..2] Pad 12 drive strength */ - __IOM uint32_t PAD12FNCSEL : 3; /*!< [5..3] Pad 12 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD13PULL : 1; /*!< [8..8] Pad 13 pullup enable */ - __IOM uint32_t PAD13INPEN : 1; /*!< [9..9] Pad 13 input enable */ - __IOM uint32_t PAD13STRNG : 1; /*!< [10..10] Pad 13 drive strength */ - __IOM uint32_t PAD13FNCSEL : 3; /*!< [13..11] Pad 13 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD14PULL : 1; /*!< [16..16] Pad 14 pullup enable */ - __IOM uint32_t PAD14INPEN : 1; /*!< [17..17] Pad 14 input enable */ - __IOM uint32_t PAD14STRNG : 1; /*!< [18..18] Pad 14 drive strength */ - __IOM uint32_t PAD14FNCSEL : 3; /*!< [21..19] Pad 14 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD15PULL : 1; /*!< [24..24] Pad 15 pullup enable */ - __IOM uint32_t PAD15INPEN : 1; /*!< [25..25] Pad 15 input enable */ - __IOM uint32_t PAD15STRNG : 1; /*!< [26..26] Pad 15 drive strength */ - __IOM uint32_t PAD15FNCSEL : 3; /*!< [29..27] Pad 15 function select */ - } PADREGD_b; - } ; - - union { - __IOM uint32_t PADREGE; /*!< (@ 0x00000010) Pad Configuration Register E (Pads 16-19) */ - - struct { - __IOM uint32_t PAD16PULL : 1; /*!< [0..0] Pad 16 pullup enable */ - __IOM uint32_t PAD16INPEN : 1; /*!< [1..1] Pad 16 input enable */ - __IOM uint32_t PAD16STRNG : 1; /*!< [2..2] Pad 16 drive strength */ - __IOM uint32_t PAD16FNCSEL : 3; /*!< [5..3] Pad 16 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD17PULL : 1; /*!< [8..8] Pad 17 pullup enable */ - __IOM uint32_t PAD17INPEN : 1; /*!< [9..9] Pad 17 input enable */ - __IOM uint32_t PAD17STRNG : 1; /*!< [10..10] Pad 17 drive strength */ - __IOM uint32_t PAD17FNCSEL : 3; /*!< [13..11] Pad 17 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD18PULL : 1; /*!< [16..16] Pad 18 pullup enable */ - __IOM uint32_t PAD18INPEN : 1; /*!< [17..17] Pad 18 input enable */ - __IOM uint32_t PAD18STRNG : 1; /*!< [18..18] Pad 18 drive strength */ - __IOM uint32_t PAD18FNCSEL : 3; /*!< [21..19] Pad 18 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD19PULL : 1; /*!< [24..24] Pad 19 pullup enable */ - __IOM uint32_t PAD19INPEN : 1; /*!< [25..25] Pad 19 input enable */ - __IOM uint32_t PAD19STRNG : 1; /*!< [26..26] Pad 19 drive strength */ - __IOM uint32_t PAD19FNCSEL : 3; /*!< [29..27] Pad 19 function select */ - } PADREGE_b; - } ; - - union { - __IOM uint32_t PADREGF; /*!< (@ 0x00000014) Pad Configuration Register F (Pads 20-23) */ - - struct { - __IOM uint32_t PAD20PULL : 1; /*!< [0..0] Pad 20 pulldown enable */ - __IOM uint32_t PAD20INPEN : 1; /*!< [1..1] Pad 20 input enable */ - __IOM uint32_t PAD20STRNG : 1; /*!< [2..2] Pad 20 drive strength */ - __IOM uint32_t PAD20FNCSEL : 3; /*!< [5..3] Pad 20 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD21PULL : 1; /*!< [8..8] Pad 21 pullup enable */ - __IOM uint32_t PAD21INPEN : 1; /*!< [9..9] Pad 21 input enable */ - __IOM uint32_t PAD21STRNG : 1; /*!< [10..10] Pad 21 drive strength */ - __IOM uint32_t PAD21FNCSEL : 3; /*!< [13..11] Pad 21 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD22PULL : 1; /*!< [16..16] Pad 22 pullup enable */ - __IOM uint32_t PAD22INPEN : 1; /*!< [17..17] Pad 22 input enable */ - __IOM uint32_t PAD22STRNG : 1; /*!< [18..18] Pad 22 drive strength */ - __IOM uint32_t PAD22FNCSEL : 3; /*!< [21..19] Pad 22 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD23PULL : 1; /*!< [24..24] Pad 23 pullup enable */ - __IOM uint32_t PAD23INPEN : 1; /*!< [25..25] Pad 23 input enable */ - __IOM uint32_t PAD23STRNG : 1; /*!< [26..26] Pad 23 drive strength */ - __IOM uint32_t PAD23FNCSEL : 3; /*!< [29..27] Pad 23 function select */ - } PADREGF_b; - } ; - - union { - __IOM uint32_t PADREGG; /*!< (@ 0x00000018) Pad Configuration Register G (Pads 24-27) */ - - struct { - __IOM uint32_t PAD24PULL : 1; /*!< [0..0] Pad 24 pullup enable */ - __IOM uint32_t PAD24INPEN : 1; /*!< [1..1] Pad 24 input enable */ - __IOM uint32_t PAD24STRNG : 1; /*!< [2..2] Pad 24 drive strength */ - __IOM uint32_t PAD24FNCSEL : 3; /*!< [5..3] Pad 24 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD25PULL : 1; /*!< [8..8] Pad 25 pullup enable */ - __IOM uint32_t PAD25INPEN : 1; /*!< [9..9] Pad 25 input enable */ - __IOM uint32_t PAD25STRNG : 1; /*!< [10..10] Pad 25 drive strength */ - __IOM uint32_t PAD25FNCSEL : 3; /*!< [13..11] Pad 25 function select */ - __IOM uint32_t PAD25RSEL : 2; /*!< [15..14] Pad 25 pullup resistor selection. */ - __IOM uint32_t PAD26PULL : 1; /*!< [16..16] Pad 26 pullup enable */ - __IOM uint32_t PAD26INPEN : 1; /*!< [17..17] Pad 26 input enable */ - __IOM uint32_t PAD26STRNG : 1; /*!< [18..18] Pad 26 drive strength */ - __IOM uint32_t PAD26FNCSEL : 3; /*!< [21..19] Pad 26 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD27PULL : 1; /*!< [24..24] Pad 27 pullup enable */ - __IOM uint32_t PAD27INPEN : 1; /*!< [25..25] Pad 27 input enable */ - __IOM uint32_t PAD27STRNG : 1; /*!< [26..26] Pad 27 drive strength */ - __IOM uint32_t PAD27FNCSEL : 3; /*!< [29..27] Pad 27 function select */ - __IOM uint32_t PAD27RSEL : 2; /*!< [31..30] Pad 27 pullup resistor selection. */ - } PADREGG_b; - } ; - - union { - __IOM uint32_t PADREGH; /*!< (@ 0x0000001C) Pad Configuration Register H (Pads 28-31) */ - - struct { - __IOM uint32_t PAD28PULL : 1; /*!< [0..0] Pad 28 pullup enable */ - __IOM uint32_t PAD28INPEN : 1; /*!< [1..1] Pad 28 input enable */ - __IOM uint32_t PAD28STRNG : 1; /*!< [2..2] Pad 28 drive strength */ - __IOM uint32_t PAD28FNCSEL : 3; /*!< [5..3] Pad 28 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD29PULL : 1; /*!< [8..8] Pad 29 pullup enable */ - __IOM uint32_t PAD29INPEN : 1; /*!< [9..9] Pad 29 input enable */ - __IOM uint32_t PAD29STRNG : 1; /*!< [10..10] Pad 29 drive strength */ - __IOM uint32_t PAD29FNCSEL : 3; /*!< [13..11] Pad 29 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD30PULL : 1; /*!< [16..16] Pad 30 pullup enable */ - __IOM uint32_t PAD30INPEN : 1; /*!< [17..17] Pad 30 input enable */ - __IOM uint32_t PAD30STRNG : 1; /*!< [18..18] Pad 30 drive strength */ - __IOM uint32_t PAD30FNCSEL : 3; /*!< [21..19] Pad 30 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD31PULL : 1; /*!< [24..24] Pad 31 pullup enable */ - __IOM uint32_t PAD31INPEN : 1; /*!< [25..25] Pad 31 input enable */ - __IOM uint32_t PAD31STRNG : 1; /*!< [26..26] Pad 31 drive strength */ - __IOM uint32_t PAD31FNCSEL : 3; /*!< [29..27] Pad 31 function select */ - } PADREGH_b; - } ; - - union { - __IOM uint32_t PADREGI; /*!< (@ 0x00000020) Pad Configuration Register I (Pads 32-35) */ - - struct { - __IOM uint32_t PAD32PULL : 1; /*!< [0..0] Pad 32 pullup enable */ - __IOM uint32_t PAD32INPEN : 1; /*!< [1..1] Pad 32 input enable */ - __IOM uint32_t PAD32STRNG : 1; /*!< [2..2] Pad 32 drive strength */ - __IOM uint32_t PAD32FNCSEL : 3; /*!< [5..3] Pad 32 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD33PULL : 1; /*!< [8..8] Pad 33 pullup enable */ - __IOM uint32_t PAD33INPEN : 1; /*!< [9..9] Pad 33 input enable */ - __IOM uint32_t PAD33STRNG : 1; /*!< [10..10] Pad 33 drive strength */ - __IOM uint32_t PAD33FNCSEL : 3; /*!< [13..11] Pad 33 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD34PULL : 1; /*!< [16..16] Pad 34 pullup enable */ - __IOM uint32_t PAD34INPEN : 1; /*!< [17..17] Pad 34 input enable */ - __IOM uint32_t PAD34STRNG : 1; /*!< [18..18] Pad 34 drive strength */ - __IOM uint32_t PAD34FNCSEL : 3; /*!< [21..19] Pad 34 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD35PULL : 1; /*!< [24..24] Pad 35 pullup enable */ - __IOM uint32_t PAD35INPEN : 1; /*!< [25..25] Pad 35 input enable */ - __IOM uint32_t PAD35STRNG : 1; /*!< [26..26] Pad 35 drive strength */ - __IOM uint32_t PAD35FNCSEL : 3; /*!< [29..27] Pad 35 function select */ - } PADREGI_b; - } ; - - union { - __IOM uint32_t PADREGJ; /*!< (@ 0x00000024) Pad Configuration Register J (Pads 36-39) */ - - struct { - __IOM uint32_t PAD36PULL : 1; /*!< [0..0] Pad 36 pullup enable */ - __IOM uint32_t PAD36INPEN : 1; /*!< [1..1] Pad 36 input enable */ - __IOM uint32_t PAD36STRNG : 1; /*!< [2..2] Pad 36 drive strength */ - __IOM uint32_t PAD36FNCSEL : 3; /*!< [5..3] Pad 36 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD37PULL : 1; /*!< [8..8] Pad 37 pullup enable */ - __IOM uint32_t PAD37INPEN : 1; /*!< [9..9] Pad 37 input enable */ - __IOM uint32_t PAD37STRNG : 1; /*!< [10..10] Pad 37 drive strength */ - __IOM uint32_t PAD37FNCSEL : 3; /*!< [13..11] Pad 37 function select */ - __IM uint32_t : 1; - __IOM uint32_t PAD37PWRDN : 1; /*!< [15..15] Pad 37 VSS power switch enable */ - __IOM uint32_t PAD38PULL : 1; /*!< [16..16] Pad 38 pullup enable */ - __IOM uint32_t PAD38INPEN : 1; /*!< [17..17] Pad 38 input enable */ - __IOM uint32_t PAD38STRNG : 1; /*!< [18..18] Pad 38 drive strength */ - __IOM uint32_t PAD38FNCSEL : 3; /*!< [21..19] Pad 38 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD39PULL : 1; /*!< [24..24] Pad 39 pullup enable */ - __IOM uint32_t PAD39INPEN : 1; /*!< [25..25] Pad 39 input enable */ - __IOM uint32_t PAD39STRNG : 1; /*!< [26..26] Pad 39 drive strength */ - __IOM uint32_t PAD39FNCSEL : 3; /*!< [29..27] Pad 39 function select */ - __IOM uint32_t PAD39RSEL : 2; /*!< [31..30] Pad 39 pullup resistor selection. */ - } PADREGJ_b; - } ; - - union { - __IOM uint32_t PADREGK; /*!< (@ 0x00000028) Pad Configuration Register K (Pads 40-43) */ - - struct { - __IOM uint32_t PAD40PULL : 1; /*!< [0..0] Pad 40 pullup enable */ - __IOM uint32_t PAD40INPEN : 1; /*!< [1..1] Pad 40 input enable */ - __IOM uint32_t PAD40STRNG : 1; /*!< [2..2] Pad 40 drive strength */ - __IOM uint32_t PAD40FNCSEL : 3; /*!< [5..3] Pad 40 function select */ - __IOM uint32_t PAD40RSEL : 2; /*!< [7..6] Pad 40 pullup resistor selection. */ - __IOM uint32_t PAD41PULL : 1; /*!< [8..8] Pad 41 pullup enable */ - __IOM uint32_t PAD41INPEN : 1; /*!< [9..9] Pad 41 input enable */ - __IOM uint32_t PAD41STRNG : 1; /*!< [10..10] Pad 41 drive strength */ - __IOM uint32_t PAD41FNCSEL : 3; /*!< [13..11] Pad 41 function select */ - __IM uint32_t : 1; - __IOM uint32_t PAD41PWRDN : 1; /*!< [15..15] Pad 41 power switch enable */ - __IOM uint32_t PAD42PULL : 1; /*!< [16..16] Pad 42 pullup enable */ - __IOM uint32_t PAD42INPEN : 1; /*!< [17..17] Pad 42 input enable */ - __IOM uint32_t PAD42STRNG : 1; /*!< [18..18] Pad 42 drive strength */ - __IOM uint32_t PAD42FNCSEL : 3; /*!< [21..19] Pad 42 function select */ - __IOM uint32_t PAD42RSEL : 2; /*!< [23..22] Pad 42 pullup resistor selection. */ - __IOM uint32_t PAD43PULL : 1; /*!< [24..24] Pad 43 pullup enable */ - __IOM uint32_t PAD43INPEN : 1; /*!< [25..25] Pad 43 input enable */ - __IOM uint32_t PAD43STRNG : 1; /*!< [26..26] Pad 43 drive strength */ - __IOM uint32_t PAD43FNCSEL : 3; /*!< [29..27] Pad 43 function select */ - __IOM uint32_t PAD43RSEL : 2; /*!< [31..30] Pad 43 pullup resistor selection. */ - } PADREGK_b; - } ; - - union { - __IOM uint32_t PADREGL; /*!< (@ 0x0000002C) Pad Configuration Register L (Pads 44-47) */ - - struct { - __IOM uint32_t PAD44PULL : 1; /*!< [0..0] Pad 44 pullup enable */ - __IOM uint32_t PAD44INPEN : 1; /*!< [1..1] Pad 44 input enable */ - __IOM uint32_t PAD44STRNG : 1; /*!< [2..2] Pad 44 drive strength */ - __IOM uint32_t PAD44FNCSEL : 3; /*!< [5..3] Pad 44 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD45PULL : 1; /*!< [8..8] Pad 45 pullup enable */ - __IOM uint32_t PAD45INPEN : 1; /*!< [9..9] Pad 45 input enable */ - __IOM uint32_t PAD45STRNG : 1; /*!< [10..10] Pad 45 drive strength */ - __IOM uint32_t PAD45FNCSEL : 3; /*!< [13..11] Pad 45 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD46PULL : 1; /*!< [16..16] Pad 46 pullup enable */ - __IOM uint32_t PAD46INPEN : 1; /*!< [17..17] Pad 46 input enable */ - __IOM uint32_t PAD46STRNG : 1; /*!< [18..18] Pad 46 drive strength */ - __IOM uint32_t PAD46FNCSEL : 3; /*!< [21..19] Pad 46 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD47PULL : 1; /*!< [24..24] Pad 47 pullup enable */ - __IOM uint32_t PAD47INPEN : 1; /*!< [25..25] Pad 47 input enable */ - __IOM uint32_t PAD47STRNG : 1; /*!< [26..26] Pad 47 drive strength */ - __IOM uint32_t PAD47FNCSEL : 3; /*!< [29..27] Pad 47 function select */ - } PADREGL_b; - } ; - - union { - __IOM uint32_t PADREGM; /*!< (@ 0x00000030) Pad Configuration Register M (Pads 48-51) */ - - struct { - __IOM uint32_t PAD48PULL : 1; /*!< [0..0] Pad 48 pullup enable */ - __IOM uint32_t PAD48INPEN : 1; /*!< [1..1] Pad 48 input enable */ - __IOM uint32_t PAD48STRNG : 1; /*!< [2..2] Pad 48 drive strength */ - __IOM uint32_t PAD48FNCSEL : 3; /*!< [5..3] Pad 48 function select */ - __IOM uint32_t PAD48RSEL : 2; /*!< [7..6] Pad 48 pullup resistor selection. */ - __IOM uint32_t PAD49PULL : 1; /*!< [8..8] Pad 49 pullup enable */ - __IOM uint32_t PAD49INPEN : 1; /*!< [9..9] Pad 49 input enable */ - __IOM uint32_t PAD49STRNG : 1; /*!< [10..10] Pad 49 drive strength */ - __IOM uint32_t PAD49FNCSEL : 3; /*!< [13..11] Pad 49 function select */ - __IOM uint32_t PAD49RSEL : 2; /*!< [15..14] Pad 49 pullup resistor selection. */ - __IOM uint32_t PAD50PULL : 1; /*!< [16..16] Pad 50 pullup enable */ - __IOM uint32_t PAD50INPEN : 1; /*!< [17..17] Pad 50 input enable */ - __IOM uint32_t PAD50STRNG : 1; /*!< [18..18] Pad 50 drive strength */ - __IOM uint32_t PAD50FNCSEL : 3; /*!< [21..19] Pad 50 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD51PULL : 1; /*!< [24..24] Pad 51 pullup enable */ - __IOM uint32_t PAD51INPEN : 1; /*!< [25..25] Pad 51 input enable */ - __IOM uint32_t PAD51STRNG : 1; /*!< [26..26] Pad 51 drive strength */ - __IOM uint32_t PAD51FNCSEL : 3; /*!< [29..27] Pad 51 function select */ - } PADREGM_b; - } ; - - union { - __IOM uint32_t PADREGN; /*!< (@ 0x00000034) Pad Configuration Register N (Pads 52-55) */ - - struct { - __IOM uint32_t PAD52PULL : 1; /*!< [0..0] Pad 52 pullup enable */ - __IOM uint32_t PAD52INPEN : 1; /*!< [1..1] Pad 52 input enable */ - __IOM uint32_t PAD52STRNG : 1; /*!< [2..2] Pad 52 drive strength */ - __IOM uint32_t PAD52FNCSEL : 3; /*!< [5..3] Pad 52 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD53PULL : 1; /*!< [8..8] Pad 53 pullup enable */ - __IOM uint32_t PAD53INPEN : 1; /*!< [9..9] Pad 53 input enable */ - __IOM uint32_t PAD53STRNG : 1; /*!< [10..10] Pad 53 drive strength */ - __IOM uint32_t PAD53FNCSEL : 3; /*!< [13..11] Pad 53 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD54PULL : 1; /*!< [16..16] Pad 54 pullup enable */ - __IOM uint32_t PAD54INPEN : 1; /*!< [17..17] Pad 54 input enable */ - __IOM uint32_t PAD54STRNG : 1; /*!< [18..18] Pad 54 drive strength */ - __IOM uint32_t PAD54FNCSEL : 3; /*!< [21..19] Pad 54 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD55PULL : 1; /*!< [24..24] Pad 55 pullup enable */ - __IOM uint32_t PAD55INPEN : 1; /*!< [25..25] Pad 55 input enable */ - __IOM uint32_t PAD55STRNG : 1; /*!< [26..26] Pad 55 drive strength */ - __IOM uint32_t PAD55FNCSEL : 3; /*!< [29..27] Pad 55 function select */ - } PADREGN_b; - } ; - - union { - __IOM uint32_t PADREGO; /*!< (@ 0x00000038) Pad Configuration Register O (Pads 56-59) */ - - struct { - __IOM uint32_t PAD56PULL : 1; /*!< [0..0] Pad 56 pullup enable */ - __IOM uint32_t PAD56INPEN : 1; /*!< [1..1] Pad 56 input enable */ - __IOM uint32_t PAD56STRNG : 1; /*!< [2..2] Pad 56 drive strength */ - __IOM uint32_t PAD56FNCSEL : 3; /*!< [5..3] Pad 56 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD57PULL : 1; /*!< [8..8] Pad 57 pullup enable */ - __IOM uint32_t PAD57INPEN : 1; /*!< [9..9] Pad 57 input enable */ - __IOM uint32_t PAD57STRNG : 1; /*!< [10..10] Pad 57 drive strength */ - __IOM uint32_t PAD57FNCSEL : 3; /*!< [13..11] Pad 57 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD58PULL : 1; /*!< [16..16] Pad 58 pullup enable */ - __IOM uint32_t PAD58INPEN : 1; /*!< [17..17] Pad 58 input enable */ - __IOM uint32_t PAD58STRNG : 1; /*!< [18..18] Pad 58 drive strength */ - __IOM uint32_t PAD58FNCSEL : 3; /*!< [21..19] Pad 58 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD59PULL : 1; /*!< [24..24] Pad 59 pullup enable */ - __IOM uint32_t PAD59INPEN : 1; /*!< [25..25] Pad 59 input enable */ - __IOM uint32_t PAD59STRNG : 1; /*!< [26..26] Pad 59 drive strength */ - __IOM uint32_t PAD59FNCSEL : 3; /*!< [29..27] Pad 59 function select */ - } PADREGO_b; - } ; - - union { - __IOM uint32_t PADREGP; /*!< (@ 0x0000003C) Pad Configuration Register P (Pads 60-63) */ - - struct { - __IOM uint32_t PAD60PULL : 1; /*!< [0..0] Pad 60 pullup enable */ - __IOM uint32_t PAD60INPEN : 1; /*!< [1..1] Pad 60 input enable */ - __IOM uint32_t PAD60STRNG : 1; /*!< [2..2] Pad 60 drive strength */ - __IOM uint32_t PAD60FNCSEL : 3; /*!< [5..3] Pad 60 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD61PULL : 1; /*!< [8..8] Pad 61 pullup enable */ - __IOM uint32_t PAD61INPEN : 1; /*!< [9..9] Pad 61 input enable */ - __IOM uint32_t PAD61STRNG : 1; /*!< [10..10] Pad 61 drive strength */ - __IOM uint32_t PAD61FNCSEL : 3; /*!< [13..11] Pad 61 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD62PULL : 1; /*!< [16..16] Pad 62 pullup enable */ - __IOM uint32_t PAD62INPEN : 1; /*!< [17..17] Pad 62 input enable */ - __IOM uint32_t PAD62STRNG : 1; /*!< [18..18] Pad 62 drive strength */ - __IOM uint32_t PAD62FNCSEL : 3; /*!< [21..19] Pad 62 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD63PULL : 1; /*!< [24..24] Pad 63 pullup enable */ - __IOM uint32_t PAD63INPEN : 1; /*!< [25..25] Pad 63 input enable */ - __IOM uint32_t PAD63STRNG : 1; /*!< [26..26] Pad 63 drive strength */ - __IOM uint32_t PAD63FNCSEL : 3; /*!< [29..27] Pad 63 function select */ - } PADREGP_b; - } ; - - union { - __IOM uint32_t PADREGQ; /*!< (@ 0x00000040) Pad Configuration Register Q (Pads 64-67) */ - - struct { - __IOM uint32_t PAD64PULL : 1; /*!< [0..0] Pad 64 pullup enable */ - __IOM uint32_t PAD64INPEN : 1; /*!< [1..1] Pad 64 input enable */ - __IOM uint32_t PAD64STRNG : 1; /*!< [2..2] Pad 64 drive strength */ - __IOM uint32_t PAD64FNCSEL : 3; /*!< [5..3] Pad 64 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD65PULL : 1; /*!< [8..8] Pad 65 pullup enable */ - __IOM uint32_t PAD65INPEN : 1; /*!< [9..9] Pad 65 input enable */ - __IOM uint32_t PAD65STRNG : 1; /*!< [10..10] Pad 65 drive strength */ - __IOM uint32_t PAD65FNCSEL : 3; /*!< [13..11] Pad 65 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD66PULL : 1; /*!< [16..16] Pad 66 pullup enable */ - __IOM uint32_t PAD66INPEN : 1; /*!< [17..17] Pad 66 input enable */ - __IOM uint32_t PAD66STRNG : 1; /*!< [18..18] Pad 66 drive strength */ - __IOM uint32_t PAD66FNCSEL : 3; /*!< [21..19] Pad 66 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD67PULL : 1; /*!< [24..24] Pad 67 pullup enable */ - __IOM uint32_t PAD67INPEN : 1; /*!< [25..25] Pad 67 input enable */ - __IOM uint32_t PAD67STRNG : 1; /*!< [26..26] Pad 67 drive strength */ - __IOM uint32_t PAD67FNCSEL : 3; /*!< [29..27] Pad 67 function select */ - } PADREGQ_b; - } ; - - union { - __IOM uint32_t PADREGR; /*!< (@ 0x00000044) Pad Configuration Register R (Pads 68-71) */ - - struct { - __IOM uint32_t PAD68PULL : 1; /*!< [0..0] Pad 68 pullup enable */ - __IOM uint32_t PAD68INPEN : 1; /*!< [1..1] Pad 68 input enable */ - __IOM uint32_t PAD68STRNG : 1; /*!< [2..2] Pad 68 drive strength */ - __IOM uint32_t PAD68FNCSEL : 3; /*!< [5..3] Pad 68 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD69PULL : 1; /*!< [8..8] Pad 69 pullup enable */ - __IOM uint32_t PAD69INPEN : 1; /*!< [9..9] Pad 69 input enable */ - __IOM uint32_t PAD69STRNG : 1; /*!< [10..10] Pad 69 drive strength */ - __IOM uint32_t PAD69FNCSEL : 3; /*!< [13..11] Pad 69 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD70PULL : 1; /*!< [16..16] Pad 70 pullup enable */ - __IOM uint32_t PAD70INPEN : 1; /*!< [17..17] Pad 70 input enable */ - __IOM uint32_t PAD70STRNG : 1; /*!< [18..18] Pad 70 drive strength */ - __IOM uint32_t PAD70FNCSEL : 3; /*!< [21..19] Pad 70 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD71PULL : 1; /*!< [24..24] Pad 71 pullup enable */ - __IOM uint32_t PAD71INPEN : 1; /*!< [25..25] Pad 71 input enable */ - __IOM uint32_t PAD71STRNG : 1; /*!< [26..26] Pad 71 drive strength */ - __IOM uint32_t PAD71FNCSEL : 3; /*!< [29..27] Pad 71 function select */ - } PADREGR_b; - } ; - - union { - __IOM uint32_t PADREGS; /*!< (@ 0x00000048) Pad Configuration Register S (Pads 72-75) */ - - struct { - __IOM uint32_t PAD72PULL : 1; /*!< [0..0] Pad 72 pullup enable */ - __IOM uint32_t PAD72INPEN : 1; /*!< [1..1] Pad 72 input enable */ - __IOM uint32_t PAD72STRNG : 1; /*!< [2..2] Pad 72 drive strength */ - __IOM uint32_t PAD72FNCSEL : 3; /*!< [5..3] Pad 72 function select */ - __IM uint32_t : 2; - __IOM uint32_t PAD73PULL : 1; /*!< [8..8] Pad 73 pullup enable */ - __IOM uint32_t PAD73INPEN : 1; /*!< [9..9] Pad 73 input enable */ - __IOM uint32_t PAD73STRNG : 1; /*!< [10..10] Pad 73 drive strength */ - __IOM uint32_t PAD73FNCSEL : 3; /*!< [13..11] Pad 73 function select */ - } PADREGS_b; - } ; - - union { - __IOM uint32_t CFGA; /*!< (@ 0x0000004C) GPIO Configuration Register A (Pads 7-0) */ - - struct { - __IOM uint32_t GPIO0INCFG : 1; /*!< [0..0] GPIO0 input enable. */ - __IOM uint32_t GPIO0OUTCFG : 2; /*!< [2..1] GPIO0 output configuration. */ - __IOM uint32_t GPIO0INTD : 1; /*!< [3..3] GPIO0 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO1INCFG : 1; /*!< [4..4] GPIO1 input enable. */ - __IOM uint32_t GPIO1OUTCFG : 2; /*!< [6..5] GPIO1 output configuration. */ - __IOM uint32_t GPIO1INTD : 1; /*!< [7..7] GPIO1 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO2INCFG : 1; /*!< [8..8] GPIO2 input enable. */ - __IOM uint32_t GPIO2OUTCFG : 2; /*!< [10..9] GPIO2 output configuration. */ - __IOM uint32_t GPIO2INTD : 1; /*!< [11..11] GPIO2 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO3INCFG : 1; /*!< [12..12] GPIO3 input enable. */ - __IOM uint32_t GPIO3OUTCFG : 2; /*!< [14..13] GPIO3 output configuration. */ - __IOM uint32_t GPIO3INTD : 1; /*!< [15..15] GPIO3 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO4INCFG : 1; /*!< [16..16] GPIO4 input enable. */ - __IOM uint32_t GPIO4OUTCFG : 2; /*!< [18..17] GPIO4 output configuration. */ - __IOM uint32_t GPIO4INTD : 1; /*!< [19..19] GPIO4 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO5INCFG : 1; /*!< [20..20] GPIO5 input enable. */ - __IOM uint32_t GPIO5OUTCFG : 2; /*!< [22..21] GPIO5 output configuration. */ - __IOM uint32_t GPIO5INTD : 1; /*!< [23..23] GPIO5 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO6INCFG : 1; /*!< [24..24] GPIO6 input enable. */ - __IOM uint32_t GPIO6OUTCFG : 2; /*!< [26..25] GPIO6 output configuration. */ - __IOM uint32_t GPIO6INTD : 1; /*!< [27..27] GPIO6 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO7INCFG : 1; /*!< [28..28] GPIO7 input enable. */ - __IOM uint32_t GPIO7OUTCFG : 2; /*!< [30..29] GPIO7 output configuration. */ - __IOM uint32_t GPIO7INTD : 1; /*!< [31..31] GPIO7 interrupt direction, nCE polarity. */ - } CFGA_b; - } ; - - union { - __IOM uint32_t CFGB; /*!< (@ 0x00000050) GPIO Configuration Register B (Pads 15-8) */ - - struct { - __IOM uint32_t GPIO8INCFG : 1; /*!< [0..0] GPIO8 input enable. */ - __IOM uint32_t GPIO8OUTCFG : 2; /*!< [2..1] GPIO8 output configuration. */ - __IOM uint32_t GPIO8INTD : 1; /*!< [3..3] GPIO8 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO9INCFG : 1; /*!< [4..4] GPIO9 input enable. */ - __IOM uint32_t GPIO9OUTCFG : 2; /*!< [6..5] GPIO9 output configuration. */ - __IOM uint32_t GPIO9INTD : 1; /*!< [7..7] GPIO9 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO10INCFG : 1; /*!< [8..8] GPIO10 input enable. */ - __IOM uint32_t GPIO10OUTCFG : 2; /*!< [10..9] GPIO10 output configuration. */ - __IOM uint32_t GPIO10INTD : 1; /*!< [11..11] GPIO10 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO11INCFG : 1; /*!< [12..12] GPIO11 input enable. */ - __IOM uint32_t GPIO11OUTCFG : 2; /*!< [14..13] GPIO11 output configuration. */ - __IOM uint32_t GPIO11INTD : 1; /*!< [15..15] GPIO11 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO12INCFG : 1; /*!< [16..16] GPIO12 input enable. */ - __IOM uint32_t GPIO12OUTCFG : 2; /*!< [18..17] GPIO12 output configuration. */ - __IOM uint32_t GPIO12INTD : 1; /*!< [19..19] GPIO12 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO13INCFG : 1; /*!< [20..20] GPIO13 input enable. */ - __IOM uint32_t GPIO13OUTCFG : 2; /*!< [22..21] GPIO13 output configuration. */ - __IOM uint32_t GPIO13INTD : 1; /*!< [23..23] GPIO13 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO14INCFG : 1; /*!< [24..24] GPIO14 input enable. */ - __IOM uint32_t GPIO14OUTCFG : 2; /*!< [26..25] GPIO14 output configuration. */ - __IOM uint32_t GPIO14INTD : 1; /*!< [27..27] GPIO14 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO15INCFG : 1; /*!< [28..28] GPIO15 input enable. */ - __IOM uint32_t GPIO15OUTCFG : 2; /*!< [30..29] GPIO15 output configuration. */ - __IOM uint32_t GPIO15INTD : 1; /*!< [31..31] GPIO15 interrupt direction, nCE polarity. */ - } CFGB_b; - } ; - - union { - __IOM uint32_t CFGC; /*!< (@ 0x00000054) GPIO Configuration Register C (Pads 23-16) */ - - struct { - __IOM uint32_t GPIO16INCFG : 1; /*!< [0..0] GPIO16 input enable. */ - __IOM uint32_t GPIO16OUTCFG : 2; /*!< [2..1] GPIO16 output configuration. */ - __IOM uint32_t GPIO16INTD : 1; /*!< [3..3] GPIO16 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO17INCFG : 1; /*!< [4..4] GPIO17 input enable. */ - __IOM uint32_t GPIO17OUTCFG : 2; /*!< [6..5] GPIO17 output configuration. */ - __IOM uint32_t GPIO17INTD : 1; /*!< [7..7] GPIO17 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO18INCFG : 1; /*!< [8..8] GPIO18 input enable. */ - __IOM uint32_t GPIO18OUTCFG : 2; /*!< [10..9] GPIO18 output configuration. */ - __IOM uint32_t GPIO18INTD : 1; /*!< [11..11] GPIO18 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO19INCFG : 1; /*!< [12..12] GPIO19 input enable. */ - __IOM uint32_t GPIO19OUTCFG : 2; /*!< [14..13] GPIO19 output configuration. */ - __IOM uint32_t GPIO19INTD : 1; /*!< [15..15] GPIO19 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO20INCFG : 1; /*!< [16..16] GPIO20 input enable. */ - __IOM uint32_t GPIO20OUTCFG : 2; /*!< [18..17] GPIO20 output configuration. */ - __IOM uint32_t GPIO20INTD : 1; /*!< [19..19] GPIO20 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO21INCFG : 1; /*!< [20..20] GPIO21 input enable. */ - __IOM uint32_t GPIO21OUTCFG : 2; /*!< [22..21] GPIO21 output configuration. */ - __IOM uint32_t GPIO21INTD : 1; /*!< [23..23] GPIO21 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO22INCFG : 1; /*!< [24..24] GPIO22 input enable. */ - __IOM uint32_t GPIO22OUTCFG : 2; /*!< [26..25] GPIO22 output configuration. */ - __IOM uint32_t GPIO22INTD : 1; /*!< [27..27] GPIO22 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO23INCFG : 1; /*!< [28..28] GPIO23 input enable. */ - __IOM uint32_t GPIO23OUTCFG : 2; /*!< [30..29] GPIO23 output configuration. */ - __IOM uint32_t GPIO23INTD : 1; /*!< [31..31] GPIO23 interrupt direction, nCE polarity. */ - } CFGC_b; - } ; - - union { - __IOM uint32_t CFGD; /*!< (@ 0x00000058) GPIO Configuration Register D (Pads 31-24) */ - - struct { - __IOM uint32_t GPIO24INCFG : 1; /*!< [0..0] GPIO24 input enable. */ - __IOM uint32_t GPIO24OUTCFG : 2; /*!< [2..1] GPIO24 output configuration. */ - __IOM uint32_t GPIO24INTD : 1; /*!< [3..3] GPIO24 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO25INCFG : 1; /*!< [4..4] GPIO25 input enable. */ - __IOM uint32_t GPIO25OUTCFG : 2; /*!< [6..5] GPIO25 output configuration. */ - __IOM uint32_t GPIO25INTD : 1; /*!< [7..7] GPIO25 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO26INCFG : 1; /*!< [8..8] GPIO26 input enable. */ - __IOM uint32_t GPIO26OUTCFG : 2; /*!< [10..9] GPIO26 output configuration. */ - __IOM uint32_t GPIO26INTD : 1; /*!< [11..11] GPIO26 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO27INCFG : 1; /*!< [12..12] GPIO27 input enable. */ - __IOM uint32_t GPIO27OUTCFG : 2; /*!< [14..13] GPIO27 output configuration. */ - __IOM uint32_t GPIO27INTD : 1; /*!< [15..15] GPIO27 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO28INCFG : 1; /*!< [16..16] GPIO28 input enable. */ - __IOM uint32_t GPIO28OUTCFG : 2; /*!< [18..17] GPIO28 output configuration. */ - __IOM uint32_t GPIO28INTD : 1; /*!< [19..19] GPIO28 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO29INCFG : 1; /*!< [20..20] GPIO29 input enable. */ - __IOM uint32_t GPIO29OUTCFG : 2; /*!< [22..21] GPIO29 output configuration. */ - __IOM uint32_t GPIO29INTD : 1; /*!< [23..23] GPIO29 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO30INCFG : 1; /*!< [24..24] GPIO30 input enable. */ - __IOM uint32_t GPIO30OUTCFG : 2; /*!< [26..25] GPIO30 output configuration. */ - __IOM uint32_t GPIO30INTD : 1; /*!< [27..27] GPIO30 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO31INCFG : 1; /*!< [28..28] GPIO31 input enable. */ - __IOM uint32_t GPIO31OUTCFG : 2; /*!< [30..29] GPIO31 output configuration. */ - __IOM uint32_t GPIO31INTD : 1; /*!< [31..31] GPIO31 interrupt direction, nCE polarity. */ - } CFGD_b; - } ; - - union { - __IOM uint32_t CFGE; /*!< (@ 0x0000005C) GPIO Configuration Register E (Pads 39-32) */ - - struct { - __IOM uint32_t GPIO32INCFG : 1; /*!< [0..0] GPIO32 input enable. */ - __IOM uint32_t GPIO32OUTCFG : 2; /*!< [2..1] GPIO32 output configuration. */ - __IOM uint32_t GPIO32INTD : 1; /*!< [3..3] GPIO32 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO33INCFG : 1; /*!< [4..4] GPIO33 input enable. */ - __IOM uint32_t GPIO33OUTCFG : 2; /*!< [6..5] GPIO33 output configuration. */ - __IOM uint32_t GPIO33INTD : 1; /*!< [7..7] GPIO33 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO34INCFG : 1; /*!< [8..8] GPIO34 input enable. */ - __IOM uint32_t GPIO34OUTCFG : 2; /*!< [10..9] GPIO34 output configuration. */ - __IOM uint32_t GPIO34INTD : 1; /*!< [11..11] GPIO34 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO35INCFG : 1; /*!< [12..12] GPIO35 input enable. */ - __IOM uint32_t GPIO35OUTCFG : 2; /*!< [14..13] GPIO35 output configuration. */ - __IOM uint32_t GPIO35INTD : 1; /*!< [15..15] GPIO35 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO36INCFG : 1; /*!< [16..16] GPIO36 input enable. */ - __IOM uint32_t GPIO36OUTCFG : 2; /*!< [18..17] GPIO36 output configuration. */ - __IOM uint32_t GPIO36INTD : 1; /*!< [19..19] GPIO36 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO37INCFG : 1; /*!< [20..20] GPIO37 input enable. */ - __IOM uint32_t GPIO37OUTCFG : 2; /*!< [22..21] GPIO37 output configuration. */ - __IOM uint32_t GPIO37INTD : 1; /*!< [23..23] GPIO37 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO38INCFG : 1; /*!< [24..24] GPIO38 input enable. */ - __IOM uint32_t GPIO38OUTCFG : 2; /*!< [26..25] GPIO38 output configuration. */ - __IOM uint32_t GPIO38INTD : 1; /*!< [27..27] GPIO38 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO39INCFG : 1; /*!< [28..28] GPIO39 input enable. */ - __IOM uint32_t GPIO39OUTCFG : 2; /*!< [30..29] GPIO39 output configuration. */ - __IOM uint32_t GPIO39INTD : 1; /*!< [31..31] GPIO39 interrupt direction, nCE polarity. */ - } CFGE_b; - } ; - - union { - __IOM uint32_t CFGF; /*!< (@ 0x00000060) GPIO Configuration Register F (Pads 47-40) */ - - struct { - __IOM uint32_t GPIO40INCFG : 1; /*!< [0..0] GPIO40 input enable. */ - __IOM uint32_t GPIO40OUTCFG : 2; /*!< [2..1] GPIO40 output configuration. */ - __IOM uint32_t GPIO40INTD : 1; /*!< [3..3] GPIO40 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO41INCFG : 1; /*!< [4..4] GPIO41 input enable. */ - __IOM uint32_t GPIO41OUTCFG : 2; /*!< [6..5] GPIO41 output configuration. */ - __IOM uint32_t GPIO41INTD : 1; /*!< [7..7] GPIO41 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO42INCFG : 1; /*!< [8..8] GPIO42 input enable. */ - __IOM uint32_t GPIO42OUTCFG : 2; /*!< [10..9] GPIO42 output configuration. */ - __IOM uint32_t GPIO42INTD : 1; /*!< [11..11] GPIO42 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO43INCFG : 1; /*!< [12..12] GPIO43 input enable. */ - __IOM uint32_t GPIO43OUTCFG : 2; /*!< [14..13] GPIO43 output configuration. */ - __IOM uint32_t GPIO43INTD : 1; /*!< [15..15] GPIO43 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO44INCFG : 1; /*!< [16..16] GPIO44 input enable. */ - __IOM uint32_t GPIO44OUTCFG : 2; /*!< [18..17] GPIO44 output configuration. */ - __IOM uint32_t GPIO44INTD : 1; /*!< [19..19] GPIO44 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO45INCFG : 1; /*!< [20..20] GPIO45 input enable. */ - __IOM uint32_t GPIO45OUTCFG : 2; /*!< [22..21] GPIO45 output configuration. */ - __IOM uint32_t GPIO45INTD : 1; /*!< [23..23] GPIO45 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO46INCFG : 1; /*!< [24..24] GPIO46 input enable. */ - __IOM uint32_t GPIO46OUTCFG : 2; /*!< [26..25] GPIO46 output configuration. */ - __IOM uint32_t GPIO46INTD : 1; /*!< [27..27] GPIO46 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO47INCFG : 1; /*!< [28..28] GPIO47 input enable. */ - __IOM uint32_t GPIO47OUTCFG : 2; /*!< [30..29] GPIO47 output configuration. */ - __IOM uint32_t GPIO47INTD : 1; /*!< [31..31] GPIO47 interrupt direction, nCE polarity. */ - } CFGF_b; - } ; - - union { - __IOM uint32_t CFGG; /*!< (@ 0x00000064) GPIO Configuration Register G (Pads 55-48) */ - - struct { - __IOM uint32_t GPIO48INCFG : 1; /*!< [0..0] GPIO48 input enable. */ - __IOM uint32_t GPIO48OUTCFG : 2; /*!< [2..1] GPIO48 output configuration. */ - __IOM uint32_t GPIO48INTD : 1; /*!< [3..3] GPIO48 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO49INCFG : 1; /*!< [4..4] GPIO49 input enable. */ - __IOM uint32_t GPIO49OUTCFG : 2; /*!< [6..5] GPIO49 output configuration. */ - __IOM uint32_t GPIO49INTD : 1; /*!< [7..7] GPIO49 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO50INCFG : 1; /*!< [8..8] GPIO50 input enable. */ - __IOM uint32_t GPIO50OUTCFG : 2; /*!< [10..9] GPIO50 output configuration. */ - __IOM uint32_t GPIO50INTD : 1; /*!< [11..11] GPIO50 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO51INCFG : 1; /*!< [12..12] GPIO51 input enable. */ - __IOM uint32_t GPIO51OUTCFG : 2; /*!< [14..13] GPIO51 output configuration. */ - __IOM uint32_t GPIO51INTD : 1; /*!< [15..15] GPIO51 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO52INCFG : 1; /*!< [16..16] GPIO52 input enable. */ - __IOM uint32_t GPIO52OUTCFG : 2; /*!< [18..17] GPIO52 output configuration. */ - __IOM uint32_t GPIO52INTD : 1; /*!< [19..19] GPIO52 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO53INCFG : 1; /*!< [20..20] GPIO53 input enable. */ - __IOM uint32_t GPIO53OUTCFG : 2; /*!< [22..21] GPIO53 output configuration. */ - __IOM uint32_t GPIO53INTD : 1; /*!< [23..23] GPIO53 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO54INCFG : 1; /*!< [24..24] GPIO54 input enable. */ - __IOM uint32_t GPIO54OUTCFG : 2; /*!< [26..25] GPIO54 output configuration. */ - __IOM uint32_t GPIO54INTD : 1; /*!< [27..27] GPIO54 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO55INCFG : 1; /*!< [28..28] GPIO55 input enable. */ - __IOM uint32_t GPIO55OUTCFG : 2; /*!< [30..29] GPIO55 output configuration. */ - __IOM uint32_t GPIO55INTD : 1; /*!< [31..31] GPIO55 interrupt direction, nCE polarity. */ - } CFGG_b; - } ; - - union { - __IOM uint32_t CFGH; /*!< (@ 0x00000068) GPIO Configuration Register H (Pads 63-56) */ - - struct { - __IOM uint32_t GPIO56INCFG : 1; /*!< [0..0] GPIO56 input enable. */ - __IOM uint32_t GPIO56OUTCFG : 2; /*!< [2..1] GPIO56 output configuration. */ - __IOM uint32_t GPIO56INTD : 1; /*!< [3..3] GPIO56 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO57INCFG : 1; /*!< [4..4] GPIO57 input enable. */ - __IOM uint32_t GPIO57OUTCFG : 2; /*!< [6..5] GPIO57 output configuration. */ - __IOM uint32_t GPIO57INTD : 1; /*!< [7..7] GPIO57 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO58INCFG : 1; /*!< [8..8] GPIO58 input enable. */ - __IOM uint32_t GPIO58OUTCFG : 2; /*!< [10..9] GPIO58 output configuration. */ - __IOM uint32_t GPIO58INTD : 1; /*!< [11..11] GPIO58 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO59INCFG : 1; /*!< [12..12] GPIO59 input enable. */ - __IOM uint32_t GPIO59OUTCFG : 2; /*!< [14..13] GPIO59 output configuration. */ - __IOM uint32_t GPIO59INTD : 1; /*!< [15..15] GPIO59 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO60INCFG : 1; /*!< [16..16] GPIO60 input enable. */ - __IOM uint32_t GPIO60OUTCFG : 2; /*!< [18..17] GPIO60 output configuration. */ - __IOM uint32_t GPIO60INTD : 1; /*!< [19..19] GPIO60 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO61INCFG : 1; /*!< [20..20] GPIO61 input enable. */ - __IOM uint32_t GPIO61OUTCFG : 2; /*!< [22..21] GPIO61 output configuration. */ - __IOM uint32_t GPIO61INTD : 1; /*!< [23..23] GPIO61 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO62INCFG : 1; /*!< [24..24] GPIO62 input enable. */ - __IOM uint32_t GPIO62OUTCFG : 2; /*!< [26..25] GPIO62 output configuration. */ - __IOM uint32_t GPIO62INTD : 1; /*!< [27..27] GPIO62 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO63INCFG : 1; /*!< [28..28] GPIO63 input enable. */ - __IOM uint32_t GPIO63OUTCFG : 2; /*!< [30..29] GPIO63 output configuration. */ - __IOM uint32_t GPIO63INTD : 1; /*!< [31..31] GPIO63 interrupt direction, nCE polarity. */ - } CFGH_b; - } ; - - union { - __IOM uint32_t CFGI; /*!< (@ 0x0000006C) GPIO Configuration Register I (Pads 71-64) */ - - struct { - __IOM uint32_t GPIO64INCFG : 1; /*!< [0..0] GPIO64 input enable. */ - __IOM uint32_t GPIO64OUTCFG : 2; /*!< [2..1] GPIO64 output configuration. */ - __IOM uint32_t GPIO64INTD : 1; /*!< [3..3] GPIO64 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO65INCFG : 1; /*!< [4..4] GPIO65 input enable. */ - __IOM uint32_t GPIO65OUTCFG : 2; /*!< [6..5] GPIO65 output configuration. */ - __IOM uint32_t GPIO65INTD : 1; /*!< [7..7] GPIO65 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO66INCFG : 1; /*!< [8..8] GPIO66 input enable. */ - __IOM uint32_t GPIO66OUTCFG : 2; /*!< [10..9] GPIO66 output configuration. */ - __IOM uint32_t GPIO66INTD : 1; /*!< [11..11] GPIO66 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO67INCFG : 1; /*!< [12..12] GPIO67 input enable. */ - __IOM uint32_t GPIO67OUTCFG : 2; /*!< [14..13] GPIO67 output configuration. */ - __IOM uint32_t GPIO67INTD : 1; /*!< [15..15] GPIO67 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO68INCFG : 1; /*!< [16..16] GPIO68 input enable. */ - __IOM uint32_t GPIO68OUTCFG : 2; /*!< [18..17] GPIO68 output configuration. */ - __IOM uint32_t GPIO68INTD : 1; /*!< [19..19] GPIO68 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO69INCFG : 1; /*!< [20..20] GPIO69 input enable. */ - __IOM uint32_t GPIO69OUTCFG : 2; /*!< [22..21] GPIO69 output configuration. */ - __IOM uint32_t GPIO69INTD : 1; /*!< [23..23] GPIO69 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO70INCFG : 1; /*!< [24..24] GPIO70 input enable. */ - __IOM uint32_t GPIO70OUTCFG : 2; /*!< [26..25] GPIO70 output configuration. */ - __IOM uint32_t GPIO70INTD : 1; /*!< [27..27] GPIO70 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO71INCFG : 1; /*!< [28..28] GPIO71 input enable. */ - __IOM uint32_t GPIO71OUTCFG : 2; /*!< [30..29] GPIO71 output configuration. */ - __IOM uint32_t GPIO71INTD : 1; /*!< [31..31] GPIO71 interrupt direction, nCE polarity. */ - } CFGI_b; - } ; - - union { - __IOM uint32_t CFGJ; /*!< (@ 0x00000070) GPIO Configuration Register J (Pads 79-72) */ - - struct { - __IOM uint32_t GPIO72INCFG : 1; /*!< [0..0] GPIO72 input enable. */ - __IOM uint32_t GPIO72OUTCFG : 2; /*!< [2..1] GPIO72 output configuration. */ - __IOM uint32_t GPIO72INTD : 1; /*!< [3..3] GPIO72 interrupt direction, nCE polarity. */ - __IOM uint32_t GPIO73INCFG : 1; /*!< [4..4] GPIO73 input enable. */ - __IOM uint32_t GPIO73OUTCFG : 2; /*!< [6..5] GPIO73 output configuration. */ - __IOM uint32_t GPIO73INTD : 1; /*!< [7..7] GPIO73 interrupt direction, nCE polarity. */ - } CFGJ_b; - } ; - - union { - __IOM uint32_t PADKEY; /*!< (@ 0x00000074) Key Register for all pad configuration registers */ - - struct { - __IOM uint32_t PADKEY : 32; /*!< [31..0] Key register value. */ - } PADKEY_b; - } ; - __IM uint32_t RESERVED[2]; - - union { - __IOM uint32_t RDA; /*!< (@ 0x00000080) GPIO Input Register A */ - - struct { - __IOM uint32_t RDA : 32; /*!< [31..0] GPIO31-0 read data. */ - } RDA_b; - } ; - - union { - __IOM uint32_t RDB; /*!< (@ 0x00000084) GPIO Input Register B */ - - struct { - __IOM uint32_t RDB : 32; /*!< [31..0] GPIO63-32 read data. */ - } RDB_b; - } ; - - union { - __IOM uint32_t RDC; /*!< (@ 0x00000088) GPIO Input Register C */ - - struct { - __IOM uint32_t RDC : 10; /*!< [9..0] GPIO73-64 read data. */ - } RDC_b; - } ; - - union { - __IOM uint32_t WTA; /*!< (@ 0x0000008C) GPIO Output Register A */ - - struct { - __IOM uint32_t WTA : 32; /*!< [31..0] GPIO31-0 write data. */ - } WTA_b; - } ; - - union { - __IOM uint32_t WTB; /*!< (@ 0x00000090) GPIO Output Register B */ - - struct { - __IOM uint32_t WTB : 32; /*!< [31..0] GPIO63-32 write data. */ - } WTB_b; - } ; - - union { - __IOM uint32_t WTC; /*!< (@ 0x00000094) GPIO Output Register C */ - - struct { - __IOM uint32_t WTC : 10; /*!< [9..0] GPIO73-64 write data. */ - } WTC_b; - } ; - - union { - __IOM uint32_t WTSA; /*!< (@ 0x00000098) GPIO Output Register A Set */ - - struct { - __IOM uint32_t WTSA : 32; /*!< [31..0] Set the GPIO31-0 write data. */ - } WTSA_b; - } ; - - union { - __IOM uint32_t WTSB; /*!< (@ 0x0000009C) GPIO Output Register B Set */ - - struct { - __IOM uint32_t WTSB : 32; /*!< [31..0] Set the GPIO63-32 write data. */ - } WTSB_b; - } ; - - union { - __IOM uint32_t WTSC; /*!< (@ 0x000000A0) GPIO Output Register C Set */ - - struct { - __IOM uint32_t WTSC : 10; /*!< [9..0] Set the GPIO73-64 write data. */ - } WTSC_b; - } ; - - union { - __IOM uint32_t WTCA; /*!< (@ 0x000000A4) GPIO Output Register A Clear */ - - struct { - __IOM uint32_t WTCA : 32; /*!< [31..0] Clear the GPIO31-0 write data. */ - } WTCA_b; - } ; - - union { - __IOM uint32_t WTCB; /*!< (@ 0x000000A8) GPIO Output Register B Clear */ - - struct { - __IOM uint32_t WTCB : 32; /*!< [31..0] Clear the GPIO63-32 write data. */ - } WTCB_b; - } ; - - union { - __IOM uint32_t WTCC; /*!< (@ 0x000000AC) GPIO Output Register C Clear */ - - struct { - __IOM uint32_t WTCB : 10; /*!< [9..0] Clear the GPIO73-64 write data. */ - } WTCC_b; - } ; - - union { - __IOM uint32_t ENA; /*!< (@ 0x000000B0) GPIO Enable Register A */ - - struct { - __IOM uint32_t ENA : 32; /*!< [31..0] GPIO31-0 output enables */ - } ENA_b; - } ; - - union { - __IOM uint32_t ENB; /*!< (@ 0x000000B4) GPIO Enable Register B */ - - struct { - __IOM uint32_t ENB : 32; /*!< [31..0] GPIO63-32 output enables */ - } ENB_b; - } ; - - union { - __IOM uint32_t ENC; /*!< (@ 0x000000B8) GPIO Enable Register C */ - - struct { - __IOM uint32_t ENC : 10; /*!< [9..0] GPIO73-64 output enables */ - } ENC_b; - } ; - - union { - __IOM uint32_t ENSA; /*!< (@ 0x000000BC) GPIO Enable Register A Set */ - - struct { - __IOM uint32_t ENSA : 32; /*!< [31..0] Set the GPIO31-0 output enables */ - } ENSA_b; - } ; - - union { - __IOM uint32_t ENSB; /*!< (@ 0x000000C0) GPIO Enable Register B Set */ - - struct { - __IOM uint32_t ENSB : 32; /*!< [31..0] Set the GPIO63-32 output enables */ - } ENSB_b; - } ; - - union { - __IOM uint32_t ENSC; /*!< (@ 0x000000C4) GPIO Enable Register C Set */ - - struct { - __IOM uint32_t ENSC : 10; /*!< [9..0] Set the GPIO73-64 output enables */ - } ENSC_b; - } ; - - union { - __IOM uint32_t ENCA; /*!< (@ 0x000000C8) GPIO Enable Register A Clear */ - - struct { - __IOM uint32_t ENCA : 32; /*!< [31..0] Clear the GPIO31-0 output enables */ - } ENCA_b; - } ; - - union { - __IOM uint32_t ENCB; /*!< (@ 0x000000CC) GPIO Enable Register B Clear */ - - struct { - __IOM uint32_t ENCB : 32; /*!< [31..0] Clear the GPIO49-32 output enables */ - } ENCB_b; - } ; - - union { - __IOM uint32_t ENCC; /*!< (@ 0x000000D0) GPIO Enable Register C Clear */ - - struct { - __IOM uint32_t ENCC : 10; /*!< [9..0] Clear the GPIO73-64 output enables */ - } ENCC_b; - } ; - - union { - __IOM uint32_t STMRCAP; /*!< (@ 0x000000D4) STIMER Capture Control */ - - struct { - __IOM uint32_t STSEL0 : 7; /*!< [6..0] STIMER Capture 0 Select. */ - __IOM uint32_t STPOL0 : 1; /*!< [7..7] STIMER Capture 0 Polarity. */ - __IOM uint32_t STSEL1 : 7; /*!< [14..8] STIMER Capture 1 Select. */ - __IOM uint32_t STPOL1 : 1; /*!< [15..15] STIMER Capture 1 Polarity. */ - __IOM uint32_t STSEL2 : 7; /*!< [22..16] STIMER Capture 2 Select. */ - __IOM uint32_t STPOL2 : 1; /*!< [23..23] STIMER Capture 2 Polarity. */ - __IOM uint32_t STSEL3 : 7; /*!< [30..24] STIMER Capture 3 Select. */ - __IOM uint32_t STPOL3 : 1; /*!< [31..31] STIMER Capture 3 Polarity. */ - } STMRCAP_b; - } ; - - union { - __IOM uint32_t IOM0IRQ; /*!< (@ 0x000000D8) IOM0 Flow Control IRQ Select */ - - struct { - __IOM uint32_t IOM0IRQ : 7; /*!< [6..0] IOMSTR0 IRQ pad select. */ - } IOM0IRQ_b; - } ; - - union { - __IOM uint32_t IOM1IRQ; /*!< (@ 0x000000DC) IOM1 Flow Control IRQ Select */ - - struct { - __IOM uint32_t IOM1IRQ : 7; /*!< [6..0] IOMSTR1 IRQ pad select. */ - } IOM1IRQ_b; - } ; - - union { - __IOM uint32_t IOM2IRQ; /*!< (@ 0x000000E0) IOM2 Flow Control IRQ Select */ - - struct { - __IOM uint32_t IOM2IRQ : 7; /*!< [6..0] IOMSTR2 IRQ pad select. */ - } IOM2IRQ_b; - } ; - - union { - __IOM uint32_t IOM3IRQ; /*!< (@ 0x000000E4) IOM3 Flow Control IRQ Select */ - - struct { - __IOM uint32_t IOM3IRQ : 7; /*!< [6..0] IOMSTR3 IRQ pad select. */ - } IOM3IRQ_b; - } ; - - union { - __IOM uint32_t IOM4IRQ; /*!< (@ 0x000000E8) IOM4 Flow Control IRQ Select */ - - struct { - __IOM uint32_t IOM4IRQ : 7; /*!< [6..0] IOMSTR4 IRQ pad select. */ - } IOM4IRQ_b; - } ; - - union { - __IOM uint32_t IOM5IRQ; /*!< (@ 0x000000EC) IOM5 Flow Control IRQ Select */ - - struct { - __IOM uint32_t IOM5IRQ : 7; /*!< [6..0] IOMSTR5 IRQ pad select. */ - } IOM5IRQ_b; - } ; - - union { - __IOM uint32_t BLEIFIRQ; /*!< (@ 0x000000F0) BLEIF Flow Control IRQ Select */ - - struct { - __IOM uint32_t BLEIFIRQ : 7; /*!< [6..0] BLEIF IRQ pad select. */ - } BLEIFIRQ_b; - } ; - - union { - __IOM uint32_t GPIOOBS; /*!< (@ 0x000000F4) GPIO Observation Mode Sample register */ - - struct { - __IOM uint32_t OBS_DATA : 16; /*!< [15..0] Sample of the data output on the GPIO observation port. - May have async sampling issues, as the data is not synronized - to the read operation. Intended for debug purposes only */ - } GPIOOBS_b; - } ; - - union { - __IOM uint32_t ALTPADCFGA; /*!< (@ 0x000000F8) Alternate Pad Configuration reg0 (Pads 3-0) */ - - struct { - __IOM uint32_t PAD0_DS1 : 1; /*!< [0..0] Pad 0 high order drive strength selection. Used in conjunction - with PAD0STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD0_SR : 1; /*!< [4..4] Pad 3 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD1_DS1 : 1; /*!< [8..8] Pad 1 high order drive strength selection. Used in conjunction - with PAD1STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD1_SR : 1; /*!< [12..12] Pad 3 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD2_DS1 : 1; /*!< [16..16] Pad 2 high order drive strength selection. Used in - conjunction with PAD2STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD2_SR : 1; /*!< [20..20] Pad 3 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD3_DS1 : 1; /*!< [24..24] Pad 3 high order drive strength selection. Used in - conjunction with PAD3STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD3_SR : 1; /*!< [28..28] Pad 3 slew rate selection. */ - } ALTPADCFGA_b; - } ; - - union { - __IOM uint32_t ALTPADCFGB; /*!< (@ 0x000000FC) Alternate Pad Configuration reg0 (Pads 7-4) */ - - struct { - __IOM uint32_t PAD4_DS1 : 1; /*!< [0..0] Pad 4 high order drive strength selection. Used in conjunction - with PAD4STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD4_SR : 1; /*!< [4..4] Pad 7 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD5_DS1 : 1; /*!< [8..8] Pad 5 high order drive strength selection. Used in conjunction - with PAD5STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD5_SR : 1; /*!< [12..12] Pad 7 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD6_DS1 : 1; /*!< [16..16] Pad 6 high order drive strength selection. Used in - conjunction with PAD6STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD6_SR : 1; /*!< [20..20] Pad 7 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD7_DS1 : 1; /*!< [24..24] Pad 7 high order drive strength selection. Used in - conjunction with PAD7STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD7_SR : 1; /*!< [28..28] Pad 7 slew rate selection. */ - } ALTPADCFGB_b; - } ; - - union { - __IOM uint32_t ALTPADCFGC; /*!< (@ 0x00000100) Alternate Pad Configuration reg0 (Pads 11-8) */ - - struct { - __IOM uint32_t PAD8_DS1 : 1; /*!< [0..0] Pad 8 high order drive strength selection. Used in conjunction - with PAD8STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD8_SR : 1; /*!< [4..4] Pad 11 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD9_DS1 : 1; /*!< [8..8] Pad 9 high order drive strength selection. Used in conjunction - with PAD9STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD9_SR : 1; /*!< [12..12] Pad 11 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD10_DS1 : 1; /*!< [16..16] Pad 10 high order drive strength selection. Used in - conjunction with PAD10STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD10_SR : 1; /*!< [20..20] Pad 11 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD11_DS1 : 1; /*!< [24..24] Pad 11 high order drive strength selection. Used in - conjunction with PAD11STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD11_SR : 1; /*!< [28..28] Pad 11 slew rate selection. */ - } ALTPADCFGC_b; - } ; - - union { - __IOM uint32_t ALTPADCFGD; /*!< (@ 0x00000104) Alternate Pad Configuration reg0 (Pads 15-12) */ - - struct { - __IOM uint32_t PAD12_DS1 : 1; /*!< [0..0] Pad 12 high order drive strength selection. Used in conjunction - with PAD12STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD12_SR : 1; /*!< [4..4] Pad 15 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD13_DS1 : 1; /*!< [8..8] Pad 13 high order drive strength selection. Used in conjunction - with PAD13STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD13_SR : 1; /*!< [12..12] Pad 15 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD14_DS1 : 1; /*!< [16..16] Pad 14 high order drive strength selection. Used in - conjunction with PAD14STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD14_SR : 1; /*!< [20..20] Pad 15 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD15_DS1 : 1; /*!< [24..24] Pad 15 high order drive strength selection. Used in - conjunction with PAD15STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD15_SR : 1; /*!< [28..28] Pad 15 slew rate selection. */ - } ALTPADCFGD_b; - } ; - - union { - __IOM uint32_t ALTPADCFGE; /*!< (@ 0x00000108) Alternate Pad Configuration reg0 (Pads 19-16) */ - - struct { - __IOM uint32_t PAD16_DS1 : 1; /*!< [0..0] Pad 16 high order drive strength selection. Used in conjunction - with PAD16STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD16_SR : 1; /*!< [4..4] Pad 19 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD17_DS1 : 1; /*!< [8..8] Pad 17 high order drive strength selection. Used in conjunction - with PAD17STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD17_SR : 1; /*!< [12..12] Pad 19 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD18_DS1 : 1; /*!< [16..16] Pad 18 high order drive strength selection. Used in - conjunction with PAD18STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD18_SR : 1; /*!< [20..20] Pad 19 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD19_DS1 : 1; /*!< [24..24] Pad 19 high order drive strength selection. Used in - conjunction with PAD19STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD19_SR : 1; /*!< [28..28] Pad 19 slew rate selection. */ - } ALTPADCFGE_b; - } ; - - union { - __IOM uint32_t ALTPADCFGF; /*!< (@ 0x0000010C) Alternate Pad Configuration reg0 (Pads 23-20) */ - - struct { - __IOM uint32_t PAD20_DS1 : 1; /*!< [0..0] Pad 20 high order drive strength selection. Used in conjunction - with PAD20STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD20_SR : 1; /*!< [4..4] Pad 23 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD21_DS1 : 1; /*!< [8..8] Pad 21 high order drive strength selection. Used in conjunction - with PAD21STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD21_SR : 1; /*!< [12..12] Pad 23 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD22_DS1 : 1; /*!< [16..16] Pad 22 high order drive strength selection. Used in - conjunction with PAD22STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD22_SR : 1; /*!< [20..20] Pad 23 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD23_DS1 : 1; /*!< [24..24] Pad 23 high order drive strength selection. Used in - conjunction with PAD23STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD23_SR : 1; /*!< [28..28] Pad 23 slew rate selection. */ - } ALTPADCFGF_b; - } ; - - union { - __IOM uint32_t ALTPADCFGG; /*!< (@ 0x00000110) Alternate Pad Configuration reg0 (Pads 27-24) */ - - struct { - __IOM uint32_t PAD24_DS1 : 1; /*!< [0..0] Pad 24 high order drive strength selection. Used in conjunction - with PAD24STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD24_SR : 1; /*!< [4..4] Pad 27 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD25_DS1 : 1; /*!< [8..8] Pad 25 high order drive strength selection. Used in conjunction - with PAD25STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD25_SR : 1; /*!< [12..12] Pad 27 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD26_DS1 : 1; /*!< [16..16] Pad 26 high order drive strength selection. Used in - conjunction with PAD26STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD26_SR : 1; /*!< [20..20] Pad 27 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD27_DS1 : 1; /*!< [24..24] Pad 27 high order drive strength selection. Used in - conjunction with PAD27STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD27_SR : 1; /*!< [28..28] Pad 27 slew rate selection. */ - } ALTPADCFGG_b; - } ; - - union { - __IOM uint32_t ALTPADCFGH; /*!< (@ 0x00000114) Alternate Pad Configuration reg0 (Pads 31-28) */ - - struct { - __IOM uint32_t PAD28_DS1 : 1; /*!< [0..0] Pad 28 high order drive strength selection. Used in conjunction - with PAD28STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD28_SR : 1; /*!< [4..4] Pad 31 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD29_DS1 : 1; /*!< [8..8] Pad 29 high order drive strength selection. Used in conjunction - with PAD29STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD29_SR : 1; /*!< [12..12] Pad 31 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD30_DS1 : 1; /*!< [16..16] Pad 30 high order drive strength selection. Used in - conjunction with PAD30STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD30_SR : 1; /*!< [20..20] Pad 31 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD31_DS1 : 1; /*!< [24..24] Pad 31 high order drive strength selection. Used in - conjunction with PAD31STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD31_SR : 1; /*!< [28..28] Pad 31 slew rate selection. */ - } ALTPADCFGH_b; - } ; - - union { - __IOM uint32_t ALTPADCFGI; /*!< (@ 0x00000118) Alternate Pad Configuration reg0 (Pads 35-32) */ - - struct { - __IOM uint32_t PAD32_DS1 : 1; /*!< [0..0] Pad 32 high order drive strength selection. Used in conjunction - with PAD32STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD32_SR : 1; /*!< [4..4] Pad 35 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD33_DS1 : 1; /*!< [8..8] Pad 33 high order drive strength selection. Used in conjunction - with PAD33STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD33_SR : 1; /*!< [12..12] Pad 35 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD34_DS1 : 1; /*!< [16..16] Pad 34 high order drive strength selection. Used in - conjunction with PAD34STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD34_SR : 1; /*!< [20..20] Pad 35 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD35_DS1 : 1; /*!< [24..24] Pad 35 high order drive strength selection. Used in - conjunction with PAD35STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD35_SR : 1; /*!< [28..28] Pad 35 slew rate selection. */ - } ALTPADCFGI_b; - } ; - - union { - __IOM uint32_t ALTPADCFGJ; /*!< (@ 0x0000011C) Alternate Pad Configuration reg0 (Pads 39-36) */ - - struct { - __IOM uint32_t PAD36_DS1 : 1; /*!< [0..0] Pad 36 high order drive strength selection. Used in conjunction - with PAD36STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD36_SR : 1; /*!< [4..4] Pad 39 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD37_DS1 : 1; /*!< [8..8] Pad 37 high order drive strength selection. Used in conjunction - with PAD37STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD37_SR : 1; /*!< [12..12] Pad 39 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD38_DS1 : 1; /*!< [16..16] Pad 38 high order drive strength selection. Used in - conjunction with PAD38STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD38_SR : 1; /*!< [20..20] Pad 39 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD39_DS1 : 1; /*!< [24..24] Pad 39 high order drive strength selection. Used in - conjunction with PAD39STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD39_SR : 1; /*!< [28..28] Pad 39 slew rate selection. */ - } ALTPADCFGJ_b; - } ; - - union { - __IOM uint32_t ALTPADCFGK; /*!< (@ 0x00000120) Alternate Pad Configuration reg0 (Pads 43-40) */ - - struct { - __IOM uint32_t PAD40_DS1 : 1; /*!< [0..0] Pad 40 high order drive strength selection. Used in conjunction - with PAD40STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD40_SR : 1; /*!< [4..4] Pad 43 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD41_DS1 : 1; /*!< [8..8] Pad 41 high order drive strength selection. Used in conjunction - with PAD41STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD41_SR : 1; /*!< [12..12] Pad 43 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD42_DS1 : 1; /*!< [16..16] Pad 42 high order drive strength selection. Used in - conjunction with PAD42STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD42_SR : 1; /*!< [20..20] Pad 43 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD43_DS1 : 1; /*!< [24..24] Pad 43 high order drive strength selection. Used in - conjunction with PAD43STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD43_SR : 1; /*!< [28..28] Pad 43 slew rate selection. */ - } ALTPADCFGK_b; - } ; - - union { - __IOM uint32_t ALTPADCFGL; /*!< (@ 0x00000124) Alternate Pad Configuration reg0 (Pads 47-44) */ - - struct { - __IOM uint32_t PAD44_DS1 : 1; /*!< [0..0] Pad 44 high order drive strength selection. Used in conjunction - with PAD44STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD44_SR : 1; /*!< [4..4] Pad 47 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD45_DS1 : 1; /*!< [8..8] Pad 45 high order drive strength selection. Used in conjunction - with PAD45STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD45_SR : 1; /*!< [12..12] Pad 47 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD46_DS1 : 1; /*!< [16..16] Pad 46 high order drive strength selection. Used in - conjunction with PAD46STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD46_SR : 1; /*!< [20..20] Pad 47 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD47_DS1 : 1; /*!< [24..24] Pad 47 high order drive strength selection. Used in - conjunction with PAD47STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD47_SR : 1; /*!< [28..28] Pad 47 slew rate selection. */ - } ALTPADCFGL_b; - } ; - - union { - __IOM uint32_t ALTPADCFGM; /*!< (@ 0x00000128) Alternate Pad Configuration reg0 (Pads 51-48) */ - - struct { - __IOM uint32_t PAD48_DS1 : 1; /*!< [0..0] Pad 48 high order drive strength selection. Used in conjunction - with PAD48STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD48_SR : 1; /*!< [4..4] Pad 51 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD49_DS1 : 1; /*!< [8..8] Pad 49 high order drive strength selection. Used in conjunction - with PAD49STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD49_SR : 1; /*!< [12..12] Pad 51 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD50_DS1 : 1; /*!< [16..16] Pad 50 high order drive strength selection. Used in - conjunction with PAD50STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD50_SR : 1; /*!< [20..20] Pad 51 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD51_DS1 : 1; /*!< [24..24] Pad 51 high order drive strength selection. Used in - conjunction with PAD51STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD51_SR : 1; /*!< [28..28] Pad 51 slew rate selection. */ - } ALTPADCFGM_b; - } ; - - union { - __IOM uint32_t ALTPADCFGN; /*!< (@ 0x0000012C) Alternate Pad Configuration reg0 (Pads 55-52) */ - - struct { - __IOM uint32_t PAD52_DS1 : 1; /*!< [0..0] Pad 52 high order drive strength selection. Used in conjunction - with PAD52STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD52_SR : 1; /*!< [4..4] Pad 55 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD53_DS1 : 1; /*!< [8..8] Pad 53 high order drive strength selection. Used in conjunction - with PAD53STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD53_SR : 1; /*!< [12..12] Pad 55 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD54_DS1 : 1; /*!< [16..16] Pad 54 high order drive strength selection. Used in - conjunction with PAD54STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD54_SR : 1; /*!< [20..20] Pad 55 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD55_DS1 : 1; /*!< [24..24] Pad 55 high order drive strength selection. Used in - conjunction with PAD55STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD55_SR : 1; /*!< [28..28] Pad 55 slew rate selection. */ - } ALTPADCFGN_b; - } ; - - union { - __IOM uint32_t ALTPADCFGO; /*!< (@ 0x00000130) Alternate Pad Configuration reg0 (Pads 59-56) */ - - struct { - __IOM uint32_t PAD56_DS1 : 1; /*!< [0..0] Pad 56 high order drive strength selection. Used in conjunction - with PAD56STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD56_SR : 1; /*!< [4..4] Pad 59 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD57_DS1 : 1; /*!< [8..8] Pad 57 high order drive strength selection. Used in conjunction - with PAD57STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD57_SR : 1; /*!< [12..12] Pad 59 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD58_DS1 : 1; /*!< [16..16] Pad 58 high order drive strength selection. Used in - conjunction with PAD58STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD58_SR : 1; /*!< [20..20] Pad 59 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD59_DS1 : 1; /*!< [24..24] Pad 59 high order drive strength selection. Used in - conjunction with PAD59STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD59_SR : 1; /*!< [28..28] Pad 59 slew rate selection. */ - } ALTPADCFGO_b; - } ; - - union { - __IOM uint32_t ALTPADCFGP; /*!< (@ 0x00000134) Alternate Pad Configuration reg0 (Pads 63-60) */ - - struct { - __IOM uint32_t PAD60_DS1 : 1; /*!< [0..0] Pad 60 high order drive strength selection. Used in conjunction - with PAD60STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD60_SR : 1; /*!< [4..4] Pad 63 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD61_DS1 : 1; /*!< [8..8] Pad 61 high order drive strength selection. Used in conjunction - with PAD61STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD61_SR : 1; /*!< [12..12] Pad 63 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD62_DS1 : 1; /*!< [16..16] Pad 62 high order drive strength selection. Used in - conjunction with PAD62STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD62_SR : 1; /*!< [20..20] Pad 63 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD63_DS1 : 1; /*!< [24..24] Pad 63 high order drive strength selection. Used in - conjunction with PAD63STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD63_SR : 1; /*!< [28..28] Pad 63 slew rate selection. */ - } ALTPADCFGP_b; - } ; - - union { - __IOM uint32_t ALTPADCFGQ; /*!< (@ 0x00000138) Alternate Pad Configuration reg0 (Pads 67-64) */ - - struct { - __IOM uint32_t PAD64_DS1 : 1; /*!< [0..0] Pad 64 high order drive strength selection. Used in conjunction - with PAD64STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD64_SR : 1; /*!< [4..4] Pad 67 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD65_DS1 : 1; /*!< [8..8] Pad 65 high order drive strength selection. Used in conjunction - with PAD65STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD65_SR : 1; /*!< [12..12] Pad 67 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD66_DS1 : 1; /*!< [16..16] Pad 66 high order drive strength selection. Used in - conjunction with PAD66STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD66_SR : 1; /*!< [20..20] Pad 67 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD67_DS1 : 1; /*!< [24..24] Pad 67 high order drive strength selection. Used in - conjunction with PAD67STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD67_SR : 1; /*!< [28..28] Pad 67 slew rate selection. */ - } ALTPADCFGQ_b; - } ; - - union { - __IOM uint32_t ALTPADCFGR; /*!< (@ 0x0000013C) Alternate Pad Configuration reg0 (Pads 71-68) */ - - struct { - __IOM uint32_t PAD68_DS1 : 1; /*!< [0..0] Pad 68 high order drive strength selection. Used in conjunction - with PAD68STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD68_SR : 1; /*!< [4..4] Pad 71 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD69_DS1 : 1; /*!< [8..8] Pad 69 high order drive strength selection. Used in conjunction - with PAD69STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD69_SR : 1; /*!< [12..12] Pad 71 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD70_DS1 : 1; /*!< [16..16] Pad 70 high order drive strength selection. Used in - conjunction with PAD70STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD70_SR : 1; /*!< [20..20] Pad 71 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD71_DS1 : 1; /*!< [24..24] Pad 71 high order drive strength selection. Used in - conjunction with PAD71STRNG field to set the pad drive - strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD71_SR : 1; /*!< [28..28] Pad 71 slew rate selection. */ - } ALTPADCFGR_b; - } ; - - union { - __IOM uint32_t ALTPADCFGS; /*!< (@ 0x00000140) Alternate Pad Configuration reg0 (Pads 75-72) */ - - struct { - __IOM uint32_t PAD72_DS1 : 1; /*!< [0..0] Pad 72 high order drive strength selection. Used in conjunction - with PAD72STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD72_SR : 1; /*!< [4..4] Pad 75 slew rate selection. */ - __IM uint32_t : 3; - __IOM uint32_t PAD73_DS1 : 1; /*!< [8..8] Pad 73 high order drive strength selection. Used in conjunction - with PAD73STRNG field to set the pad drive strength. */ - __IM uint32_t : 3; - __IOM uint32_t PAD73_SR : 1; /*!< [12..12] Pad 75 slew rate selection. */ - } ALTPADCFGS_b; - } ; - - union { - __IOM uint32_t SCDET; /*!< (@ 0x00000144) SCARD Card Detect select */ - - struct { - __IOM uint32_t SCDET : 7; /*!< [6..0] SCARD card detect pad select. */ - } SCDET_b; - } ; - - union { - __IOM uint32_t CTENCFG; /*!< (@ 0x00000148) Counter/Timer Enable Config */ - - struct { - __IOM uint32_t EN0 : 1; /*!< [0..0] CT0 Enable */ - __IOM uint32_t EN1 : 1; /*!< [1..1] CT1 Enable */ - __IOM uint32_t EN2 : 1; /*!< [2..2] CT2 Enable */ - __IOM uint32_t EN3 : 1; /*!< [3..3] CT3 Enable */ - __IOM uint32_t EN4 : 1; /*!< [4..4] CT4 Enable */ - __IOM uint32_t EN5 : 1; /*!< [5..5] CT5 Enable */ - __IOM uint32_t EN6 : 1; /*!< [6..6] CT6 Enable */ - __IOM uint32_t EN7 : 1; /*!< [7..7] CT7 Enable */ - __IOM uint32_t EN8 : 1; /*!< [8..8] CT8 Enable */ - __IOM uint32_t EN9 : 1; /*!< [9..9] CT9 Enable */ - __IOM uint32_t EN10 : 1; /*!< [10..10] CT10 Enable */ - __IOM uint32_t EN11 : 1; /*!< [11..11] CT11 Enable */ - __IOM uint32_t EN12 : 1; /*!< [12..12] CT12 Enable */ - __IOM uint32_t EN13 : 1; /*!< [13..13] CT13 Enable */ - __IOM uint32_t EN14 : 1; /*!< [14..14] CT14 Enable */ - __IOM uint32_t EN15 : 1; /*!< [15..15] CT15 Enable */ - __IOM uint32_t EN16 : 1; /*!< [16..16] CT16 Enable */ - __IOM uint32_t EN17 : 1; /*!< [17..17] CT17 Enable */ - __IOM uint32_t EN18 : 1; /*!< [18..18] CT18 Enable */ - __IOM uint32_t EN19 : 1; /*!< [19..19] CT19 Enable */ - __IOM uint32_t EN20 : 1; /*!< [20..20] CT20 Enable */ - __IOM uint32_t EN21 : 1; /*!< [21..21] CT21 Enable */ - __IOM uint32_t EN22 : 1; /*!< [22..22] CT22 Enable */ - __IOM uint32_t EN23 : 1; /*!< [23..23] CT23 Enable */ - __IOM uint32_t EN24 : 1; /*!< [24..24] CT24 Enable */ - __IOM uint32_t EN25 : 1; /*!< [25..25] CT25 Enable */ - __IOM uint32_t EN26 : 1; /*!< [26..26] CT26 Enable */ - __IOM uint32_t EN27 : 1; /*!< [27..27] CT27 Enable */ - __IOM uint32_t EN28 : 1; /*!< [28..28] CT28 Enable */ - __IOM uint32_t EN29 : 1; /*!< [29..29] CT29 Enable */ - __IOM uint32_t EN30 : 1; /*!< [30..30] CT30 Enable */ - __IOM uint32_t EN31 : 1; /*!< [31..31] CT31 Enable */ - } CTENCFG_b; - } ; - __IM uint32_t RESERVED1[45]; - - union { - __IOM uint32_t INT0EN; /*!< (@ 0x00000200) GPIO Interrupt Registers 31-0: Enable */ - - struct { - __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ - __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ - __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ - __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ - __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ - __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ - __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ - __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ - __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ - __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ - __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ - __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ - __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ - __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ - __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ - __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ - __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ - __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ - __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ - __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ - __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ - __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ - __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ - __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ - __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ - __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ - __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ - __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ - __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ - __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ - __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ - __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ - } INT0EN_b; - } ; - - union { - __IOM uint32_t INT0STAT; /*!< (@ 0x00000204) GPIO Interrupt Registers 31-0: Status */ - - struct { - __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ - __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ - __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ - __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ - __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ - __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ - __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ - __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ - __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ - __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ - __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ - __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ - __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ - __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ - __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ - __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ - __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ - __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ - __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ - __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ - __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ - __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ - __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ - __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ - __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ - __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ - __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ - __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ - __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ - __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ - __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ - __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ - } INT0STAT_b; - } ; - - union { - __IOM uint32_t INT0CLR; /*!< (@ 0x00000208) GPIO Interrupt Registers 31-0: Clear */ - - struct { - __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ - __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ - __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ - __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ - __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ - __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ - __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ - __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ - __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ - __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ - __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ - __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ - __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ - __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ - __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ - __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ - __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ - __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ - __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ - __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ - __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ - __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ - __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ - __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ - __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ - __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ - __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ - __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ - __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ - __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ - __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ - __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ - } INT0CLR_b; - } ; - - union { - __IOM uint32_t INT0SET; /*!< (@ 0x0000020C) GPIO Interrupt Registers 31-0: Set */ - - struct { - __IOM uint32_t GPIO0 : 1; /*!< [0..0] GPIO0 interrupt. */ - __IOM uint32_t GPIO1 : 1; /*!< [1..1] GPIO1 interrupt. */ - __IOM uint32_t GPIO2 : 1; /*!< [2..2] GPIO2 interrupt. */ - __IOM uint32_t GPIO3 : 1; /*!< [3..3] GPIO3 interrupt. */ - __IOM uint32_t GPIO4 : 1; /*!< [4..4] GPIO4 interrupt. */ - __IOM uint32_t GPIO5 : 1; /*!< [5..5] GPIO5 interrupt. */ - __IOM uint32_t GPIO6 : 1; /*!< [6..6] GPIO6 interrupt. */ - __IOM uint32_t GPIO7 : 1; /*!< [7..7] GPIO7 interrupt. */ - __IOM uint32_t GPIO8 : 1; /*!< [8..8] GPIO8 interrupt. */ - __IOM uint32_t GPIO9 : 1; /*!< [9..9] GPIO9 interrupt. */ - __IOM uint32_t GPIO10 : 1; /*!< [10..10] GPIO10 interrupt. */ - __IOM uint32_t GPIO11 : 1; /*!< [11..11] GPIO11 interrupt. */ - __IOM uint32_t GPIO12 : 1; /*!< [12..12] GPIO12 interrupt. */ - __IOM uint32_t GPIO13 : 1; /*!< [13..13] GPIO13 interrupt. */ - __IOM uint32_t GPIO14 : 1; /*!< [14..14] GPIO14 interrupt. */ - __IOM uint32_t GPIO15 : 1; /*!< [15..15] GPIO15 interrupt. */ - __IOM uint32_t GPIO16 : 1; /*!< [16..16] GPIO16 interrupt. */ - __IOM uint32_t GPIO17 : 1; /*!< [17..17] GPIO17 interrupt. */ - __IOM uint32_t GPIO18 : 1; /*!< [18..18] GPIO18interrupt. */ - __IOM uint32_t GPIO19 : 1; /*!< [19..19] GPIO19 interrupt. */ - __IOM uint32_t GPIO20 : 1; /*!< [20..20] GPIO20 interrupt. */ - __IOM uint32_t GPIO21 : 1; /*!< [21..21] GPIO21 interrupt. */ - __IOM uint32_t GPIO22 : 1; /*!< [22..22] GPIO22 interrupt. */ - __IOM uint32_t GPIO23 : 1; /*!< [23..23] GPIO23 interrupt. */ - __IOM uint32_t GPIO24 : 1; /*!< [24..24] GPIO24 interrupt. */ - __IOM uint32_t GPIO25 : 1; /*!< [25..25] GPIO25 interrupt. */ - __IOM uint32_t GPIO26 : 1; /*!< [26..26] GPIO26 interrupt. */ - __IOM uint32_t GPIO27 : 1; /*!< [27..27] GPIO27 interrupt. */ - __IOM uint32_t GPIO28 : 1; /*!< [28..28] GPIO28 interrupt. */ - __IOM uint32_t GPIO29 : 1; /*!< [29..29] GPIO29 interrupt. */ - __IOM uint32_t GPIO30 : 1; /*!< [30..30] GPIO30 interrupt. */ - __IOM uint32_t GPIO31 : 1; /*!< [31..31] GPIO31 interrupt. */ - } INT0SET_b; - } ; - __IM uint32_t RESERVED2[4]; - - union { - __IOM uint32_t INT1EN; /*!< (@ 0x00000220) GPIO Interrupt Registers 63-32: Enable */ - - struct { - __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ - __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ - __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ - __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ - __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ - __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ - __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ - __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ - __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ - __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ - __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ - __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ - __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ - __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ - __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ - __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ - __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ - __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ - __IOM uint32_t GPIO50 : 1; /*!< [18..18] GPIO50 interrupt. */ - __IOM uint32_t GPIO51 : 1; /*!< [19..19] GPIO51 interrupt. */ - __IOM uint32_t GPIO52 : 1; /*!< [20..20] GPIO52 interrupt. */ - __IOM uint32_t GPIO53 : 1; /*!< [21..21] GPIO53 interrupt. */ - __IOM uint32_t GPIO54 : 1; /*!< [22..22] GPIO54 interrupt. */ - __IOM uint32_t GPIO55 : 1; /*!< [23..23] GPIO55 interrupt. */ - __IOM uint32_t GPIO56 : 1; /*!< [24..24] GPIO56 interrupt. */ - __IOM uint32_t GPIO57 : 1; /*!< [25..25] GPIO57 interrupt. */ - __IOM uint32_t GPIO58 : 1; /*!< [26..26] GPIO58 interrupt. */ - __IOM uint32_t GPIO59 : 1; /*!< [27..27] GPIO59 interrupt. */ - __IOM uint32_t GPIO60 : 1; /*!< [28..28] GPIO60 interrupt. */ - __IOM uint32_t GPIO61 : 1; /*!< [29..29] GPIO61 interrupt. */ - __IOM uint32_t GPIO62 : 1; /*!< [30..30] GPIO62 interrupt. */ - __IOM uint32_t GPIO63 : 1; /*!< [31..31] GPIO63 interrupt. */ - } INT1EN_b; - } ; - - union { - __IOM uint32_t INT1STAT; /*!< (@ 0x00000224) GPIO Interrupt Registers 63-32: Status */ - - struct { - __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ - __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ - __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ - __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ - __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ - __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ - __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ - __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ - __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ - __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ - __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ - __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ - __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ - __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ - __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ - __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ - __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ - __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ - __IOM uint32_t GPIO50 : 1; /*!< [18..18] GPIO50 interrupt. */ - __IOM uint32_t GPIO51 : 1; /*!< [19..19] GPIO51 interrupt. */ - __IOM uint32_t GPIO52 : 1; /*!< [20..20] GPIO52 interrupt. */ - __IOM uint32_t GPIO53 : 1; /*!< [21..21] GPIO53 interrupt. */ - __IOM uint32_t GPIO54 : 1; /*!< [22..22] GPIO54 interrupt. */ - __IOM uint32_t GPIO55 : 1; /*!< [23..23] GPIO55 interrupt. */ - __IOM uint32_t GPIO56 : 1; /*!< [24..24] GPIO56 interrupt. */ - __IOM uint32_t GPIO57 : 1; /*!< [25..25] GPIO57 interrupt. */ - __IOM uint32_t GPIO58 : 1; /*!< [26..26] GPIO58 interrupt. */ - __IOM uint32_t GPIO59 : 1; /*!< [27..27] GPIO59 interrupt. */ - __IOM uint32_t GPIO60 : 1; /*!< [28..28] GPIO60 interrupt. */ - __IOM uint32_t GPIO61 : 1; /*!< [29..29] GPIO61 interrupt. */ - __IOM uint32_t GPIO62 : 1; /*!< [30..30] GPIO62 interrupt. */ - __IOM uint32_t GPIO63 : 1; /*!< [31..31] GPIO63 interrupt. */ - } INT1STAT_b; - } ; - - union { - __IOM uint32_t INT1CLR; /*!< (@ 0x00000228) GPIO Interrupt Registers 63-32: Clear */ - - struct { - __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ - __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ - __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ - __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ - __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ - __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ - __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ - __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ - __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ - __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ - __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ - __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ - __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ - __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ - __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ - __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ - __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ - __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ - __IOM uint32_t GPIO50 : 1; /*!< [18..18] GPIO50 interrupt. */ - __IOM uint32_t GPIO51 : 1; /*!< [19..19] GPIO51 interrupt. */ - __IOM uint32_t GPIO52 : 1; /*!< [20..20] GPIO52 interrupt. */ - __IOM uint32_t GPIO53 : 1; /*!< [21..21] GPIO53 interrupt. */ - __IOM uint32_t GPIO54 : 1; /*!< [22..22] GPIO54 interrupt. */ - __IOM uint32_t GPIO55 : 1; /*!< [23..23] GPIO55 interrupt. */ - __IOM uint32_t GPIO56 : 1; /*!< [24..24] GPIO56 interrupt. */ - __IOM uint32_t GPIO57 : 1; /*!< [25..25] GPIO57 interrupt. */ - __IOM uint32_t GPIO58 : 1; /*!< [26..26] GPIO58 interrupt. */ - __IOM uint32_t GPIO59 : 1; /*!< [27..27] GPIO59 interrupt. */ - __IOM uint32_t GPIO60 : 1; /*!< [28..28] GPIO60 interrupt. */ - __IOM uint32_t GPIO61 : 1; /*!< [29..29] GPIO61 interrupt. */ - __IOM uint32_t GPIO62 : 1; /*!< [30..30] GPIO62 interrupt. */ - __IOM uint32_t GPIO63 : 1; /*!< [31..31] GPIO63 interrupt. */ - } INT1CLR_b; - } ; - - union { - __IOM uint32_t INT1SET; /*!< (@ 0x0000022C) GPIO Interrupt Registers 63-32: Set */ - - struct { - __IOM uint32_t GPIO32 : 1; /*!< [0..0] GPIO32 interrupt. */ - __IOM uint32_t GPIO33 : 1; /*!< [1..1] GPIO33 interrupt. */ - __IOM uint32_t GPIO34 : 1; /*!< [2..2] GPIO34 interrupt. */ - __IOM uint32_t GPIO35 : 1; /*!< [3..3] GPIO35 interrupt. */ - __IOM uint32_t GPIO36 : 1; /*!< [4..4] GPIO36 interrupt. */ - __IOM uint32_t GPIO37 : 1; /*!< [5..5] GPIO37 interrupt. */ - __IOM uint32_t GPIO38 : 1; /*!< [6..6] GPIO38 interrupt. */ - __IOM uint32_t GPIO39 : 1; /*!< [7..7] GPIO39 interrupt. */ - __IOM uint32_t GPIO40 : 1; /*!< [8..8] GPIO40 interrupt. */ - __IOM uint32_t GPIO41 : 1; /*!< [9..9] GPIO41 interrupt. */ - __IOM uint32_t GPIO42 : 1; /*!< [10..10] GPIO42 interrupt. */ - __IOM uint32_t GPIO43 : 1; /*!< [11..11] GPIO43 interrupt. */ - __IOM uint32_t GPIO44 : 1; /*!< [12..12] GPIO44 interrupt. */ - __IOM uint32_t GPIO45 : 1; /*!< [13..13] GPIO45 interrupt. */ - __IOM uint32_t GPIO46 : 1; /*!< [14..14] GPIO46 interrupt. */ - __IOM uint32_t GPIO47 : 1; /*!< [15..15] GPIO47 interrupt. */ - __IOM uint32_t GPIO48 : 1; /*!< [16..16] GPIO48 interrupt. */ - __IOM uint32_t GPIO49 : 1; /*!< [17..17] GPIO49 interrupt. */ - __IOM uint32_t GPIO50 : 1; /*!< [18..18] GPIO50 interrupt. */ - __IOM uint32_t GPIO51 : 1; /*!< [19..19] GPIO51 interrupt. */ - __IOM uint32_t GPIO52 : 1; /*!< [20..20] GPIO52 interrupt. */ - __IOM uint32_t GPIO53 : 1; /*!< [21..21] GPIO53 interrupt. */ - __IOM uint32_t GPIO54 : 1; /*!< [22..22] GPIO54 interrupt. */ - __IOM uint32_t GPIO55 : 1; /*!< [23..23] GPIO55 interrupt. */ - __IOM uint32_t GPIO56 : 1; /*!< [24..24] GPIO56 interrupt. */ - __IOM uint32_t GPIO57 : 1; /*!< [25..25] GPIO57 interrupt. */ - __IOM uint32_t GPIO58 : 1; /*!< [26..26] GPIO58 interrupt. */ - __IOM uint32_t GPIO59 : 1; /*!< [27..27] GPIO59 interrupt. */ - __IOM uint32_t GPIO60 : 1; /*!< [28..28] GPIO60 interrupt. */ - __IOM uint32_t GPIO61 : 1; /*!< [29..29] GPIO61 interrupt. */ - __IOM uint32_t GPIO62 : 1; /*!< [30..30] GPIO62 interrupt. */ - __IOM uint32_t GPIO63 : 1; /*!< [31..31] GPIO63 interrupt. */ - } INT1SET_b; - } ; - __IM uint32_t RESERVED3[4]; - - union { - __IOM uint32_t INT2EN; /*!< (@ 0x00000240) GPIO Interrupt Registers 73-64: Enable */ - - struct { - __IOM uint32_t GPIO64 : 1; /*!< [0..0] GPIO64 interrupt. */ - __IOM uint32_t GPIO65 : 1; /*!< [1..1] GPIO65 interrupt. */ - __IOM uint32_t GPIO66 : 1; /*!< [2..2] GPIO66 interrupt. */ - __IOM uint32_t GPIO67 : 1; /*!< [3..3] GPIO67 interrupt. */ - __IOM uint32_t GPIO68 : 1; /*!< [4..4] GPIO68 interrupt. */ - __IOM uint32_t GPIO69 : 1; /*!< [5..5] GPIO69 interrupt. */ - __IOM uint32_t GPIO70 : 1; /*!< [6..6] GPIO70 interrupt. */ - __IOM uint32_t GPIO71 : 1; /*!< [7..7] GPIO71 interrupt. */ - __IOM uint32_t GPIO72 : 1; /*!< [8..8] GPIO72 interrupt. */ - __IOM uint32_t GPIO73 : 1; /*!< [9..9] GPIO73 interrupt. */ - } INT2EN_b; - } ; - - union { - __IOM uint32_t INT2STAT; /*!< (@ 0x00000244) GPIO Interrupt Registers 73-64: Status */ - - struct { - __IOM uint32_t GPIO64 : 1; /*!< [0..0] GPIO64 interrupt. */ - __IOM uint32_t GPIO65 : 1; /*!< [1..1] GPIO65 interrupt. */ - __IOM uint32_t GPIO66 : 1; /*!< [2..2] GPIO66 interrupt. */ - __IOM uint32_t GPIO67 : 1; /*!< [3..3] GPIO67 interrupt. */ - __IOM uint32_t GPIO68 : 1; /*!< [4..4] GPIO68 interrupt. */ - __IOM uint32_t GPIO69 : 1; /*!< [5..5] GPIO69 interrupt. */ - __IOM uint32_t GPIO70 : 1; /*!< [6..6] GPIO70 interrupt. */ - __IOM uint32_t GPIO71 : 1; /*!< [7..7] GPIO71 interrupt. */ - __IOM uint32_t GPIO72 : 1; /*!< [8..8] GPIO72 interrupt. */ - __IOM uint32_t GPIO73 : 1; /*!< [9..9] GPIO73 interrupt. */ - } INT2STAT_b; - } ; - - union { - __IOM uint32_t INT2CLR; /*!< (@ 0x00000248) GPIO Interrupt Registers 73-64: Clear */ - - struct { - __IOM uint32_t GPIO64 : 1; /*!< [0..0] GPIO64 interrupt. */ - __IOM uint32_t GPIO65 : 1; /*!< [1..1] GPIO65 interrupt. */ - __IOM uint32_t GPIO66 : 1; /*!< [2..2] GPIO66 interrupt. */ - __IOM uint32_t GPIO67 : 1; /*!< [3..3] GPIO67 interrupt. */ - __IOM uint32_t GPIO68 : 1; /*!< [4..4] GPIO68 interrupt. */ - __IOM uint32_t GPIO69 : 1; /*!< [5..5] GPIO69 interrupt. */ - __IOM uint32_t GPIO70 : 1; /*!< [6..6] GPIO70 interrupt. */ - __IOM uint32_t GPIO71 : 1; /*!< [7..7] GPIO71 interrupt. */ - __IOM uint32_t GPIO72 : 1; /*!< [8..8] GPIO72 interrupt. */ - __IOM uint32_t GPIO73 : 1; /*!< [9..9] GPIO73 interrupt. */ - } INT2CLR_b; - } ; - - union { - __IOM uint32_t INT2SET; /*!< (@ 0x0000024C) GPIO Interrupt Registers 73-64: Set */ - - struct { - __IOM uint32_t GPIO64 : 1; /*!< [0..0] GPIO64 interrupt. */ - __IOM uint32_t GPIO65 : 1; /*!< [1..1] GPIO65 interrupt. */ - __IOM uint32_t GPIO66 : 1; /*!< [2..2] GPIO66 interrupt. */ - __IOM uint32_t GPIO67 : 1; /*!< [3..3] GPIO67 interrupt. */ - __IOM uint32_t GPIO68 : 1; /*!< [4..4] GPIO68 interrupt. */ - __IOM uint32_t GPIO69 : 1; /*!< [5..5] GPIO69 interrupt. */ - __IOM uint32_t GPIO70 : 1; /*!< [6..6] GPIO70 interrupt. */ - __IOM uint32_t GPIO71 : 1; /*!< [7..7] GPIO71 interrupt. */ - __IOM uint32_t GPIO72 : 1; /*!< [8..8] GPIO72 interrupt. */ - __IOM uint32_t GPIO73 : 1; /*!< [9..9] GPIO73 interrupt. */ - } INT2SET_b; - } ; - - union { - __IOM uint32_t DBGCTRL; /*!< (@ 0x00000250) Debug Control */ - - struct { - __IOM uint32_t GCLK0 : 1; /*!< [0..0] Gate IOM0 CLK in SPI mode, allowing external input clock */ - __IOM uint32_t GCLK1 : 1; /*!< [1..1] Gate IOM1 CLK in SPI mode, allowing external input clock */ - __IOM uint32_t GCLK2 : 1; /*!< [2..2] Gate IOM2 CLK in SPI mode, allowing external input clock */ - __IOM uint32_t GCLK3 : 1; /*!< [3..3] Gate IOM3 CLK in SPI mode, allowing external input clock */ - __IOM uint32_t GCLK4 : 1; /*!< [4..4] Gate IOM4 CLK in SPI mode, allowing external input clock */ - __IOM uint32_t GCLK5 : 1; /*!< [5..5] Gate IOM5 CLK in SPI mode, allowing external input clock */ - } DBGCTRL_b; - } ; -} GPIO_Type; /*!< Size = 596 (0x254) */ - - - -/* =========================================================================================================================== */ -/* ================ IOM0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief IO Peripheral Master (IOM0) - */ - -typedef struct { /*!< (@ 0x50004000) IOM0 Structure */ - - union { - __IOM uint32_t FIFO; /*!< (@ 0x00000000) FIFO Access Port */ - - struct { - __IOM uint32_t FIFO : 32; /*!< [31..0] FIFO direct access. Only locations 0 - 3F will return - valid information. */ - } FIFO_b; - } ; - __IM uint32_t RESERVED[63]; - - union { - __IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) FIFO size and remaining slots open values */ - - struct { - __IOM uint32_t FIFO0SIZ : 8; /*!< [7..0] The number of valid data bytes currently in the FIFO - 0 (written by MCU, read by interface) */ - __IOM uint32_t FIFO0REM : 8; /*!< [15..8] The number of remaining data bytes slots currently in - FIFO 0 (written by MCU, read by interface) */ - __IOM uint32_t FIFO1SIZ : 8; /*!< [23..16] The number of valid data bytes currently in FIFO 1 - (written by interface, read by MCU) */ - __IOM uint32_t FIFO1REM : 8; /*!< [31..24] The number of remaining data bytes slots currently - in FIFO 1 (written by interface, read by MCU) */ - } FIFOPTR_b; - } ; - - union { - __IOM uint32_t FIFOTHR; /*!< (@ 0x00000104) FIFO Threshold Configuration */ - - struct { - __IOM uint32_t FIFORTHR : 6; /*!< [5..0] FIFO read threshold in bytes. A value of 0 will disable - the read FIFO level from activating the threshold interrupt. - If this field is non-zero, it will trigger a threshold - interrupt when the read fifo contains FIFORTHR valid bytes - of data, as indicated by the FIFO1SIZ field. This is intended - to signal when a data transfer of FIFORTHR bytes can be - done from the IOM module to the host via the read fifo - to support large IOM read operations. */ - __IM uint32_t : 2; - __IOM uint32_t FIFOWTHR : 6; /*!< [13..8] FIFO write threshold in bytes. A value of 0 will disable - the write FIFO level from activating the threshold interrupt. - If this field is non-zero, it will trigger a threshold - interrupt when the write fifo contains FIFOWTHR free bytes, - as indicated by the FIFO0REM field. This is intended to - signal when a transfer of FIFOWTHR bytes can be done from - the host to the IOM write fifo to support large IOM write - operations. */ - } FIFOTHR_b; - } ; - - union { - __IOM uint32_t FIFOPOP; /*!< (@ 0x00000108) FIFO POP register */ - - struct { - __IOM uint32_t FIFODOUT : 32; /*!< [31..0] This register will return the read data indicated by - the current read pointer on reads. If the POPWR control - bit in the FIFOCTRL register is reset (0), the fifo read - pointer will be advanced by one word as a result of the - read.If the POPWR bit is set (1), the fifo read pointer - will only be advanced after a write operation to this register. - The write data is ignored for this register.If less than - a even word multiple is available, and the command is completed, - the module will return the word containing */ - } FIFOPOP_b; - } ; - - union { - __IOM uint32_t FIFOPUSH; /*!< (@ 0x0000010C) FIFO PUSH register */ - - struct { - __IOM uint32_t FIFODIN : 32; /*!< [31..0] This register is used to write the FIFORAM in FIFO mode - and will cause a push event to occur to the next open slot - within the FIFORAM. Writing to this register will cause - the write point to increment by 1 word(4 bytes). */ - } FIFOPUSH_b; - } ; - - union { - __IOM uint32_t FIFOCTRL; /*!< (@ 0x00000110) FIFO Control Register */ - - struct { - __IOM uint32_t POPWR : 1; /*!< [0..0] Selects the mode in which 'pop' events are done for the - fifo read operations. A value of '1' will prevent a pop - event on a read operation, and will require a write to - the FIFOPOP register to create a pop event.A value of '0' - in this register will allow a pop event to occur on the - read of the FIFOPOP register, and may cause inadvertant - fifo pops when used in a debugging mode. */ - __IOM uint32_t FIFORSTN : 1; /*!< [1..1] Active low manual reset of the fifo. Write to 0 to reset - fifo, and then write to 1 to remove the reset. */ - } FIFOCTRL_b; - } ; - - union { - __IOM uint32_t FIFOLOC; /*!< (@ 0x00000114) FIFO Pointers */ - - struct { - __IOM uint32_t FIFOWPTR : 4; /*!< [3..0] Current FIFO write pointer. Value is the index into the - outgoing FIFO (FIFO0), which is used during write operations - to external devices. */ - __IM uint32_t : 4; - __IOM uint32_t FIFORPTR : 4; /*!< [11..8] Current FIFO read pointer. Used to index into the incoming - FIFO (FIFO1), which is used to store read data returned - from external devices during a read operation. */ - } FIFOLOC_b; - } ; - __IM uint32_t RESERVED1[58]; - - union { - __IOM uint32_t INTEN; /*!< (@ 0x00000200) IO Master Interrupts: Enable */ - - struct { - __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command complete interrupt */ - __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted - when the number of free bytes in the write FIFO equals - or exceeds the WTHR field.For read operations, asserted - when the number of valid bytes in the read FIFO equals - of exceeds the value set in the RTHR field. */ - __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software - tries to pop from an empty fifo. */ - __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software - tries to write to a full fifo. The current operation does - not stop. */ - __IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has - been received on the I2C bus. */ - __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is - a overflow or underflow event */ - __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is - written when an active command is in progress. */ - __IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master - on the bus has signaled a START command. */ - __IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master - on the bus has signaled a STOP command. */ - __IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration - is enabled and has been lost to another master on the bus. */ - __IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed - and the DMA submodule is returned into the idle state */ - __IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the - DMA command. The DMA error could occur when the memory - access specified in the DMA operation is not available - or incorrectly specified. */ - __IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled - in the PAUSEEN register. The interrupt is posted when the - event is enabled within the PAUSEEN register, the mask - is active in the CQIRQMASK field and the event occurs. */ - __IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with - the register address bit 0 set to 1. The low address bits - in the CQ address fields are unused and bit 0 can be used - to trigger an interrupt to indicate when this register - write is performed by the CQ operation. */ - __IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */ - } INTEN_b; - } ; - - union { - __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) IO Master Interrupts: Status */ - - struct { - __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command complete interrupt */ - __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted - when the number of free bytes in the write FIFO equals - or exceeds the WTHR field.For read operations, asserted - when the number of valid bytes in the read FIFO equals - of exceeds the value set in the RTHR field. */ - __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software - tries to pop from an empty fifo. */ - __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software - tries to write to a full fifo. The current operation does - not stop. */ - __IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has - been received on the I2C bus. */ - __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is - a overflow or underflow event */ - __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is - written when an active command is in progress. */ - __IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master - on the bus has signaled a START command. */ - __IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master - on the bus has signaled a STOP command. */ - __IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration - is enabled and has been lost to another master on the bus. */ - __IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed - and the DMA submodule is returned into the idle state */ - __IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the - DMA command. The DMA error could occur when the memory - access specified in the DMA operation is not available - or incorrectly specified. */ - __IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled - in the PAUSEEN register. The interrupt is posted when the - event is enabled within the PAUSEEN register, the mask - is active in the CQIRQMASK field and the event occurs. */ - __IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with - the register address bit 0 set to 1. The low address bits - in the CQ address fields are unused and bit 0 can be used - to trigger an interrupt to indicate when this register - write is performed by the CQ operation. */ - __IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */ - } INTSTAT_b; - } ; - - union { - __IOM uint32_t INTCLR; /*!< (@ 0x00000208) IO Master Interrupts: Clear */ - - struct { - __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command complete interrupt */ - __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted - when the number of free bytes in the write FIFO equals - or exceeds the WTHR field.For read operations, asserted - when the number of valid bytes in the read FIFO equals - of exceeds the value set in the RTHR field. */ - __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software - tries to pop from an empty fifo. */ - __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software - tries to write to a full fifo. The current operation does - not stop. */ - __IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has - been received on the I2C bus. */ - __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is - a overflow or underflow event */ - __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is - written when an active command is in progress. */ - __IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master - on the bus has signaled a START command. */ - __IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master - on the bus has signaled a STOP command. */ - __IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration - is enabled and has been lost to another master on the bus. */ - __IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed - and the DMA submodule is returned into the idle state */ - __IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the - DMA command. The DMA error could occur when the memory - access specified in the DMA operation is not available - or incorrectly specified. */ - __IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled - in the PAUSEEN register. The interrupt is posted when the - event is enabled within the PAUSEEN register, the mask - is active in the CQIRQMASK field and the event occurs. */ - __IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with - the register address bit 0 set to 1. The low address bits - in the CQ address fields are unused and bit 0 can be used - to trigger an interrupt to indicate when this register - write is performed by the CQ operation. */ - __IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */ - } INTCLR_b; - } ; - - union { - __IOM uint32_t INTSET; /*!< (@ 0x0000020C) IO Master Interrupts: Set */ - - struct { - __IOM uint32_t CMDCMP : 1; /*!< [0..0] Command complete interrupt */ - __IOM uint32_t THR : 1; /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted - when the number of free bytes in the write FIFO equals - or exceeds the WTHR field.For read operations, asserted - when the number of valid bytes in the read FIFO equals - of exceeds the value set in the RTHR field. */ - __IOM uint32_t FUNDFL : 1; /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software - tries to pop from an empty fifo. */ - __IOM uint32_t FOVFL : 1; /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software - tries to write to a full fifo. The current operation does - not stop. */ - __IOM uint32_t NAK : 1; /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has - been received on the I2C bus. */ - __IOM uint32_t IACC : 1; /*!< [5..5] illegal FIFO access interrupt. Asserted when there is - a overflow or underflow event */ - __IOM uint32_t ICMD : 1; /*!< [6..6] illegal command interrupt. Asserted when a command is - written when an active command is in progress. */ - __IOM uint32_t START : 1; /*!< [7..7] START command interrupt. Asserted when another master - on the bus has signaled a START command. */ - __IOM uint32_t STOP : 1; /*!< [8..8] STOP command interrupt. Asserted when another master - on the bus has signaled a STOP command. */ - __IOM uint32_t ARB : 1; /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration - is enabled and has been lost to another master on the bus. */ - __IOM uint32_t DCMP : 1; /*!< [10..10] DMA Complete. Processing of the DMA operation has completed - and the DMA submodule is returned into the idle state */ - __IOM uint32_t DERR : 1; /*!< [11..11] DMA Error encountered during the processing of the - DMA command. The DMA error could occur when the memory - access specified in the DMA operation is not available - or incorrectly specified. */ - __IOM uint32_t CQPAUSED : 1; /*!< [12..12] Command queue is paused due to an active event enabled - in the PAUSEEN register. The interrupt is posted when the - event is enabled within the PAUSEEN register, the mask - is active in the CQIRQMASK field and the event occurs. */ - __IOM uint32_t CQUPD : 1; /*!< [13..13] CQ write operation performed a register write with - the register address bit 0 set to 1. The low address bits - in the CQ address fields are unused and bit 0 can be used - to trigger an interrupt to indicate when this register - write is performed by the CQ operation. */ - __IOM uint32_t CQERR : 1; /*!< [14..14] Error during command queue operations */ - } INTSET_b; - } ; - - union { - __IOM uint32_t CLKCFG; /*!< (@ 0x00000210) I/O Clock Configuration */ - - struct { - __IOM uint32_t IOCLKEN : 1; /*!< [0..0] Enable for the interface clock. Must be enabled prior - to executing any IO operations. */ - __IM uint32_t : 7; - __IOM uint32_t FSEL : 3; /*!< [10..8] Select the input clock frequency. */ - __IOM uint32_t DIV3 : 1; /*!< [11..11] Enable divide by 3 of the source IOCLK. Division by - 3 is done before the DIVEN programmable divider, and if - enabledwill provide the divided by 3 clock as the source - to the programmable divider. */ - __IOM uint32_t DIVEN : 1; /*!< [12..12] Enable clock division by TOTPER and LOWPER */ - __IM uint32_t : 3; - __IOM uint32_t LOWPER : 8; /*!< [23..16] Clock low clock count minus 1. This provides the number - of clocks the divided clock will be low when the DIVEN - = 1.Only applicable when DIVEN = 1. */ - __IOM uint32_t TOTPER : 8; /*!< [31..24] Clock total clock count minus 1. This provides the - total period of the divided clock -1 when the DIVEN is - active. Thesource clock is selected by FSEL. Only applicable - when DIVEN = 1. */ - } CLKCFG_b; - } ; - - union { - __IOM uint32_t SUBMODCTRL; /*!< (@ 0x00000214) Submodule control */ - - struct { - __IOM uint32_t SMOD0EN : 1; /*!< [0..0] Submodule 0 enable (1) or disable (0) */ - __IOM uint32_t SMOD0TYPE : 3; /*!< [3..1] Submodule 0 module type. This is the SPI Master interface. */ - __IOM uint32_t SMOD1EN : 1; /*!< [4..4] Submodule 1 enable (1) or disable (0) */ - __IOM uint32_t SMOD1TYPE : 3; /*!< [7..5] Submodule 0 module type. This is the I2C Master interface */ - } SUBMODCTRL_b; - } ; - - union { - __IOM uint32_t CMD; /*!< (@ 0x00000218) Command and offset Register */ - - struct { - __IOM uint32_t CMD : 5; /*!< [4..0] Command for submodule. */ - __IOM uint32_t OFFSETCNT : 2; /*!< [6..5] Number of offset bytes to use for the command - 0, 1, - 2, 3 are valid selections. The second (byte 1) and third - byte (byte 2) are read from the OFFSETHI register, and - the low order byte is pulled from this register in the - OFFSETLO field.Offset bytes are transmitted highest byte - first. EG if offsetcnt == 3, OFFSETHI[15:8] will be transmitted - first, then OFFSETHI[7:0] then OFFSETLO.If offsetcnt == - 2, OFFSETHI[7:0] will be transmitted, then OFFSETLO.If - offsetcnt == 1, only OFFSETLO will be transmitted. */ - __IOM uint32_t CONT : 1; /*!< [7..7] Contine to hold the bus after the current transaction - if set to a 1 with a new command issued. */ - __IOM uint32_t TSIZE : 12; /*!< [19..8] Defines the transaction size in bytes. The offset transfer - is not included in this size. */ - __IOM uint32_t CMDSEL : 2; /*!< [21..20] Command Specific selection information. Not used in - Master I2C. Used as CEn select for Master SPI transactions */ - __IM uint32_t : 2; - __IOM uint32_t OFFSETLO : 8; /*!< [31..24] This register holds the low order byte of offset to - be used in the transaction. The number of offset bytes - to use is set with bits 1:0 of the command. */ - } CMD_b; - } ; - - union { - __IOM uint32_t DCX; /*!< (@ 0x0000021C) DCX Control Register */ - - struct { - __IOM uint32_t CE0OUT : 1; /*!< [0..0] Enable DCX output using CE0 output */ - __IOM uint32_t CE1OUT : 1; /*!< [1..1] Enable DCX output using CE1 output */ - __IOM uint32_t CE2OUT : 1; /*!< [2..2] Enable DCX output using CE2 output */ - __IOM uint32_t CE3OUT : 1; /*!< [3..3] Enable DCX output using CE3 output */ - __IOM uint32_t DCXEN : 1; /*!< [4..4] DCX Signaling Enable The selected DCX signal (unused - CE pin) will be driven low during write of offset byte, - and high during transmission of data bytes. */ - } DCX_b; - } ; - - union { - __IOM uint32_t OFFSETHI; /*!< (@ 0x00000220) High order 2 bytes of 3 byte offset for IO transaction */ - - struct { - __IOM uint32_t OFFSETHI : 16; /*!< [15..0] Holds the high order 2 bytes of the 3 byte addressing/offset - field to use with IO commands. The number of offset bytes - to use is specified in the command register */ - } OFFSETHI_b; - } ; - - union { - __IOM uint32_t CMDSTAT; /*!< (@ 0x00000224) Command status */ - - struct { - __IOM uint32_t CCMD : 5; /*!< [4..0] current command that is being executed */ - __IOM uint32_t CMDSTAT : 3; /*!< [7..5] The current status of the command execution. */ - __IOM uint32_t CTSIZE : 12; /*!< [19..8] The current number of bytes still to be transferred - with this command. This field will count down to zero. */ - } CMDSTAT_b; - } ; - __IM uint32_t RESERVED2[6]; - - union { - __IOM uint32_t DMATRIGEN; /*!< (@ 0x00000240) DMA Trigger Enable Register */ - - struct { - __IOM uint32_t DCMDCMPEN : 1; /*!< [0..0] Trigger DMA upon command complete. Enables the trigger - of the DMA when a command is completed. When this event - is triggered, the number of words transferred will be the - lesser of the remaining TOTCOUNT bytes, or */ - __IOM uint32_t DTHREN : 1; /*!< [1..1] Trigger DMA upon THR level reached. For M2P DMA operations - (IOM writes), the trigger will assert when the write FIFO - has (WTHR/4) number of words free in the write FIFO, and - will transfer (WTHR/4) number of wordsor, if the number - of words left to transfer is less than the WTHR value, - will transfer the remaining byte count.For P2M DMA operations, - the trigger will assert when the read FIFO has (RTHR/4) - words available in the read FIFO, and will transfer (RTHR/4) - words to SRAM. This trigger will NOT asser */ - } DMATRIGEN_b; - } ; - - union { - __IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000244) DMA Trigger Status Register */ - - struct { - __IOM uint32_t DCMDCMP : 1; /*!< [0..0] Triggered DMA from Command complete event. Bit is read - only and can be cleared by disabling the DCMDCMP trigger - enable or by disabling DMA. */ - __IOM uint32_t DTHR : 1; /*!< [1..1] Triggered DMA from THR event. Bit is read only and can - be cleared by disabling the DTHR trigger enable or by disabling - DMA. */ - __IOM uint32_t DTOTCMP : 1; /*!< [2..2] DMA triggered when DCMDCMP = 0, and the amount of data - in the FIFO was enough to complete the DMA operation (greater - than or equal to current TOTCOUNT) when the command completed. - This trigger is default active when the DCMDCMP trigger - isdisabled and there is enough data in the FIFO to complete - the DMA operation. */ - } DMATRIGSTAT_b; - } ; - __IM uint32_t RESERVED3[14]; - - union { - __IOM uint32_t DMACFG; /*!< (@ 0x00000280) DMA Configuration Register */ - - struct { - __IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable. Setting this bit to EN will start the DMA - operation. This should be the last DMA related register - set prior to issuing the command */ - __IOM uint32_t DMADIR : 1; /*!< [1..1] Direction */ - __IM uint32_t : 6; - __IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */ - __IOM uint32_t DPWROFF : 1; /*!< [9..9] Power off module after DMA is complete. If this bit is - active, the module will request to power off the supply - it is attached to. If there are other units still requiring - power from the same domain, power down will not be performed. */ - } DMACFG_b; - } ; - __IM uint32_t RESERVED4; - - union { - __IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000288) DMA Total Transfer Count */ - - struct { - __IOM uint32_t TOTCOUNT : 12; /*!< [11..0] Triggered DMA from Command complete event occured. Bit - is read only and can be cleared by disabling the DTHR trigger - enable or by disabling DMA. */ - } DMATOTCOUNT_b; - } ; - - union { - __IOM uint32_t DMATARGADDR; /*!< (@ 0x0000028C) DMA Target Address Register */ - - struct { - __IOM uint32_t TARGADDR : 21; /*!< [20..0] Bits [19:0] of the target byte address for source of - DMA (either read or write). The address can be any byte - alignment, and does not have to be word aligned. In cases - of non-word aligned addresses, the DMA logic will take - care for ensuring only the target bytes are read/written. */ - __IM uint32_t : 7; - __IOM uint32_t TARGADDR28 : 1; /*!< [28..28] Bit 28 of the target byte address for source of DMA - (either read or write). In cases of non-word aligned addresses, - the DMA logic will take care for ensuring only the target - bytes are read/written.Setting to '1' will select the SRAM. - Setting to '0' will select the flash */ - } DMATARGADDR_b; - } ; - - union { - __IOM uint32_t DMASTAT; /*!< (@ 0x00000290) DMA Status Register */ - - struct { - __IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that - a DMA transfer is active. The DMA transfer may be waiting - on data, transferring data, or waiting for priority.All - of these will be indicated with a 1. A 0 will indicate - that the DMA is fully complete and no further transactions - will be done. This bit is read only. */ - __IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA - operation. This bit can be cleared by writing to 0, and - will also be cleared when a new DMA is started. */ - __IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error. This active high bit signals an error was - encountered during the DMA operation. The bit can be cleared - by writing to 0. Once set, this bit will remain set until - cleared by software. */ - } DMASTAT_b; - } ; - - union { - __IOM uint32_t CQCFG; /*!< (@ 0x00000294) Command Queue Configuration Register */ - - struct { - __IOM uint32_t CQEN : 1; /*!< [0..0] Command queue enable. When set, will enable the processing - of the command queue and fetches of address/data pairs - will proceed from the word address within the CQADDR register. - Can be disabled using a CQ executed write to this bit as - well. */ - __IOM uint32_t CQPRI : 1; /*!< [1..1] Sets the Priority of the command queue dma request */ - __IOM uint32_t MSPIFLGSEL : 2; /*!< [3..2] Selects the MPSI modules used for sourcing the CQFLAG - [11:8]. */ - } CQCFG_b; - } ; - - union { - __IOM uint32_t CQADDR; /*!< (@ 0x00000298) CQ Target Read Address Register */ - - struct { - __IM uint32_t : 2; - __IOM uint32_t CQADDR : 19; /*!< [20..2] Bits 19:2 of target byte address for source of CQ. The - buffer must be aligned on a word boundary */ - __IM uint32_t : 7; - __IOM uint32_t CQADDR28 : 1; /*!< [28..28] Bit 28 of target byte address for source of CQ. Used - to denote Flash (0) or SRAM (1) access */ - } CQADDR_b; - } ; - - union { - __IOM uint32_t CQSTAT; /*!< (@ 0x0000029C) Command Queue Status Register */ - - struct { - __IOM uint32_t CQTIP : 1; /*!< [0..0] Command queue Transfer In Progress indicator. 1 will - indicate that a CQ transfer is active and this will remain - active even when paused waiting for external event. */ - __IOM uint32_t CQPAUSED : 1; /*!< [1..1] Command queue operation is currently paused. */ - __IOM uint32_t CQERR : 1; /*!< [2..2] Command queue processing Error. This active high bit - signals that an error was encountered during the CQ operation. */ - } CQSTAT_b; - } ; - - union { - __IOM uint32_t CQFLAGS; /*!< (@ 0x000002A0) Command Queue Flag Register */ - - struct { - __IOM uint32_t CQFLAGS : 16; /*!< [15..0] Current flag status (read-only). Bits [7:0] are software - controllable and bits [15:8] are hardware status. */ - __IOM uint32_t CQIRQMASK : 16; /*!< [31..16] Mask the bits used to generate the command queue interrupt. - A '1' in the bit position will enable the pause event to - trigger the interrupt, if the CQWT_int interrupt is enabled. - Bits definitions are the same as CQPAUSE */ - } CQFLAGS_b; - } ; - - union { - __IOM uint32_t CQSETCLEAR; /*!< (@ 0x000002A4) Command Queue Flag Set/Clear Register */ - - struct { - __IOM uint32_t CQFSET : 8; /*!< [7..0] Set CQFlag status bits. Will set to 1 the value of any - SWFLAG with a '1' in the corresponding bit position of - this field */ - __IOM uint32_t CQFTGL : 8; /*!< [15..8] Toggle the indicated bit. Will toggle the value of any - SWFLAG with a '1' in the corresponding bit position of - this field */ - __IOM uint32_t CQFCLR : 8; /*!< [23..16] Clear CQFlag status bits. Will clear to 0 any SWFLAG - with a '1' in the corresponding bit position of this field */ - } CQSETCLEAR_b; - } ; - - union { - __IOM uint32_t CQPAUSEEN; /*!< (@ 0x000002A8) Command Queue Pause Enable Register */ - - struct { - __IOM uint32_t CQPEN : 16; /*!< [15..0] Enables the specified event to pause command processing - when active */ - } CQPAUSEEN_b; - } ; - - union { - __IOM uint32_t CQCURIDX; /*!< (@ 0x000002AC) IOM Command Queue current index value . Compared - to the CQENDIDX reg contents to generate - the IDXEQ Pause event for command queue */ - - struct { - __IOM uint32_t CQCURIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQENDIX - register field. If the values match, the IDXEQ pause event - will be activated, which will cause the pausing of command - quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */ - } CQCURIDX_b; - } ; - - union { - __IOM uint32_t CQENDIDX; /*!< (@ 0x000002B0) IOM Command Queue current index value . Compared - to the CQCURIDX reg contents to generate - the IDXEQ Pause event for command queue */ - - struct { - __IOM uint32_t CQENDIDX : 8; /*!< [7..0] Holds 8 bits of data that will be compared with the CQCURIX - register field. If the values match, the IDXEQ pause event - will be activated, which will cause the pausing of command - quue operation if the IDXEQ bit is enabled in CQPAUSEEN. */ - } CQENDIDX_b; - } ; - - union { - __IOM uint32_t STATUS; /*!< (@ 0x000002B4) IOM Module Status Register */ - - struct { - __IOM uint32_t ERR : 1; /*!< [0..0] Bit has been deprecated. Please refer to the other error - indicators. This will always return 0. */ - __IOM uint32_t CMDACT : 1; /*!< [1..1] Indicates if the active I/O Command is currently processing - a transaction, or command is complete, but the FIFO pointers - are still syncronizing internally. This bit will go high - atthe start of the transaction, and will go low when the - command is complete, and the data and pointers within the - FIFO have been syncronized. */ - __IOM uint32_t IDLEST : 1; /*!< [2..2] indicates if the active I/O state machine is IDLE. Note - - The state machine could be in idle state due to holdoffs - from data availability, or as the command gets propagated - into the logic from the registers. */ - } STATUS_b; - } ; - __IM uint32_t RESERVED5[18]; - - union { - __IOM uint32_t MSPICFG; /*!< (@ 0x00000300) SPI module master configuration */ - - struct { - __IOM uint32_t SPOL : 1; /*!< [0..0] selects SPI polarity. */ - __IOM uint32_t SPHA : 1; /*!< [1..1] selects SPI phase. */ - __IOM uint32_t FULLDUP : 1; /*!< [2..2] Enables full duplex mode for Master SPI write operations. - Data will be captured simultaneously into the read fifo */ - __IM uint32_t : 13; - __IOM uint32_t WTFC : 1; /*!< [16..16] enables write mode flow control. */ - __IOM uint32_t RDFC : 1; /*!< [17..17] enables read mode flow control. */ - __IOM uint32_t MOSIINV : 1; /*!< [18..18] inverts MOSI when flow control is enabled. */ - __IM uint32_t : 1; - __IOM uint32_t WTFCIRQ : 1; /*!< [20..20] selects the write mode flow control signal. */ - __IOM uint32_t WTFCPOL : 1; /*!< [21..21] selects the write flow control signal polarity. The - transfers are halted when the selected flow control signal - is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 - will allow a IRQ=1 to pause transfers). */ - __IOM uint32_t RDFCPOL : 1; /*!< [22..22] selects the read flow control signal polarity. */ - __IOM uint32_t SPILSB : 1; /*!< [23..23] Selects data transfer as MSB first (0) or LSB first - (1) for the data portion of the SPI transaction. The offset - bytes are always transmitted MSB first. */ - __IOM uint32_t DINDLY : 3; /*!< [26..24] Delay tap to use for the input signal (MISO). This - gives more hold time on the input data. */ - __IOM uint32_t DOUTDLY : 3; /*!< [29..27] Delay tap to use for the output signal (MOSI). This - give more hold time on the output data */ - __IOM uint32_t MSPIRST : 1; /*!< [30..30] Not used. To reset the module, toggle the SMOD_EN for - the module */ - } MSPICFG_b; - } ; - __IM uint32_t RESERVED6[63]; - - union { - __IOM uint32_t MI2CCFG; /*!< (@ 0x00000400) I2C Master configuration */ - - struct { - __IOM uint32_t ADDRSZ : 1; /*!< [0..0] Sets the I2C master device address size to either 7b - (0) or 10b (1). */ - __IOM uint32_t I2CLSB : 1; /*!< [1..1] Direction of data transmit and receive, MSB(0) or LSB(1) - first. Default per I2C specification is MSB first. This - applies to both read and write data, and read data will - be bit */ - __IOM uint32_t ARBEN : 1; /*!< [2..2] Enables multi-master arbitration for the I2C master. - If the bus is known to have only a single master, this - function can be disabled to save clock cycles on I2C transactions */ - __IM uint32_t : 1; - __IOM uint32_t SDADLY : 2; /*!< [5..4] Delay to enable on the SDA output. Values are 0x0-0x3. */ - __IOM uint32_t MI2CRST : 1; /*!< [6..6] Not used. To reset the module, toggle the SMOD_EN for - the module */ - __IM uint32_t : 1; - __IOM uint32_t SCLENDLY : 4; /*!< [11..8] Number of IOCLK cycles to delay the rising edge of the - SCL output en (clock will go low on this edge). Used to - allow clock shaping. */ - __IOM uint32_t SDAENDLY : 4; /*!< [15..12] Number of IOCLK cycles to delay the SDA output en (all - transitions affected). Used to delay data relative to clock */ - __IOM uint32_t SMPCNT : 8; /*!< [23..16] Number of Base clk cycles to wait before sampling the - SCL clock to determine if a clock stretch event has occured */ - __IOM uint32_t STRDIS : 1; /*!< [24..24] Disable detection of clock stretch events smaller than - 1 cycle */ - } MI2CCFG_b; - } ; - - union { - __IOM uint32_t DEVCFG; /*!< (@ 0x00000404) I2C Device Configuration register */ - - struct { - __IOM uint32_t DEVADDR : 10; /*!< [9..0] I2C address of the device that the Master will use to - target for read/write operations. This can be either a - 7b or 10b address. */ - } DEVCFG_b; - } ; - __IM uint32_t RESERVED7[2]; - - union { - __IOM uint32_t IOMDBG; /*!< (@ 0x00000410) IOM Debug Register */ - - struct { - __IOM uint32_t DBGEN : 1; /*!< [0..0] Debug Enable. Setting bit will enable the update of data - within this register, otherwise it is clock gated for power - savings */ - __IOM uint32_t IOCLKON : 1; /*!< [1..1] IOCLK debug clock control. Enable IO_CLK to be active - when this bit is '1'. Otherwise, the clock is controlled - with gating from the logic as needed. */ - __IOM uint32_t APBCLKON : 1; /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active - when this bit is '1'. Otherwise, the clock is controlled - with gating from the logic as needed. */ - __IOM uint32_t DBGDATA : 29; /*!< [31..3] Debug control for various options. DBGDATA[1:0] is used - to select between different debug data available in the - DBG0 and DBG1 registers. */ - } IOMDBG_b; - } ; -} IOM0_Type; /*!< Size = 1044 (0x414) */ - - - -/* =========================================================================================================================== */ -/* ================ IOSLAVE ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief I2C/SPI Slave (IOSLAVE) - */ - -typedef struct { /*!< (@ 0x50000000) IOSLAVE Structure */ - __IM uint32_t RESERVED[64]; - - union { - __IOM uint32_t FIFOPTR; /*!< (@ 0x00000100) Current FIFO Pointer */ - - struct { - __IOM uint32_t FIFOPTR : 8; /*!< [7..0] Current FIFO pointer. */ - __IOM uint32_t FIFOSIZ : 8; /*!< [15..8] The number of bytes currently in the hardware FIFO. */ - } FIFOPTR_b; - } ; - - union { - __IOM uint32_t FIFOCFG; /*!< (@ 0x00000104) FIFO Configuration */ - - struct { - __IOM uint32_t FIFOBASE : 5; /*!< [4..0] These bits hold the base address of the I/O FIFO in 8 - byte segments. The IO Slave FIFO is situated in LRAM at - (FIFOBASE*8) to (FIFOMAX*8-1). */ - __IM uint32_t : 3; - __IOM uint32_t FIFOMAX : 6; /*!< [13..8] These bits hold the maximum FIFO address in 8 byte segments. - It is also the beginning of the RAM area of the LRAM. Note - that no RAM area is configured if FIFOMAX is set to 0x1F. */ - __IM uint32_t : 10; - __IOM uint32_t ROBASE : 6; /*!< [29..24] Defines the read-only area. The IO Slave read-only - area is situated in LRAM at (ROBASE*8) to (FIFOBASE*8-1) */ - } FIFOCFG_b; - } ; - - union { - __IOM uint32_t FIFOTHR; /*!< (@ 0x00000108) FIFO Threshold Configuration */ - - struct { - __IOM uint32_t FIFOTHR : 8; /*!< [7..0] FIFO size interrupt threshold. */ - } FIFOTHR_b; - } ; - - union { - __IOM uint32_t FUPD; /*!< (@ 0x0000010C) FIFO Update Status */ - - struct { - __IOM uint32_t FIFOUPD : 1; /*!< [0..0] This bit indicates that a FIFO update is underway. */ - __IOM uint32_t IOREAD : 1; /*!< [1..1] This bitfield indicates an IO read is active. */ - } FUPD_b; - } ; - - union { - __IOM uint32_t FIFOCTR; /*!< (@ 0x00000110) Overall FIFO Counter */ - - struct { - __IOM uint32_t FIFOCTR : 10; /*!< [9..0] Virtual FIFO byte count */ - } FIFOCTR_b; - } ; - - union { - __IOM uint32_t FIFOINC; /*!< (@ 0x00000114) Overall FIFO Counter Increment */ - - struct { - __IOM uint32_t FIFOINC : 10; /*!< [9..0] Increment the Overall FIFO Counter by this value on a - write */ - } FIFOINC_b; - } ; - - union { - __IOM uint32_t CFG; /*!< (@ 0x00000118) I/O Slave Configuration */ - - struct { - __IOM uint32_t IFCSEL : 1; /*!< [0..0] This bit selects the I/O interface. */ - __IOM uint32_t SPOL : 1; /*!< [1..1] This bit selects SPI polarity. */ - __IOM uint32_t LSB : 1; /*!< [2..2] This bit selects the transfer bit ordering. */ - __IM uint32_t : 1; - __IOM uint32_t STARTRD : 1; /*!< [4..4] This bit holds the cycle to initiate an I/O RAM read. */ - __IM uint32_t : 3; - __IOM uint32_t I2CADDR : 12; /*!< [19..8] 7-bit or 10-bit I2C device address. */ - __IM uint32_t : 11; - __IOM uint32_t IFCEN : 1; /*!< [31..31] IOSLAVE interface enable. */ - } CFG_b; - } ; - - union { - __IOM uint32_t PRENC; /*!< (@ 0x0000011C) I/O Slave Interrupt Priority Encode */ - - struct { - __IOM uint32_t PRENC : 5; /*!< [4..0] These bits hold the priority encode of the REGACC interrupts. */ - } PRENC_b; - } ; - - union { - __IOM uint32_t IOINTCTL; /*!< (@ 0x00000120) I/O Interrupt Control */ - - struct { - __IOM uint32_t IOINTEN : 8; /*!< [7..0] These read-only bits indicate whether the IOINT interrupts - are enabled. */ - __IOM uint32_t IOINT : 8; /*!< [15..8] These bits read the IOINT interrupts. */ - __IOM uint32_t IOINTCLR : 1; /*!< [16..16] This bit clears all of the IOINT interrupts when written - with a 1. */ - __IM uint32_t : 7; - __IOM uint32_t IOINTSET : 8; /*!< [31..24] These bits set the IOINT interrupts when written with - a 1. */ - } IOINTCTL_b; - } ; - - union { - __IOM uint32_t GENADD; /*!< (@ 0x00000124) General Address Data */ - - struct { - __IOM uint32_t GADATA : 8; /*!< [7..0] The data supplied on the last General Address reference. */ - } GENADD_b; - } ; - __IM uint32_t RESERVED1[54]; - - union { - __IOM uint32_t INTEN; /*!< (@ 0x00000200) IO Slave Interrupts: Enable */ - - struct { - __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ - __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ - __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ - __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ - __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ - __IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */ - __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ - __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ - __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ - __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ - } INTEN_b; - } ; - - union { - __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) IO Slave Interrupts: Status */ - - struct { - __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ - __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ - __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ - __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ - __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ - __IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */ - __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ - __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ - __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ - __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ - } INTSTAT_b; - } ; - - union { - __IOM uint32_t INTCLR; /*!< (@ 0x00000208) IO Slave Interrupts: Clear */ - - struct { - __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ - __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ - __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ - __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ - __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ - __IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */ - __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ - __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ - __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ - __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ - } INTCLR_b; - } ; - - union { - __IOM uint32_t INTSET; /*!< (@ 0x0000020C) IO Slave Interrupts: Set */ - - struct { - __IOM uint32_t FSIZE : 1; /*!< [0..0] FIFO Size interrupt. */ - __IOM uint32_t FOVFL : 1; /*!< [1..1] FIFO Overflow interrupt. */ - __IOM uint32_t FUNDFL : 1; /*!< [2..2] FIFO Underflow interrupt. */ - __IOM uint32_t FRDERR : 1; /*!< [3..3] FIFO Read Error interrupt. */ - __IOM uint32_t GENAD : 1; /*!< [4..4] I2C General Address interrupt. */ - __IOM uint32_t IOINTW : 1; /*!< [5..5] IO Write interrupt. */ - __IOM uint32_t XCMPRF : 1; /*!< [6..6] Transfer complete interrupt, read from FIFO space. */ - __IOM uint32_t XCMPRR : 1; /*!< [7..7] Transfer complete interrupt, read from register space. */ - __IOM uint32_t XCMPWF : 1; /*!< [8..8] Transfer complete interrupt, write to FIFO space. */ - __IOM uint32_t XCMPWR : 1; /*!< [9..9] Transfer complete interrupt, write to register space. */ - } INTSET_b; - } ; - - union { - __IOM uint32_t REGACCINTEN; /*!< (@ 0x00000210) Register Access Interrupts: Enable */ - - struct { - __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ - } REGACCINTEN_b; - } ; - - union { - __IOM uint32_t REGACCINTSTAT; /*!< (@ 0x00000214) Register Access Interrupts: Status */ - - struct { - __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ - } REGACCINTSTAT_b; - } ; - - union { - __IOM uint32_t REGACCINTCLR; /*!< (@ 0x00000218) Register Access Interrupts: Clear */ - - struct { - __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ - } REGACCINTCLR_b; - } ; - - union { - __IOM uint32_t REGACCINTSET; /*!< (@ 0x0000021C) Register Access Interrupts: Set */ - - struct { - __IOM uint32_t REGACC : 32; /*!< [31..0] Register access interrupts. */ - } REGACCINTSET_b; - } ; -} IOSLAVE_Type; /*!< Size = 544 (0x220) */ - - - -/* =========================================================================================================================== */ -/* ================ MCUCTRL ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief MCU Miscellaneous Control Logic (MCUCTRL) - */ - -typedef struct { /*!< (@ 0x40020000) MCUCTRL Structure */ - - union { - __IOM uint32_t CHIPPN; /*!< (@ 0x00000000) Chip Information Register */ - - struct { - __IOM uint32_t PARTNUM : 32; /*!< [31..0] BCD part number. */ - } CHIPPN_b; - } ; - - union { - __IOM uint32_t CHIPID0; /*!< (@ 0x00000004) Unique Chip ID 0 */ - - struct { - __IOM uint32_t CHIPID0 : 32; /*!< [31..0] Unique chip ID 0. */ - } CHIPID0_b; - } ; - - union { - __IOM uint32_t CHIPID1; /*!< (@ 0x00000008) Unique Chip ID 1 */ - - struct { - __IOM uint32_t CHIPID1 : 32; /*!< [31..0] Unique chip ID 1. */ - } CHIPID1_b; - } ; - - union { - __IOM uint32_t CHIPREV; /*!< (@ 0x0000000C) Chip Revision */ - - struct { - __IOM uint32_t REVMIN : 4; /*!< [3..0] Minor Revision ID. */ - __IOM uint32_t REVMAJ : 4; /*!< [7..4] Major Revision ID. */ - __IOM uint32_t SIPART : 12; /*!< [19..8] Silicon Part ID */ - } CHIPREV_b; - } ; - - union { - __IOM uint32_t VENDORID; /*!< (@ 0x00000010) Unique Vendor ID */ - - struct { - __IOM uint32_t VENDORID : 32; /*!< [31..0] Unique Vendor ID */ - } VENDORID_b; - } ; - - union { - __IOM uint32_t SKU; /*!< (@ 0x00000014) Unique Chip SKU */ - - struct { - __IOM uint32_t ALLOWBURST : 1; /*!< [0..0] Allow Burst feature */ - __IOM uint32_t ALLOWBLE : 1; /*!< [1..1] Allow BLE feature */ - __IOM uint32_t SECBOOT : 1; /*!< [2..2] Secure boot feature allowed */ - } SKU_b; - } ; - - union { - __IOM uint32_t FEATUREENABLE; /*!< (@ 0x00000018) Feature Enable on Burst and BLE */ - - struct { - __IOM uint32_t BLEREQ : 1; /*!< [0..0] Controls the BLE functionality */ - __IOM uint32_t BLEACK : 1; /*!< [1..1] ACK for BLEREQ */ - __IOM uint32_t BLEAVAIL : 1; /*!< [2..2] AVAILABILITY of the BLE functionality */ - __IM uint32_t : 1; - __IOM uint32_t BURSTREQ : 1; /*!< [4..4] Controls the Burst functionality */ - __IOM uint32_t BURSTACK : 1; /*!< [5..5] ACK for BURSTREQ */ - __IOM uint32_t BURSTAVAIL : 1; /*!< [6..6] Availability of Burst functionality */ - } FEATUREENABLE_b; - } ; - __IM uint32_t RESERVED; - - union { - __IOM uint32_t DEBUGGER; /*!< (@ 0x00000020) Debugger Control */ - - struct { - __IOM uint32_t LOCKOUT : 1; /*!< [0..0] Lockout of debugger (SWD). */ - } DEBUGGER_b; - } ; - __IM uint32_t RESERVED1[5]; - - union { - __IOM uint32_t DMASRAMWRITEPROTECT2; /*!< (@ 0x00000038) SRAM write-protection bits. */ - - struct { - __IOM uint32_t DMA_WPROT2 : 32; /*!< [31..0] Write protect SRAM from DMA. Each bit provides write - protection for an 8KB region of memory. When set to 1, - the region will be protected from DMA writes, when set - to 0, DMA may write the region. */ - } DMASRAMWRITEPROTECT2_b; - } ; - __IM uint32_t RESERVED2[49]; - - union { - __IOM uint32_t BODCTRL; /*!< (@ 0x00000100) BOD control Register */ - - struct { - __IOM uint32_t BODLPWD : 1; /*!< [0..0] BODL Power Down. */ - __IOM uint32_t BODHPWD : 1; /*!< [1..1] BODH Power Down. */ - __IOM uint32_t BODCPWD : 1; /*!< [2..2] BODC Power Down. */ - __IOM uint32_t BODFPWD : 1; /*!< [3..3] BODF Power Down. */ - __IOM uint32_t BODLVREFSEL : 1; /*!< [4..4] BODL External Reference Select. Note: the SWE mux select - in PWRSEQ2SWE must be set for this to take effect. */ - __IOM uint32_t BODHVREFSEL : 1; /*!< [5..5] BODH External Reference Select. Note: the SWE mux select - in PWRSEQ2SWE must be set for this to take effect. */ - } BODCTRL_b; - } ; - - union { - __IOM uint32_t ADCPWRDLY; /*!< (@ 0x00000104) ADC Power Up Delay Control */ - - struct { - __IOM uint32_t ADCPWR0 : 8; /*!< [7..0] ADC Reference Buffer Power Enable delay in 64 ADC CLK - increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments - for ADC_CLKSEL = 0x2. */ - __IOM uint32_t ADCPWR1 : 8; /*!< [15..8] ADC Reference Keeper enable delay in 16 ADC CLK increments - for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL - = 0x2. */ - } ADCPWRDLY_b; - } ; - __IM uint32_t RESERVED3; - - union { - __IOM uint32_t ADCCAL; /*!< (@ 0x0000010C) ADC Calibration Control */ - - struct { - __IOM uint32_t CALONPWRUP : 1; /*!< [0..0] Run ADC Calibration on initial power up sequence */ - __IOM uint32_t ADCCALIBRATED : 1; /*!< [1..1] Status for ADC Calibration */ - } ADCCAL_b; - } ; - - union { - __IOM uint32_t ADCBATTLOAD; /*!< (@ 0x00000110) ADC Battery Load Enable */ - - struct { - __IOM uint32_t BATTLOAD : 1; /*!< [0..0] Enable the ADC battery load resistor */ - } ADCBATTLOAD_b; - } ; - __IM uint32_t RESERVED4; - - union { - __IOM uint32_t ADCTRIM; /*!< (@ 0x00000118) ADC Trims */ - - struct { - __IOM uint32_t ADCREFKEEPIBTRIM : 2; /*!< [1..0] ADC Reference Ibias trim */ - __IM uint32_t : 4; - __IOM uint32_t ADCREFBUFTRIM : 5; /*!< [10..6] ADC Reference buffer trim */ - __IOM uint32_t ADCRFBUFIBTRIM : 2; /*!< [12..11] ADC reference buffer input bias trim */ - } ADCTRIM_b; - } ; - - union { - __IOM uint32_t ADCREFCOMP; /*!< (@ 0x0000011C) ADC Referece Keeper and Comparator Control */ - - struct { - __IOM uint32_t ADC_REFCOMP_OUT : 1; /*!< [0..0] Output of the ADC reference comparator */ - __IM uint32_t : 7; - __IOM uint32_t ADCREFKEEPTRIM : 5; /*!< [12..8] ADC Reference Keeper Trim */ - __IM uint32_t : 3; - __IOM uint32_t ADCRFCMPEN : 1; /*!< [16..16] ADC Reference comparator power down */ - } ADCREFCOMP_b; - } ; - - union { - __IOM uint32_t XTALCTRL; /*!< (@ 0x00000120) XTAL Oscillator Control */ - - struct { - __IOM uint32_t XTALSWE : 1; /*!< [0..0] XTAL Software Override Enable. */ - __IOM uint32_t FDBKDSBLXTAL : 1; /*!< [1..1] XTAL Oscillator Disable Feedback. */ - __IOM uint32_t BYPCMPRXTAL : 1; /*!< [2..2] XTAL Oscillator Bypass Comparator. */ - __IOM uint32_t PDNBCOREXTAL : 1; /*!< [3..3] XTAL Oscillator Power Down Core. */ - __IOM uint32_t PDNBCMPRXTAL : 1; /*!< [4..4] XTAL Oscillator Power Down Comparator. */ - __IOM uint32_t PWDBODXTAL : 1; /*!< [5..5] XTAL Power down on brown out. */ - __IOM uint32_t XTALIBUFTRIM : 2; /*!< [7..6] XTAL IBUFF trim */ - __IOM uint32_t XTALICOMPTRIM : 2; /*!< [9..8] XTAL ICOMP trim */ - } XTALCTRL_b; - } ; - - union { - __IOM uint32_t XTALGENCTRL; /*!< (@ 0x00000124) XTAL Oscillator General Control */ - - struct { - __IOM uint32_t ACWARMUP : 2; /*!< [1..0] Auto-calibration delay control */ - __IOM uint32_t XTALBIASTRIM : 6; /*!< [7..2] XTAL BIAS trim */ - __IOM uint32_t XTALKSBIASTRIM : 6; /*!< [13..8] XTAL IBIAS Kick start trim. This trim value is used - during the startup process to enable a faster lock. */ - } XTALGENCTRL_b; - } ; - __IM uint32_t RESERVED5[28]; - - union { - __IOM uint32_t MISCCTRL; /*!< (@ 0x00000198) Miscellaneous control register. */ - - struct { - __IOM uint32_t RESERVED_RW_0 : 5; /*!< [4..0] Reserved bits, always leave unchanged. The MISCCTRL register - must be modified via atomic RMW, leaving this bitfield - completely unmodified. Failure to do so will result in - unpredictable behavior. */ - __IOM uint32_t BLE_RESETN : 1; /*!< [5..5] BLE reset signal. */ - } MISCCTRL_b; - } ; - __IM uint32_t RESERVED6; - - union { - __IOM uint32_t BOOTLOADER; /*!< (@ 0x000001A0) Bootloader and secure boot functions */ - - struct { - __IOM uint32_t BOOTLOADERLOW : 1; /*!< [0..0] Determines whether the bootloader code is visible at - address 0x00000000 or not. Resets to 1, write 1 to clear. */ - __IOM uint32_t SBLOCK : 1; /*!< [1..1] Secure boot lock. Always resets to 1, write 1 to clear. - Enables system visibility to bootloader until set. */ - __IOM uint32_t PROTLOCK : 1; /*!< [2..2] Flash protection lock. Always resets to 1, write 1 to - clear. Enables writes to flash protection register set. */ - __IM uint32_t : 23; - __IOM uint32_t SECBOOTFEATURE : 2; /*!< [27..26] Indicates whether the secure boot feature is enabled. */ - __IOM uint32_t SECBOOT : 2; /*!< [29..28] Indicates whether the secure boot on cold reset is - enabled */ - __IOM uint32_t SECBOOTONRST : 2; /*!< [31..30] Indicates whether the secure boot on warm reset is - enabled */ - } BOOTLOADER_b; - } ; - - union { - __IOM uint32_t SHADOWVALID; /*!< (@ 0x000001A4) Register to indicate whether the shadow registers - have been successfully loaded from the Flash - Information Space. */ - - struct { - __IOM uint32_t VALID : 1; /*!< [0..0] Indicates whether the shadow registers contain valid - data from the Flash Information Space. */ - __IOM uint32_t BLDSLEEP : 1; /*!< [1..1] Indicates whether the bootloader should sleep or deep - sleep if no image loaded. */ - __IOM uint32_t INFO0_VALID : 1; /*!< [2..2] Indicates whether info0 contains valid data */ - } SHADOWVALID_b; - } ; - __IM uint32_t RESERVED7[2]; - - union { - __IOM uint32_t SCRATCH0; /*!< (@ 0x000001B0) Scratch register that is not reset by any reset */ - - struct { - __IOM uint32_t SCRATCH0 : 32; /*!< [31..0] Scratch register 0. */ - } SCRATCH0_b; - } ; - - union { - __IOM uint32_t SCRATCH1; /*!< (@ 0x000001B4) Scratch register that is not reset by any reset */ - - struct { - __IOM uint32_t SCRATCH1 : 32; /*!< [31..0] Scratch register 1. */ - } SCRATCH1_b; - } ; - __IM uint32_t RESERVED8[2]; - - union { - __IOM uint32_t ICODEFAULTADDR; /*!< (@ 0x000001C0) ICODE bus address which was present when a bus - fault occurred. */ - - struct { - __IOM uint32_t ICODEFAULTADDR : 32; /*!< [31..0] The ICODE bus address observed when a Bus Fault occurred. - Once an address is captured in this field, it is held until - the corresponding Fault Observed bit is cleared in the - FAULTSTATUS register. */ - } ICODEFAULTADDR_b; - } ; - - union { - __IOM uint32_t DCODEFAULTADDR; /*!< (@ 0x000001C4) DCODE bus address which was present when a bus - fault occurred. */ - - struct { - __IOM uint32_t DCODEFAULTADDR : 32; /*!< [31..0] The DCODE bus address observed when a Bus Fault occurred. - Once an address is captured in this field, it is held until - the corresponding Fault Observed bit is cleared in the - FAULTSTATUS register. */ - } DCODEFAULTADDR_b; - } ; - - union { - __IOM uint32_t SYSFAULTADDR; /*!< (@ 0x000001C8) System bus address which was present when a bus - fault occurred. */ - - struct { - __IOM uint32_t SYSFAULTADDR : 32; /*!< [31..0] SYS bus address observed when a Bus Fault occurred. - Once an address is captured in this field, it is held until - the corresponding Fault Observed bit is cleared in the - FAULTSTATUS register. */ - } SYSFAULTADDR_b; - } ; - - union { - __IOM uint32_t FAULTSTATUS; /*!< (@ 0x000001CC) Reflects the status of the bus decoders' fault - detection. Any write to this register will - clear all of the status bits within the - register. */ - - struct { - __IOM uint32_t ICODEFAULT : 1; /*!< [0..0] The ICODE Bus Decoder Fault Detected bit. When set, a - fault has been detected, and the ICODEFAULTADDR register - will contain the bus address which generated the fault. */ - __IOM uint32_t DCODEFAULT : 1; /*!< [1..1] DCODE Bus Decoder Fault Detected bit. When set, a fault - has been detected, and the DCODEFAULTADDR register will - contain the bus address which generated the fault. */ - __IOM uint32_t SYSFAULT : 1; /*!< [2..2] SYS Bus Decoder Fault Detected bit. When set, a fault - has been detected, and the SYSFAULTADDR register will contain - the bus address which generated the fault. */ - } FAULTSTATUS_b; - } ; - - union { - __IOM uint32_t FAULTCAPTUREEN; /*!< (@ 0x000001D0) Enable the fault capture registers */ - - struct { - __IOM uint32_t FAULTCAPTUREEN : 1; /*!< [0..0] Fault Capture Enable field. When set, the Fault Capture - monitors are enabled and addresses which generate a hard - fault are captured into the FAULTADDR registers. */ - } FAULTCAPTUREEN_b; - } ; - __IM uint32_t RESERVED9[11]; - - union { - __IOM uint32_t DBGR1; /*!< (@ 0x00000200) Read-only debug register 1 */ - - struct { - __IOM uint32_t ONETO8 : 32; /*!< [31..0] Read-only register for communication validation */ - } DBGR1_b; - } ; - - union { - __IOM uint32_t DBGR2; /*!< (@ 0x00000204) Read-only debug register 2 */ - - struct { - __IOM uint32_t COOLCODE : 32; /*!< [31..0] Read-only register for communication validation */ - } DBGR2_b; - } ; - __IM uint32_t RESERVED10[6]; - - union { - __IOM uint32_t PMUENABLE; /*!< (@ 0x00000220) Control bit to enable/disable the PMU */ - - struct { - __IOM uint32_t ENABLE : 1; /*!< [0..0] PMU Enable Control bit. When set, the MCU's PMU will - place the MCU into the lowest power consuming Deep Sleep - mode upon execution of a WFI instruction (dependent on - the setting of the SLEEPDEEP bit in the ARM SCR register). - When cleared, regardless of the requested sleep mode, the - PMU will not enter the lowest power Deep Sleep mode, instead - entering the Sleep mode. */ - } PMUENABLE_b; - } ; - __IM uint32_t RESERVED11[11]; - - union { - __IOM uint32_t TPIUCTRL; /*!< (@ 0x00000250) TPIU Control Register. Determines the clock enable - and frequency for the M4's TPIU interface. */ - - struct { - __IOM uint32_t ENABLE : 1; /*!< [0..0] TPIU Enable field. When set, the ARM M4 TPIU is enabled - and data can be streamed out of the MCU's SWO port using - the ARM ITM and TPIU modules. */ - __IM uint32_t : 7; - __IOM uint32_t CLKSEL : 3; /*!< [10..8] This field selects the frequency of the ARM M4 TPIU - port. */ - } TPIUCTRL_b; - } ; - __IM uint32_t RESERVED12[4]; - - union { - __IOM uint32_t OTAPOINTER; /*!< (@ 0x00000264) OTA (Over the Air) Update Pointer/Status. Reset - only by POA */ - - struct { - __IOM uint32_t OTAVALID : 1; /*!< [0..0] Indicates that an OTA update is valid */ - __IOM uint32_t OTASBLUPDATE : 1; /*!< [1..1] Indicates that the sbl_init has been updated */ - __IOM uint32_t OTAPOINTER : 30; /*!< [31..2] Flash page pointer with updated OTA image */ - } OTAPOINTER_b; - } ; - __IM uint32_t RESERVED13[6]; - - union { - __IOM uint32_t APBDMACTRL; /*!< (@ 0x00000280) DMA Control Register. Determines misc settings - for DMA operation */ - - struct { - __IOM uint32_t DMA_ENABLE : 1; /*!< [0..0] Enable the DMA controller. When disabled, DMA requests - will be ignored by the controller */ - __IOM uint32_t DECODEABORT : 1; /*!< [1..1] APB Decode Abort. When set, the APB bridge will issue - a data abort (bus fault) on transactions to peripherals - that are powered down. When set to 0, writes are quietly - discarded and reads return 0. */ - __IOM uint32_t DMAOPT : 1; /*!< [2..2] Enables DMA latency optimizations */ - __IM uint32_t : 5; - __IOM uint32_t HYSTERESIS : 8; /*!< [15..8] This field determines how long the DMA will remain active - during deep sleep before shutting down and returning the - system to full deep sleep. Values are based on a 94KHz - clock and are roughly 10us increments for a range of ~10us - to 2.55ms */ - } APBDMACTRL_b; - } ; - - union { - __IOM uint32_t SRAMMODE; /*!< (@ 0x00000284) SRAM Controller mode bits */ - - struct { - __IOM uint32_t IPREFETCH : 1; /*!< [0..0] When set, instruction accesses to the SRAM banks will - be prefetched (normally 2 cycle read access). Generally, - this mode bit should be set for improved performance when - executing instructions from SRAM. */ - __IOM uint32_t IPREFETCH_CACHE : 1; /*!< [1..1] Secondary prefetch feature that will cache prefetched - data across bus waitstates (requires IPREFETCH to be set). */ - __IM uint32_t : 2; - __IOM uint32_t DPREFETCH : 1; /*!< [4..4] When set, data bus accesses to the SRAM banks will be - prefetched (normally 2 cycle read access). Use of this - mode bit is only recommended if the work flow has a large - number of sequential accesses. */ - __IOM uint32_t DPREFETCH_CACHE : 1; /*!< [5..5] Secondary prefetch feature that will cache prefetched - data across bus waitstates (requires DPREFETCH to be set). */ - } SRAMMODE_b; - } ; - __IM uint32_t RESERVED14[48]; - - union { - __IOM uint32_t KEXTCLKSEL; /*!< (@ 0x00000348) Key Register to enable the use of external clock - selects via the EXTCLKSEL reg */ - - struct { - __IOM uint32_t KEXTCLKSEL : 32; /*!< [31..0] Key register value. */ - } KEXTCLKSEL_b; - } ; - __IM uint32_t RESERVED15[4]; - - union { - __IOM uint32_t SIMOBUCK4; /*!< (@ 0x0000035C) SIMO Buck Control Reg1 */ - - struct { - __IM uint32_t : 21; - __IOM uint32_t SIMOBUCKCLKDIVSEL : 2; /*!< [22..21] simobuck_clkdiv_sel */ - } SIMOBUCK4_b; - } ; - __IM uint32_t RESERVED16[2]; - - union { - __IOM uint32_t BLEBUCK2; /*!< (@ 0x00000368) BLEBUCK2 Control Reg */ - - struct { - __IOM uint32_t BLEBUCKTONLOWTRIM : 6; /*!< [5..0] blebuck_ton_low_trim */ - __IOM uint32_t BLEBUCKTONHITRIM : 6; /*!< [11..6] blebuck_ton_hi_trim */ - __IOM uint32_t BLEBUCKTOND2ATRIM : 6; /*!< [17..12] blebuck_ton_trim */ - } BLEBUCK2_b; - } ; - __IM uint32_t RESERVED17[13]; - - union { - __IOM uint32_t FLASHWPROT0; /*!< (@ 0x000003A0) Flash Write Protection Bits */ - - struct { - __IOM uint32_t FW0BITS : 32; /*!< [31..0] Write protect flash 0x00000000 - 0x0007FFFF. Each bit - provides write protection for 16KB chunks of flash data - space. Bits are cleared by writing a 1 to the bit. When - read, 0 indicates the region is protected. Bits are sticky - (can be set when PROTLOCK is 1, but only cleared by reset) */ - } FLASHWPROT0_b; - } ; - - union { - __IOM uint32_t FLASHWPROT1; /*!< (@ 0x000003A4) Flash Write Protection Bits */ - - struct { - __IOM uint32_t FW1BITS : 32; /*!< [31..0] Write protect flash 0x00080000 - 0x000FFFFF. Each bit - provides write protection for 16KB chunks of flash data - space. Bits are cleared by writing a 1 to the bit. When - read, 0 indicates the region is protected. Bits are sticky - (can be set when PROTLOCK is 1, but only cleared by reset) */ - } FLASHWPROT1_b; - } ; - - union { - __IOM uint32_t FLASHWPROT2; /*!< (@ 0x000003A8) Flash Write Protection Bits */ - - struct { - __IOM uint32_t FW2BITS : 32; /*!< [31..0] Write protect flash 0x00100000 - 0x0017FFFF. Each bit - provides write protection for 16KB chunks of flash data - space. Bits are cleared by writing a 1 to the bit. When - read, 0 indicates the region is protected. Bits are sticky - (can be set when PROTLOCK is 1, but only cleared by reset) */ - } FLASHWPROT2_b; - } ; - - union { - __IOM uint32_t FLASHWPROT3; /*!< (@ 0x000003AC) Flash Write Protection Bits */ - - struct { - __IOM uint32_t FW3BITS : 32; /*!< [31..0] Write protect flash 0x00180000 - 0x001FFFFF. Each bit - provides write protection for 16KB chunks of flash data - space. Bits are cleared by writing a 1 to the bit. When - read, 0 indicates the region is protected. Bits are sticky - (can be set when PROTLOCK is 1, but only cleared by reset) */ - } FLASHWPROT3_b; - } ; - - union { - __IOM uint32_t FLASHRPROT0; /*!< (@ 0x000003B0) Flash Read Protection Bits */ - - struct { - __IOM uint32_t FR0BITS : 32; /*!< [31..0] Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each - bit provides read protection for 16KB chunks of flash. - Bits are cleared by writing a 1 to the bit. When read, - 0 indicates the region is protected. Bits are sticky (can - be set when PROTLOCK is 1, but only cleared by reset) */ - } FLASHRPROT0_b; - } ; - - union { - __IOM uint32_t FLASHRPROT1; /*!< (@ 0x000003B4) Flash Read Protection Bits */ - - struct { - __IOM uint32_t FR1BITS : 32; /*!< [31..0] Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each - bit provides read protection for 16KB chunks of flash. - Bits are cleared by writing a 1 to the bit. When read, - 0 indicates the region is protected. Bits are sticky (can - be set when PROTLOCK is 1, but only cleared by reset) */ - } FLASHRPROT1_b; - } ; - - union { - __IOM uint32_t FLASHRPROT2; /*!< (@ 0x000003B8) Flash Read Protection Bits */ - - struct { - __IOM uint32_t FR2BITS : 32; /*!< [31..0] Copy (read) protect flash 0x00100000 - 0x0017FFFF. Each - bit provides read protection for 16KB chunks of flash. - Bits are cleared by writing a 1 to the bit. When read, - 0 indicates the region is protected. Bits are sticky (can - be set when PROTLOCK is 1, but only cleared by reset) */ - } FLASHRPROT2_b; - } ; - - union { - __IOM uint32_t FLASHRPROT3; /*!< (@ 0x000003BC) Flash Read Protection Bits */ - - struct { - __IOM uint32_t FR3BITS : 32; /*!< [31..0] Copy (read) protect flash 0x00180000 - 0x001FFFFF. Each - bit provides read protection for 16KB chunks of flash. - Bits are cleared by writing a 1 to the bit. When read, - 0 indicates the region is protected. Bits are sticky (can - be set when PROTLOCK is 1, but only cleared by reset) */ - } FLASHRPROT3_b; - } ; - - union { - __IOM uint32_t DMASRAMWRITEPROTECT0; /*!< (@ 0x000003C0) SRAM write-protection bits. */ - - struct { - __IOM uint32_t DMA_WPROT0 : 32; /*!< [31..0] Write protect SRAM from DMA. Each bit provides write - protection for an 8KB region of memory. When set to 1, - the region will be protected from DMA writes, when set - to 0, DMA may write the region. */ - } DMASRAMWRITEPROTECT0_b; - } ; - - union { - __IOM uint32_t DMASRAMWRITEPROTECT1; /*!< (@ 0x000003C4) SRAM write-protection bits. */ - - struct { - __IOM uint32_t DMA_WPROT1 : 32; /*!< [31..0] Write protect SRAM from DMA. Each bit provides write - protection for an 8KB region of memory. When set to 1, - the region will be protected from DMA writes, when set - to 0, DMA may write the region. */ - } DMASRAMWRITEPROTECT1_b; - } ; - __IM uint32_t RESERVED18[2]; - - union { - __IOM uint32_t DMASRAMREADPROTECT0; /*!< (@ 0x000003D0) SRAM read-protection bits. */ - - struct { - __IOM uint32_t DMA_RPROT0 : 32; /*!< [31..0] Read protect SRAM from DMA. Each bit provides write - protection for an 8KB region of memory. When set to 1, - the region will be protected from DMA reads, when set to - 0, DMA may read the region. */ - } DMASRAMREADPROTECT0_b; - } ; - - union { - __IOM uint32_t DMASRAMREADPROTECT1; /*!< (@ 0x000003D4) SRAM read-protection bits. */ - - struct { - __IOM uint32_t DMA_RPROT1 : 32; /*!< [31..0] Read protect SRAM from DMA. Each bit provides write - protection for an 8KB region of memory. When set to 1, - the region will be protected from DMA reads, when set to - 0, DMA may read the region. */ - } DMASRAMREADPROTECT1_b; - } ; - - union { - __IOM uint32_t DMASRAMREADPROTECT2; /*!< (@ 0x000003D8) SRAM read-protection bits. */ - - struct { - __IOM uint32_t DMA_RPROT2 : 32; /*!< [31..0] Read protect SRAM from DMA. Each bit provides write - protection for an 8KB region of memory. When set to 1, - the region will be protected from DMA reads, when set to - 0, DMA may read the region. */ - } DMASRAMREADPROTECT2_b; - } ; -} MCUCTRL_Type; /*!< Size = 988 (0x3dc) */ - - - -/* =========================================================================================================================== */ -/* ================ MSPI0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Multibit SPI Master (MSPI0) - */ - -typedef struct { /*!< (@ 0x50014000) MSPI0 Structure */ - - union { - __IOM uint32_t CTRL; /*!< (@ 0x00000000) MSPI PIO Transfer Control/Status Register */ - - struct { - __IOM uint32_t START : 1; /*!< [0..0] Write to 1 to initiate a PIO transaction on the bus (typically - the entire register should be written at once with this - bit set). */ - __IOM uint32_t STATUS : 1; /*!< [1..1] Command status: 1 indicates command has completed. Cleared - by writing 1 to this bit or starting a new transfer. */ - __IOM uint32_t BUSY : 1; /*!< [2..2] Command status: 1 indicates controller is busy (command - in progress) */ - __IOM uint32_t QUADCMD : 1; /*!< [3..3] Flag indicating that the operation is a command that - should be replicated to both devices in paired QUAD mode. - This is typically only used when reading/writing configuration - registers in paired flash devices (do not set for memory - transfers). */ - __IOM uint32_t ENWLAT : 1; /*!< [4..4] Enable Write Latency Counter (time between address and - first data byte). Counter value is WRITELATENCY. */ - __IOM uint32_t CONT : 1; /*!< [5..5] Continuation transfer. When 1, indicates that the MSPI - will hold CE low after the transaction completes. This - is included for compatibility with IOM module since the - MSPI transfer module can handle most cases in a single - transfer. NOTE: CONT functionality only works with CLKDIV=2 - (24 MHz). */ - __IOM uint32_t BIGENDIAN : 1; /*!< [6..6] 1 indicates data in FIFO is in big endian format (MSB - first); 0 indicates little endian data (default, LSB first). */ - __IOM uint32_t ENTURN : 1; /*!< [7..7] Indicates whether TX->RX turnaround cycles should be - enabled for this operation (see TURNAROUND field in CFG - register). */ - __IOM uint32_t SENDA : 1; /*!< [8..8] Indicates whether an address phase should be sent (see - ADDR register and ASIZE field in CFG register) */ - __IOM uint32_t SENDI : 1; /*!< [9..9] Indicates whether an instruction phase should be sent - (see INSTR field and ISIZE field in CFG register) */ - __IOM uint32_t TXRX : 1; /*!< [10..10] 1 Indicates a TX operation, 0 indicates an RX operation - of XFERBYTES */ - __IOM uint32_t PIOSCRAMBLE : 1; /*!< [11..11] Enables data scrambling for PIO opertions. This should - only be used for data operations and never for commands - to a device. */ - __IOM uint32_t ENDCX : 1; /*!< [12..12] Enable DCX signal on data [1] */ - __IM uint32_t : 3; - __IOM uint32_t XFERBYTES : 16; /*!< [31..16] Number of bytes to transmit or receive (based on TXRX - bit) */ - } CTRL_b; - } ; - - union { - __IOM uint32_t CFG; /*!< (@ 0x00000004) MSPI Transfer Configuration Register */ - - struct { - __IOM uint32_t DEVCFG : 4; /*!< [3..0] Flash configuration for XIP and AUTO DMA operations. - Controls value for SER (Slave Enable) for XIP operations - and address generation for DMA/XIP modes. Also used to - configure SPIFRF (frame format). */ - __IOM uint32_t ASIZE : 2; /*!< [5..4] Address Size. Address bytes to send from ADDR register */ - __IOM uint32_t ISIZE : 1; /*!< [6..6] Instruction Sizeenum name = I8 value = 0x0 desc = Instruction - is 1 byteenum name = I16 value = 0x1 desc = Instruction - is 2 bytes */ - __IOM uint32_t SEPIO : 1; /*!< [7..7] Separate IO configuration. This bit should be set when - the target device has separate MOSI and MISO pins. Respective - IN/OUT bits below should be set to map pins. */ - __IOM uint32_t TURNAROUND : 6; /*!< [13..8] Number of turnaound cycles (for TX->RX transitions). - Qualified by ENTURN or XIPENTURN bit field. */ - __IM uint32_t : 2; - __IOM uint32_t CPHA : 1; /*!< [16..16] Serial clock phase. */ - __IOM uint32_t CPOL : 1; /*!< [17..17] Serial clock polarity. */ - __IM uint32_t : 2; - __IOM uint32_t WRITELATENCY : 6; /*!< [25..20] Number of cycles between addressn and TX data. Qualified - by ENLAT */ - } CFG_b; - } ; - - union { - __IOM uint32_t ADDR; /*!< (@ 0x00000008) MSPI Transfer Address Register */ - - struct { - __IOM uint32_t ADDR : 32; /*!< [31..0] Optional Address field to send (after optional instruction - field) - qualified by ASIZE in CMD register. NOTE: This - register is aliased to DMADEVADDR. */ - } ADDR_b; - } ; - - union { - __IOM uint32_t INSTR; /*!< (@ 0x0000000C) MSPI Transfer Instruction */ - - struct { - __IOM uint32_t INSTR : 16; /*!< [15..0] Optional Instruction field to send (1st byte) - qualified - by ISEND/ISIZE */ - } INSTR_b; - } ; - - union { - __IOM uint32_t TXFIFO; /*!< (@ 0x00000010) TX Data FIFO */ - - struct { - __IOM uint32_t TXFIFO : 32; /*!< [31..0] Data to be transmitted. Data should normall be aligned - to the LSB (pad the upper bits with zeros) unless BIGENDIAN - is set. */ - } TXFIFO_b; - } ; - - union { - __IOM uint32_t RXFIFO; /*!< (@ 0x00000014) RX Data FIFO */ - - struct { - __IOM uint32_t RXFIFO : 32; /*!< [31..0] Receive data. Data is aligned to the LSB (padded zeros - on upper bits) unless BIGENDIAN is set. */ - } RXFIFO_b; - } ; - - union { - __IOM uint32_t TXENTRIES; /*!< (@ 0x00000018) TX FIFO Entries */ - - struct { - __IOM uint32_t TXENTRIES : 6; /*!< [5..0] Number of 32-bit words/entries in TX FIFO */ - } TXENTRIES_b; - } ; - - union { - __IOM uint32_t RXENTRIES; /*!< (@ 0x0000001C) RX FIFO Entries */ - - struct { - __IOM uint32_t RXENTRIES : 6; /*!< [5..0] Number of 32-bit words/entries in RX FIFO */ - } RXENTRIES_b; - } ; - - union { - __IOM uint32_t THRESHOLD; /*!< (@ 0x00000020) TX/RX FIFO Threshhold Levels */ - - struct { - __IOM uint32_t TXTHRESH : 6; /*!< [5..0] Number of entries in TX FIFO that cause TXF interrupt */ - __IM uint32_t : 2; - __IOM uint32_t RXTHRESH : 6; /*!< [13..8] Number of entries in TX FIFO that cause RXE interrupt */ - } THRESHOLD_b; - } ; - __IM uint32_t RESERVED[55]; - - union { - __IOM uint32_t MSPICFG; /*!< (@ 0x00000100) MSPI Module Configuration */ - - struct { - __IOM uint32_t APBCLK : 1; /*!< [0..0] Enable continuous APB clock. For power-efficient operation, - APBCLK should be set to 0. */ - __IOM uint32_t RXCAP : 1; /*!< [1..1] Controls RX data capture phase. A setting of 0 (NORMAL) - captures read data at the normal capture point relative - to the internal clock launch point. However, to accomodate - chip/pad/board delays, a setting of RXCAP of 1 is expected - to be used to align the capture point with the return data - window. This bit is used in conjunction with RXNEG to provide - 4 unique capture points, all about 10ns apart. */ - __IOM uint32_t RXNEG : 1; /*!< [2..2] Adjusts the RX capture phase to the negedge of the 48MHz - internal clock (~10ns early). For normal operation, it - is expected that RXNEG will be set to 0. */ - __IOM uint32_t TXNEG : 1; /*!< [3..3] Launches TX data a half clock cycle (~10ns) early. This - should normally be programmed to zero (NORMAL). */ - __IOM uint32_t IOMSEL : 4; /*!< [7..4] Selects which IOM is selected for CQ handshake status. */ - __IOM uint32_t CLKDIV : 6; /*!< [13..8] Clock Divider. Allows dividing 48 MHz base clock by - integer multiples. Enumerations are provided for common - frequency, but any integer divide from 48 MHz is allowed. - Odd divide ratios will result in a 33/66 percent duty cycle - with a long low clock pulse (to allow longer round-trip - for read data). */ - __IM uint32_t : 15; - __IOM uint32_t FIFORESET : 1; /*!< [29..29] Reset MSPI FIFO (active high). 1=reset FIFO, 0=normal - operation. May be used to manually flush the FIFO in error - handling. */ - __IOM uint32_t IPRSTN : 1; /*!< [30..30] IP block reset. Write to 0 to put the transfer module - in reset or 1 for normal operation. This may be required - after error conditions to clear the transfer on the bus. */ - __IOM uint32_t PRSTN : 1; /*!< [31..31] Peripheral reset. Master reset to the entire MSPI module - (DMA, XIP, and transfer state machines). 1=normal operation, - 0=in reset. */ - } MSPICFG_b; - } ; - - union { - __IOM uint32_t MSPIDDR; /*!< (@ 0x00000104) MSPI Module DDR Configuration Bits */ - - struct { - __IOM uint32_t EMULATEDDR : 1; /*!< [0..0] Drive external clock at 1/2 rate to emulate DDR mode */ - __IOM uint32_t QUADDDR : 1; /*!< [1..1] Enables use of delay line to provide fine control over - traditional RX capture clock. */ - __IOM uint32_t ENABLEDQS : 1; /*!< [2..2] In EMULATEDDR mode, enable DQS for read capture */ - __IOM uint32_t DQSSYNCNEG : 1; /*!< [3..3] Use negative edge of clock for DDR data sync */ - __IOM uint32_t OVERRIDERXDQSDELAY : 1; /*!< [4..4] Override DQS delay line with the value in DQSDELAY (for - RX capture in QUADDDR mode) */ - __IOM uint32_t OVERRIDEDDRCLKOUTDELAY : 1;/*!< [5..5] Override TX delay line with the value in DQSDELAY (for - TX clock offset when in QUADDDR mode) */ - __IOM uint32_t ENABLEFINEDELAY : 1; /*!< [6..6] Enables use of delay line to provide fine control over - traditional RX capture clock. */ - __IM uint32_t : 1; - __IOM uint32_t RXDQSDELAY : 5; /*!< [12..8] When OVERRIDEDQSDELAY is set this sets the DQS delayline - value. In ENABLEDQS mode, this acts as an offset to the - computed value (should be set to 0 by default) */ - __IM uint32_t : 3; - __IOM uint32_t TXDQSDELAY : 5; /*!< [20..16] When OVERRIDEDQSDELAY is set this sets the DQS delayline - value. In ENABLEDQS mode, this acts as an offset to the - computed value (should be set to 0 by default) */ - } MSPIDDR_b; - } ; - __IM uint32_t RESERVED1[2]; - - union { - __IOM uint32_t PADCFG; /*!< (@ 0x00000110) MSPI Output Pad Configuration */ - - struct { - __IOM uint32_t OUT3 : 1; /*!< [0..0] Output pad 3 configuration. 0=data[3] 1=CLK */ - __IOM uint32_t OUT4 : 1; /*!< [1..1] Output pad 4 configuration. 0=data[4] 1=data[0] */ - __IOM uint32_t OUT5 : 1; /*!< [2..2] Output pad 5 configuration. 0=data[5] 1=data[1] */ - __IOM uint32_t OUT6 : 1; /*!< [3..3] Output pad 6 configuration. 0=data[6] 1=data[2] */ - __IOM uint32_t OUT7 : 1; /*!< [4..4] Output pad 7 configuration. 0=data[7] 1=data[3] */ - __IM uint32_t : 11; - __IOM uint32_t IN0 : 2; /*!< [17..16] Data Input pad 0 pin muxing: 0=pad[0] 1=pad[4] 2=pad[1] - 3=pad[5] */ - __IOM uint32_t IN1 : 1; /*!< [18..18] Data Input pad 1 pin muxing: 0=pad[1] 1=pad[5] */ - __IOM uint32_t IN2 : 1; /*!< [19..19] Data Input pad 2 pin muxing: 0=pad[2] 1=pad[6] */ - __IOM uint32_t IN3 : 1; /*!< [20..20] Data Input pad 3 pin muxing: 0=pad[3] 1=pad[7] */ - __IOM uint32_t REVCS : 1; /*!< [21..21] Reverse CS connections. Allows CS1 to be associated - with lower data lanes and CS0 to be associated with upper - data lines */ - } PADCFG_b; - } ; - - union { - __IOM uint32_t PADOUTEN; /*!< (@ 0x00000114) MSPI Output Enable Pad Configuration */ - - struct { - __IOM uint32_t OUTEN : 10; /*!< [9..0] Output pad enable configuration. Indicates which pads - should be driven. Bits [3:0] are Quad0 data, [7:4] are - Quad1 data, and [8] is clock. */ - } PADOUTEN_b; - } ; - - union { - __IOM uint32_t PADOVEREN; /*!< (@ 0x00000118) MSPI Output Pad Override */ - - struct { - __IOM uint32_t OVERRIDEEN : 10; /*!< [9..0] Output pad override enable. Bit mask for pad outputs. - When set to 1, the values in the OVERRIDE field are driven - on the pad (output enable is implicitly set in this mode). - [7:0]=data [8]=clock [9]=DM */ - } PADOVEREN_b; - } ; - - union { - __IOM uint32_t PADOVER; /*!< (@ 0x0000011C) MSPI Output Pad Override Value */ - - struct { - __IOM uint32_t OVERRIDE : 10; /*!< [9..0] Output pad override value. [7:0]=data [8]=clock [9]=DM */ - } PADOVER_b; - } ; - - union { - __IOM uint32_t FLASH; /*!< (@ 0x00000120) Configuration for XIP/DMA support of SPI flash - modules. */ - - struct { - __IOM uint32_t XIPEN : 1; /*!< [0..0] Enable the XIP (eXecute In Place) function which effectively - enables the address decoding of the MSPI device in the - flash/cache address space at address 0x04000000-0x07FFFFFF. */ - __IOM uint32_t XIPENDCX : 1; /*!< [1..1] Enable DCX signal on data [1] for XIP/DMA operations */ - __IOM uint32_t XIPACK : 2; /*!< [3..2] Controls transmission of Micron XIP acknowledge cycles - (Micron Flash devices only) */ - __IOM uint32_t XIPBIGENDIAN : 1; /*!< [4..4] Indicates whether XIP/AUTO DMA data transfers are in - big or little endian format */ - __IOM uint32_t XIPENTURN : 1; /*!< [5..5] Indicates whether XIP/AUTO DMA operations should enable - TX->RX turnaround cycles */ - __IOM uint32_t XIPSENDA : 1; /*!< [6..6] Indicates whether XIP/AUTO DMA operations should send - an an address phase (see DMADEVADDR register and ASIZE - field in CFG) */ - __IOM uint32_t XIPSENDI : 1; /*!< [7..7] Indicates whether XIP/AUTO DMA operations should send - an instruction (see READINSTR field and ISIZE field in - CFG) */ - __IOM uint32_t XIPMIXED : 3; /*!< [10..8] Reserved. Set to 0x0 */ - __IOM uint32_t XIPENWLAT : 1; /*!< [11..11] Enable Write Latency counter for XIP write transactions */ - } FLASH_b; - } ; - - union { - __IOM uint32_t XIPINSTR; /*!< (@ 0x00000124) Configuration for XIP/DMA support of SPI flash - modules. */ - - struct { - __IOM uint32_t WRITEINSTR : 16; /*!< [15..0] Write command sent for DMA operations */ - __IOM uint32_t READINSTR : 16; /*!< [31..16] Read command sent to flash for DMA/XIP operations */ - } XIPINSTR_b; - } ; - - union { - __IOM uint32_t SCRAMBLING; /*!< (@ 0x00000128) External Flash Scrambling Controls */ - - struct { - __IOM uint32_t SCRSTART : 10; /*!< [9..0] Scrambling region start address [25:16] (64K block granularity). - The START block is the FIRST block included in the scrambled - address range. */ - __IM uint32_t : 6; - __IOM uint32_t SCREND : 10; /*!< [25..16] Scrambling region end address [25:16] (64K block granularity). - The END block is the LAST block included in the scrambled - address range. */ - __IM uint32_t : 5; - __IOM uint32_t SCRENABLE : 1; /*!< [31..31] Enables Data Scrambling Region. When 1 reads and writes - to the range will be scrambled. When 0, data will be read/written - unmodified. Address range is specified in 64K granularity - and the START/END ranges are included within the range. */ - } SCRAMBLING_b; - } ; - __IM uint32_t RESERVED2[53]; - - union { - __IOM uint32_t INTEN; /*!< (@ 0x00000200) MSPI Master Interrupts: Enable */ - - struct { - __IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are - layered, so CMDCMP, DCMP, and CQ* can all be signalled - simultaneously */ - __IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */ - __IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to - a full FIFO). */ - __IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from - an empty FIFO) */ - __IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design -- - MSPI bus pins will stall) */ - __IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */ - __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */ - __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */ - __IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */ - __IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ - performs an operation where address bit[0] is set. Useful - for triggering CURIDX interrupts. */ - __IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */ - __IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */ - __IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must - be aligned to word (4-byte) start address. */ - } INTEN_b; - } ; - - union { - __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) MSPI Master Interrupts: Status */ - - struct { - __IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are - layered, so CMDCMP, DCMP, and CQ* can all be signalled - simultaneously */ - __IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */ - __IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to - a full FIFO). */ - __IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from - an empty FIFO) */ - __IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design -- - MSPI bus pins will stall) */ - __IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */ - __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */ - __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */ - __IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */ - __IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ - performs an operation where address bit[0] is set. Useful - for triggering CURIDX interrupts. */ - __IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */ - __IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */ - __IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must - be aligned to word (4-byte) start address. */ - } INTSTAT_b; - } ; - - union { - __IOM uint32_t INTCLR; /*!< (@ 0x00000208) MSPI Master Interrupts: Clear */ - - struct { - __IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are - layered, so CMDCMP, DCMP, and CQ* can all be signalled - simultaneously */ - __IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */ - __IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to - a full FIFO). */ - __IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from - an empty FIFO) */ - __IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design -- - MSPI bus pins will stall) */ - __IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */ - __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */ - __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */ - __IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */ - __IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ - performs an operation where address bit[0] is set. Useful - for triggering CURIDX interrupts. */ - __IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */ - __IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */ - __IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must - be aligned to word (4-byte) start address. */ - } INTCLR_b; - } ; - - union { - __IOM uint32_t INTSET; /*!< (@ 0x0000020C) MSPI Master Interrupts: Set */ - - struct { - __IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ operations are - layered, so CMDCMP, DCMP, and CQ* can all be signalled - simultaneously */ - __IOM uint32_t TXE : 1; /*!< [1..1] Transmit FIFO empty. */ - __IOM uint32_t TXO : 1; /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to - a full FIFO). */ - __IOM uint32_t RXU : 1; /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from - an empty FIFO) */ - __IOM uint32_t RXO : 1; /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design -- - MSPI bus pins will stall) */ - __IOM uint32_t RXF : 1; /*!< [5..5] Receive FIFO full */ - __IOM uint32_t DCMP : 1; /*!< [6..6] DMA Complete Interrupt */ - __IOM uint32_t DERR : 1; /*!< [7..7] DMA Error Interrupt */ - __IOM uint32_t CQCMP : 1; /*!< [8..8] Command Queue Complete Interrupt */ - __IOM uint32_t CQUPD : 1; /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ - performs an operation where address bit[0] is set. Useful - for triggering CURIDX interrupts. */ - __IOM uint32_t CQPAUSED : 1; /*!< [10..10] Command Queue is Paused. */ - __IOM uint32_t CQERR : 1; /*!< [11..11] Command Queue Error Interrupt */ - __IOM uint32_t SCRERR : 1; /*!< [12..12] Scrambling Alignment Error. Scrambling operations must - be aligned to word (4-byte) start address. */ - } INTSET_b; - } ; - __IM uint32_t RESERVED3[16]; - - union { - __IOM uint32_t DMACFG; /*!< (@ 0x00000250) DMA Configuration Register */ - - struct { - __IOM uint32_t DMAEN : 2; /*!< [1..0] DMA Enable. Setting this bit to EN will start the DMA - operation */ - __IOM uint32_t DMADIR : 1; /*!< [2..2] Direction */ - __IOM uint32_t DMAPRI : 2; /*!< [4..3] Sets the Priority of the DMA request */ - __IM uint32_t : 13; - __IOM uint32_t DMAPWROFF : 1; /*!< [18..18] Power off MSPI domain upon completion of DMA operation. */ - } DMACFG_b; - } ; - - union { - __IOM uint32_t DMASTAT; /*!< (@ 0x00000254) DMA Status Register */ - - struct { - __IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that - a DMA transfer is active. The DMA transfer may be waiting - on data, transferring data, or waiting for priority. All - of these will be indicated with a 1. A 0 will indicate - that the DMA is fully complete and no further transactions - will be done. */ - __IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA - operation. */ - __IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error. This active high bit signals that an error - was encountered during the DMA operation. */ - __IOM uint32_t SCRERR : 1; /*!< [3..3] Scrambling Access Alignment Error. This active high bit - signals that a scrambling operation was specified for a - non-word aligned DEVADDR. */ - } DMASTAT_b; - } ; - - union { - __IOM uint32_t DMATARGADDR; /*!< (@ 0x00000258) DMA Target Address Register */ - - struct { - __IOM uint32_t TARGADDR : 32; /*!< [31..0] Target byte address for source of DMA (either read or - write). In cases of non-word aligned addresses, the DMA - logic will take care for ensuring only the target bytes - are read/written. */ - } DMATARGADDR_b; - } ; - - union { - __IOM uint32_t DMADEVADDR; /*!< (@ 0x0000025C) DMA Device Address Register */ - - struct { - __IOM uint32_t DEVADDR : 32; /*!< [31..0] SPI Device address for automated DMA transactions (both - read and write). */ - } DMADEVADDR_b; - } ; - - union { - __IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000260) DMA Total Transfer Count */ - - struct { - __IOM uint32_t TOTCOUNT : 24; /*!< [23..0] Total Transfer Count in bytes. */ - } DMATOTCOUNT_b; - } ; - - union { - __IOM uint32_t DMABCOUNT; /*!< (@ 0x00000264) DMA BYTE Transfer Count */ - - struct { - __IOM uint32_t BCOUNT : 8; /*!< [7..0] Burst transfer size in bytes. This is the number of bytes - transferred when a FIFO trigger event occurs. Recommended - value is 32. */ - } DMABCOUNT_b; - } ; - - union { - __IOM uint32_t DMATHRESH; /*!< (@ 0x00000268) DMA Transmit Trigger Threshhold */ - - struct { - __IOM uint32_t DMATXTHRESH : 5; /*!< [4..0] DMA transfer FIFO level trigger. For read operations, - DMA is triggered when the FIFO level is greater than this - value. For write operations, DMA is triggered when the - FIFO level is less than this level. Each DMA operation - will consist of BCOUNT bytes. */ - __IM uint32_t : 3; - __IOM uint32_t DMARXTHRESH : 5; /*!< [12..8] DMA transfer FIFO level trigger. For read operations, - DMA is triggered when the FIFO level is greater than this - value. For write operations, DMA is triggered when the - FIFO level is less than this level. Each DMA operation - will consist of BCOUNT bytes. */ - } DMATHRESH_b; - } ; - - union { - __IOM uint32_t DMABOUNDARY; /*!< (@ 0x0000026C) DMA Transfer Boundary */ - - struct { - __IOM uint32_t DMATIMELIMIT : 12; /*!< [11..0] DMA time limit. Can be used to limit the tranaction - time on the MSPI bus. The count is in 100ns incremements. - A value of 0 disables the counter */ - __IOM uint32_t DMABOUND : 4; /*!< [15..12] DMA Address boundray */ - } DMABOUNDARY_b; - } ; - __IM uint32_t RESERVED4[12]; - - union { - __IOM uint32_t CQCFG; /*!< (@ 0x000002A0) Command Queue Configuration Register */ - - struct { - __IOM uint32_t CQEN : 1; /*!< [0..0] Command queue enable. When set, will enable the processing - of the command queue */ - __IOM uint32_t CQPRI : 1; /*!< [1..1] Sets the Priority of the command queue dma request */ - __IOM uint32_t CQPWROFF : 1; /*!< [2..2] Power off MSPI domain upon completion of DMA operation. */ - __IOM uint32_t CQAUTOCLEARMASK : 1; /*!< [3..3] Enable clear of CQMASK after each pause operation. This - may be useful when using software flags to pause CQ. */ - } CQCFG_b; - } ; - __IM uint32_t RESERVED5; - - union { - __IOM uint32_t CQADDR; /*!< (@ 0x000002A8) CQ Target Read Address Register */ - - struct { - __IOM uint32_t CQADDR : 29; /*!< [28..0] Address of command queue buffer in SRAM or flash. The - buffer address must be aligned to a word boundary. */ - } CQADDR_b; - } ; - - union { - __IOM uint32_t CQSTAT; /*!< (@ 0x000002AC) Command Queue Status Register */ - - struct { - __IOM uint32_t CQTIP : 1; /*!< [0..0] Command queue Transfer In Progress indicator. 1 will - indicate that a CQ transfer is active and this will remain - active even when paused waiting for external event. */ - __IOM uint32_t CQCPL : 1; /*!< [1..1] Command queue operation Complete. This signals the end - of the command queue operation. */ - __IOM uint32_t CQERR : 1; /*!< [2..2] Command queue processing Error. This active high bit - signals that an error was encountered during the CQ operation. */ - __IOM uint32_t CQPAUSED : 1; /*!< [3..3] Command queue is currently paused status. */ - } CQSTAT_b; - } ; - - union { - __IOM uint32_t CQFLAGS; /*!< (@ 0x000002B0) Command Queue Flag Register */ - - struct { - __IOM uint32_t CQFLAGS : 16; /*!< [15..0] Current flag status (read-only). Bits [7:0] are software - controllable and bits [15:8] are hardware status. */ - } CQFLAGS_b; - } ; - - union { - __IOM uint32_t CQSETCLEAR; /*!< (@ 0x000002B4) Command Queue Flag Set/Clear Register */ - - struct { - __IOM uint32_t CQFSET : 8; /*!< [7..0] Set CQFlag status bits. Set has priority over clear if - both are high. */ - __IOM uint32_t CQFTOGGLE : 8; /*!< [15..8] Toggle CQFlag status bits */ - __IOM uint32_t CQFCLR : 8; /*!< [23..16] Clear CQFlag status bits. */ - } CQSETCLEAR_b; - } ; - - union { - __IOM uint32_t CQPAUSE; /*!< (@ 0x000002B8) Command Queue Pause Mask Register */ - - struct { - __IOM uint32_t CQMASK : 16; /*!< [15..0] CQ will pause processing when ALL specified events are - satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK. */ - } CQPAUSE_b; - } ; - __IM uint32_t RESERVED6; - - union { - __IOM uint32_t CQCURIDX; /*!< (@ 0x000002C0) Command Queue Current Index */ - - struct { - __IOM uint32_t CQCURIDX : 8; /*!< [7..0] Can be used to indicate the current position of the command - queue by having CQ operations write this field. A CQ hardware - status flag indicates when CURIDX and ENDIDX are not equal, - allowing SW to pause the CQ processing until the end index - is updated. */ - } CQCURIDX_b; - } ; - - union { - __IOM uint32_t CQENDIDX; /*!< (@ 0x000002C4) Command Queue End Index */ - - struct { - __IOM uint32_t CQENDIDX : 8; /*!< [7..0] Can be used to indicate the end position of the command - queue. A CQ hardware status bit indices when CURIDX != - ENDIDX so that the CQ can be paused when it reaches the - end pointer. */ - } CQENDIDX_b; - } ; -} MSPI0_Type; /*!< Size = 712 (0x2c8) */ - - - -/* =========================================================================================================================== */ -/* ================ PDM ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief PDM Audio (PDM) - */ - -typedef struct { /*!< (@ 0x50011000) PDM Structure */ - - union { - __IOM uint32_t PCFG; /*!< (@ 0x00000000) PDM Configuration Register */ - - struct { - __IOM uint32_t PDMCOREEN : 1; /*!< [0..0] Data Streaming Control. */ - __IOM uint32_t SOFTMUTE : 1; /*!< [1..1] Soft mute control. */ - __IOM uint32_t CYCLES : 3; /*!< [4..2] Number of clocks during gain-setting changes. */ - __IOM uint32_t HPCUTOFF : 4; /*!< [8..5] High pass filter coefficients. */ - __IOM uint32_t ADCHPD : 1; /*!< [9..9] High pass filter control. */ - __IOM uint32_t SINCRATE : 7; /*!< [16..10] SINC decimation rate. */ - __IOM uint32_t MCLKDIV : 2; /*!< [18..17] PDM_CLK frequency divisor. */ - __IM uint32_t : 2; - __IOM uint32_t PGALEFT : 5; /*!< [25..21] Left channel PGA gain. */ - __IOM uint32_t PGARIGHT : 5; /*!< [30..26] Right channel PGA gain. */ - __IOM uint32_t LRSWAP : 1; /*!< [31..31] Left/right channel swap. */ - } PCFG_b; - } ; - - union { - __IOM uint32_t VCFG; /*!< (@ 0x00000004) Voice Configuration Register */ - - struct { - __IM uint32_t : 3; - __IOM uint32_t CHSET : 2; /*!< [4..3] Set PCM channels. */ - __IM uint32_t : 3; - __IOM uint32_t PCMPACK : 1; /*!< [8..8] PCM data packing enable. */ - __IM uint32_t : 7; - __IOM uint32_t SELAP : 1; /*!< [16..16] Select PDM input clock source. */ - __IOM uint32_t DMICKDEL : 1; /*!< [17..17] PDM clock sampling delay. */ - __IM uint32_t : 1; - __IOM uint32_t BCLKINV : 1; /*!< [19..19] I2S BCLK input inversion. */ - __IOM uint32_t I2SEN : 1; /*!< [20..20] I2S interface enable. */ - __IM uint32_t : 5; - __IOM uint32_t PDMCLKEN : 1; /*!< [26..26] Enable the serial clock. */ - __IOM uint32_t PDMCLKSEL : 3; /*!< [29..27] Select the PDM input clock. */ - __IOM uint32_t RSTB : 1; /*!< [30..30] Reset the IP core. */ - __IOM uint32_t IOCLKEN : 1; /*!< [31..31] Enable the IO clock. */ - } VCFG_b; - } ; - - union { - __IOM uint32_t VOICESTAT; /*!< (@ 0x00000008) Voice Status Register */ - - struct { - __IOM uint32_t FIFOCNT : 6; /*!< [5..0] Valid 32-bit entries currently in the FIFO. */ - } VOICESTAT_b; - } ; - - union { - __IOM uint32_t FIFOREAD; /*!< (@ 0x0000000C) FIFO Read */ - - struct { - __IOM uint32_t FIFOREAD : 32; /*!< [31..0] FIFO read data. */ - } FIFOREAD_b; - } ; - - union { - __IOM uint32_t FIFOFLUSH; /*!< (@ 0x00000010) FIFO Flush */ - - struct { - __IOM uint32_t FIFOFLUSH : 1; /*!< [0..0] FIFO FLUSH. */ - } FIFOFLUSH_b; - } ; - - union { - __IOM uint32_t FIFOTHR; /*!< (@ 0x00000014) FIFO Threshold */ - - struct { - __IOM uint32_t FIFOTHR : 5; /*!< [4..0] FIFO Threshold value. When the FIFO count is equal to, - or larger than this value (in words), a THR interrupt is - generated (if enabled) */ - } FIFOTHR_b; - } ; - __IM uint32_t RESERVED[122]; - - union { - __IOM uint32_t INTEN; /*!< (@ 0x00000200) IO Master Interrupts: Enable */ - - struct { - __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ - __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ - __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ - __IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */ - __IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */ - } INTEN_b; - } ; - - union { - __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) IO Master Interrupts: Status */ - - struct { - __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ - __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ - __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ - __IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */ - __IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */ - } INTSTAT_b; - } ; - - union { - __IOM uint32_t INTCLR; /*!< (@ 0x00000208) IO Master Interrupts: Clear */ - - struct { - __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ - __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ - __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ - __IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */ - __IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */ - } INTCLR_b; - } ; - - union { - __IOM uint32_t INTSET; /*!< (@ 0x0000020C) IO Master Interrupts: Set */ - - struct { - __IOM uint32_t THR : 1; /*!< [0..0] This is the FIFO threshold interrupt. */ - __IOM uint32_t OVF : 1; /*!< [1..1] This is the FIFO overflow interrupt. */ - __IOM uint32_t UNDFL : 1; /*!< [2..2] This is the FIFO underflow interrupt. */ - __IOM uint32_t DCMP : 1; /*!< [3..3] DMA completed a transfer */ - __IOM uint32_t DERR : 1; /*!< [4..4] DMA Error receieved */ - } INTSET_b; - } ; - __IM uint32_t RESERVED1[12]; - - union { - __IOM uint32_t DMATRIGEN; /*!< (@ 0x00000240) DMA Trigger Enable Register */ - - struct { - __IOM uint32_t DTHR : 1; /*!< [0..0] Trigger DMA upon when FIFO iss filled to level indicated - by the FIFO THRESHOLD,at granularity of 16 bytes only */ - __IOM uint32_t DTHR90 : 1; /*!< [1..1] Trigger DMA at FIFO 90 percent full. This signal is also - used internally for AUTOHIP function */ - } DMATRIGEN_b; - } ; - - union { - __IOM uint32_t DMATRIGSTAT; /*!< (@ 0x00000244) DMA Trigger Status Register */ - - struct { - __IOM uint32_t DTHRSTAT : 1; /*!< [0..0] Triggered DMA from FIFO reaching threshold */ - __IOM uint32_t DTHR90STAT : 1; /*!< [1..1] Triggered DMA from FIFO reaching 90 percent full */ - } DMATRIGSTAT_b; - } ; - __IM uint32_t RESERVED2[14]; - - union { - __IOM uint32_t DMACFG; /*!< (@ 0x00000280) DMA Configuration Register */ - - struct { - __IOM uint32_t DMAEN : 1; /*!< [0..0] DMA Enable */ - __IM uint32_t : 1; - __IOM uint32_t DMADIR : 1; /*!< [2..2] Direction */ - __IM uint32_t : 5; - __IOM uint32_t DMAPRI : 1; /*!< [8..8] Sets the Priority of the DMA request */ - __IOM uint32_t DAUTOHIP : 1; /*!< [9..9] Raise priority to high on fifo full, and DMAPRI set to - low */ - __IOM uint32_t DPWROFF : 1; /*!< [10..10] Power Off the ADC System upon DMACPL. */ - } DMACFG_b; - } ; - __IM uint32_t RESERVED3; - - union { - __IOM uint32_t DMATOTCOUNT; /*!< (@ 0x00000288) DMA Total Transfer Count */ - - struct { - __IOM uint32_t TOTCOUNT : 20; /*!< [19..0] Total Transfer Count. The transfer count must be a multiple - of the THR setting to avoid DMA overruns. */ - } DMATOTCOUNT_b; - } ; - - union { - __IOM uint32_t DMATARGADDR; /*!< (@ 0x0000028C) DMA Target Address Register */ - - struct { - __IOM uint32_t LTARGADDR : 21; /*!< [20..0] DMA Target Address. This register is not updated with - the current address of the DMA, but will remain static - with the original address during the DMA transfer. */ - __IOM uint32_t UTARGADDR : 11; /*!< [31..21] SRAM Target */ - } DMATARGADDR_b; - } ; - - union { - __IOM uint32_t DMASTAT; /*!< (@ 0x00000290) DMA Status Register */ - - struct { - __IOM uint32_t DMATIP : 1; /*!< [0..0] DMA Transfer In Progress */ - __IOM uint32_t DMACPL : 1; /*!< [1..1] DMA Transfer Complete */ - __IOM uint32_t DMAERR : 1; /*!< [2..2] DMA Error */ - } DMASTAT_b; - } ; -} PDM_Type; /*!< Size = 660 (0x294) */ - - - -/* =========================================================================================================================== */ -/* ================ PWRCTRL ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief PWR Controller Register Bank (PWRCTRL) - */ - -typedef struct { /*!< (@ 0x40021000) PWRCTRL Structure */ - - union { - __IOM uint32_t SUPPLYSRC; /*!< (@ 0x00000000) Voltage Regulator Select Register */ - - struct { - __IOM uint32_t BLEBUCKEN : 1; /*!< [0..0] Enables and Selects the BLE Buck as the supply for the - BLE power domain or for Burst LDO. It takes the initial - value from Customer INFO space. Buck will be powered up - only if there is an active request for BLEH domain or Burst - mode and appropriate feature is allowed. */ - } SUPPLYSRC_b; - } ; - - union { - __IOM uint32_t SUPPLYSTATUS; /*!< (@ 0x00000004) Voltage Regulators status */ - - struct { - __IOM uint32_t SIMOBUCKON : 1; /*!< [0..0] Indicates whether the Core/Mem low-voltage domains are - supplied from the LDO or the Buck. */ - __IOM uint32_t BLEBUCKON : 1; /*!< [1..1] Indicates whether the BLE (if supported) domain and burst - (if supported) domain is supplied from the LDO or the Buck. - Buck will be powered up only if there is an active request - for BLEH domain or Burst mode and appropriate reature is - allowed. */ - } SUPPLYSTATUS_b; - } ; - - union { - __IOM uint32_t DEVPWREN; /*!< (@ 0x00000008) Device Power Enables */ - - struct { - __IOM uint32_t PWRIOS : 1; /*!< [0..0] Power up IO Slave */ - __IOM uint32_t PWRIOM0 : 1; /*!< [1..1] Power up IO Master 0 */ - __IOM uint32_t PWRIOM1 : 1; /*!< [2..2] Power up IO Master 1 */ - __IOM uint32_t PWRIOM2 : 1; /*!< [3..3] Power up IO Master 2 */ - __IOM uint32_t PWRIOM3 : 1; /*!< [4..4] Power up IO Master 3 */ - __IOM uint32_t PWRIOM4 : 1; /*!< [5..5] Power up IO Master 4 */ - __IOM uint32_t PWRIOM5 : 1; /*!< [6..6] Power up IO Master 5 */ - __IOM uint32_t PWRUART0 : 1; /*!< [7..7] Power up UART Controller 0 */ - __IOM uint32_t PWRUART1 : 1; /*!< [8..8] Power up UART Controller 1 */ - __IOM uint32_t PWRADC : 1; /*!< [9..9] Power up ADC Digital Controller */ - __IOM uint32_t PWRSCARD : 1; /*!< [10..10] Power up SCARD Controller */ - __IOM uint32_t PWRMSPI0 : 1; /*!< [11..11] Power up MSPI0 Controller */ - __IOM uint32_t PWRMSPI1 : 1; /*!< [12..12] Power up MSPI1 Controller */ - __IOM uint32_t PWRMSPI2 : 1; /*!< [13..13] Power up MSPI2 Controller */ - __IOM uint32_t PWRPDM : 1; /*!< [14..14] Power up PDM block */ - __IOM uint32_t PWRBLEL : 1; /*!< [15..15] Power up BLE controller */ - } DEVPWREN_b; - } ; - - union { - __IOM uint32_t MEMPWDINSLEEP; /*!< (@ 0x0000000C) Powerdown SRAM banks in Deep Sleep mode */ - - struct { - __IOM uint32_t DTCMPWDSLP : 3; /*!< [2..0] power down DTCM in deep sleep */ - __IOM uint32_t SRAMPWDSLP : 10; /*!< [12..3] Selects which SRAM banks are powered down in deep sleep - mode, causing the contents of the bank to be lost. */ - __IOM uint32_t FLASH0PWDSLP : 1; /*!< [13..13] Powerdown flash0 in deep sleep */ - __IOM uint32_t FLASH1PWDSLP : 1; /*!< [14..14] Powerdown flash1 in deep sleep */ - __IM uint32_t : 16; - __IOM uint32_t CACHEPWDSLP : 1; /*!< [31..31] power down cache in deep sleep */ - } MEMPWDINSLEEP_b; - } ; - - union { - __IOM uint32_t MEMPWREN; /*!< (@ 0x00000010) Enables individual banks of the MEMORY array */ - - struct { - __IOM uint32_t DTCM : 3; /*!< [2..0] Power up DTCM */ - __IOM uint32_t SRAM : 10; /*!< [12..3] Power up SRAM groups */ - __IOM uint32_t FLASH0 : 1; /*!< [13..13] Power up Flash group 0 (0MB-1MB) */ - __IOM uint32_t FLASH1 : 1; /*!< [14..14] Power up Flash group 1 (1MB-2MB) */ - __IM uint32_t : 15; - __IOM uint32_t CACHEB0 : 1; /*!< [30..30] Power up Cache Bank 0. This works in conjunction with - Cache enable from flash_cache module. To power up cache - bank0, cache has to be enabled and this bit has to be set. */ - __IOM uint32_t CACHEB2 : 1; /*!< [31..31] Power up Cache Bank 2. This works in conjunction with - Cache enable from flash_cache module. To power up cache - bank2, cache has to be enabled and this bit has to be set. */ - } MEMPWREN_b; - } ; - - union { - __IOM uint32_t MEMPWRSTATUS; /*!< (@ 0x00000014) Mem Power ON Status */ - - struct { - __IOM uint32_t DTCM00 : 1; /*!< [0..0] This bit is 1 if power is supplied to DTCM GROUP0_0 */ - __IOM uint32_t DTCM01 : 1; /*!< [1..1] This bit is 1 if power is supplied to DTCM GROUP0_1 */ - __IOM uint32_t DTCM1 : 1; /*!< [2..2] This bit is 1 if power is supplied to DTCM GROUP1 */ - __IOM uint32_t SRAM0 : 1; /*!< [3..3] This bit is 1 if power is supplied to SRAM GROUP0 */ - __IOM uint32_t SRAM1 : 1; /*!< [4..4] This bit is 1 if power is supplied to SRAM GROUP1 */ - __IOM uint32_t SRAM2 : 1; /*!< [5..5] This bit is 1 if power is supplied to SRAM GROUP2 */ - __IOM uint32_t SRAM3 : 1; /*!< [6..6] This bit is 1 if power is supplied to SRAM GROUP3 */ - __IOM uint32_t SRAM4 : 1; /*!< [7..7] This bit is 1 if power is supplied to SRAM GROUP4 */ - __IOM uint32_t SRAM5 : 1; /*!< [8..8] This bit is 1 if power is supplied to SRAM GROUP5 */ - __IOM uint32_t SRAM6 : 1; /*!< [9..9] This bit is 1 if power is supplied to SRAM GROUP6 */ - __IOM uint32_t SRAM7 : 1; /*!< [10..10] This bit is 1 if power is supplied to SRAM GROUP7 */ - __IOM uint32_t SRAM8 : 1; /*!< [11..11] This bit is 1 if power is supplied to SRAM GROUP8 */ - __IOM uint32_t SRAM9 : 1; /*!< [12..12] This bit is 1 if power is supplied to SRAM GROUP9 */ - __IOM uint32_t FLASH0 : 1; /*!< [13..13] This bit is 1 if power is supplied to FLASH group 0 */ - __IOM uint32_t FLASH1 : 1; /*!< [14..14] This bit is 1 if power is supplied to FLASH group 1 */ - __IOM uint32_t CACHEB0 : 1; /*!< [15..15] This bit is 1 if power is supplied to Cache Bank 0 */ - __IOM uint32_t CACHEB2 : 1; /*!< [16..16] This bit is 1 if power is supplied to Cache Bank 2 */ - } MEMPWRSTATUS_b; - } ; - - union { - __IOM uint32_t DEVPWRSTATUS; /*!< (@ 0x00000018) Device Power ON Status */ - - struct { - __IOM uint32_t MCUL : 1; /*!< [0..0] This bit is 1 if power is supplied to MCUL */ - __IOM uint32_t MCUH : 1; /*!< [1..1] This bit is 1 if power is supplied to MCUH */ - __IOM uint32_t HCPA : 1; /*!< [2..2] This bit is 1 if power is supplied to HCPA domain (IO - SLAVE, UART0, UART1, SCARD) */ - __IOM uint32_t HCPB : 1; /*!< [3..3] This bit is 1 if power is supplied to HCPB domain (IO - MASTER 0, 1, 2) */ - __IOM uint32_t HCPC : 1; /*!< [4..4] This bit is 1 if power is supplied to HCPC domain (IO - MASTER4, 5, 6) */ - __IOM uint32_t PWRADC : 1; /*!< [5..5] This bit is 1 if power is supplied to ADC */ - __IOM uint32_t PWRMSPI : 1; /*!< [6..6] This bit is 1 if power is supplied to MSPI */ - __IOM uint32_t PWRPDM : 1; /*!< [7..7] This bit is 1 if power is supplied to PDM */ - __IOM uint32_t BLEL : 1; /*!< [8..8] This bit is 1 if power is supplied to BLEL */ - __IOM uint32_t BLEH : 1; /*!< [9..9] This bit is 1 if power is supplied to BLEH */ - } DEVPWRSTATUS_b; - } ; - - union { - __IOM uint32_t SRAMCTRL; /*!< (@ 0x0000001C) SRAM Control register */ - - struct { - __IM uint32_t : 1; - __IOM uint32_t SRAMCLKGATE : 1; /*!< [1..1] This bit is 1 if clock gating is allowed for individual - system SRAMs */ - __IOM uint32_t SRAMMASTERCLKGATE : 1; /*!< [2..2] This bit is 1 when the master clock gate is enabled (top-level - clock gate for entire SRAM block) */ - __IM uint32_t : 5; - __IOM uint32_t SRAMLIGHTSLEEP : 12; /*!< [19..8] Light Sleep enable for each TCM/SRAM bank. When 1, corresponding - bank will be put into light sleep. For optimal power, banks - should be put into light sleep while the system is active - but the bank has minimal or no accesses. */ - } SRAMCTRL_b; - } ; - - union { - __IOM uint32_t ADCSTATUS; /*!< (@ 0x00000020) Power Status Register for ADC Block */ - - struct { - __IOM uint32_t ADCPWD : 1; /*!< [0..0] This bit indicates that the ADC is powered down */ - __IOM uint32_t BGTPWD : 1; /*!< [1..1] This bit indicates that the ADC Band Gap is powered down */ - __IOM uint32_t VPTATPWD : 1; /*!< [2..2] This bit indicates that the ADC temperature sensor input - buffer is powered down */ - __IOM uint32_t VBATPWD : 1; /*!< [3..3] This bit indicates that the ADC VBAT resistor divider - is powered down */ - __IOM uint32_t REFKEEPPWD : 1; /*!< [4..4] This bit indicates that the ADC REFKEEP is powered down */ - __IOM uint32_t REFBUFPWD : 1; /*!< [5..5] This bit indicates that the ADC REFBUF is powered down */ - } ADCSTATUS_b; - } ; - - union { - __IOM uint32_t MISC; /*!< (@ 0x00000024) Power Optimization Control Bits */ - - struct { - __IM uint32_t : 3; - __IOM uint32_t FORCEMEMVRLPTIMERS : 1; /*!< [3..3] Control Bit to force Mem VR to LP mode in deep sleep - even when hfrc based ctimer or stimer is running. */ - __IM uint32_t : 2; - __IOM uint32_t MEMVRLPBLE : 1; /*!< [6..6] Control Bit to let Mem VR go to lp mode in deep sleep - even when BLEL or BLEH is powered on given none of the - other domains require it. */ - } MISC_b; - } ; - - union { - __IOM uint32_t DEVPWREVENTEN; /*!< (@ 0x00000028) Event enable register to control which DEVPWRSTATUS - bits are routed to event input of CPU. */ - - struct { - __IOM uint32_t MCULEVEN : 1; /*!< [0..0] Control MCUL power-on status event */ - __IOM uint32_t MCUHEVEN : 1; /*!< [1..1] Control MCUH power-on status event */ - __IOM uint32_t HCPAEVEN : 1; /*!< [2..2] Control HCPA power-on status event */ - __IOM uint32_t HCPBEVEN : 1; /*!< [3..3] Control HCPB power-on status event */ - __IOM uint32_t HCPCEVEN : 1; /*!< [4..4] Control HCPC power-on status event */ - __IOM uint32_t ADCEVEN : 1; /*!< [5..5] Control ADC power-on status event */ - __IOM uint32_t MSPIEVEN : 1; /*!< [6..6] Control MSPI power-on status event */ - __IOM uint32_t PDMEVEN : 1; /*!< [7..7] Control PDM power-on status event */ - __IOM uint32_t BLELEVEN : 1; /*!< [8..8] Control BLE power-on status event */ - __IM uint32_t : 20; - __IOM uint32_t BLEFEATUREEVEN : 1; /*!< [29..29] Control BLEFEATURE status event */ - __IOM uint32_t BURSTFEATUREEVEN : 1; /*!< [30..30] Control BURSTFEATURE status event */ - __IOM uint32_t BURSTEVEN : 1; /*!< [31..31] Control BURST status event */ - } DEVPWREVENTEN_b; - } ; - - union { - __IOM uint32_t MEMPWREVENTEN; /*!< (@ 0x0000002C) Event enable register to control which MEMPWRSTATUS - bits are routed to event input of CPU. */ - - struct { - __IOM uint32_t DTCMEN : 3; /*!< [2..0] Enable DTCM power-on status event */ - __IOM uint32_t SRAMEN : 10; /*!< [12..3] Control SRAM power-on status event */ - __IOM uint32_t FLASH0EN : 1; /*!< [13..13] Control Flash power-on status event */ - __IOM uint32_t FLASH1EN : 1; /*!< [14..14] Control Flash power-on status event */ - __IM uint32_t : 15; - __IOM uint32_t CACHEB0EN : 1; /*!< [30..30] Control CACHE BANK 0 power-on status event */ - __IOM uint32_t CACHEB2EN : 1; /*!< [31..31] Control CACHEB2 power-on status event */ - } MEMPWREVENTEN_b; - } ; -} PWRCTRL_Type; /*!< Size = 48 (0x30) */ - - - -/* =========================================================================================================================== */ -/* ================ RSTGEN ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief MCU Reset Generator (RSTGEN) - */ - -typedef struct { /*!< (@ 0x40000000) RSTGEN Structure */ - - union { - __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ - - struct { - __IOM uint32_t BODHREN : 1; /*!< [0..0] Brown out high (2.1v) reset enable. */ - __IOM uint32_t WDREN : 1; /*!< [1..1] Watchdog Timer Reset Enable. NOTE: The WDT module must - also be configured for WDT reset. This includes enabling - the RESEN bit in WDTCFG register in Watch dog timer block. */ - } CFG_b; - } ; - - union { - __IOM uint32_t SWPOI; /*!< (@ 0x00000004) Software POI Reset */ - - struct { - __IOM uint32_t SWPOIKEY : 8; /*!< [7..0] 0x1B generates a software POI reset. This is a write-only - register. Reading from this register will yield only all - 0s. */ - } SWPOI_b; - } ; - - union { - __IOM uint32_t SWPOR; /*!< (@ 0x00000008) Software POR Reset */ - - struct { - __IOM uint32_t SWPORKEY : 8; /*!< [7..0] 0xD4 generates a software POR reset. */ - } SWPOR_b; - } ; - __IM uint32_t RESERVED[2]; - - union { - __IOM uint32_t TPIURST; /*!< (@ 0x00000014) TPIU reset */ - - struct { - __IOM uint32_t TPIURST : 1; /*!< [0..0] Static reset for the TPIU. Write to '1' to assert reset - to TPIU. Write to '0' to clear the reset. */ - } TPIURST_b; - } ; - __IM uint32_t RESERVED1[122]; - - union { - __IOM uint32_t INTEN; /*!< (@ 0x00000200) Reset Interrupt register: Enable */ - - struct { - __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below - BODH level. */ - } INTEN_b; - } ; - - union { - __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Reset Interrupt register: Status */ - - struct { - __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below - BODH level. */ - } INTSTAT_b; - } ; - - union { - __IOM uint32_t INTCLR; /*!< (@ 0x00000208) Reset Interrupt register: Clear */ - - struct { - __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below - BODH level. */ - } INTCLR_b; - } ; - - union { - __IOM uint32_t INTSET; /*!< (@ 0x0000020C) Reset Interrupt register: Set */ - - struct { - __IOM uint32_t BODH : 1; /*!< [0..0] Enables an interrupt that triggers when VCC is below - BODH level. */ - } INTSET_b; - } ; - __IM uint32_t RESERVED2[67107708]; - - union { - __IOM uint32_t STAT; /*!< (@ 0x0FFFF000) Status Register (SBL) */ - - struct { - __IOM uint32_t EXRSTAT : 1; /*!< [0..0] Reset was initiated by an External Reset (SBL). */ - __IOM uint32_t PORSTAT : 1; /*!< [1..1] Reset was initiated by a Power-On Reset (SBL). */ - __IOM uint32_t BORSTAT : 1; /*!< [2..2] Reset was initiated by a Brown-Out Reset (SBL). */ - __IOM uint32_t SWRSTAT : 1; /*!< [3..3] Reset was a initiated by SW POR or AIRCR Reset (SBL). */ - __IOM uint32_t POIRSTAT : 1; /*!< [4..4] Reset was a initiated by Software POI Reset (SBL). */ - __IOM uint32_t DBGRSTAT : 1; /*!< [5..5] Reset was a initiated by Debugger Reset (SBL). */ - __IOM uint32_t WDRSTAT : 1; /*!< [6..6] Reset was initiated by a Watchdog Timer Reset (SBL). */ - __IOM uint32_t BOUSTAT : 1; /*!< [7..7] An Unregulated Supply Brownout Event occurred (SBL). */ - __IOM uint32_t BOCSTAT : 1; /*!< [8..8] A Core Regulator Brownout Event occurred (SBL). */ - __IOM uint32_t BOFSTAT : 1; /*!< [9..9] A Memory Regulator Brownout Event occurred (SBL). */ - __IOM uint32_t BOBSTAT : 1; /*!< [10..10] A BLE/Burst Regulator Brownout Event occurred (SBL). */ - __IM uint32_t : 19; - __IOM uint32_t FBOOT : 1; /*!< [30..30] Set if current boot was initiated by soft reset and - resulted in Fast Boot (SBL). */ - __IOM uint32_t SBOOT : 1; /*!< [31..31] Set when booting securely (SBL). */ - } STAT_b; - } ; -} RSTGEN_Type; /*!< Size = 268431364 (0xffff004) */ - - - -/* =========================================================================================================================== */ -/* ================ RTC ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Real Time Clock (RTC) - */ - -typedef struct { /*!< (@ 0x40004200) RTC Structure */ - __IM uint32_t RESERVED[16]; - - union { - __IOM uint32_t CTRLOW; /*!< (@ 0x00000040) RTC Counters Lower */ - - struct { - __IOM uint32_t CTR100 : 8; /*!< [7..0] 100ths of a second Counter */ - __IOM uint32_t CTRSEC : 7; /*!< [14..8] Seconds Counter */ - __IM uint32_t : 1; - __IOM uint32_t CTRMIN : 7; /*!< [22..16] Minutes Counter */ - __IM uint32_t : 1; - __IOM uint32_t CTRHR : 6; /*!< [29..24] Hours Counter */ - } CTRLOW_b; - } ; - - union { - __IOM uint32_t CTRUP; /*!< (@ 0x00000044) RTC Counters Upper */ - - struct { - __IOM uint32_t CTRDATE : 6; /*!< [5..0] Date Counter */ - __IM uint32_t : 2; - __IOM uint32_t CTRMO : 5; /*!< [12..8] Months Counter */ - __IM uint32_t : 3; - __IOM uint32_t CTRYR : 8; /*!< [23..16] Years Counter */ - __IOM uint32_t CTRWKDY : 3; /*!< [26..24] Weekdays Counter */ - __IOM uint32_t CB : 1; /*!< [27..27] Century */ - __IOM uint32_t CEB : 1; /*!< [28..28] Century enable */ - __IM uint32_t : 2; - __IOM uint32_t CTERR : 1; /*!< [31..31] Counter read error status. Error is triggered when - software reads the lower word of the counters, and fails - to read the upper counter within 1/100 second. This is - because when the lower counter is read, the upper counter - is held off from incrementing until it is read so that - the full time stamp can be read. */ - } CTRUP_b; - } ; - - union { - __IOM uint32_t ALMLOW; /*!< (@ 0x00000048) RTC Alarms Lower */ - - struct { - __IOM uint32_t ALM100 : 8; /*!< [7..0] 100ths of a second Alarm */ - __IOM uint32_t ALMSEC : 7; /*!< [14..8] Seconds Alarm */ - __IM uint32_t : 1; - __IOM uint32_t ALMMIN : 7; /*!< [22..16] Minutes Alarm */ - __IM uint32_t : 1; - __IOM uint32_t ALMHR : 6; /*!< [29..24] Hours Alarm */ - } ALMLOW_b; - } ; - - union { - __IOM uint32_t ALMUP; /*!< (@ 0x0000004C) RTC Alarms Upper */ - - struct { - __IOM uint32_t ALMDATE : 6; /*!< [5..0] Date Alarm */ - __IM uint32_t : 2; - __IOM uint32_t ALMMO : 5; /*!< [12..8] Months Alarm */ - __IM uint32_t : 3; - __IOM uint32_t ALMWKDY : 3; /*!< [18..16] Weekdays Alarm */ - } ALMUP_b; - } ; - - union { - __IOM uint32_t RTCCTL; /*!< (@ 0x00000050) RTC Control Register */ - - struct { - __IOM uint32_t WRTC : 1; /*!< [0..0] Counter write control */ - __IOM uint32_t RPT : 3; /*!< [3..1] Alarm repeat interval */ - __IOM uint32_t RSTOP : 1; /*!< [4..4] RTC input clock control */ - __IOM uint32_t HR1224 : 1; /*!< [5..5] Hours Counter mode */ - } RTCCTL_b; - } ; - __IM uint32_t RESERVED1[43]; - - union { - __IOM uint32_t INTEN; /*!< (@ 0x00000100) RTC Interrupt Register: Enable */ - - struct { - __IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */ - } INTEN_b; - } ; - - union { - __IOM uint32_t INTSTAT; /*!< (@ 0x00000104) RTC Interrupt Register: Status */ - - struct { - __IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */ - } INTSTAT_b; - } ; - - union { - __IOM uint32_t INTCLR; /*!< (@ 0x00000108) RTC Interrupt Register: Clear */ - - struct { - __IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */ - } INTCLR_b; - } ; - - union { - __IOM uint32_t INTSET; /*!< (@ 0x0000010C) RTC Interrupt Register: Set */ - - struct { - __IOM uint32_t ALM : 1; /*!< [0..0] RTC Alarm interrupt */ - } INTSET_b; - } ; -} RTC_Type; /*!< Size = 272 (0x110) */ - - - -/* =========================================================================================================================== */ -/* ================ SCARD ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Serial ISO7816 (SCARD) - */ - -typedef struct { /*!< (@ 0x40080000) SCARD Structure */ - - union { - __IOM uint32_t SR; /*!< (@ 0x00000000) ISO7816 interrupt status */ - - struct { - __IOM uint32_t FNE : 1; /*!< [0..0] RX FIFO not empty. */ - __IOM uint32_t TBERBF : 1; /*!< [1..1] FIFO empty (transmit) or full (receive). */ - __IOM uint32_t FER : 1; /*!< [2..2] Framing error. */ - __IOM uint32_t OVR : 1; /*!< [3..3] RX FIFO overflow. */ - __IOM uint32_t PE : 1; /*!< [4..4] Parity Error. */ - __IOM uint32_t FT2REND : 1; /*!< [5..5] TX to RX finished. */ - __IOM uint32_t FHF : 1; /*!< [6..6] FIFO Half Full. */ - } SR_b; - } ; - - union { - __IOM uint32_t IER; /*!< (@ 0x00000004) ISO7816 interrupt enable */ - - struct { - __IOM uint32_t FNEEN : 1; /*!< [0..0] RX FIFO not empty interrupt enable. */ - __IOM uint32_t TBERBFEN : 1; /*!< [1..1] FIFO empty (transmit) or full (receive) interrupt enable. */ - __IOM uint32_t FEREN : 1; /*!< [2..2] Framing error interrupt enable. */ - __IOM uint32_t OVREN : 1; /*!< [3..3] RX FIFOI overflow interrupt enable. */ - __IOM uint32_t PEEN : 1; /*!< [4..4] Parity Error interrupt enable. */ - __IOM uint32_t FT2RENDEN : 1; /*!< [5..5] TX to RX finished interrupt enable. */ - __IOM uint32_t FHFEN : 1; /*!< [6..6] FIFO Half Full interrupt enable. */ - } IER_b; - } ; - - union { - __IOM uint32_t TCR; /*!< (@ 0x00000008) ISO7816 transmit control */ - - struct { - __IOM uint32_t CONV : 1; /*!< [0..0] Conversion inversion control. */ - __IOM uint32_t SS : 1; /*!< [1..1] Use first byte to configure conversion. */ - __IOM uint32_t LCT : 1; /*!< [2..2] Fast TX to RX. */ - __IOM uint32_t TR : 1; /*!< [3..3] Transmit/receive mode. */ - __IOM uint32_t PROT : 1; /*!< [4..4] PROT control. */ - __IOM uint32_t AUTOCONV : 1; /*!< [5..5] Automatic conversion. */ - __IOM uint32_t FIP : 1; /*!< [6..6] Parity select. */ - __IOM uint32_t DMAMD : 1; /*!< [7..7] DMA direction. */ - } TCR_b; - } ; - - union { - __IOM uint32_t UCR; /*!< (@ 0x0000000C) ISO7816 user control */ - - struct { - __IOM uint32_t CST : 1; /*!< [0..0] Clock control. */ - __IOM uint32_t RIU : 1; /*!< [1..1] ISO7816 reset. This bit is write-only. */ - __IOM uint32_t RSTIN : 1; /*!< [2..2] Reset polarity. */ - __IOM uint32_t RETXEN : 1; /*!< [3..3] Enable TX/RX time configuration. */ - } UCR_b; - } ; - - union { - __IOM uint32_t DR; /*!< (@ 0x00000010) ISO7816 data */ - - struct { - __IOM uint32_t DR : 8; /*!< [7..0] Data register. */ - } DR_b; - } ; - - union { - __IOM uint32_t BPRL; /*!< (@ 0x00000014) ISO7816 baud rate low */ - - struct { - __IOM uint32_t BPRL : 8; /*!< [7..0] Baud rate low */ - } BPRL_b; - } ; - - union { - __IOM uint32_t BPRH; /*!< (@ 0x00000018) ISO7816 baud rate high */ - - struct { - __IOM uint32_t BPRH : 4; /*!< [3..0] Baud rate high */ - } BPRH_b; - } ; - - union { - __IOM uint32_t UCR1; /*!< (@ 0x0000001C) ISO7816 user control 1 */ - - struct { - __IOM uint32_t PR : 1; /*!< [0..0] Query Card Detect. */ - __IM uint32_t : 1; - __IOM uint32_t STSP : 1; /*!< [2..2] ETU counter control. This bit is write-only. */ - __IOM uint32_t T1PAREN : 1; /*!< [3..3] Parity check control. */ - __IOM uint32_t CLKIOV : 1; /*!< [4..4] Output clock level. */ - __IOM uint32_t ENLASTB : 1; /*!< [5..5] Enable last byte function. */ - } UCR1_b; - } ; - - union { - __IOM uint32_t SR1; /*!< (@ 0x00000020) ISO7816 interrupt status 1 */ - - struct { - __IOM uint32_t ECNTOVER : 1; /*!< [0..0] ETU counter overflow. */ - __IOM uint32_t PRL : 1; /*!< [1..1] Card insert/remove. */ - __IOM uint32_t SYNCEND : 1; /*!< [2..2] Write complete synchronization. */ - __IOM uint32_t IDLE : 1; /*!< [3..3] ISO7816 idle. */ - } SR1_b; - } ; - - union { - __IOM uint32_t IER1; /*!< (@ 0x00000024) ISO7816 interrupt enable 1 */ - - struct { - __IOM uint32_t ECNTOVEREN : 1; /*!< [0..0] ETU counter overflow interrupt enable. */ - __IOM uint32_t PRLEN : 1; /*!< [1..1] Card insert/remove interrupt enable. */ - __IOM uint32_t SYNCENDEN : 1; /*!< [2..2] Write complete synchronization interrupt enable. */ - } IER1_b; - } ; - - union { - __IOM uint32_t ECNTL; /*!< (@ 0x00000028) ETU counter low */ - - struct { - __IOM uint32_t ECNTL : 8; /*!< [7..0] ETU counter low register. */ - } ECNTL_b; - } ; - - union { - __IOM uint32_t ECNTH; /*!< (@ 0x0000002C) ETU counter high */ - - struct { - __IOM uint32_t ECNTH : 8; /*!< [7..0] ETU counter high register. */ - } ECNTH_b; - } ; - - union { - __IOM uint32_t GTR; /*!< (@ 0x00000030) ISO7816 guard time configuration */ - - struct { - __IOM uint32_t GTR : 8; /*!< [7..0] Guard time configuration register. */ - } GTR_b; - } ; - - union { - __IOM uint32_t RETXCNT; /*!< (@ 0x00000034) ISO7816 resend count */ - - struct { - __IOM uint32_t RETXCNT : 4; /*!< [3..0] Resend count register. */ - } RETXCNT_b; - } ; - - union { - __IOM uint32_t RETXCNTRMI; /*!< (@ 0x00000038) ISO7816 resent count inquiry */ - - struct { - __IOM uint32_t RETXCNTRMI : 4; /*!< [3..0] Resent count inquiry register. */ - } RETXCNTRMI_b; - } ; - __IM uint32_t RESERVED[49]; - - union { - __IOM uint32_t CLKCTRL; /*!< (@ 0x00000100) Clock Control */ - - struct { - __IOM uint32_t CLKEN : 1; /*!< [0..0] Enable the serial source clock for SCARD. */ - __IOM uint32_t APBCLKEN : 1; /*!< [1..1] Enable the SCARD APB clock to run continuously. */ - } CLKCTRL_b; - } ; -} SCARD_Type; /*!< Size = 260 (0x104) */ - - - -/* =========================================================================================================================== */ -/* ================ SECURITY ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Security Interfaces (SECURITY) - */ - -typedef struct { /*!< (@ 0x40030000) SECURITY Structure */ - - union { - __IOM uint32_t CTRL; /*!< (@ 0x00000000) Control Register */ - - struct { - __IOM uint32_t ENABLE : 1; /*!< [0..0] Function Enable. Software should set the ENABLE bit to - initiate a CRC operation. Hardware will clear the ENABLE - bit upon completion. */ - __IM uint32_t : 3; - __IOM uint32_t FUNCTION : 4; /*!< [7..4] Function Select */ - __IM uint32_t : 23; - __IOM uint32_t CRCERROR : 1; /*!< [31..31] CRC Error Status - Set to 1 if an error occurs during - a CRC operation. Cleared when CTRL register is written - (with any value). Usually indicates an invalid address - range. */ - } CTRL_b; - } ; - __IM uint32_t RESERVED[3]; - - union { - __IOM uint32_t SRCADDR; /*!< (@ 0x00000010) Source Addresss */ - - struct { - __IOM uint32_t ADDR : 32; /*!< [31..0] Source Buffer Address. Address may be byte aligned, - but the length must be a multiple of 4 bits. */ - } SRCADDR_b; - } ; - __IM uint32_t RESERVED1[3]; - - union { - __IOM uint32_t LEN; /*!< (@ 0x00000020) Length */ - - struct { - __IM uint32_t : 2; - __IOM uint32_t LEN : 22; /*!< [23..2] Buffer size (bottom two bits assumed to be zero to ensure - a multiple of 4 bytes) */ - } LEN_b; - } ; - __IM uint32_t RESERVED2[3]; - - union { - __IOM uint32_t RESULT; /*!< (@ 0x00000030) CRC Seed/Result Register */ - - struct { - __IOM uint32_t CRC : 32; /*!< [31..0] CRC Seed/Result. Software must seed the CRC with 0xFFFFFFFF - before starting a CRC operation (unless the CRC is continued - from a previous operation). */ - } RESULT_b; - } ; - __IM uint32_t RESERVED3[17]; - - union { - __IOM uint32_t LOCKCTRL; /*!< (@ 0x00000078) LOCK Control Register */ - - struct { - __IOM uint32_t SELECT : 8; /*!< [7..0] LOCK Function Select register. */ - } LOCKCTRL_b; - } ; - - union { - __IOM uint32_t LOCKSTAT; /*!< (@ 0x0000007C) LOCK Status Register */ - - struct { - __IOM uint32_t STATUS : 32; /*!< [31..0] LOCK Status register. This register is a bitmask for - which resources are currently unlocked. These bits are - one-hot per resource. */ - } LOCKSTAT_b; - } ; - - union { - __IOM uint32_t KEY0; /*!< (@ 0x00000080) Key0 Register */ - - struct { - __IOM uint32_t KEY0 : 32; /*!< [31..0] Bits [31:0] of the 128-bit key should be written to - this register. To protect key values, the register always - returns 0x00000000. */ - } KEY0_b; - } ; - - union { - __IOM uint32_t KEY1; /*!< (@ 0x00000084) Key1 Register */ - - struct { - __IOM uint32_t KEY1 : 32; /*!< [31..0] Bits [63:32] of the 128-bit key should be written to - this register. To protect key values, the register always - returns 0x00000000. */ - } KEY1_b; - } ; - - union { - __IOM uint32_t KEY2; /*!< (@ 0x00000088) Key2 Register */ - - struct { - __IOM uint32_t KEY2 : 32; /*!< [31..0] Bits [95:64] of the 128-bit key should be written to - this register. To protect key values, the register always - returns 0x00000000. */ - } KEY2_b; - } ; - - union { - __IOM uint32_t KEY3; /*!< (@ 0x0000008C) Key3 Register */ - - struct { - __IOM uint32_t KEY3 : 32; /*!< [31..0] Bits [127:96] of the 128-bit key should be written to - this register. To protect key values, the register always - returns 0x00000000. */ - } KEY3_b; - } ; -} SECURITY_Type; /*!< Size = 144 (0x90) */ - - - -/* =========================================================================================================================== */ -/* ================ UART0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Serial UART (UART0) - */ - -typedef struct { /*!< (@ 0x4001C000) UART0 Structure */ - - union { - __IOM uint32_t DR; /*!< (@ 0x00000000) UART Data Register */ - - struct { - __IOM uint32_t DATA : 8; /*!< [7..0] This is the UART data port. */ - __IOM uint32_t FEDATA : 1; /*!< [8..8] This is the framing error indicator. */ - __IOM uint32_t PEDATA : 1; /*!< [9..9] This is the parity error indicator. */ - __IOM uint32_t BEDATA : 1; /*!< [10..10] This is the break error indicator. */ - __IOM uint32_t OEDATA : 1; /*!< [11..11] This is the overrun error indicator. */ - } DR_b; - } ; - - union { - __IOM uint32_t RSR; /*!< (@ 0x00000004) UART Status Register */ - - struct { - __IOM uint32_t FESTAT : 1; /*!< [0..0] This is the framing error indicator. */ - __IOM uint32_t PESTAT : 1; /*!< [1..1] This is the parity error indicator. */ - __IOM uint32_t BESTAT : 1; /*!< [2..2] This is the break error indicator. */ - __IOM uint32_t OESTAT : 1; /*!< [3..3] This is the overrun error indicator. */ - } RSR_b; - } ; - __IM uint32_t RESERVED[4]; - - union { - __IOM uint32_t FR; /*!< (@ 0x00000018) Flag Register */ - - struct { - __IOM uint32_t CTS : 1; /*!< [0..0] This bit holds the clear to send indicator. */ - __IOM uint32_t DSR : 1; /*!< [1..1] This bit holds the data set ready indicator. */ - __IOM uint32_t DCD : 1; /*!< [2..2] This bit holds the data carrier detect indicator. */ - __IOM uint32_t BUSY : 1; /*!< [3..3] This bit holds the busy indicator. */ - __IOM uint32_t RXFE : 1; /*!< [4..4] This bit holds the receive FIFO empty indicator. */ - __IOM uint32_t TXFF : 1; /*!< [5..5] This bit holds the transmit FIFO full indicator. */ - __IOM uint32_t RXFF : 1; /*!< [6..6] This bit holds the receive FIFO full indicator. */ - __IOM uint32_t TXFE : 1; /*!< [7..7] This bit holds the transmit FIFO empty indicator. */ - __IOM uint32_t TXBUSY : 1; /*!< [8..8] This bit holds the transmit BUSY indicator. */ - } FR_b; - } ; - __IM uint32_t RESERVED1; - - union { - __IOM uint32_t ILPR; /*!< (@ 0x00000020) IrDA Counter */ - - struct { - __IOM uint32_t ILPDVSR : 8; /*!< [7..0] These bits hold the IrDA counter divisor. */ - } ILPR_b; - } ; - - union { - __IOM uint32_t IBRD; /*!< (@ 0x00000024) Integer Baud Rate Divisor */ - - struct { - __IOM uint32_t DIVINT : 16; /*!< [15..0] These bits hold the baud integer divisor. */ - } IBRD_b; - } ; - - union { - __IOM uint32_t FBRD; /*!< (@ 0x00000028) Fractional Baud Rate Divisor */ - - struct { - __IOM uint32_t DIVFRAC : 6; /*!< [5..0] These bits hold the baud fractional divisor. */ - } FBRD_b; - } ; - - union { - __IOM uint32_t LCRH; /*!< (@ 0x0000002C) Line Control High */ - - struct { - __IOM uint32_t BRK : 1; /*!< [0..0] This bit holds the break set. */ - __IOM uint32_t PEN : 1; /*!< [1..1] This bit holds the parity enable. */ - __IOM uint32_t EPS : 1; /*!< [2..2] This bit holds the even parity select. */ - __IOM uint32_t STP2 : 1; /*!< [3..3] This bit holds the two stop bits select. */ - __IOM uint32_t FEN : 1; /*!< [4..4] This bit holds the FIFO enable. */ - __IOM uint32_t WLEN : 2; /*!< [6..5] These bits hold the write length. */ - __IOM uint32_t SPS : 1; /*!< [7..7] This bit holds the stick parity select. */ - } LCRH_b; - } ; - - union { - __IOM uint32_t CR; /*!< (@ 0x00000030) Control Register */ - - struct { - __IOM uint32_t UARTEN : 1; /*!< [0..0] This bit is the UART enable. */ - __IOM uint32_t SIREN : 1; /*!< [1..1] This bit is the SIR ENDEC enable. */ - __IOM uint32_t SIRLP : 1; /*!< [2..2] This bit is the SIR low power select. */ - __IOM uint32_t CLKEN : 1; /*!< [3..3] This bit is the UART clock enable. */ - __IOM uint32_t CLKSEL : 3; /*!< [6..4] This bitfield is the UART clock select. */ - __IOM uint32_t LBE : 1; /*!< [7..7] This bit is the loopback enable. */ - __IOM uint32_t TXE : 1; /*!< [8..8] This bit is the transmit enable. */ - __IOM uint32_t RXE : 1; /*!< [9..9] This bit is the receive enable. */ - __IOM uint32_t DTR : 1; /*!< [10..10] This bit enables data transmit ready. */ - __IOM uint32_t RTS : 1; /*!< [11..11] This bit enables request to send. */ - __IOM uint32_t OUT1 : 1; /*!< [12..12] This bit holds modem Out1. */ - __IOM uint32_t OUT2 : 1; /*!< [13..13] This bit holds modem Out2. */ - __IOM uint32_t RTSEN : 1; /*!< [14..14] This bit enables RTS hardware flow control. */ - __IOM uint32_t CTSEN : 1; /*!< [15..15] This bit enables CTS hardware flow control. */ - } CR_b; - } ; - - union { - __IOM uint32_t IFLS; /*!< (@ 0x00000034) FIFO Interrupt Level Select */ - - struct { - __IOM uint32_t TXIFLSEL : 3; /*!< [2..0] These bits hold the transmit FIFO interrupt level. */ - __IOM uint32_t RXIFLSEL : 3; /*!< [5..3] These bits hold the receive FIFO interrupt level. */ - } IFLS_b; - } ; - - union { - __IOM uint32_t IER; /*!< (@ 0x00000038) Interrupt Enable */ - - struct { - __IOM uint32_t TXCMPMIM : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt enable. */ - __IOM uint32_t CTSMIM : 1; /*!< [1..1] This bit holds the modem CTS interrupt enable. */ - __IOM uint32_t DCDMIM : 1; /*!< [2..2] This bit holds the modem DCD interrupt enable. */ - __IOM uint32_t DSRMIM : 1; /*!< [3..3] This bit holds the modem DSR interrupt enable. */ - __IOM uint32_t RXIM : 1; /*!< [4..4] This bit holds the receive interrupt enable. */ - __IOM uint32_t TXIM : 1; /*!< [5..5] This bit holds the transmit interrupt enable. */ - __IOM uint32_t RTIM : 1; /*!< [6..6] This bit holds the receive timeout interrupt enable. */ - __IOM uint32_t FEIM : 1; /*!< [7..7] This bit holds the framing error interrupt enable. */ - __IOM uint32_t PEIM : 1; /*!< [8..8] This bit holds the parity error interrupt enable. */ - __IOM uint32_t BEIM : 1; /*!< [9..9] This bit holds the break error interrupt enable. */ - __IOM uint32_t OEIM : 1; /*!< [10..10] This bit holds the overflow interrupt enable. */ - } IER_b; - } ; - - union { - __IOM uint32_t IES; /*!< (@ 0x0000003C) Interrupt Status */ - - struct { - __IOM uint32_t TXCMPMRIS : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt status. */ - __IOM uint32_t CTSMRIS : 1; /*!< [1..1] This bit holds the modem CTS interrupt status. */ - __IOM uint32_t DCDMRIS : 1; /*!< [2..2] This bit holds the modem DCD interrupt status. */ - __IOM uint32_t DSRMRIS : 1; /*!< [3..3] This bit holds the modem DSR interrupt status. */ - __IOM uint32_t RXRIS : 1; /*!< [4..4] This bit holds the receive interrupt status. */ - __IOM uint32_t TXRIS : 1; /*!< [5..5] This bit holds the transmit interrupt status. */ - __IOM uint32_t RTRIS : 1; /*!< [6..6] This bit holds the receive timeout interrupt status. */ - __IOM uint32_t FERIS : 1; /*!< [7..7] This bit holds the framing error interrupt status. */ - __IOM uint32_t PERIS : 1; /*!< [8..8] This bit holds the parity error interrupt status. */ - __IOM uint32_t BERIS : 1; /*!< [9..9] This bit holds the break error interrupt status. */ - __IOM uint32_t OERIS : 1; /*!< [10..10] This bit holds the overflow interrupt status. */ - } IES_b; - } ; - - union { - __IOM uint32_t MIS; /*!< (@ 0x00000040) Masked Interrupt Status */ - - struct { - __IOM uint32_t TXCMPMMIS : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt status masked. */ - __IOM uint32_t CTSMMIS : 1; /*!< [1..1] This bit holds the modem CTS interrupt status masked. */ - __IOM uint32_t DCDMMIS : 1; /*!< [2..2] This bit holds the modem DCD interrupt status masked. */ - __IOM uint32_t DSRMMIS : 1; /*!< [3..3] This bit holds the modem DSR interrupt status masked. */ - __IOM uint32_t RXMIS : 1; /*!< [4..4] This bit holds the receive interrupt status masked. */ - __IOM uint32_t TXMIS : 1; /*!< [5..5] This bit holds the transmit interrupt status masked. */ - __IOM uint32_t RTMIS : 1; /*!< [6..6] This bit holds the receive timeout interrupt status masked. */ - __IOM uint32_t FEMIS : 1; /*!< [7..7] This bit holds the framing error interrupt status masked. */ - __IOM uint32_t PEMIS : 1; /*!< [8..8] This bit holds the parity error interrupt status masked. */ - __IOM uint32_t BEMIS : 1; /*!< [9..9] This bit holds the break error interrupt status masked. */ - __IOM uint32_t OEMIS : 1; /*!< [10..10] This bit holds the overflow interrupt status masked. */ - } MIS_b; - } ; - - union { - __IOM uint32_t IEC; /*!< (@ 0x00000044) Interrupt Clear */ - - struct { - __IOM uint32_t TXCMPMIC : 1; /*!< [0..0] This bit holds the modem TXCMP interrupt clear. */ - __IOM uint32_t CTSMIC : 1; /*!< [1..1] This bit holds the modem CTS interrupt clear. */ - __IOM uint32_t DCDMIC : 1; /*!< [2..2] This bit holds the modem DCD interrupt clear. */ - __IOM uint32_t DSRMIC : 1; /*!< [3..3] This bit holds the modem DSR interrupt clear. */ - __IOM uint32_t RXIC : 1; /*!< [4..4] This bit holds the receive interrupt clear. */ - __IOM uint32_t TXIC : 1; /*!< [5..5] This bit holds the transmit interrupt clear. */ - __IOM uint32_t RTIC : 1; /*!< [6..6] This bit holds the receive timeout interrupt clear. */ - __IOM uint32_t FEIC : 1; /*!< [7..7] This bit holds the framing error interrupt clear. */ - __IOM uint32_t PEIC : 1; /*!< [8..8] This bit holds the parity error interrupt clear. */ - __IOM uint32_t BEIC : 1; /*!< [9..9] This bit holds the break error interrupt clear. */ - __IOM uint32_t OEIC : 1; /*!< [10..10] This bit holds the overflow interrupt clear. */ - } IEC_b; - } ; -} UART0_Type; /*!< Size = 72 (0x48) */ - - - -/* =========================================================================================================================== */ -/* ================ VCOMP ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Voltage Comparator (VCOMP) - */ - -typedef struct { /*!< (@ 0x4000C000) VCOMP Structure */ - - union { - __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ - - struct { - __IOM uint32_t PSEL : 2; /*!< [1..0] This bitfield selects the positive input to the comparator. */ - __IM uint32_t : 6; - __IOM uint32_t NSEL : 2; /*!< [9..8] This bitfield selects the negative input to the comparator. */ - __IM uint32_t : 6; - __IOM uint32_t LVLSEL : 4; /*!< [19..16] When the reference input NSEL is set to NSEL_DAC, this - bitfield selects the voltage level for the negative input - to the comparator. */ - } CFG_b; - } ; - - union { - __IOM uint32_t STAT; /*!< (@ 0x00000004) Status Register */ - - struct { - __IOM uint32_t CMPOUT : 1; /*!< [0..0] This bit is 1 if the positive input of the comparator - is greater than the negative input. */ - __IOM uint32_t PWDSTAT : 1; /*!< [1..1] This bit indicates the power down state of the voltage - comparator. */ - } STAT_b; - } ; - - union { - __IOM uint32_t PWDKEY; /*!< (@ 0x00000008) Key Register for Powering Down the Voltage Comparator */ - - struct { - __IOM uint32_t PWDKEY : 32; /*!< [31..0] Key register value. */ - } PWDKEY_b; - } ; - __IM uint32_t RESERVED[125]; - - union { - __IOM uint32_t INTEN; /*!< (@ 0x00000200) Voltage Comparator Interrupt registers: Enable */ - - struct { - __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ - __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ - } INTEN_b; - } ; - - union { - __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) Voltage Comparator Interrupt registers: Status */ - - struct { - __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ - __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ - } INTSTAT_b; - } ; - - union { - __IOM uint32_t INTCLR; /*!< (@ 0x00000208) Voltage Comparator Interrupt registers: Clear */ - - struct { - __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ - __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ - } INTCLR_b; - } ; - - union { - __IOM uint32_t INTSET; /*!< (@ 0x0000020C) Voltage Comparator Interrupt registers: Set */ - - struct { - __IOM uint32_t OUTLOW : 1; /*!< [0..0] This bit is the vcompout low interrupt. */ - __IOM uint32_t OUTHI : 1; /*!< [1..1] This bit is the vcompout high interrupt. */ - } INTSET_b; - } ; -} VCOMP_Type; /*!< Size = 528 (0x210) */ - - - -/* =========================================================================================================================== */ -/* ================ WDT ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Watchdog Timer (WDT) - */ - -typedef struct { /*!< (@ 0x40024000) WDT Structure */ - - union { - __IOM uint32_t CFG; /*!< (@ 0x00000000) Configuration Register */ - - struct { - __IOM uint32_t WDTEN : 1; /*!< [0..0] This bitfield enables the WDT. */ - __IOM uint32_t INTEN : 1; /*!< [1..1] This bitfield enables the WDT interrupt. Note : This - bit must be set before the interrupt status bit will reflect - a watchdog timer expiration. The IER interrupt register - must also be enabled for a WDT interrupt to be sent to - the NVIC. */ - __IOM uint32_t RESEN : 1; /*!< [2..2] This bitfield enables the WDT reset. This needs to be - set together with the WDREN bit in REG_RSTGEN_CFG register - (in reset gen) to trigger the reset. */ - __IM uint32_t : 5; - __IOM uint32_t RESVAL : 8; /*!< [15..8] This bitfield is the compare value for counter bits - 7:0 to generate a watchdog reset. This will cause a software - reset. */ - __IOM uint32_t INTVAL : 8; /*!< [23..16] This bitfield is the compare value for counter bits - 7:0 to generate a watchdog interrupt. */ - __IOM uint32_t CLKSEL : 3; /*!< [26..24] Select the frequency for the WDT. All values not enumerated - below are undefined. */ - } CFG_b; - } ; - - union { - __IOM uint32_t RSTRT; /*!< (@ 0x00000004) Restart the watchdog timer. */ - - struct { - __IOM uint32_t RSTRT : 8; /*!< [7..0] Writing 0xB2 to WDTRSTRT restarts the watchdog timer. - This is a write only register. Reading this register will - only provide all 0. */ - } RSTRT_b; - } ; - - union { - __IOM uint32_t LOCK; /*!< (@ 0x00000008) Locks the WDT */ - - struct { - __IOM uint32_t LOCK : 8; /*!< [7..0] Writing 0x3A locks the watchdog timer. Once locked, the - WDTCFG reg cannot be written and WDTEN is set. */ - } LOCK_b; - } ; - - union { - __IOM uint32_t COUNT; /*!< (@ 0x0000000C) Current Counter Value for WDT */ - - struct { - __IOM uint32_t COUNT : 8; /*!< [7..0] Read-Only current value of the WDT counter */ - } COUNT_b; - } ; - __IM uint32_t RESERVED[124]; - - union { - __IOM uint32_t INTEN; /*!< (@ 0x00000200) WDT Interrupt register: Enable */ - - struct { - __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ - } INTEN_b; - } ; - - union { - __IOM uint32_t INTSTAT; /*!< (@ 0x00000204) WDT Interrupt register: Status */ - - struct { - __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ - } INTSTAT_b; - } ; - - union { - __IOM uint32_t INTCLR; /*!< (@ 0x00000208) WDT Interrupt register: Clear */ - - struct { - __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ - } INTCLR_b; - } ; - - union { - __IOM uint32_t INTSET; /*!< (@ 0x0000020C) WDT Interrupt register: Set */ - - struct { - __IOM uint32_t WDTINT : 1; /*!< [0..0] Watchdog Timer Interrupt. */ - } INTSET_b; - } ; -} WDT_Type; /*!< Size = 528 (0x210) */ - - -/** @} */ /* End of group Device_Peripheral_peripherals */ - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_peripheralAddr - * @{ - */ - -#define ADC_BASE 0x50010000UL -#define APBDMA_BASE 0x40011000UL -#define BLEIF_BASE 0x5000C000UL -#define CACHECTRL_BASE 0x40018000UL -#define CLKGEN_BASE 0x40004000UL -#define CTIMER_BASE 0x40008000UL -#define GPIO_BASE 0x40010000UL -#define IOM0_BASE 0x50004000UL -#define IOM1_BASE 0x50005000UL -#define IOM2_BASE 0x50006000UL -#define IOM3_BASE 0x50007000UL -#define IOM4_BASE 0x50008000UL -#define IOM5_BASE 0x50009000UL -#define IOSLAVE_BASE 0x50000000UL -#define MCUCTRL_BASE 0x40020000UL -#define MSPI0_BASE 0x50014000UL -#define MSPI1_BASE 0x50015000UL -#define MSPI2_BASE 0x50016000UL -#define PDM_BASE 0x50011000UL -#define PWRCTRL_BASE 0x40021000UL -#define RSTGEN_BASE 0x40000000UL -#define RTC_BASE 0x40004200UL -#define SCARD_BASE 0x40080000UL -#define SECURITY_BASE 0x40030000UL -#define UART0_BASE 0x4001C000UL -#define UART1_BASE 0x4001D000UL -#define VCOMP_BASE 0x4000C000UL -#define WDT_BASE 0x40024000UL - -/** @} */ /* End of group Device_Peripheral_peripheralAddr */ - - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_declaration - * @{ - */ - -#define ADC ((ADC_Type*) ADC_BASE) -#define APBDMA ((APBDMA_Type*) APBDMA_BASE) -#define BLEIF ((BLEIF_Type*) BLEIF_BASE) -#define CACHECTRL ((CACHECTRL_Type*) CACHECTRL_BASE) -#define CLKGEN ((CLKGEN_Type*) CLKGEN_BASE) -#define CTIMER ((CTIMER_Type*) CTIMER_BASE) -#define GPIO ((GPIO_Type*) GPIO_BASE) -#define IOM0 ((IOM0_Type*) IOM0_BASE) -#define IOM1 ((IOM0_Type*) IOM1_BASE) -#define IOM2 ((IOM0_Type*) IOM2_BASE) -#define IOM3 ((IOM0_Type*) IOM3_BASE) -#define IOM4 ((IOM0_Type*) IOM4_BASE) -#define IOM5 ((IOM0_Type*) IOM5_BASE) -#define IOSLAVE ((IOSLAVE_Type*) IOSLAVE_BASE) -#define MCUCTRL ((MCUCTRL_Type*) MCUCTRL_BASE) -#define MSPI0 ((MSPI0_Type*) MSPI0_BASE) -#define MSPI1 ((MSPI0_Type*) MSPI1_BASE) -#define MSPI2 ((MSPI0_Type*) MSPI2_BASE) -#define PDM ((PDM_Type*) PDM_BASE) -#define PWRCTRL ((PWRCTRL_Type*) PWRCTRL_BASE) -#define RSTGEN ((RSTGEN_Type*) RSTGEN_BASE) -#define RTC ((RTC_Type*) RTC_BASE) -#define SCARD ((SCARD_Type*) SCARD_BASE) -#define SECURITY ((SECURITY_Type*) SECURITY_BASE) -#define UART0 ((UART0_Type*) UART0_BASE) -#define UART1 ((UART0_Type*) UART1_BASE) -#define VCOMP ((VCOMP_Type*) VCOMP_BASE) -#define WDT ((WDT_Type*) WDT_BASE) - -/** @} */ /* End of group Device_Peripheral_declaration */ - - -/* ========================================= End of section using anonymous unions ========================================= */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#endif - - -/* =========================================================================================================================== */ -/* ================ Pos/Mask Peripheral Section ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup PosMask_peripherals - * @{ - */ - - - -/* =========================================================================================================================== */ -/* ================ ADC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CFG ========================================================== */ -#define ADC_CFG_CLKSEL_Pos (24UL) /*!< ADC CFG: CLKSEL (Bit 24) */ -#define ADC_CFG_CLKSEL_Msk (0x3000000UL) /*!< ADC CFG: CLKSEL (Bitfield-Mask: 0x03) */ -#define ADC_CFG_TRIGPOL_Pos (19UL) /*!< ADC CFG: TRIGPOL (Bit 19) */ -#define ADC_CFG_TRIGPOL_Msk (0x80000UL) /*!< ADC CFG: TRIGPOL (Bitfield-Mask: 0x01) */ -#define ADC_CFG_TRIGSEL_Pos (16UL) /*!< ADC CFG: TRIGSEL (Bit 16) */ -#define ADC_CFG_TRIGSEL_Msk (0x70000UL) /*!< ADC CFG: TRIGSEL (Bitfield-Mask: 0x07) */ -#define ADC_CFG_DFIFORDEN_Pos (12UL) /*!< ADC CFG: DFIFORDEN (Bit 12) */ -#define ADC_CFG_DFIFORDEN_Msk (0x1000UL) /*!< ADC CFG: DFIFORDEN (Bitfield-Mask: 0x01) */ -#define ADC_CFG_REFSEL_Pos (8UL) /*!< ADC CFG: REFSEL (Bit 8) */ -#define ADC_CFG_REFSEL_Msk (0x300UL) /*!< ADC CFG: REFSEL (Bitfield-Mask: 0x03) */ -#define ADC_CFG_CKMODE_Pos (4UL) /*!< ADC CFG: CKMODE (Bit 4) */ -#define ADC_CFG_CKMODE_Msk (0x10UL) /*!< ADC CFG: CKMODE (Bitfield-Mask: 0x01) */ -#define ADC_CFG_LPMODE_Pos (3UL) /*!< ADC CFG: LPMODE (Bit 3) */ -#define ADC_CFG_LPMODE_Msk (0x8UL) /*!< ADC CFG: LPMODE (Bitfield-Mask: 0x01) */ -#define ADC_CFG_RPTEN_Pos (2UL) /*!< ADC CFG: RPTEN (Bit 2) */ -#define ADC_CFG_RPTEN_Msk (0x4UL) /*!< ADC CFG: RPTEN (Bitfield-Mask: 0x01) */ -#define ADC_CFG_ADCEN_Pos (0UL) /*!< ADC CFG: ADCEN (Bit 0) */ -#define ADC_CFG_ADCEN_Msk (0x1UL) /*!< ADC CFG: ADCEN (Bitfield-Mask: 0x01) */ -/* ========================================================= STAT ========================================================== */ -#define ADC_STAT_PWDSTAT_Pos (0UL) /*!< ADC STAT: PWDSTAT (Bit 0) */ -#define ADC_STAT_PWDSTAT_Msk (0x1UL) /*!< ADC STAT: PWDSTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== SWT ========================================================== */ -#define ADC_SWT_SWT_Pos (0UL) /*!< ADC SWT: SWT (Bit 0) */ -#define ADC_SWT_SWT_Msk (0xffUL) /*!< ADC SWT: SWT (Bitfield-Mask: 0xff) */ -/* ======================================================== SL0CFG ========================================================= */ -#define ADC_SL0CFG_ADSEL0_Pos (24UL) /*!< ADC SL0CFG: ADSEL0 (Bit 24) */ -#define ADC_SL0CFG_ADSEL0_Msk (0x7000000UL) /*!< ADC SL0CFG: ADSEL0 (Bitfield-Mask: 0x07) */ -#define ADC_SL0CFG_PRMODE0_Pos (16UL) /*!< ADC SL0CFG: PRMODE0 (Bit 16) */ -#define ADC_SL0CFG_PRMODE0_Msk (0x30000UL) /*!< ADC SL0CFG: PRMODE0 (Bitfield-Mask: 0x03) */ -#define ADC_SL0CFG_CHSEL0_Pos (8UL) /*!< ADC SL0CFG: CHSEL0 (Bit 8) */ -#define ADC_SL0CFG_CHSEL0_Msk (0xf00UL) /*!< ADC SL0CFG: CHSEL0 (Bitfield-Mask: 0x0f) */ -#define ADC_SL0CFG_WCEN0_Pos (1UL) /*!< ADC SL0CFG: WCEN0 (Bit 1) */ -#define ADC_SL0CFG_WCEN0_Msk (0x2UL) /*!< ADC SL0CFG: WCEN0 (Bitfield-Mask: 0x01) */ -#define ADC_SL0CFG_SLEN0_Pos (0UL) /*!< ADC SL0CFG: SLEN0 (Bit 0) */ -#define ADC_SL0CFG_SLEN0_Msk (0x1UL) /*!< ADC SL0CFG: SLEN0 (Bitfield-Mask: 0x01) */ -/* ======================================================== SL1CFG ========================================================= */ -#define ADC_SL1CFG_ADSEL1_Pos (24UL) /*!< ADC SL1CFG: ADSEL1 (Bit 24) */ -#define ADC_SL1CFG_ADSEL1_Msk (0x7000000UL) /*!< ADC SL1CFG: ADSEL1 (Bitfield-Mask: 0x07) */ -#define ADC_SL1CFG_PRMODE1_Pos (16UL) /*!< ADC SL1CFG: PRMODE1 (Bit 16) */ -#define ADC_SL1CFG_PRMODE1_Msk (0x30000UL) /*!< ADC SL1CFG: PRMODE1 (Bitfield-Mask: 0x03) */ -#define ADC_SL1CFG_CHSEL1_Pos (8UL) /*!< ADC SL1CFG: CHSEL1 (Bit 8) */ -#define ADC_SL1CFG_CHSEL1_Msk (0xf00UL) /*!< ADC SL1CFG: CHSEL1 (Bitfield-Mask: 0x0f) */ -#define ADC_SL1CFG_WCEN1_Pos (1UL) /*!< ADC SL1CFG: WCEN1 (Bit 1) */ -#define ADC_SL1CFG_WCEN1_Msk (0x2UL) /*!< ADC SL1CFG: WCEN1 (Bitfield-Mask: 0x01) */ -#define ADC_SL1CFG_SLEN1_Pos (0UL) /*!< ADC SL1CFG: SLEN1 (Bit 0) */ -#define ADC_SL1CFG_SLEN1_Msk (0x1UL) /*!< ADC SL1CFG: SLEN1 (Bitfield-Mask: 0x01) */ -/* ======================================================== SL2CFG ========================================================= */ -#define ADC_SL2CFG_ADSEL2_Pos (24UL) /*!< ADC SL2CFG: ADSEL2 (Bit 24) */ -#define ADC_SL2CFG_ADSEL2_Msk (0x7000000UL) /*!< ADC SL2CFG: ADSEL2 (Bitfield-Mask: 0x07) */ -#define ADC_SL2CFG_PRMODE2_Pos (16UL) /*!< ADC SL2CFG: PRMODE2 (Bit 16) */ -#define ADC_SL2CFG_PRMODE2_Msk (0x30000UL) /*!< ADC SL2CFG: PRMODE2 (Bitfield-Mask: 0x03) */ -#define ADC_SL2CFG_CHSEL2_Pos (8UL) /*!< ADC SL2CFG: CHSEL2 (Bit 8) */ -#define ADC_SL2CFG_CHSEL2_Msk (0xf00UL) /*!< ADC SL2CFG: CHSEL2 (Bitfield-Mask: 0x0f) */ -#define ADC_SL2CFG_WCEN2_Pos (1UL) /*!< ADC SL2CFG: WCEN2 (Bit 1) */ -#define ADC_SL2CFG_WCEN2_Msk (0x2UL) /*!< ADC SL2CFG: WCEN2 (Bitfield-Mask: 0x01) */ -#define ADC_SL2CFG_SLEN2_Pos (0UL) /*!< ADC SL2CFG: SLEN2 (Bit 0) */ -#define ADC_SL2CFG_SLEN2_Msk (0x1UL) /*!< ADC SL2CFG: SLEN2 (Bitfield-Mask: 0x01) */ -/* ======================================================== SL3CFG ========================================================= */ -#define ADC_SL3CFG_ADSEL3_Pos (24UL) /*!< ADC SL3CFG: ADSEL3 (Bit 24) */ -#define ADC_SL3CFG_ADSEL3_Msk (0x7000000UL) /*!< ADC SL3CFG: ADSEL3 (Bitfield-Mask: 0x07) */ -#define ADC_SL3CFG_PRMODE3_Pos (16UL) /*!< ADC SL3CFG: PRMODE3 (Bit 16) */ -#define ADC_SL3CFG_PRMODE3_Msk (0x30000UL) /*!< ADC SL3CFG: PRMODE3 (Bitfield-Mask: 0x03) */ -#define ADC_SL3CFG_CHSEL3_Pos (8UL) /*!< ADC SL3CFG: CHSEL3 (Bit 8) */ -#define ADC_SL3CFG_CHSEL3_Msk (0xf00UL) /*!< ADC SL3CFG: CHSEL3 (Bitfield-Mask: 0x0f) */ -#define ADC_SL3CFG_WCEN3_Pos (1UL) /*!< ADC SL3CFG: WCEN3 (Bit 1) */ -#define ADC_SL3CFG_WCEN3_Msk (0x2UL) /*!< ADC SL3CFG: WCEN3 (Bitfield-Mask: 0x01) */ -#define ADC_SL3CFG_SLEN3_Pos (0UL) /*!< ADC SL3CFG: SLEN3 (Bit 0) */ -#define ADC_SL3CFG_SLEN3_Msk (0x1UL) /*!< ADC SL3CFG: SLEN3 (Bitfield-Mask: 0x01) */ -/* ======================================================== SL4CFG ========================================================= */ -#define ADC_SL4CFG_ADSEL4_Pos (24UL) /*!< ADC SL4CFG: ADSEL4 (Bit 24) */ -#define ADC_SL4CFG_ADSEL4_Msk (0x7000000UL) /*!< ADC SL4CFG: ADSEL4 (Bitfield-Mask: 0x07) */ -#define ADC_SL4CFG_PRMODE4_Pos (16UL) /*!< ADC SL4CFG: PRMODE4 (Bit 16) */ -#define ADC_SL4CFG_PRMODE4_Msk (0x30000UL) /*!< ADC SL4CFG: PRMODE4 (Bitfield-Mask: 0x03) */ -#define ADC_SL4CFG_CHSEL4_Pos (8UL) /*!< ADC SL4CFG: CHSEL4 (Bit 8) */ -#define ADC_SL4CFG_CHSEL4_Msk (0xf00UL) /*!< ADC SL4CFG: CHSEL4 (Bitfield-Mask: 0x0f) */ -#define ADC_SL4CFG_WCEN4_Pos (1UL) /*!< ADC SL4CFG: WCEN4 (Bit 1) */ -#define ADC_SL4CFG_WCEN4_Msk (0x2UL) /*!< ADC SL4CFG: WCEN4 (Bitfield-Mask: 0x01) */ -#define ADC_SL4CFG_SLEN4_Pos (0UL) /*!< ADC SL4CFG: SLEN4 (Bit 0) */ -#define ADC_SL4CFG_SLEN4_Msk (0x1UL) /*!< ADC SL4CFG: SLEN4 (Bitfield-Mask: 0x01) */ -/* ======================================================== SL5CFG ========================================================= */ -#define ADC_SL5CFG_ADSEL5_Pos (24UL) /*!< ADC SL5CFG: ADSEL5 (Bit 24) */ -#define ADC_SL5CFG_ADSEL5_Msk (0x7000000UL) /*!< ADC SL5CFG: ADSEL5 (Bitfield-Mask: 0x07) */ -#define ADC_SL5CFG_PRMODE5_Pos (16UL) /*!< ADC SL5CFG: PRMODE5 (Bit 16) */ -#define ADC_SL5CFG_PRMODE5_Msk (0x30000UL) /*!< ADC SL5CFG: PRMODE5 (Bitfield-Mask: 0x03) */ -#define ADC_SL5CFG_CHSEL5_Pos (8UL) /*!< ADC SL5CFG: CHSEL5 (Bit 8) */ -#define ADC_SL5CFG_CHSEL5_Msk (0xf00UL) /*!< ADC SL5CFG: CHSEL5 (Bitfield-Mask: 0x0f) */ -#define ADC_SL5CFG_WCEN5_Pos (1UL) /*!< ADC SL5CFG: WCEN5 (Bit 1) */ -#define ADC_SL5CFG_WCEN5_Msk (0x2UL) /*!< ADC SL5CFG: WCEN5 (Bitfield-Mask: 0x01) */ -#define ADC_SL5CFG_SLEN5_Pos (0UL) /*!< ADC SL5CFG: SLEN5 (Bit 0) */ -#define ADC_SL5CFG_SLEN5_Msk (0x1UL) /*!< ADC SL5CFG: SLEN5 (Bitfield-Mask: 0x01) */ -/* ======================================================== SL6CFG ========================================================= */ -#define ADC_SL6CFG_ADSEL6_Pos (24UL) /*!< ADC SL6CFG: ADSEL6 (Bit 24) */ -#define ADC_SL6CFG_ADSEL6_Msk (0x7000000UL) /*!< ADC SL6CFG: ADSEL6 (Bitfield-Mask: 0x07) */ -#define ADC_SL6CFG_PRMODE6_Pos (16UL) /*!< ADC SL6CFG: PRMODE6 (Bit 16) */ -#define ADC_SL6CFG_PRMODE6_Msk (0x30000UL) /*!< ADC SL6CFG: PRMODE6 (Bitfield-Mask: 0x03) */ -#define ADC_SL6CFG_CHSEL6_Pos (8UL) /*!< ADC SL6CFG: CHSEL6 (Bit 8) */ -#define ADC_SL6CFG_CHSEL6_Msk (0xf00UL) /*!< ADC SL6CFG: CHSEL6 (Bitfield-Mask: 0x0f) */ -#define ADC_SL6CFG_WCEN6_Pos (1UL) /*!< ADC SL6CFG: WCEN6 (Bit 1) */ -#define ADC_SL6CFG_WCEN6_Msk (0x2UL) /*!< ADC SL6CFG: WCEN6 (Bitfield-Mask: 0x01) */ -#define ADC_SL6CFG_SLEN6_Pos (0UL) /*!< ADC SL6CFG: SLEN6 (Bit 0) */ -#define ADC_SL6CFG_SLEN6_Msk (0x1UL) /*!< ADC SL6CFG: SLEN6 (Bitfield-Mask: 0x01) */ -/* ======================================================== SL7CFG ========================================================= */ -#define ADC_SL7CFG_ADSEL7_Pos (24UL) /*!< ADC SL7CFG: ADSEL7 (Bit 24) */ -#define ADC_SL7CFG_ADSEL7_Msk (0x7000000UL) /*!< ADC SL7CFG: ADSEL7 (Bitfield-Mask: 0x07) */ -#define ADC_SL7CFG_PRMODE7_Pos (16UL) /*!< ADC SL7CFG: PRMODE7 (Bit 16) */ -#define ADC_SL7CFG_PRMODE7_Msk (0x30000UL) /*!< ADC SL7CFG: PRMODE7 (Bitfield-Mask: 0x03) */ -#define ADC_SL7CFG_CHSEL7_Pos (8UL) /*!< ADC SL7CFG: CHSEL7 (Bit 8) */ -#define ADC_SL7CFG_CHSEL7_Msk (0xf00UL) /*!< ADC SL7CFG: CHSEL7 (Bitfield-Mask: 0x0f) */ -#define ADC_SL7CFG_WCEN7_Pos (1UL) /*!< ADC SL7CFG: WCEN7 (Bit 1) */ -#define ADC_SL7CFG_WCEN7_Msk (0x2UL) /*!< ADC SL7CFG: WCEN7 (Bitfield-Mask: 0x01) */ -#define ADC_SL7CFG_SLEN7_Pos (0UL) /*!< ADC SL7CFG: SLEN7 (Bit 0) */ -#define ADC_SL7CFG_SLEN7_Msk (0x1UL) /*!< ADC SL7CFG: SLEN7 (Bitfield-Mask: 0x01) */ -/* ========================================================= WULIM ========================================================= */ -#define ADC_WULIM_ULIM_Pos (0UL) /*!< ADC WULIM: ULIM (Bit 0) */ -#define ADC_WULIM_ULIM_Msk (0xfffffUL) /*!< ADC WULIM: ULIM (Bitfield-Mask: 0xfffff) */ -/* ========================================================= WLLIM ========================================================= */ -#define ADC_WLLIM_LLIM_Pos (0UL) /*!< ADC WLLIM: LLIM (Bit 0) */ -#define ADC_WLLIM_LLIM_Msk (0xfffffUL) /*!< ADC WLLIM: LLIM (Bitfield-Mask: 0xfffff) */ -/* ======================================================== SCWLIM ========================================================= */ -#define ADC_SCWLIM_SCWLIMEN_Pos (0UL) /*!< ADC SCWLIM: SCWLIMEN (Bit 0) */ -#define ADC_SCWLIM_SCWLIMEN_Msk (0x1UL) /*!< ADC SCWLIM: SCWLIMEN (Bitfield-Mask: 0x01) */ -/* ========================================================= FIFO ========================================================== */ -#define ADC_FIFO_RSVD_Pos (31UL) /*!< ADC FIFO: RSVD (Bit 31) */ -#define ADC_FIFO_RSVD_Msk (0x80000000UL) /*!< ADC FIFO: RSVD (Bitfield-Mask: 0x01) */ -#define ADC_FIFO_SLOTNUM_Pos (28UL) /*!< ADC FIFO: SLOTNUM (Bit 28) */ -#define ADC_FIFO_SLOTNUM_Msk (0x70000000UL) /*!< ADC FIFO: SLOTNUM (Bitfield-Mask: 0x07) */ -#define ADC_FIFO_COUNT_Pos (20UL) /*!< ADC FIFO: COUNT (Bit 20) */ -#define ADC_FIFO_COUNT_Msk (0xff00000UL) /*!< ADC FIFO: COUNT (Bitfield-Mask: 0xff) */ -#define ADC_FIFO_DATA_Pos (0UL) /*!< ADC FIFO: DATA (Bit 0) */ -#define ADC_FIFO_DATA_Msk (0xfffffUL) /*!< ADC FIFO: DATA (Bitfield-Mask: 0xfffff) */ -/* ======================================================== FIFOPR ========================================================= */ -#define ADC_FIFOPR_RSVDPR_Pos (31UL) /*!< ADC FIFOPR: RSVDPR (Bit 31) */ -#define ADC_FIFOPR_RSVDPR_Msk (0x80000000UL) /*!< ADC FIFOPR: RSVDPR (Bitfield-Mask: 0x01) */ -#define ADC_FIFOPR_SLOTNUMPR_Pos (28UL) /*!< ADC FIFOPR: SLOTNUMPR (Bit 28) */ -#define ADC_FIFOPR_SLOTNUMPR_Msk (0x70000000UL) /*!< ADC FIFOPR: SLOTNUMPR (Bitfield-Mask: 0x07) */ -#define ADC_FIFOPR_COUNT_Pos (20UL) /*!< ADC FIFOPR: COUNT (Bit 20) */ -#define ADC_FIFOPR_COUNT_Msk (0xff00000UL) /*!< ADC FIFOPR: COUNT (Bitfield-Mask: 0xff) */ -#define ADC_FIFOPR_DATA_Pos (0UL) /*!< ADC FIFOPR: DATA (Bit 0) */ -#define ADC_FIFOPR_DATA_Msk (0xfffffUL) /*!< ADC FIFOPR: DATA (Bitfield-Mask: 0xfffff) */ -/* ========================================================= INTEN ========================================================= */ -#define ADC_INTEN_DERR_Pos (7UL) /*!< ADC INTEN: DERR (Bit 7) */ -#define ADC_INTEN_DERR_Msk (0x80UL) /*!< ADC INTEN: DERR (Bitfield-Mask: 0x01) */ -#define ADC_INTEN_DCMP_Pos (6UL) /*!< ADC INTEN: DCMP (Bit 6) */ -#define ADC_INTEN_DCMP_Msk (0x40UL) /*!< ADC INTEN: DCMP (Bitfield-Mask: 0x01) */ -#define ADC_INTEN_WCINC_Pos (5UL) /*!< ADC INTEN: WCINC (Bit 5) */ -#define ADC_INTEN_WCINC_Msk (0x20UL) /*!< ADC INTEN: WCINC (Bitfield-Mask: 0x01) */ -#define ADC_INTEN_WCEXC_Pos (4UL) /*!< ADC INTEN: WCEXC (Bit 4) */ -#define ADC_INTEN_WCEXC_Msk (0x10UL) /*!< ADC INTEN: WCEXC (Bitfield-Mask: 0x01) */ -#define ADC_INTEN_FIFOOVR2_Pos (3UL) /*!< ADC INTEN: FIFOOVR2 (Bit 3) */ -#define ADC_INTEN_FIFOOVR2_Msk (0x8UL) /*!< ADC INTEN: FIFOOVR2 (Bitfield-Mask: 0x01) */ -#define ADC_INTEN_FIFOOVR1_Pos (2UL) /*!< ADC INTEN: FIFOOVR1 (Bit 2) */ -#define ADC_INTEN_FIFOOVR1_Msk (0x4UL) /*!< ADC INTEN: FIFOOVR1 (Bitfield-Mask: 0x01) */ -#define ADC_INTEN_SCNCMP_Pos (1UL) /*!< ADC INTEN: SCNCMP (Bit 1) */ -#define ADC_INTEN_SCNCMP_Msk (0x2UL) /*!< ADC INTEN: SCNCMP (Bitfield-Mask: 0x01) */ -#define ADC_INTEN_CNVCMP_Pos (0UL) /*!< ADC INTEN: CNVCMP (Bit 0) */ -#define ADC_INTEN_CNVCMP_Msk (0x1UL) /*!< ADC INTEN: CNVCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTAT ======================================================== */ -#define ADC_INTSTAT_DERR_Pos (7UL) /*!< ADC INTSTAT: DERR (Bit 7) */ -#define ADC_INTSTAT_DERR_Msk (0x80UL) /*!< ADC INTSTAT: DERR (Bitfield-Mask: 0x01) */ -#define ADC_INTSTAT_DCMP_Pos (6UL) /*!< ADC INTSTAT: DCMP (Bit 6) */ -#define ADC_INTSTAT_DCMP_Msk (0x40UL) /*!< ADC INTSTAT: DCMP (Bitfield-Mask: 0x01) */ -#define ADC_INTSTAT_WCINC_Pos (5UL) /*!< ADC INTSTAT: WCINC (Bit 5) */ -#define ADC_INTSTAT_WCINC_Msk (0x20UL) /*!< ADC INTSTAT: WCINC (Bitfield-Mask: 0x01) */ -#define ADC_INTSTAT_WCEXC_Pos (4UL) /*!< ADC INTSTAT: WCEXC (Bit 4) */ -#define ADC_INTSTAT_WCEXC_Msk (0x10UL) /*!< ADC INTSTAT: WCEXC (Bitfield-Mask: 0x01) */ -#define ADC_INTSTAT_FIFOOVR2_Pos (3UL) /*!< ADC INTSTAT: FIFOOVR2 (Bit 3) */ -#define ADC_INTSTAT_FIFOOVR2_Msk (0x8UL) /*!< ADC INTSTAT: FIFOOVR2 (Bitfield-Mask: 0x01) */ -#define ADC_INTSTAT_FIFOOVR1_Pos (2UL) /*!< ADC INTSTAT: FIFOOVR1 (Bit 2) */ -#define ADC_INTSTAT_FIFOOVR1_Msk (0x4UL) /*!< ADC INTSTAT: FIFOOVR1 (Bitfield-Mask: 0x01) */ -#define ADC_INTSTAT_SCNCMP_Pos (1UL) /*!< ADC INTSTAT: SCNCMP (Bit 1) */ -#define ADC_INTSTAT_SCNCMP_Msk (0x2UL) /*!< ADC INTSTAT: SCNCMP (Bitfield-Mask: 0x01) */ -#define ADC_INTSTAT_CNVCMP_Pos (0UL) /*!< ADC INTSTAT: CNVCMP (Bit 0) */ -#define ADC_INTSTAT_CNVCMP_Msk (0x1UL) /*!< ADC INTSTAT: CNVCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== INTCLR ========================================================= */ -#define ADC_INTCLR_DERR_Pos (7UL) /*!< ADC INTCLR: DERR (Bit 7) */ -#define ADC_INTCLR_DERR_Msk (0x80UL) /*!< ADC INTCLR: DERR (Bitfield-Mask: 0x01) */ -#define ADC_INTCLR_DCMP_Pos (6UL) /*!< ADC INTCLR: DCMP (Bit 6) */ -#define ADC_INTCLR_DCMP_Msk (0x40UL) /*!< ADC INTCLR: DCMP (Bitfield-Mask: 0x01) */ -#define ADC_INTCLR_WCINC_Pos (5UL) /*!< ADC INTCLR: WCINC (Bit 5) */ -#define ADC_INTCLR_WCINC_Msk (0x20UL) /*!< ADC INTCLR: WCINC (Bitfield-Mask: 0x01) */ -#define ADC_INTCLR_WCEXC_Pos (4UL) /*!< ADC INTCLR: WCEXC (Bit 4) */ -#define ADC_INTCLR_WCEXC_Msk (0x10UL) /*!< ADC INTCLR: WCEXC (Bitfield-Mask: 0x01) */ -#define ADC_INTCLR_FIFOOVR2_Pos (3UL) /*!< ADC INTCLR: FIFOOVR2 (Bit 3) */ -#define ADC_INTCLR_FIFOOVR2_Msk (0x8UL) /*!< ADC INTCLR: FIFOOVR2 (Bitfield-Mask: 0x01) */ -#define ADC_INTCLR_FIFOOVR1_Pos (2UL) /*!< ADC INTCLR: FIFOOVR1 (Bit 2) */ -#define ADC_INTCLR_FIFOOVR1_Msk (0x4UL) /*!< ADC INTCLR: FIFOOVR1 (Bitfield-Mask: 0x01) */ -#define ADC_INTCLR_SCNCMP_Pos (1UL) /*!< ADC INTCLR: SCNCMP (Bit 1) */ -#define ADC_INTCLR_SCNCMP_Msk (0x2UL) /*!< ADC INTCLR: SCNCMP (Bitfield-Mask: 0x01) */ -#define ADC_INTCLR_CNVCMP_Pos (0UL) /*!< ADC INTCLR: CNVCMP (Bit 0) */ -#define ADC_INTCLR_CNVCMP_Msk (0x1UL) /*!< ADC INTCLR: CNVCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSET ========================================================= */ -#define ADC_INTSET_DERR_Pos (7UL) /*!< ADC INTSET: DERR (Bit 7) */ -#define ADC_INTSET_DERR_Msk (0x80UL) /*!< ADC INTSET: DERR (Bitfield-Mask: 0x01) */ -#define ADC_INTSET_DCMP_Pos (6UL) /*!< ADC INTSET: DCMP (Bit 6) */ -#define ADC_INTSET_DCMP_Msk (0x40UL) /*!< ADC INTSET: DCMP (Bitfield-Mask: 0x01) */ -#define ADC_INTSET_WCINC_Pos (5UL) /*!< ADC INTSET: WCINC (Bit 5) */ -#define ADC_INTSET_WCINC_Msk (0x20UL) /*!< ADC INTSET: WCINC (Bitfield-Mask: 0x01) */ -#define ADC_INTSET_WCEXC_Pos (4UL) /*!< ADC INTSET: WCEXC (Bit 4) */ -#define ADC_INTSET_WCEXC_Msk (0x10UL) /*!< ADC INTSET: WCEXC (Bitfield-Mask: 0x01) */ -#define ADC_INTSET_FIFOOVR2_Pos (3UL) /*!< ADC INTSET: FIFOOVR2 (Bit 3) */ -#define ADC_INTSET_FIFOOVR2_Msk (0x8UL) /*!< ADC INTSET: FIFOOVR2 (Bitfield-Mask: 0x01) */ -#define ADC_INTSET_FIFOOVR1_Pos (2UL) /*!< ADC INTSET: FIFOOVR1 (Bit 2) */ -#define ADC_INTSET_FIFOOVR1_Msk (0x4UL) /*!< ADC INTSET: FIFOOVR1 (Bitfield-Mask: 0x01) */ -#define ADC_INTSET_SCNCMP_Pos (1UL) /*!< ADC INTSET: SCNCMP (Bit 1) */ -#define ADC_INTSET_SCNCMP_Msk (0x2UL) /*!< ADC INTSET: SCNCMP (Bitfield-Mask: 0x01) */ -#define ADC_INTSET_CNVCMP_Pos (0UL) /*!< ADC INTSET: CNVCMP (Bit 0) */ -#define ADC_INTSET_CNVCMP_Msk (0x1UL) /*!< ADC INTSET: CNVCMP (Bitfield-Mask: 0x01) */ -/* ======================================================= DMATRIGEN ======================================================= */ -#define ADC_DMATRIGEN_DFIFOFULL_Pos (1UL) /*!< ADC DMATRIGEN: DFIFOFULL (Bit 1) */ -#define ADC_DMATRIGEN_DFIFOFULL_Msk (0x2UL) /*!< ADC DMATRIGEN: DFIFOFULL (Bitfield-Mask: 0x01) */ -#define ADC_DMATRIGEN_DFIFO75_Pos (0UL) /*!< ADC DMATRIGEN: DFIFO75 (Bit 0) */ -#define ADC_DMATRIGEN_DFIFO75_Msk (0x1UL) /*!< ADC DMATRIGEN: DFIFO75 (Bitfield-Mask: 0x01) */ -/* ====================================================== DMATRIGSTAT ====================================================== */ -#define ADC_DMATRIGSTAT_DFULLSTAT_Pos (1UL) /*!< ADC DMATRIGSTAT: DFULLSTAT (Bit 1) */ -#define ADC_DMATRIGSTAT_DFULLSTAT_Msk (0x2UL) /*!< ADC DMATRIGSTAT: DFULLSTAT (Bitfield-Mask: 0x01) */ -#define ADC_DMATRIGSTAT_D75STAT_Pos (0UL) /*!< ADC DMATRIGSTAT: D75STAT (Bit 0) */ -#define ADC_DMATRIGSTAT_D75STAT_Msk (0x1UL) /*!< ADC DMATRIGSTAT: D75STAT (Bitfield-Mask: 0x01) */ -/* ======================================================== DMACFG ========================================================= */ -#define ADC_DMACFG_DPWROFF_Pos (18UL) /*!< ADC DMACFG: DPWROFF (Bit 18) */ -#define ADC_DMACFG_DPWROFF_Msk (0x40000UL) /*!< ADC DMACFG: DPWROFF (Bitfield-Mask: 0x01) */ -#define ADC_DMACFG_DMAMSK_Pos (17UL) /*!< ADC DMACFG: DMAMSK (Bit 17) */ -#define ADC_DMACFG_DMAMSK_Msk (0x20000UL) /*!< ADC DMACFG: DMAMSK (Bitfield-Mask: 0x01) */ -#define ADC_DMACFG_DMAHONSTAT_Pos (16UL) /*!< ADC DMACFG: DMAHONSTAT (Bit 16) */ -#define ADC_DMACFG_DMAHONSTAT_Msk (0x10000UL) /*!< ADC DMACFG: DMAHONSTAT (Bitfield-Mask: 0x01) */ -#define ADC_DMACFG_DMADYNPRI_Pos (9UL) /*!< ADC DMACFG: DMADYNPRI (Bit 9) */ -#define ADC_DMACFG_DMADYNPRI_Msk (0x200UL) /*!< ADC DMACFG: DMADYNPRI (Bitfield-Mask: 0x01) */ -#define ADC_DMACFG_DMAPRI_Pos (8UL) /*!< ADC DMACFG: DMAPRI (Bit 8) */ -#define ADC_DMACFG_DMAPRI_Msk (0x100UL) /*!< ADC DMACFG: DMAPRI (Bitfield-Mask: 0x01) */ -#define ADC_DMACFG_DMADIR_Pos (2UL) /*!< ADC DMACFG: DMADIR (Bit 2) */ -#define ADC_DMACFG_DMADIR_Msk (0x4UL) /*!< ADC DMACFG: DMADIR (Bitfield-Mask: 0x01) */ -#define ADC_DMACFG_DMAEN_Pos (0UL) /*!< ADC DMACFG: DMAEN (Bit 0) */ -#define ADC_DMACFG_DMAEN_Msk (0x1UL) /*!< ADC DMACFG: DMAEN (Bitfield-Mask: 0x01) */ -/* ====================================================== DMATOTCOUNT ====================================================== */ -#define ADC_DMATOTCOUNT_TOTCOUNT_Pos (2UL) /*!< ADC DMATOTCOUNT: TOTCOUNT (Bit 2) */ -#define ADC_DMATOTCOUNT_TOTCOUNT_Msk (0x3fffcUL) /*!< ADC DMATOTCOUNT: TOTCOUNT (Bitfield-Mask: 0xffff) */ -/* ====================================================== DMATARGADDR ====================================================== */ -#define ADC_DMATARGADDR_UTARGADDR_Pos (20UL) /*!< ADC DMATARGADDR: UTARGADDR (Bit 20) */ -#define ADC_DMATARGADDR_UTARGADDR_Msk (0xfff00000UL) /*!< ADC DMATARGADDR: UTARGADDR (Bitfield-Mask: 0xfff) */ -#define ADC_DMATARGADDR_LTARGADDR_Pos (0UL) /*!< ADC DMATARGADDR: LTARGADDR (Bit 0) */ -#define ADC_DMATARGADDR_LTARGADDR_Msk (0xfffffUL) /*!< ADC DMATARGADDR: LTARGADDR (Bitfield-Mask: 0xfffff) */ -/* ======================================================== DMASTAT ======================================================== */ -#define ADC_DMASTAT_DMAERR_Pos (2UL) /*!< ADC DMASTAT: DMAERR (Bit 2) */ -#define ADC_DMASTAT_DMAERR_Msk (0x4UL) /*!< ADC DMASTAT: DMAERR (Bitfield-Mask: 0x01) */ -#define ADC_DMASTAT_DMACPL_Pos (1UL) /*!< ADC DMASTAT: DMACPL (Bit 1) */ -#define ADC_DMASTAT_DMACPL_Msk (0x2UL) /*!< ADC DMASTAT: DMACPL (Bitfield-Mask: 0x01) */ -#define ADC_DMASTAT_DMATIP_Pos (0UL) /*!< ADC DMASTAT: DMATIP (Bit 0) */ -#define ADC_DMASTAT_DMATIP_Msk (0x1UL) /*!< ADC DMASTAT: DMATIP (Bitfield-Mask: 0x01) */ - - -/* =========================================================================================================================== */ -/* ================ APBDMA ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== BBVALUE ======================================================== */ -#define APBDMA_BBVALUE_PIN_Pos (16UL) /*!< APBDMA BBVALUE: PIN (Bit 16) */ -#define APBDMA_BBVALUE_PIN_Msk (0xff0000UL) /*!< APBDMA BBVALUE: PIN (Bitfield-Mask: 0xff) */ -#define APBDMA_BBVALUE_DATAOUT_Pos (0UL) /*!< APBDMA BBVALUE: DATAOUT (Bit 0) */ -#define APBDMA_BBVALUE_DATAOUT_Msk (0xffUL) /*!< APBDMA BBVALUE: DATAOUT (Bitfield-Mask: 0xff) */ -/* ====================================================== BBSETCLEAR ======================================================= */ -#define APBDMA_BBSETCLEAR_CLEAR_Pos (16UL) /*!< APBDMA BBSETCLEAR: CLEAR (Bit 16) */ -#define APBDMA_BBSETCLEAR_CLEAR_Msk (0xff0000UL) /*!< APBDMA BBSETCLEAR: CLEAR (Bitfield-Mask: 0xff) */ -#define APBDMA_BBSETCLEAR_SET_Pos (0UL) /*!< APBDMA BBSETCLEAR: SET (Bit 0) */ -#define APBDMA_BBSETCLEAR_SET_Msk (0xffUL) /*!< APBDMA BBSETCLEAR: SET (Bitfield-Mask: 0xff) */ -/* ======================================================== BBINPUT ======================================================== */ -#define APBDMA_BBINPUT_DATAIN_Pos (0UL) /*!< APBDMA BBINPUT: DATAIN (Bit 0) */ -#define APBDMA_BBINPUT_DATAIN_Msk (0xffUL) /*!< APBDMA BBINPUT: DATAIN (Bitfield-Mask: 0xff) */ -/* ======================================================= DEBUGDATA ======================================================= */ -#define APBDMA_DEBUGDATA_DEBUGDATA_Pos (0UL) /*!< APBDMA DEBUGDATA: DEBUGDATA (Bit 0) */ -#define APBDMA_DEBUGDATA_DEBUGDATA_Msk (0xffffffffUL) /*!< APBDMA DEBUGDATA: DEBUGDATA (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DEBUG ========================================================= */ -#define APBDMA_DEBUG_DEBUGEN_Pos (0UL) /*!< APBDMA DEBUG: DEBUGEN (Bit 0) */ -#define APBDMA_DEBUG_DEBUGEN_Msk (0xfUL) /*!< APBDMA DEBUG: DEBUGEN (Bitfield-Mask: 0x0f) */ - - -/* =========================================================================================================================== */ -/* ================ BLEIF ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= FIFO ========================================================== */ -#define BLEIF_FIFO_FIFO_Pos (0UL) /*!< BLEIF FIFO: FIFO (Bit 0) */ -#define BLEIF_FIFO_FIFO_Msk (0xffffffffUL) /*!< BLEIF FIFO: FIFO (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== FIFOPTR ======================================================== */ -#define BLEIF_FIFOPTR_FIFO1REM_Pos (24UL) /*!< BLEIF FIFOPTR: FIFO1REM (Bit 24) */ -#define BLEIF_FIFOPTR_FIFO1REM_Msk (0xff000000UL) /*!< BLEIF FIFOPTR: FIFO1REM (Bitfield-Mask: 0xff) */ -#define BLEIF_FIFOPTR_FIFO1SIZ_Pos (16UL) /*!< BLEIF FIFOPTR: FIFO1SIZ (Bit 16) */ -#define BLEIF_FIFOPTR_FIFO1SIZ_Msk (0xff0000UL) /*!< BLEIF FIFOPTR: FIFO1SIZ (Bitfield-Mask: 0xff) */ -#define BLEIF_FIFOPTR_FIFO0REM_Pos (8UL) /*!< BLEIF FIFOPTR: FIFO0REM (Bit 8) */ -#define BLEIF_FIFOPTR_FIFO0REM_Msk (0xff00UL) /*!< BLEIF FIFOPTR: FIFO0REM (Bitfield-Mask: 0xff) */ -#define BLEIF_FIFOPTR_FIFO0SIZ_Pos (0UL) /*!< BLEIF FIFOPTR: FIFO0SIZ (Bit 0) */ -#define BLEIF_FIFOPTR_FIFO0SIZ_Msk (0xffUL) /*!< BLEIF FIFOPTR: FIFO0SIZ (Bitfield-Mask: 0xff) */ -/* ======================================================== FIFOTHR ======================================================== */ -#define BLEIF_FIFOTHR_FIFOWTHR_Pos (8UL) /*!< BLEIF FIFOTHR: FIFOWTHR (Bit 8) */ -#define BLEIF_FIFOTHR_FIFOWTHR_Msk (0x3f00UL) /*!< BLEIF FIFOTHR: FIFOWTHR (Bitfield-Mask: 0x3f) */ -#define BLEIF_FIFOTHR_FIFORTHR_Pos (0UL) /*!< BLEIF FIFOTHR: FIFORTHR (Bit 0) */ -#define BLEIF_FIFOTHR_FIFORTHR_Msk (0x3fUL) /*!< BLEIF FIFOTHR: FIFORTHR (Bitfield-Mask: 0x3f) */ -/* ======================================================== FIFOPOP ======================================================== */ -#define BLEIF_FIFOPOP_FIFODOUT_Pos (0UL) /*!< BLEIF FIFOPOP: FIFODOUT (Bit 0) */ -#define BLEIF_FIFOPOP_FIFODOUT_Msk (0xffffffffUL) /*!< BLEIF FIFOPOP: FIFODOUT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= FIFOPUSH ======================================================== */ -#define BLEIF_FIFOPUSH_FIFODIN_Pos (0UL) /*!< BLEIF FIFOPUSH: FIFODIN (Bit 0) */ -#define BLEIF_FIFOPUSH_FIFODIN_Msk (0xffffffffUL) /*!< BLEIF FIFOPUSH: FIFODIN (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= FIFOCTRL ======================================================== */ -#define BLEIF_FIFOCTRL_FIFORSTN_Pos (1UL) /*!< BLEIF FIFOCTRL: FIFORSTN (Bit 1) */ -#define BLEIF_FIFOCTRL_FIFORSTN_Msk (0x2UL) /*!< BLEIF FIFOCTRL: FIFORSTN (Bitfield-Mask: 0x01) */ -#define BLEIF_FIFOCTRL_POPWR_Pos (0UL) /*!< BLEIF FIFOCTRL: POPWR (Bit 0) */ -#define BLEIF_FIFOCTRL_POPWR_Msk (0x1UL) /*!< BLEIF FIFOCTRL: POPWR (Bitfield-Mask: 0x01) */ -/* ======================================================== FIFOLOC ======================================================== */ -#define BLEIF_FIFOLOC_FIFORPTR_Pos (8UL) /*!< BLEIF FIFOLOC: FIFORPTR (Bit 8) */ -#define BLEIF_FIFOLOC_FIFORPTR_Msk (0xf00UL) /*!< BLEIF FIFOLOC: FIFORPTR (Bitfield-Mask: 0x0f) */ -#define BLEIF_FIFOLOC_FIFOWPTR_Pos (0UL) /*!< BLEIF FIFOLOC: FIFOWPTR (Bit 0) */ -#define BLEIF_FIFOLOC_FIFOWPTR_Msk (0xfUL) /*!< BLEIF FIFOLOC: FIFOWPTR (Bitfield-Mask: 0x0f) */ -/* ======================================================== CLKCFG ========================================================= */ -#define BLEIF_CLKCFG_DIV3_Pos (12UL) /*!< BLEIF CLKCFG: DIV3 (Bit 12) */ -#define BLEIF_CLKCFG_DIV3_Msk (0x1000UL) /*!< BLEIF CLKCFG: DIV3 (Bitfield-Mask: 0x01) */ -#define BLEIF_CLKCFG_CLK32KEN_Pos (11UL) /*!< BLEIF CLKCFG: CLK32KEN (Bit 11) */ -#define BLEIF_CLKCFG_CLK32KEN_Msk (0x800UL) /*!< BLEIF CLKCFG: CLK32KEN (Bitfield-Mask: 0x01) */ -#define BLEIF_CLKCFG_FSEL_Pos (8UL) /*!< BLEIF CLKCFG: FSEL (Bit 8) */ -#define BLEIF_CLKCFG_FSEL_Msk (0x700UL) /*!< BLEIF CLKCFG: FSEL (Bitfield-Mask: 0x07) */ -#define BLEIF_CLKCFG_IOCLKEN_Pos (0UL) /*!< BLEIF CLKCFG: IOCLKEN (Bit 0) */ -#define BLEIF_CLKCFG_IOCLKEN_Msk (0x1UL) /*!< BLEIF CLKCFG: IOCLKEN (Bitfield-Mask: 0x01) */ -/* ========================================================== CMD ========================================================== */ -#define BLEIF_CMD_OFFSETLO_Pos (24UL) /*!< BLEIF CMD: OFFSETLO (Bit 24) */ -#define BLEIF_CMD_OFFSETLO_Msk (0xff000000UL) /*!< BLEIF CMD: OFFSETLO (Bitfield-Mask: 0xff) */ -#define BLEIF_CMD_CMDSEL_Pos (20UL) /*!< BLEIF CMD: CMDSEL (Bit 20) */ -#define BLEIF_CMD_CMDSEL_Msk (0x300000UL) /*!< BLEIF CMD: CMDSEL (Bitfield-Mask: 0x03) */ -#define BLEIF_CMD_TSIZE_Pos (8UL) /*!< BLEIF CMD: TSIZE (Bit 8) */ -#define BLEIF_CMD_TSIZE_Msk (0xfff00UL) /*!< BLEIF CMD: TSIZE (Bitfield-Mask: 0xfff) */ -#define BLEIF_CMD_CONT_Pos (7UL) /*!< BLEIF CMD: CONT (Bit 7) */ -#define BLEIF_CMD_CONT_Msk (0x80UL) /*!< BLEIF CMD: CONT (Bitfield-Mask: 0x01) */ -#define BLEIF_CMD_OFFSETCNT_Pos (5UL) /*!< BLEIF CMD: OFFSETCNT (Bit 5) */ -#define BLEIF_CMD_OFFSETCNT_Msk (0x60UL) /*!< BLEIF CMD: OFFSETCNT (Bitfield-Mask: 0x03) */ -#define BLEIF_CMD_CMD_Pos (0UL) /*!< BLEIF CMD: CMD (Bit 0) */ -#define BLEIF_CMD_CMD_Msk (0x1fUL) /*!< BLEIF CMD: CMD (Bitfield-Mask: 0x1f) */ -/* ======================================================== CMDRPT ========================================================= */ -#define BLEIF_CMDRPT_CMDRPT_Pos (0UL) /*!< BLEIF CMDRPT: CMDRPT (Bit 0) */ -#define BLEIF_CMDRPT_CMDRPT_Msk (0x1fUL) /*!< BLEIF CMDRPT: CMDRPT (Bitfield-Mask: 0x1f) */ -/* ======================================================= OFFSETHI ======================================================== */ -#define BLEIF_OFFSETHI_OFFSETHI_Pos (0UL) /*!< BLEIF OFFSETHI: OFFSETHI (Bit 0) */ -#define BLEIF_OFFSETHI_OFFSETHI_Msk (0xffffUL) /*!< BLEIF OFFSETHI: OFFSETHI (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMDSTAT ======================================================== */ -#define BLEIF_CMDSTAT_CTSIZE_Pos (8UL) /*!< BLEIF CMDSTAT: CTSIZE (Bit 8) */ -#define BLEIF_CMDSTAT_CTSIZE_Msk (0xfff00UL) /*!< BLEIF CMDSTAT: CTSIZE (Bitfield-Mask: 0xfff) */ -#define BLEIF_CMDSTAT_CMDSTAT_Pos (5UL) /*!< BLEIF CMDSTAT: CMDSTAT (Bit 5) */ -#define BLEIF_CMDSTAT_CMDSTAT_Msk (0xe0UL) /*!< BLEIF CMDSTAT: CMDSTAT (Bitfield-Mask: 0x07) */ -#define BLEIF_CMDSTAT_CCMD_Pos (0UL) /*!< BLEIF CMDSTAT: CCMD (Bit 0) */ -#define BLEIF_CMDSTAT_CCMD_Msk (0x1fUL) /*!< BLEIF CMDSTAT: CCMD (Bitfield-Mask: 0x1f) */ -/* ========================================================= INTEN ========================================================= */ -#define BLEIF_INTEN_B2MSHUTDN_Pos (16UL) /*!< BLEIF INTEN: B2MSHUTDN (Bit 16) */ -#define BLEIF_INTEN_B2MSHUTDN_Msk (0x10000UL) /*!< BLEIF INTEN: B2MSHUTDN (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_B2MACTIVE_Pos (15UL) /*!< BLEIF INTEN: B2MACTIVE (Bit 15) */ -#define BLEIF_INTEN_B2MACTIVE_Msk (0x8000UL) /*!< BLEIF INTEN: B2MACTIVE (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_B2MSLEEP_Pos (14UL) /*!< BLEIF INTEN: B2MSLEEP (Bit 14) */ -#define BLEIF_INTEN_B2MSLEEP_Msk (0x4000UL) /*!< BLEIF INTEN: B2MSLEEP (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_CQERR_Pos (13UL) /*!< BLEIF INTEN: CQERR (Bit 13) */ -#define BLEIF_INTEN_CQERR_Msk (0x2000UL) /*!< BLEIF INTEN: CQERR (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_CQUPD_Pos (12UL) /*!< BLEIF INTEN: CQUPD (Bit 12) */ -#define BLEIF_INTEN_CQUPD_Msk (0x1000UL) /*!< BLEIF INTEN: CQUPD (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_CQPAUSED_Pos (11UL) /*!< BLEIF INTEN: CQPAUSED (Bit 11) */ -#define BLEIF_INTEN_CQPAUSED_Msk (0x800UL) /*!< BLEIF INTEN: CQPAUSED (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_DERR_Pos (10UL) /*!< BLEIF INTEN: DERR (Bit 10) */ -#define BLEIF_INTEN_DERR_Msk (0x400UL) /*!< BLEIF INTEN: DERR (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_DCMP_Pos (9UL) /*!< BLEIF INTEN: DCMP (Bit 9) */ -#define BLEIF_INTEN_DCMP_Msk (0x200UL) /*!< BLEIF INTEN: DCMP (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_BLECSSTAT_Pos (8UL) /*!< BLEIF INTEN: BLECSSTAT (Bit 8) */ -#define BLEIF_INTEN_BLECSSTAT_Msk (0x100UL) /*!< BLEIF INTEN: BLECSSTAT (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_BLECIRQ_Pos (7UL) /*!< BLEIF INTEN: BLECIRQ (Bit 7) */ -#define BLEIF_INTEN_BLECIRQ_Msk (0x80UL) /*!< BLEIF INTEN: BLECIRQ (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_ICMD_Pos (6UL) /*!< BLEIF INTEN: ICMD (Bit 6) */ -#define BLEIF_INTEN_ICMD_Msk (0x40UL) /*!< BLEIF INTEN: ICMD (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_IACC_Pos (5UL) /*!< BLEIF INTEN: IACC (Bit 5) */ -#define BLEIF_INTEN_IACC_Msk (0x20UL) /*!< BLEIF INTEN: IACC (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_B2MST_Pos (4UL) /*!< BLEIF INTEN: B2MST (Bit 4) */ -#define BLEIF_INTEN_B2MST_Msk (0x10UL) /*!< BLEIF INTEN: B2MST (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_FOVFL_Pos (3UL) /*!< BLEIF INTEN: FOVFL (Bit 3) */ -#define BLEIF_INTEN_FOVFL_Msk (0x8UL) /*!< BLEIF INTEN: FOVFL (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_FUNDFL_Pos (2UL) /*!< BLEIF INTEN: FUNDFL (Bit 2) */ -#define BLEIF_INTEN_FUNDFL_Msk (0x4UL) /*!< BLEIF INTEN: FUNDFL (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_THR_Pos (1UL) /*!< BLEIF INTEN: THR (Bit 1) */ -#define BLEIF_INTEN_THR_Msk (0x2UL) /*!< BLEIF INTEN: THR (Bitfield-Mask: 0x01) */ -#define BLEIF_INTEN_CMDCMP_Pos (0UL) /*!< BLEIF INTEN: CMDCMP (Bit 0) */ -#define BLEIF_INTEN_CMDCMP_Msk (0x1UL) /*!< BLEIF INTEN: CMDCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTAT ======================================================== */ -#define BLEIF_INTSTAT_B2MSHUTDN_Pos (16UL) /*!< BLEIF INTSTAT: B2MSHUTDN (Bit 16) */ -#define BLEIF_INTSTAT_B2MSHUTDN_Msk (0x10000UL) /*!< BLEIF INTSTAT: B2MSHUTDN (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_B2MACTIVE_Pos (15UL) /*!< BLEIF INTSTAT: B2MACTIVE (Bit 15) */ -#define BLEIF_INTSTAT_B2MACTIVE_Msk (0x8000UL) /*!< BLEIF INTSTAT: B2MACTIVE (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_B2MSLEEP_Pos (14UL) /*!< BLEIF INTSTAT: B2MSLEEP (Bit 14) */ -#define BLEIF_INTSTAT_B2MSLEEP_Msk (0x4000UL) /*!< BLEIF INTSTAT: B2MSLEEP (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_CQERR_Pos (13UL) /*!< BLEIF INTSTAT: CQERR (Bit 13) */ -#define BLEIF_INTSTAT_CQERR_Msk (0x2000UL) /*!< BLEIF INTSTAT: CQERR (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_CQUPD_Pos (12UL) /*!< BLEIF INTSTAT: CQUPD (Bit 12) */ -#define BLEIF_INTSTAT_CQUPD_Msk (0x1000UL) /*!< BLEIF INTSTAT: CQUPD (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_CQPAUSED_Pos (11UL) /*!< BLEIF INTSTAT: CQPAUSED (Bit 11) */ -#define BLEIF_INTSTAT_CQPAUSED_Msk (0x800UL) /*!< BLEIF INTSTAT: CQPAUSED (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_DERR_Pos (10UL) /*!< BLEIF INTSTAT: DERR (Bit 10) */ -#define BLEIF_INTSTAT_DERR_Msk (0x400UL) /*!< BLEIF INTSTAT: DERR (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_DCMP_Pos (9UL) /*!< BLEIF INTSTAT: DCMP (Bit 9) */ -#define BLEIF_INTSTAT_DCMP_Msk (0x200UL) /*!< BLEIF INTSTAT: DCMP (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_BLECSSTAT_Pos (8UL) /*!< BLEIF INTSTAT: BLECSSTAT (Bit 8) */ -#define BLEIF_INTSTAT_BLECSSTAT_Msk (0x100UL) /*!< BLEIF INTSTAT: BLECSSTAT (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_BLECIRQ_Pos (7UL) /*!< BLEIF INTSTAT: BLECIRQ (Bit 7) */ -#define BLEIF_INTSTAT_BLECIRQ_Msk (0x80UL) /*!< BLEIF INTSTAT: BLECIRQ (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_ICMD_Pos (6UL) /*!< BLEIF INTSTAT: ICMD (Bit 6) */ -#define BLEIF_INTSTAT_ICMD_Msk (0x40UL) /*!< BLEIF INTSTAT: ICMD (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_IACC_Pos (5UL) /*!< BLEIF INTSTAT: IACC (Bit 5) */ -#define BLEIF_INTSTAT_IACC_Msk (0x20UL) /*!< BLEIF INTSTAT: IACC (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_B2MST_Pos (4UL) /*!< BLEIF INTSTAT: B2MST (Bit 4) */ -#define BLEIF_INTSTAT_B2MST_Msk (0x10UL) /*!< BLEIF INTSTAT: B2MST (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_FOVFL_Pos (3UL) /*!< BLEIF INTSTAT: FOVFL (Bit 3) */ -#define BLEIF_INTSTAT_FOVFL_Msk (0x8UL) /*!< BLEIF INTSTAT: FOVFL (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_FUNDFL_Pos (2UL) /*!< BLEIF INTSTAT: FUNDFL (Bit 2) */ -#define BLEIF_INTSTAT_FUNDFL_Msk (0x4UL) /*!< BLEIF INTSTAT: FUNDFL (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_THR_Pos (1UL) /*!< BLEIF INTSTAT: THR (Bit 1) */ -#define BLEIF_INTSTAT_THR_Msk (0x2UL) /*!< BLEIF INTSTAT: THR (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSTAT_CMDCMP_Pos (0UL) /*!< BLEIF INTSTAT: CMDCMP (Bit 0) */ -#define BLEIF_INTSTAT_CMDCMP_Msk (0x1UL) /*!< BLEIF INTSTAT: CMDCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== INTCLR ========================================================= */ -#define BLEIF_INTCLR_B2MSHUTDN_Pos (16UL) /*!< BLEIF INTCLR: B2MSHUTDN (Bit 16) */ -#define BLEIF_INTCLR_B2MSHUTDN_Msk (0x10000UL) /*!< BLEIF INTCLR: B2MSHUTDN (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_B2MACTIVE_Pos (15UL) /*!< BLEIF INTCLR: B2MACTIVE (Bit 15) */ -#define BLEIF_INTCLR_B2MACTIVE_Msk (0x8000UL) /*!< BLEIF INTCLR: B2MACTIVE (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_B2MSLEEP_Pos (14UL) /*!< BLEIF INTCLR: B2MSLEEP (Bit 14) */ -#define BLEIF_INTCLR_B2MSLEEP_Msk (0x4000UL) /*!< BLEIF INTCLR: B2MSLEEP (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_CQERR_Pos (13UL) /*!< BLEIF INTCLR: CQERR (Bit 13) */ -#define BLEIF_INTCLR_CQERR_Msk (0x2000UL) /*!< BLEIF INTCLR: CQERR (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_CQUPD_Pos (12UL) /*!< BLEIF INTCLR: CQUPD (Bit 12) */ -#define BLEIF_INTCLR_CQUPD_Msk (0x1000UL) /*!< BLEIF INTCLR: CQUPD (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_CQPAUSED_Pos (11UL) /*!< BLEIF INTCLR: CQPAUSED (Bit 11) */ -#define BLEIF_INTCLR_CQPAUSED_Msk (0x800UL) /*!< BLEIF INTCLR: CQPAUSED (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_DERR_Pos (10UL) /*!< BLEIF INTCLR: DERR (Bit 10) */ -#define BLEIF_INTCLR_DERR_Msk (0x400UL) /*!< BLEIF INTCLR: DERR (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_DCMP_Pos (9UL) /*!< BLEIF INTCLR: DCMP (Bit 9) */ -#define BLEIF_INTCLR_DCMP_Msk (0x200UL) /*!< BLEIF INTCLR: DCMP (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_BLECSSTAT_Pos (8UL) /*!< BLEIF INTCLR: BLECSSTAT (Bit 8) */ -#define BLEIF_INTCLR_BLECSSTAT_Msk (0x100UL) /*!< BLEIF INTCLR: BLECSSTAT (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_BLECIRQ_Pos (7UL) /*!< BLEIF INTCLR: BLECIRQ (Bit 7) */ -#define BLEIF_INTCLR_BLECIRQ_Msk (0x80UL) /*!< BLEIF INTCLR: BLECIRQ (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_ICMD_Pos (6UL) /*!< BLEIF INTCLR: ICMD (Bit 6) */ -#define BLEIF_INTCLR_ICMD_Msk (0x40UL) /*!< BLEIF INTCLR: ICMD (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_IACC_Pos (5UL) /*!< BLEIF INTCLR: IACC (Bit 5) */ -#define BLEIF_INTCLR_IACC_Msk (0x20UL) /*!< BLEIF INTCLR: IACC (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_B2MST_Pos (4UL) /*!< BLEIF INTCLR: B2MST (Bit 4) */ -#define BLEIF_INTCLR_B2MST_Msk (0x10UL) /*!< BLEIF INTCLR: B2MST (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_FOVFL_Pos (3UL) /*!< BLEIF INTCLR: FOVFL (Bit 3) */ -#define BLEIF_INTCLR_FOVFL_Msk (0x8UL) /*!< BLEIF INTCLR: FOVFL (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_FUNDFL_Pos (2UL) /*!< BLEIF INTCLR: FUNDFL (Bit 2) */ -#define BLEIF_INTCLR_FUNDFL_Msk (0x4UL) /*!< BLEIF INTCLR: FUNDFL (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_THR_Pos (1UL) /*!< BLEIF INTCLR: THR (Bit 1) */ -#define BLEIF_INTCLR_THR_Msk (0x2UL) /*!< BLEIF INTCLR: THR (Bitfield-Mask: 0x01) */ -#define BLEIF_INTCLR_CMDCMP_Pos (0UL) /*!< BLEIF INTCLR: CMDCMP (Bit 0) */ -#define BLEIF_INTCLR_CMDCMP_Msk (0x1UL) /*!< BLEIF INTCLR: CMDCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSET ========================================================= */ -#define BLEIF_INTSET_B2MSHUTDN_Pos (16UL) /*!< BLEIF INTSET: B2MSHUTDN (Bit 16) */ -#define BLEIF_INTSET_B2MSHUTDN_Msk (0x10000UL) /*!< BLEIF INTSET: B2MSHUTDN (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_B2MACTIVE_Pos (15UL) /*!< BLEIF INTSET: B2MACTIVE (Bit 15) */ -#define BLEIF_INTSET_B2MACTIVE_Msk (0x8000UL) /*!< BLEIF INTSET: B2MACTIVE (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_B2MSLEEP_Pos (14UL) /*!< BLEIF INTSET: B2MSLEEP (Bit 14) */ -#define BLEIF_INTSET_B2MSLEEP_Msk (0x4000UL) /*!< BLEIF INTSET: B2MSLEEP (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_CQERR_Pos (13UL) /*!< BLEIF INTSET: CQERR (Bit 13) */ -#define BLEIF_INTSET_CQERR_Msk (0x2000UL) /*!< BLEIF INTSET: CQERR (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_CQUPD_Pos (12UL) /*!< BLEIF INTSET: CQUPD (Bit 12) */ -#define BLEIF_INTSET_CQUPD_Msk (0x1000UL) /*!< BLEIF INTSET: CQUPD (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_CQPAUSED_Pos (11UL) /*!< BLEIF INTSET: CQPAUSED (Bit 11) */ -#define BLEIF_INTSET_CQPAUSED_Msk (0x800UL) /*!< BLEIF INTSET: CQPAUSED (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_DERR_Pos (10UL) /*!< BLEIF INTSET: DERR (Bit 10) */ -#define BLEIF_INTSET_DERR_Msk (0x400UL) /*!< BLEIF INTSET: DERR (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_DCMP_Pos (9UL) /*!< BLEIF INTSET: DCMP (Bit 9) */ -#define BLEIF_INTSET_DCMP_Msk (0x200UL) /*!< BLEIF INTSET: DCMP (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_BLECSSTAT_Pos (8UL) /*!< BLEIF INTSET: BLECSSTAT (Bit 8) */ -#define BLEIF_INTSET_BLECSSTAT_Msk (0x100UL) /*!< BLEIF INTSET: BLECSSTAT (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_BLECIRQ_Pos (7UL) /*!< BLEIF INTSET: BLECIRQ (Bit 7) */ -#define BLEIF_INTSET_BLECIRQ_Msk (0x80UL) /*!< BLEIF INTSET: BLECIRQ (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_ICMD_Pos (6UL) /*!< BLEIF INTSET: ICMD (Bit 6) */ -#define BLEIF_INTSET_ICMD_Msk (0x40UL) /*!< BLEIF INTSET: ICMD (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_IACC_Pos (5UL) /*!< BLEIF INTSET: IACC (Bit 5) */ -#define BLEIF_INTSET_IACC_Msk (0x20UL) /*!< BLEIF INTSET: IACC (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_B2MST_Pos (4UL) /*!< BLEIF INTSET: B2MST (Bit 4) */ -#define BLEIF_INTSET_B2MST_Msk (0x10UL) /*!< BLEIF INTSET: B2MST (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_FOVFL_Pos (3UL) /*!< BLEIF INTSET: FOVFL (Bit 3) */ -#define BLEIF_INTSET_FOVFL_Msk (0x8UL) /*!< BLEIF INTSET: FOVFL (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_FUNDFL_Pos (2UL) /*!< BLEIF INTSET: FUNDFL (Bit 2) */ -#define BLEIF_INTSET_FUNDFL_Msk (0x4UL) /*!< BLEIF INTSET: FUNDFL (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_THR_Pos (1UL) /*!< BLEIF INTSET: THR (Bit 1) */ -#define BLEIF_INTSET_THR_Msk (0x2UL) /*!< BLEIF INTSET: THR (Bitfield-Mask: 0x01) */ -#define BLEIF_INTSET_CMDCMP_Pos (0UL) /*!< BLEIF INTSET: CMDCMP (Bit 0) */ -#define BLEIF_INTSET_CMDCMP_Msk (0x1UL) /*!< BLEIF INTSET: CMDCMP (Bitfield-Mask: 0x01) */ -/* ======================================================= DMATRIGEN ======================================================= */ -#define BLEIF_DMATRIGEN_DTHREN_Pos (1UL) /*!< BLEIF DMATRIGEN: DTHREN (Bit 1) */ -#define BLEIF_DMATRIGEN_DTHREN_Msk (0x2UL) /*!< BLEIF DMATRIGEN: DTHREN (Bitfield-Mask: 0x01) */ -#define BLEIF_DMATRIGEN_DCMDCMPEN_Pos (0UL) /*!< BLEIF DMATRIGEN: DCMDCMPEN (Bit 0) */ -#define BLEIF_DMATRIGEN_DCMDCMPEN_Msk (0x1UL) /*!< BLEIF DMATRIGEN: DCMDCMPEN (Bitfield-Mask: 0x01) */ -/* ====================================================== DMATRIGSTAT ====================================================== */ -#define BLEIF_DMATRIGSTAT_DTOTCMP_Pos (2UL) /*!< BLEIF DMATRIGSTAT: DTOTCMP (Bit 2) */ -#define BLEIF_DMATRIGSTAT_DTOTCMP_Msk (0x4UL) /*!< BLEIF DMATRIGSTAT: DTOTCMP (Bitfield-Mask: 0x01) */ -#define BLEIF_DMATRIGSTAT_DTHR_Pos (1UL) /*!< BLEIF DMATRIGSTAT: DTHR (Bit 1) */ -#define BLEIF_DMATRIGSTAT_DTHR_Msk (0x2UL) /*!< BLEIF DMATRIGSTAT: DTHR (Bitfield-Mask: 0x01) */ -#define BLEIF_DMATRIGSTAT_DCMDCMP_Pos (0UL) /*!< BLEIF DMATRIGSTAT: DCMDCMP (Bit 0) */ -#define BLEIF_DMATRIGSTAT_DCMDCMP_Msk (0x1UL) /*!< BLEIF DMATRIGSTAT: DCMDCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== DMACFG ========================================================= */ -#define BLEIF_DMACFG_DMAPRI_Pos (8UL) /*!< BLEIF DMACFG: DMAPRI (Bit 8) */ -#define BLEIF_DMACFG_DMAPRI_Msk (0x100UL) /*!< BLEIF DMACFG: DMAPRI (Bitfield-Mask: 0x01) */ -#define BLEIF_DMACFG_DMADIR_Pos (1UL) /*!< BLEIF DMACFG: DMADIR (Bit 1) */ -#define BLEIF_DMACFG_DMADIR_Msk (0x2UL) /*!< BLEIF DMACFG: DMADIR (Bitfield-Mask: 0x01) */ -#define BLEIF_DMACFG_DMAEN_Pos (0UL) /*!< BLEIF DMACFG: DMAEN (Bit 0) */ -#define BLEIF_DMACFG_DMAEN_Msk (0x1UL) /*!< BLEIF DMACFG: DMAEN (Bitfield-Mask: 0x01) */ -/* ====================================================== DMATOTCOUNT ====================================================== */ -#define BLEIF_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< BLEIF DMATOTCOUNT: TOTCOUNT (Bit 0) */ -#define BLEIF_DMATOTCOUNT_TOTCOUNT_Msk (0xfffUL) /*!< BLEIF DMATOTCOUNT: TOTCOUNT (Bitfield-Mask: 0xfff) */ -/* ====================================================== DMATARGADDR ====================================================== */ -#define BLEIF_DMATARGADDR_TARGADDR28_Pos (28UL) /*!< BLEIF DMATARGADDR: TARGADDR28 (Bit 28) */ -#define BLEIF_DMATARGADDR_TARGADDR28_Msk (0x10000000UL) /*!< BLEIF DMATARGADDR: TARGADDR28 (Bitfield-Mask: 0x01) */ -#define BLEIF_DMATARGADDR_TARGADDR_Pos (0UL) /*!< BLEIF DMATARGADDR: TARGADDR (Bit 0) */ -#define BLEIF_DMATARGADDR_TARGADDR_Msk (0x1fffffUL) /*!< BLEIF DMATARGADDR: TARGADDR (Bitfield-Mask: 0x1fffff) */ -/* ======================================================== DMASTAT ======================================================== */ -#define BLEIF_DMASTAT_DMAERR_Pos (2UL) /*!< BLEIF DMASTAT: DMAERR (Bit 2) */ -#define BLEIF_DMASTAT_DMAERR_Msk (0x4UL) /*!< BLEIF DMASTAT: DMAERR (Bitfield-Mask: 0x01) */ -#define BLEIF_DMASTAT_DMACPL_Pos (1UL) /*!< BLEIF DMASTAT: DMACPL (Bit 1) */ -#define BLEIF_DMASTAT_DMACPL_Msk (0x2UL) /*!< BLEIF DMASTAT: DMACPL (Bitfield-Mask: 0x01) */ -#define BLEIF_DMASTAT_DMATIP_Pos (0UL) /*!< BLEIF DMASTAT: DMATIP (Bit 0) */ -#define BLEIF_DMASTAT_DMATIP_Msk (0x1UL) /*!< BLEIF DMASTAT: DMATIP (Bitfield-Mask: 0x01) */ -/* ========================================================= CQCFG ========================================================= */ -#define BLEIF_CQCFG_CQPRI_Pos (1UL) /*!< BLEIF CQCFG: CQPRI (Bit 1) */ -#define BLEIF_CQCFG_CQPRI_Msk (0x2UL) /*!< BLEIF CQCFG: CQPRI (Bitfield-Mask: 0x01) */ -#define BLEIF_CQCFG_CQEN_Pos (0UL) /*!< BLEIF CQCFG: CQEN (Bit 0) */ -#define BLEIF_CQCFG_CQEN_Msk (0x1UL) /*!< BLEIF CQCFG: CQEN (Bitfield-Mask: 0x01) */ -/* ======================================================== CQADDR ========================================================= */ -#define BLEIF_CQADDR_CQADDR28_Pos (28UL) /*!< BLEIF CQADDR: CQADDR28 (Bit 28) */ -#define BLEIF_CQADDR_CQADDR28_Msk (0x10000000UL) /*!< BLEIF CQADDR: CQADDR28 (Bitfield-Mask: 0x01) */ -#define BLEIF_CQADDR_CQADDR_Pos (2UL) /*!< BLEIF CQADDR: CQADDR (Bit 2) */ -#define BLEIF_CQADDR_CQADDR_Msk (0x1ffffcUL) /*!< BLEIF CQADDR: CQADDR (Bitfield-Mask: 0x7ffff) */ -/* ======================================================== CQSTAT ========================================================= */ -#define BLEIF_CQSTAT_CQERR_Pos (2UL) /*!< BLEIF CQSTAT: CQERR (Bit 2) */ -#define BLEIF_CQSTAT_CQERR_Msk (0x4UL) /*!< BLEIF CQSTAT: CQERR (Bitfield-Mask: 0x01) */ -#define BLEIF_CQSTAT_CQPAUSED_Pos (1UL) /*!< BLEIF CQSTAT: CQPAUSED (Bit 1) */ -#define BLEIF_CQSTAT_CQPAUSED_Msk (0x2UL) /*!< BLEIF CQSTAT: CQPAUSED (Bitfield-Mask: 0x01) */ -#define BLEIF_CQSTAT_CQTIP_Pos (0UL) /*!< BLEIF CQSTAT: CQTIP (Bit 0) */ -#define BLEIF_CQSTAT_CQTIP_Msk (0x1UL) /*!< BLEIF CQSTAT: CQTIP (Bitfield-Mask: 0x01) */ -/* ======================================================== CQFLAGS ======================================================== */ -#define BLEIF_CQFLAGS_CQIRQMASK_Pos (16UL) /*!< BLEIF CQFLAGS: CQIRQMASK (Bit 16) */ -#define BLEIF_CQFLAGS_CQIRQMASK_Msk (0xffff0000UL) /*!< BLEIF CQFLAGS: CQIRQMASK (Bitfield-Mask: 0xffff) */ -#define BLEIF_CQFLAGS_CQFLAGS_Pos (0UL) /*!< BLEIF CQFLAGS: CQFLAGS (Bit 0) */ -#define BLEIF_CQFLAGS_CQFLAGS_Msk (0xffffUL) /*!< BLEIF CQFLAGS: CQFLAGS (Bitfield-Mask: 0xffff) */ -/* ====================================================== CQSETCLEAR ======================================================= */ -#define BLEIF_CQSETCLEAR_CQFCLR_Pos (16UL) /*!< BLEIF CQSETCLEAR: CQFCLR (Bit 16) */ -#define BLEIF_CQSETCLEAR_CQFCLR_Msk (0xff0000UL) /*!< BLEIF CQSETCLEAR: CQFCLR (Bitfield-Mask: 0xff) */ -#define BLEIF_CQSETCLEAR_CQFTGL_Pos (8UL) /*!< BLEIF CQSETCLEAR: CQFTGL (Bit 8) */ -#define BLEIF_CQSETCLEAR_CQFTGL_Msk (0xff00UL) /*!< BLEIF CQSETCLEAR: CQFTGL (Bitfield-Mask: 0xff) */ -#define BLEIF_CQSETCLEAR_CQFSET_Pos (0UL) /*!< BLEIF CQSETCLEAR: CQFSET (Bit 0) */ -#define BLEIF_CQSETCLEAR_CQFSET_Msk (0xffUL) /*!< BLEIF CQSETCLEAR: CQFSET (Bitfield-Mask: 0xff) */ -/* ======================================================= CQPAUSEEN ======================================================= */ -#define BLEIF_CQPAUSEEN_CQPEN_Pos (0UL) /*!< BLEIF CQPAUSEEN: CQPEN (Bit 0) */ -#define BLEIF_CQPAUSEEN_CQPEN_Msk (0xffffUL) /*!< BLEIF CQPAUSEEN: CQPEN (Bitfield-Mask: 0xffff) */ -/* ======================================================= CQCURIDX ======================================================== */ -#define BLEIF_CQCURIDX_CQCURIDX_Pos (0UL) /*!< BLEIF CQCURIDX: CQCURIDX (Bit 0) */ -#define BLEIF_CQCURIDX_CQCURIDX_Msk (0xffUL) /*!< BLEIF CQCURIDX: CQCURIDX (Bitfield-Mask: 0xff) */ -/* ======================================================= CQENDIDX ======================================================== */ -#define BLEIF_CQENDIDX_CQENDIDX_Pos (0UL) /*!< BLEIF CQENDIDX: CQENDIDX (Bit 0) */ -#define BLEIF_CQENDIDX_CQENDIDX_Msk (0xffUL) /*!< BLEIF CQENDIDX: CQENDIDX (Bitfield-Mask: 0xff) */ -/* ======================================================== STATUS ========================================================= */ -#define BLEIF_STATUS_IDLEST_Pos (2UL) /*!< BLEIF STATUS: IDLEST (Bit 2) */ -#define BLEIF_STATUS_IDLEST_Msk (0x4UL) /*!< BLEIF STATUS: IDLEST (Bitfield-Mask: 0x01) */ -#define BLEIF_STATUS_CMDACT_Pos (1UL) /*!< BLEIF STATUS: CMDACT (Bit 1) */ -#define BLEIF_STATUS_CMDACT_Msk (0x2UL) /*!< BLEIF STATUS: CMDACT (Bitfield-Mask: 0x01) */ -#define BLEIF_STATUS_ERR_Pos (0UL) /*!< BLEIF STATUS: ERR (Bit 0) */ -#define BLEIF_STATUS_ERR_Msk (0x1UL) /*!< BLEIF STATUS: ERR (Bitfield-Mask: 0x01) */ -/* ======================================================== MSPICFG ======================================================== */ -#define BLEIF_MSPICFG_MSPIRST_Pos (30UL) /*!< BLEIF MSPICFG: MSPIRST (Bit 30) */ -#define BLEIF_MSPICFG_MSPIRST_Msk (0x40000000UL) /*!< BLEIF MSPICFG: MSPIRST (Bitfield-Mask: 0x01) */ -#define BLEIF_MSPICFG_DOUTDLY_Pos (27UL) /*!< BLEIF MSPICFG: DOUTDLY (Bit 27) */ -#define BLEIF_MSPICFG_DOUTDLY_Msk (0x38000000UL) /*!< BLEIF MSPICFG: DOUTDLY (Bitfield-Mask: 0x07) */ -#define BLEIF_MSPICFG_DINDLY_Pos (24UL) /*!< BLEIF MSPICFG: DINDLY (Bit 24) */ -#define BLEIF_MSPICFG_DINDLY_Msk (0x7000000UL) /*!< BLEIF MSPICFG: DINDLY (Bitfield-Mask: 0x07) */ -#define BLEIF_MSPICFG_SPILSB_Pos (23UL) /*!< BLEIF MSPICFG: SPILSB (Bit 23) */ -#define BLEIF_MSPICFG_SPILSB_Msk (0x800000UL) /*!< BLEIF MSPICFG: SPILSB (Bitfield-Mask: 0x01) */ -#define BLEIF_MSPICFG_RDFCPOL_Pos (22UL) /*!< BLEIF MSPICFG: RDFCPOL (Bit 22) */ -#define BLEIF_MSPICFG_RDFCPOL_Msk (0x400000UL) /*!< BLEIF MSPICFG: RDFCPOL (Bitfield-Mask: 0x01) */ -#define BLEIF_MSPICFG_WTFCPOL_Pos (21UL) /*!< BLEIF MSPICFG: WTFCPOL (Bit 21) */ -#define BLEIF_MSPICFG_WTFCPOL_Msk (0x200000UL) /*!< BLEIF MSPICFG: WTFCPOL (Bitfield-Mask: 0x01) */ -#define BLEIF_MSPICFG_RDFC_Pos (17UL) /*!< BLEIF MSPICFG: RDFC (Bit 17) */ -#define BLEIF_MSPICFG_RDFC_Msk (0x20000UL) /*!< BLEIF MSPICFG: RDFC (Bitfield-Mask: 0x01) */ -#define BLEIF_MSPICFG_WTFC_Pos (16UL) /*!< BLEIF MSPICFG: WTFC (Bit 16) */ -#define BLEIF_MSPICFG_WTFC_Msk (0x10000UL) /*!< BLEIF MSPICFG: WTFC (Bitfield-Mask: 0x01) */ -#define BLEIF_MSPICFG_FULLDUP_Pos (2UL) /*!< BLEIF MSPICFG: FULLDUP (Bit 2) */ -#define BLEIF_MSPICFG_FULLDUP_Msk (0x4UL) /*!< BLEIF MSPICFG: FULLDUP (Bitfield-Mask: 0x01) */ -#define BLEIF_MSPICFG_SPHA_Pos (1UL) /*!< BLEIF MSPICFG: SPHA (Bit 1) */ -#define BLEIF_MSPICFG_SPHA_Msk (0x2UL) /*!< BLEIF MSPICFG: SPHA (Bitfield-Mask: 0x01) */ -#define BLEIF_MSPICFG_SPOL_Pos (0UL) /*!< BLEIF MSPICFG: SPOL (Bit 0) */ -#define BLEIF_MSPICFG_SPOL_Msk (0x1UL) /*!< BLEIF MSPICFG: SPOL (Bitfield-Mask: 0x01) */ -/* ======================================================== BLECFG ========================================================= */ -#define BLEIF_BLECFG_SPIISOCTL_Pos (14UL) /*!< BLEIF BLECFG: SPIISOCTL (Bit 14) */ -#define BLEIF_BLECFG_SPIISOCTL_Msk (0xc000UL) /*!< BLEIF BLECFG: SPIISOCTL (Bitfield-Mask: 0x03) */ -#define BLEIF_BLECFG_PWRISOCTL_Pos (12UL) /*!< BLEIF BLECFG: PWRISOCTL (Bit 12) */ -#define BLEIF_BLECFG_PWRISOCTL_Msk (0x3000UL) /*!< BLEIF BLECFG: PWRISOCTL (Bitfield-Mask: 0x03) */ -#define BLEIF_BLECFG_STAYASLEEP_Pos (11UL) /*!< BLEIF BLECFG: STAYASLEEP (Bit 11) */ -#define BLEIF_BLECFG_STAYASLEEP_Msk (0x800UL) /*!< BLEIF BLECFG: STAYASLEEP (Bitfield-Mask: 0x01) */ -#define BLEIF_BLECFG_FRCCLK_Pos (10UL) /*!< BLEIF BLECFG: FRCCLK (Bit 10) */ -#define BLEIF_BLECFG_FRCCLK_Msk (0x400UL) /*!< BLEIF BLECFG: FRCCLK (Bitfield-Mask: 0x01) */ -#define BLEIF_BLECFG_MCUFRCSLP_Pos (9UL) /*!< BLEIF BLECFG: MCUFRCSLP (Bit 9) */ -#define BLEIF_BLECFG_MCUFRCSLP_Msk (0x200UL) /*!< BLEIF BLECFG: MCUFRCSLP (Bitfield-Mask: 0x01) */ -#define BLEIF_BLECFG_WT4ACTOFF_Pos (8UL) /*!< BLEIF BLECFG: WT4ACTOFF (Bit 8) */ -#define BLEIF_BLECFG_WT4ACTOFF_Msk (0x100UL) /*!< BLEIF BLECFG: WT4ACTOFF (Bitfield-Mask: 0x01) */ -#define BLEIF_BLECFG_BLEHREQCTL_Pos (6UL) /*!< BLEIF BLECFG: BLEHREQCTL (Bit 6) */ -#define BLEIF_BLECFG_BLEHREQCTL_Msk (0xc0UL) /*!< BLEIF BLECFG: BLEHREQCTL (Bitfield-Mask: 0x03) */ -#define BLEIF_BLECFG_DCDCFLGCTL_Pos (4UL) /*!< BLEIF BLECFG: DCDCFLGCTL (Bit 4) */ -#define BLEIF_BLECFG_DCDCFLGCTL_Msk (0x30UL) /*!< BLEIF BLECFG: DCDCFLGCTL (Bitfield-Mask: 0x03) */ -#define BLEIF_BLECFG_WAKEUPCTL_Pos (2UL) /*!< BLEIF BLECFG: WAKEUPCTL (Bit 2) */ -#define BLEIF_BLECFG_WAKEUPCTL_Msk (0xcUL) /*!< BLEIF BLECFG: WAKEUPCTL (Bitfield-Mask: 0x03) */ -#define BLEIF_BLECFG_BLERSTN_Pos (1UL) /*!< BLEIF BLECFG: BLERSTN (Bit 1) */ -#define BLEIF_BLECFG_BLERSTN_Msk (0x2UL) /*!< BLEIF BLECFG: BLERSTN (Bitfield-Mask: 0x01) */ -#define BLEIF_BLECFG_PWRSMEN_Pos (0UL) /*!< BLEIF BLECFG: PWRSMEN (Bit 0) */ -#define BLEIF_BLECFG_PWRSMEN_Msk (0x1UL) /*!< BLEIF BLECFG: PWRSMEN (Bitfield-Mask: 0x01) */ -/* ======================================================== PWRCMD ========================================================= */ -#define BLEIF_PWRCMD_RESTART_Pos (1UL) /*!< BLEIF PWRCMD: RESTART (Bit 1) */ -#define BLEIF_PWRCMD_RESTART_Msk (0x2UL) /*!< BLEIF PWRCMD: RESTART (Bitfield-Mask: 0x01) */ -#define BLEIF_PWRCMD_WAKEREQ_Pos (0UL) /*!< BLEIF PWRCMD: WAKEREQ (Bit 0) */ -#define BLEIF_PWRCMD_WAKEREQ_Msk (0x1UL) /*!< BLEIF PWRCMD: WAKEREQ (Bitfield-Mask: 0x01) */ -/* ======================================================== BSTATUS ======================================================== */ -#define BLEIF_BSTATUS_BLEHREQ_Pos (12UL) /*!< BLEIF BSTATUS: BLEHREQ (Bit 12) */ -#define BLEIF_BSTATUS_BLEHREQ_Msk (0x1000UL) /*!< BLEIF BSTATUS: BLEHREQ (Bitfield-Mask: 0x01) */ -#define BLEIF_BSTATUS_BLEHACK_Pos (11UL) /*!< BLEIF BSTATUS: BLEHACK (Bit 11) */ -#define BLEIF_BSTATUS_BLEHACK_Msk (0x800UL) /*!< BLEIF BSTATUS: BLEHACK (Bitfield-Mask: 0x01) */ -#define BLEIF_BSTATUS_PWRST_Pos (8UL) /*!< BLEIF BSTATUS: PWRST (Bit 8) */ -#define BLEIF_BSTATUS_PWRST_Msk (0x700UL) /*!< BLEIF BSTATUS: PWRST (Bitfield-Mask: 0x07) */ -#define BLEIF_BSTATUS_BLEIRQ_Pos (7UL) /*!< BLEIF BSTATUS: BLEIRQ (Bit 7) */ -#define BLEIF_BSTATUS_BLEIRQ_Msk (0x80UL) /*!< BLEIF BSTATUS: BLEIRQ (Bitfield-Mask: 0x01) */ -#define BLEIF_BSTATUS_WAKEUP_Pos (6UL) /*!< BLEIF BSTATUS: WAKEUP (Bit 6) */ -#define BLEIF_BSTATUS_WAKEUP_Msk (0x40UL) /*!< BLEIF BSTATUS: WAKEUP (Bitfield-Mask: 0x01) */ -#define BLEIF_BSTATUS_DCDCFLAG_Pos (5UL) /*!< BLEIF BSTATUS: DCDCFLAG (Bit 5) */ -#define BLEIF_BSTATUS_DCDCFLAG_Msk (0x20UL) /*!< BLEIF BSTATUS: DCDCFLAG (Bitfield-Mask: 0x01) */ -#define BLEIF_BSTATUS_DCDCREQ_Pos (4UL) /*!< BLEIF BSTATUS: DCDCREQ (Bit 4) */ -#define BLEIF_BSTATUS_DCDCREQ_Msk (0x10UL) /*!< BLEIF BSTATUS: DCDCREQ (Bitfield-Mask: 0x01) */ -#define BLEIF_BSTATUS_SPISTATUS_Pos (3UL) /*!< BLEIF BSTATUS: SPISTATUS (Bit 3) */ -#define BLEIF_BSTATUS_SPISTATUS_Msk (0x8UL) /*!< BLEIF BSTATUS: SPISTATUS (Bitfield-Mask: 0x01) */ -#define BLEIF_BSTATUS_B2MSTATE_Pos (0UL) /*!< BLEIF BSTATUS: B2MSTATE (Bit 0) */ -#define BLEIF_BSTATUS_B2MSTATE_Msk (0x7UL) /*!< BLEIF BSTATUS: B2MSTATE (Bitfield-Mask: 0x07) */ -/* ======================================================== BLEDBG ========================================================= */ -#define BLEIF_BLEDBG_DBGDATA_Pos (3UL) /*!< BLEIF BLEDBG: DBGDATA (Bit 3) */ -#define BLEIF_BLEDBG_DBGDATA_Msk (0xfffffff8UL) /*!< BLEIF BLEDBG: DBGDATA (Bitfield-Mask: 0x1fffffff) */ -#define BLEIF_BLEDBG_APBCLKON_Pos (2UL) /*!< BLEIF BLEDBG: APBCLKON (Bit 2) */ -#define BLEIF_BLEDBG_APBCLKON_Msk (0x4UL) /*!< BLEIF BLEDBG: APBCLKON (Bitfield-Mask: 0x01) */ -#define BLEIF_BLEDBG_IOCLKON_Pos (1UL) /*!< BLEIF BLEDBG: IOCLKON (Bit 1) */ -#define BLEIF_BLEDBG_IOCLKON_Msk (0x2UL) /*!< BLEIF BLEDBG: IOCLKON (Bitfield-Mask: 0x01) */ -#define BLEIF_BLEDBG_DBGEN_Pos (0UL) /*!< BLEIF BLEDBG: DBGEN (Bit 0) */ -#define BLEIF_BLEDBG_DBGEN_Msk (0x1UL) /*!< BLEIF BLEDBG: DBGEN (Bitfield-Mask: 0x01) */ - - -/* =========================================================================================================================== */ -/* ================ CACHECTRL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================= CACHECFG ======================================================== */ -#define CACHECTRL_CACHECFG_ENABLE_MONITOR_Pos (24UL) /*!< CACHECTRL CACHECFG: ENABLE_MONITOR (Bit 24) */ -#define CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk (0x1000000UL) /*!< CACHECTRL CACHECFG: ENABLE_MONITOR (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CACHECFG_DATA_CLKGATE_Pos (20UL) /*!< CACHECTRL CACHECFG: DATA_CLKGATE (Bit 20) */ -#define CACHECTRL_CACHECFG_DATA_CLKGATE_Msk (0x100000UL) /*!< CACHECTRL CACHECFG: DATA_CLKGATE (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CACHECFG_CACHE_LS_Pos (11UL) /*!< CACHECTRL CACHECFG: CACHE_LS (Bit 11) */ -#define CACHECTRL_CACHECFG_CACHE_LS_Msk (0x800UL) /*!< CACHECTRL CACHECFG: CACHE_LS (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CACHECFG_CACHE_CLKGATE_Pos (10UL) /*!< CACHECTRL CACHECFG: CACHE_CLKGATE (Bit 10) */ -#define CACHECTRL_CACHECFG_CACHE_CLKGATE_Msk (0x400UL) /*!< CACHECTRL CACHECFG: CACHE_CLKGATE (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CACHECFG_DCACHE_ENABLE_Pos (9UL) /*!< CACHECTRL CACHECFG: DCACHE_ENABLE (Bit 9) */ -#define CACHECTRL_CACHECFG_DCACHE_ENABLE_Msk (0x200UL) /*!< CACHECTRL CACHECFG: DCACHE_ENABLE (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CACHECFG_ICACHE_ENABLE_Pos (8UL) /*!< CACHECTRL CACHECFG: ICACHE_ENABLE (Bit 8) */ -#define CACHECTRL_CACHECFG_ICACHE_ENABLE_Msk (0x100UL) /*!< CACHECTRL CACHECFG: ICACHE_ENABLE (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CACHECFG_CONFIG_Pos (4UL) /*!< CACHECTRL CACHECFG: CONFIG (Bit 4) */ -#define CACHECTRL_CACHECFG_CONFIG_Msk (0xf0UL) /*!< CACHECTRL CACHECFG: CONFIG (Bitfield-Mask: 0x0f) */ -#define CACHECTRL_CACHECFG_ENABLE_NC1_Pos (3UL) /*!< CACHECTRL CACHECFG: ENABLE_NC1 (Bit 3) */ -#define CACHECTRL_CACHECFG_ENABLE_NC1_Msk (0x8UL) /*!< CACHECTRL CACHECFG: ENABLE_NC1 (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CACHECFG_ENABLE_NC0_Pos (2UL) /*!< CACHECTRL CACHECFG: ENABLE_NC0 (Bit 2) */ -#define CACHECTRL_CACHECFG_ENABLE_NC0_Msk (0x4UL) /*!< CACHECTRL CACHECFG: ENABLE_NC0 (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CACHECFG_LRU_Pos (1UL) /*!< CACHECTRL CACHECFG: LRU (Bit 1) */ -#define CACHECTRL_CACHECFG_LRU_Msk (0x2UL) /*!< CACHECTRL CACHECFG: LRU (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CACHECFG_ENABLE_Pos (0UL) /*!< CACHECTRL CACHECFG: ENABLE (Bit 0) */ -#define CACHECTRL_CACHECFG_ENABLE_Msk (0x1UL) /*!< CACHECTRL CACHECFG: ENABLE (Bitfield-Mask: 0x01) */ -/* ========================================================= CTRL ========================================================== */ -#define CACHECTRL_CTRL_FLASH3_SLM_ENABLE_Pos (18UL) /*!< CACHECTRL CTRL: FLASH3_SLM_ENABLE (Bit 18) */ -#define CACHECTRL_CTRL_FLASH3_SLM_ENABLE_Msk (0x40000UL) /*!< CACHECTRL CTRL: FLASH3_SLM_ENABLE (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CTRL_FLASH3_SLM_DISABLE_Pos (17UL) /*!< CACHECTRL CTRL: FLASH3_SLM_DISABLE (Bit 17) */ -#define CACHECTRL_CTRL_FLASH3_SLM_DISABLE_Msk (0x20000UL) /*!< CACHECTRL CTRL: FLASH3_SLM_DISABLE (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CTRL_FLASH3_SLM_STATUS_Pos (16UL) /*!< CACHECTRL CTRL: FLASH3_SLM_STATUS (Bit 16) */ -#define CACHECTRL_CTRL_FLASH3_SLM_STATUS_Msk (0x10000UL) /*!< CACHECTRL CTRL: FLASH3_SLM_STATUS (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CTRL_FLASH2_SLM_ENABLE_Pos (14UL) /*!< CACHECTRL CTRL: FLASH2_SLM_ENABLE (Bit 14) */ -#define CACHECTRL_CTRL_FLASH2_SLM_ENABLE_Msk (0x4000UL) /*!< CACHECTRL CTRL: FLASH2_SLM_ENABLE (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CTRL_FLASH2_SLM_DISABLE_Pos (13UL) /*!< CACHECTRL CTRL: FLASH2_SLM_DISABLE (Bit 13) */ -#define CACHECTRL_CTRL_FLASH2_SLM_DISABLE_Msk (0x2000UL) /*!< CACHECTRL CTRL: FLASH2_SLM_DISABLE (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CTRL_FLASH2_SLM_STATUS_Pos (12UL) /*!< CACHECTRL CTRL: FLASH2_SLM_STATUS (Bit 12) */ -#define CACHECTRL_CTRL_FLASH2_SLM_STATUS_Msk (0x1000UL) /*!< CACHECTRL CTRL: FLASH2_SLM_STATUS (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Pos (10UL) /*!< CACHECTRL CTRL: FLASH1_SLM_ENABLE (Bit 10) */ -#define CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Msk (0x400UL) /*!< CACHECTRL CTRL: FLASH1_SLM_ENABLE (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Pos (9UL) /*!< CACHECTRL CTRL: FLASH1_SLM_DISABLE (Bit 9) */ -#define CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Msk (0x200UL) /*!< CACHECTRL CTRL: FLASH1_SLM_DISABLE (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CTRL_FLASH1_SLM_STATUS_Pos (8UL) /*!< CACHECTRL CTRL: FLASH1_SLM_STATUS (Bit 8) */ -#define CACHECTRL_CTRL_FLASH1_SLM_STATUS_Msk (0x100UL) /*!< CACHECTRL CTRL: FLASH1_SLM_STATUS (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Pos (6UL) /*!< CACHECTRL CTRL: FLASH0_SLM_ENABLE (Bit 6) */ -#define CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Msk (0x40UL) /*!< CACHECTRL CTRL: FLASH0_SLM_ENABLE (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Pos (5UL) /*!< CACHECTRL CTRL: FLASH0_SLM_DISABLE (Bit 5) */ -#define CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Msk (0x20UL) /*!< CACHECTRL CTRL: FLASH0_SLM_DISABLE (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CTRL_FLASH0_SLM_STATUS_Pos (4UL) /*!< CACHECTRL CTRL: FLASH0_SLM_STATUS (Bit 4) */ -#define CACHECTRL_CTRL_FLASH0_SLM_STATUS_Msk (0x10UL) /*!< CACHECTRL CTRL: FLASH0_SLM_STATUS (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CTRL_CACHE_READY_Pos (2UL) /*!< CACHECTRL CTRL: CACHE_READY (Bit 2) */ -#define CACHECTRL_CTRL_CACHE_READY_Msk (0x4UL) /*!< CACHECTRL CTRL: CACHE_READY (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CTRL_RESET_STAT_Pos (1UL) /*!< CACHECTRL CTRL: RESET_STAT (Bit 1) */ -#define CACHECTRL_CTRL_RESET_STAT_Msk (0x2UL) /*!< CACHECTRL CTRL: RESET_STAT (Bitfield-Mask: 0x01) */ -#define CACHECTRL_CTRL_INVALIDATE_Pos (0UL) /*!< CACHECTRL CTRL: INVALIDATE (Bit 0) */ -#define CACHECTRL_CTRL_INVALIDATE_Msk (0x1UL) /*!< CACHECTRL CTRL: INVALIDATE (Bitfield-Mask: 0x01) */ -/* ======================================================= NCR0START ======================================================= */ -#define CACHECTRL_NCR0START_ADDR_Pos (4UL) /*!< CACHECTRL NCR0START: ADDR (Bit 4) */ -#define CACHECTRL_NCR0START_ADDR_Msk (0x7fffff0UL) /*!< CACHECTRL NCR0START: ADDR (Bitfield-Mask: 0x7fffff) */ -/* ======================================================== NCR0END ======================================================== */ -#define CACHECTRL_NCR0END_ADDR_Pos (4UL) /*!< CACHECTRL NCR0END: ADDR (Bit 4) */ -#define CACHECTRL_NCR0END_ADDR_Msk (0x7fffff0UL) /*!< CACHECTRL NCR0END: ADDR (Bitfield-Mask: 0x7fffff) */ -/* ======================================================= NCR1START ======================================================= */ -#define CACHECTRL_NCR1START_ADDR_Pos (4UL) /*!< CACHECTRL NCR1START: ADDR (Bit 4) */ -#define CACHECTRL_NCR1START_ADDR_Msk (0x7fffff0UL) /*!< CACHECTRL NCR1START: ADDR (Bitfield-Mask: 0x7fffff) */ -/* ======================================================== NCR1END ======================================================== */ -#define CACHECTRL_NCR1END_ADDR_Pos (4UL) /*!< CACHECTRL NCR1END: ADDR (Bit 4) */ -#define CACHECTRL_NCR1END_ADDR_Msk (0x7fffff0UL) /*!< CACHECTRL NCR1END: ADDR (Bitfield-Mask: 0x7fffff) */ -/* ========================================================= DMON0 ========================================================= */ -#define CACHECTRL_DMON0_DACCESS_COUNT_Pos (0UL) /*!< CACHECTRL DMON0: DACCESS_COUNT (Bit 0) */ -#define CACHECTRL_DMON0_DACCESS_COUNT_Msk (0xffffffffUL) /*!< CACHECTRL DMON0: DACCESS_COUNT (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMON1 ========================================================= */ -#define CACHECTRL_DMON1_DLOOKUP_COUNT_Pos (0UL) /*!< CACHECTRL DMON1: DLOOKUP_COUNT (Bit 0) */ -#define CACHECTRL_DMON1_DLOOKUP_COUNT_Msk (0xffffffffUL) /*!< CACHECTRL DMON1: DLOOKUP_COUNT (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMON2 ========================================================= */ -#define CACHECTRL_DMON2_DHIT_COUNT_Pos (0UL) /*!< CACHECTRL DMON2: DHIT_COUNT (Bit 0) */ -#define CACHECTRL_DMON2_DHIT_COUNT_Msk (0xffffffffUL) /*!< CACHECTRL DMON2: DHIT_COUNT (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DMON3 ========================================================= */ -#define CACHECTRL_DMON3_DLINE_COUNT_Pos (0UL) /*!< CACHECTRL DMON3: DLINE_COUNT (Bit 0) */ -#define CACHECTRL_DMON3_DLINE_COUNT_Msk (0xffffffffUL) /*!< CACHECTRL DMON3: DLINE_COUNT (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= IMON0 ========================================================= */ -#define CACHECTRL_IMON0_IACCESS_COUNT_Pos (0UL) /*!< CACHECTRL IMON0: IACCESS_COUNT (Bit 0) */ -#define CACHECTRL_IMON0_IACCESS_COUNT_Msk (0xffffffffUL) /*!< CACHECTRL IMON0: IACCESS_COUNT (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= IMON1 ========================================================= */ -#define CACHECTRL_IMON1_ILOOKUP_COUNT_Pos (0UL) /*!< CACHECTRL IMON1: ILOOKUP_COUNT (Bit 0) */ -#define CACHECTRL_IMON1_ILOOKUP_COUNT_Msk (0xffffffffUL) /*!< CACHECTRL IMON1: ILOOKUP_COUNT (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= IMON2 ========================================================= */ -#define CACHECTRL_IMON2_IHIT_COUNT_Pos (0UL) /*!< CACHECTRL IMON2: IHIT_COUNT (Bit 0) */ -#define CACHECTRL_IMON2_IHIT_COUNT_Msk (0xffffffffUL) /*!< CACHECTRL IMON2: IHIT_COUNT (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= IMON3 ========================================================= */ -#define CACHECTRL_IMON3_ILINE_COUNT_Pos (0UL) /*!< CACHECTRL IMON3: ILINE_COUNT (Bit 0) */ -#define CACHECTRL_IMON3_ILINE_COUNT_Msk (0xffffffffUL) /*!< CACHECTRL IMON3: ILINE_COUNT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= FLASH0CFG ======================================================= */ -#define CACHECTRL_FLASH0CFG_LPMMODE0_Pos (12UL) /*!< CACHECTRL FLASH0CFG: LPMMODE0 (Bit 12) */ -#define CACHECTRL_FLASH0CFG_LPMMODE0_Msk (0x3000UL) /*!< CACHECTRL FLASH0CFG: LPMMODE0 (Bitfield-Mask: 0x03) */ -#define CACHECTRL_FLASH0CFG_LPMRDWAIT0_Pos (8UL) /*!< CACHECTRL FLASH0CFG: LPMRDWAIT0 (Bit 8) */ -#define CACHECTRL_FLASH0CFG_LPMRDWAIT0_Msk (0xf00UL) /*!< CACHECTRL FLASH0CFG: LPMRDWAIT0 (Bitfield-Mask: 0x0f) */ -#define CACHECTRL_FLASH0CFG_SEDELAY0_Pos (4UL) /*!< CACHECTRL FLASH0CFG: SEDELAY0 (Bit 4) */ -#define CACHECTRL_FLASH0CFG_SEDELAY0_Msk (0x70UL) /*!< CACHECTRL FLASH0CFG: SEDELAY0 (Bitfield-Mask: 0x07) */ -#define CACHECTRL_FLASH0CFG_RDWAIT0_Pos (0UL) /*!< CACHECTRL FLASH0CFG: RDWAIT0 (Bit 0) */ -#define CACHECTRL_FLASH0CFG_RDWAIT0_Msk (0xfUL) /*!< CACHECTRL FLASH0CFG: RDWAIT0 (Bitfield-Mask: 0x0f) */ -/* ======================================================= FLASH1CFG ======================================================= */ -#define CACHECTRL_FLASH1CFG_LPMMODE1_Pos (12UL) /*!< CACHECTRL FLASH1CFG: LPMMODE1 (Bit 12) */ -#define CACHECTRL_FLASH1CFG_LPMMODE1_Msk (0x3000UL) /*!< CACHECTRL FLASH1CFG: LPMMODE1 (Bitfield-Mask: 0x03) */ -#define CACHECTRL_FLASH1CFG_LPMRDWAIT1_Pos (8UL) /*!< CACHECTRL FLASH1CFG: LPMRDWAIT1 (Bit 8) */ -#define CACHECTRL_FLASH1CFG_LPMRDWAIT1_Msk (0xf00UL) /*!< CACHECTRL FLASH1CFG: LPMRDWAIT1 (Bitfield-Mask: 0x0f) */ -#define CACHECTRL_FLASH1CFG_SEDELAY1_Pos (4UL) /*!< CACHECTRL FLASH1CFG: SEDELAY1 (Bit 4) */ -#define CACHECTRL_FLASH1CFG_SEDELAY1_Msk (0x70UL) /*!< CACHECTRL FLASH1CFG: SEDELAY1 (Bitfield-Mask: 0x07) */ -#define CACHECTRL_FLASH1CFG_RDWAIT1_Pos (0UL) /*!< CACHECTRL FLASH1CFG: RDWAIT1 (Bit 0) */ -#define CACHECTRL_FLASH1CFG_RDWAIT1_Msk (0xfUL) /*!< CACHECTRL FLASH1CFG: RDWAIT1 (Bitfield-Mask: 0x0f) */ -/* ======================================================= FLASH2CFG ======================================================= */ -#define CACHECTRL_FLASH2CFG_LPMMODE2_Pos (12UL) /*!< CACHECTRL FLASH2CFG: LPMMODE2 (Bit 12) */ -#define CACHECTRL_FLASH2CFG_LPMMODE2_Msk (0x3000UL) /*!< CACHECTRL FLASH2CFG: LPMMODE2 (Bitfield-Mask: 0x03) */ -#define CACHECTRL_FLASH2CFG_LPMRDWAIT2_Pos (8UL) /*!< CACHECTRL FLASH2CFG: LPMRDWAIT2 (Bit 8) */ -#define CACHECTRL_FLASH2CFG_LPMRDWAIT2_Msk (0xf00UL) /*!< CACHECTRL FLASH2CFG: LPMRDWAIT2 (Bitfield-Mask: 0x0f) */ -#define CACHECTRL_FLASH2CFG_SEDELAY2_Pos (4UL) /*!< CACHECTRL FLASH2CFG: SEDELAY2 (Bit 4) */ -#define CACHECTRL_FLASH2CFG_SEDELAY2_Msk (0x70UL) /*!< CACHECTRL FLASH2CFG: SEDELAY2 (Bitfield-Mask: 0x07) */ -#define CACHECTRL_FLASH2CFG_RDWAIT2_Pos (0UL) /*!< CACHECTRL FLASH2CFG: RDWAIT2 (Bit 0) */ -#define CACHECTRL_FLASH2CFG_RDWAIT2_Msk (0xfUL) /*!< CACHECTRL FLASH2CFG: RDWAIT2 (Bitfield-Mask: 0x0f) */ -/* ======================================================= FLASH3CFG ======================================================= */ -#define CACHECTRL_FLASH3CFG_LPMMODE3_Pos (12UL) /*!< CACHECTRL FLASH3CFG: LPMMODE3 (Bit 12) */ -#define CACHECTRL_FLASH3CFG_LPMMODE3_Msk (0x3000UL) /*!< CACHECTRL FLASH3CFG: LPMMODE3 (Bitfield-Mask: 0x03) */ -#define CACHECTRL_FLASH3CFG_LPMRDWAIT3_Pos (8UL) /*!< CACHECTRL FLASH3CFG: LPMRDWAIT3 (Bit 8) */ -#define CACHECTRL_FLASH3CFG_LPMRDWAIT3_Msk (0xf00UL) /*!< CACHECTRL FLASH3CFG: LPMRDWAIT3 (Bitfield-Mask: 0x0f) */ -#define CACHECTRL_FLASH3CFG_SEDELAY3_Pos (4UL) /*!< CACHECTRL FLASH3CFG: SEDELAY3 (Bit 4) */ -#define CACHECTRL_FLASH3CFG_SEDELAY3_Msk (0x70UL) /*!< CACHECTRL FLASH3CFG: SEDELAY3 (Bitfield-Mask: 0x07) */ -#define CACHECTRL_FLASH3CFG_RDWAIT3_Pos (0UL) /*!< CACHECTRL FLASH3CFG: RDWAIT3 (Bit 0) */ -#define CACHECTRL_FLASH3CFG_RDWAIT3_Msk (0xfUL) /*!< CACHECTRL FLASH3CFG: RDWAIT3 (Bitfield-Mask: 0x0f) */ - - -/* =========================================================================================================================== */ -/* ================ CLKGEN ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CALXT ========================================================= */ -#define CLKGEN_CALXT_CALXT_Pos (0UL) /*!< CLKGEN CALXT: CALXT (Bit 0) */ -#define CLKGEN_CALXT_CALXT_Msk (0x7ffUL) /*!< CLKGEN CALXT: CALXT (Bitfield-Mask: 0x7ff) */ -/* ========================================================= CALRC ========================================================= */ -#define CLKGEN_CALRC_CALRC_Pos (0UL) /*!< CLKGEN CALRC: CALRC (Bit 0) */ -#define CLKGEN_CALRC_CALRC_Msk (0x3ffffUL) /*!< CLKGEN CALRC: CALRC (Bitfield-Mask: 0x3ffff) */ -/* ======================================================== ACALCTR ======================================================== */ -#define CLKGEN_ACALCTR_ACALCTR_Pos (0UL) /*!< CLKGEN ACALCTR: ACALCTR (Bit 0) */ -#define CLKGEN_ACALCTR_ACALCTR_Msk (0xffffffUL) /*!< CLKGEN ACALCTR: ACALCTR (Bitfield-Mask: 0xffffff) */ -/* ========================================================= OCTRL ========================================================= */ -#define CLKGEN_OCTRL_ACAL_Pos (8UL) /*!< CLKGEN OCTRL: ACAL (Bit 8) */ -#define CLKGEN_OCTRL_ACAL_Msk (0x700UL) /*!< CLKGEN OCTRL: ACAL (Bitfield-Mask: 0x07) */ -#define CLKGEN_OCTRL_OSEL_Pos (7UL) /*!< CLKGEN OCTRL: OSEL (Bit 7) */ -#define CLKGEN_OCTRL_OSEL_Msk (0x80UL) /*!< CLKGEN OCTRL: OSEL (Bitfield-Mask: 0x01) */ -#define CLKGEN_OCTRL_FOS_Pos (6UL) /*!< CLKGEN OCTRL: FOS (Bit 6) */ -#define CLKGEN_OCTRL_FOS_Msk (0x40UL) /*!< CLKGEN OCTRL: FOS (Bitfield-Mask: 0x01) */ -#define CLKGEN_OCTRL_STOPRC_Pos (1UL) /*!< CLKGEN OCTRL: STOPRC (Bit 1) */ -#define CLKGEN_OCTRL_STOPRC_Msk (0x2UL) /*!< CLKGEN OCTRL: STOPRC (Bitfield-Mask: 0x01) */ -#define CLKGEN_OCTRL_STOPXT_Pos (0UL) /*!< CLKGEN OCTRL: STOPXT (Bit 0) */ -#define CLKGEN_OCTRL_STOPXT_Msk (0x1UL) /*!< CLKGEN OCTRL: STOPXT (Bitfield-Mask: 0x01) */ -/* ======================================================== CLKOUT ========================================================= */ -#define CLKGEN_CLKOUT_CKEN_Pos (7UL) /*!< CLKGEN CLKOUT: CKEN (Bit 7) */ -#define CLKGEN_CLKOUT_CKEN_Msk (0x80UL) /*!< CLKGEN CLKOUT: CKEN (Bitfield-Mask: 0x01) */ -#define CLKGEN_CLKOUT_CKSEL_Pos (0UL) /*!< CLKGEN CLKOUT: CKSEL (Bit 0) */ -#define CLKGEN_CLKOUT_CKSEL_Msk (0x3fUL) /*!< CLKGEN CLKOUT: CKSEL (Bitfield-Mask: 0x3f) */ -/* ======================================================== CLKKEY ========================================================= */ -#define CLKGEN_CLKKEY_CLKKEY_Pos (0UL) /*!< CLKGEN CLKKEY: CLKKEY (Bit 0) */ -#define CLKGEN_CLKKEY_CLKKEY_Msk (0xffffffffUL) /*!< CLKGEN CLKKEY: CLKKEY (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= CCTRL ========================================================= */ -#define CLKGEN_CCTRL_CORESEL_Pos (0UL) /*!< CLKGEN CCTRL: CORESEL (Bit 0) */ -#define CLKGEN_CCTRL_CORESEL_Msk (0x1UL) /*!< CLKGEN CCTRL: CORESEL (Bitfield-Mask: 0x01) */ -/* ======================================================== STATUS ========================================================= */ -#define CLKGEN_STATUS_OSCF_Pos (1UL) /*!< CLKGEN STATUS: OSCF (Bit 1) */ -#define CLKGEN_STATUS_OSCF_Msk (0x2UL) /*!< CLKGEN STATUS: OSCF (Bitfield-Mask: 0x01) */ -#define CLKGEN_STATUS_OMODE_Pos (0UL) /*!< CLKGEN STATUS: OMODE (Bit 0) */ -#define CLKGEN_STATUS_OMODE_Msk (0x1UL) /*!< CLKGEN STATUS: OMODE (Bitfield-Mask: 0x01) */ -/* ========================================================= HFADJ ========================================================= */ -#define CLKGEN_HFADJ_HFADJGAIN_Pos (21UL) /*!< CLKGEN HFADJ: HFADJGAIN (Bit 21) */ -#define CLKGEN_HFADJ_HFADJGAIN_Msk (0xe00000UL) /*!< CLKGEN HFADJ: HFADJGAIN (Bitfield-Mask: 0x07) */ -#define CLKGEN_HFADJ_HFWARMUP_Pos (20UL) /*!< CLKGEN HFADJ: HFWARMUP (Bit 20) */ -#define CLKGEN_HFADJ_HFWARMUP_Msk (0x100000UL) /*!< CLKGEN HFADJ: HFWARMUP (Bitfield-Mask: 0x01) */ -#define CLKGEN_HFADJ_HFXTADJ_Pos (8UL) /*!< CLKGEN HFADJ: HFXTADJ (Bit 8) */ -#define CLKGEN_HFADJ_HFXTADJ_Msk (0xfff00UL) /*!< CLKGEN HFADJ: HFXTADJ (Bitfield-Mask: 0xfff) */ -#define CLKGEN_HFADJ_HFADJCK_Pos (1UL) /*!< CLKGEN HFADJ: HFADJCK (Bit 1) */ -#define CLKGEN_HFADJ_HFADJCK_Msk (0xeUL) /*!< CLKGEN HFADJ: HFADJCK (Bitfield-Mask: 0x07) */ -#define CLKGEN_HFADJ_HFADJEN_Pos (0UL) /*!< CLKGEN HFADJ: HFADJEN (Bit 0) */ -#define CLKGEN_HFADJ_HFADJEN_Msk (0x1UL) /*!< CLKGEN HFADJ: HFADJEN (Bitfield-Mask: 0x01) */ -/* ====================================================== CLOCKENSTAT ====================================================== */ -#define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Pos (0UL) /*!< CLKGEN CLOCKENSTAT: CLOCKENSTAT (Bit 0) */ -#define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Msk (0xffffffffUL) /*!< CLKGEN CLOCKENSTAT: CLOCKENSTAT (Bitfield-Mask: 0xffffffff) */ -/* ===================================================== CLOCKEN2STAT ====================================================== */ -#define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Pos (0UL) /*!< CLKGEN CLOCKEN2STAT: CLOCKEN2STAT (Bit 0) */ -#define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Msk (0xffffffffUL) /*!< CLKGEN CLOCKEN2STAT: CLOCKEN2STAT (Bitfield-Mask: 0xffffffff) */ -/* ===================================================== CLOCKEN3STAT ====================================================== */ -#define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Pos (0UL) /*!< CLKGEN CLOCKEN3STAT: CLOCKEN3STAT (Bit 0) */ -#define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Msk (0xffffffffUL) /*!< CLKGEN CLOCKEN3STAT: CLOCKEN3STAT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= FREQCTRL ======================================================== */ -#define CLKGEN_FREQCTRL_BURSTSTATUS_Pos (2UL) /*!< CLKGEN FREQCTRL: BURSTSTATUS (Bit 2) */ -#define CLKGEN_FREQCTRL_BURSTSTATUS_Msk (0x4UL) /*!< CLKGEN FREQCTRL: BURSTSTATUS (Bitfield-Mask: 0x01) */ -#define CLKGEN_FREQCTRL_BURSTACK_Pos (1UL) /*!< CLKGEN FREQCTRL: BURSTACK (Bit 1) */ -#define CLKGEN_FREQCTRL_BURSTACK_Msk (0x2UL) /*!< CLKGEN FREQCTRL: BURSTACK (Bitfield-Mask: 0x01) */ -#define CLKGEN_FREQCTRL_BURSTREQ_Pos (0UL) /*!< CLKGEN FREQCTRL: BURSTREQ (Bit 0) */ -#define CLKGEN_FREQCTRL_BURSTREQ_Msk (0x1UL) /*!< CLKGEN FREQCTRL: BURSTREQ (Bitfield-Mask: 0x01) */ -/* ===================================================== BLEBUCKTONADJ ===================================================== */ -#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Pos (27UL) /*!< CLKGEN BLEBUCKTONADJ: ZEROLENDETECTEN (Bit 27) */ -#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Msk (0x8000000UL) /*!< CLKGEN BLEBUCKTONADJ: ZEROLENDETECTEN (Bitfield-Mask: 0x01) */ -#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Pos (23UL) /*!< CLKGEN BLEBUCKTONADJ: ZEROLENDETECTTRIM (Bit 23) */ -#define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Msk (0x7800000UL) /*!< CLKGEN BLEBUCKTONADJ: ZEROLENDETECTTRIM (Bitfield-Mask: 0x0f) */ -#define CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Pos (22UL) /*!< CLKGEN BLEBUCKTONADJ: TONADJUSTEN (Bit 22) */ -#define CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Msk (0x400000UL) /*!< CLKGEN BLEBUCKTONADJ: TONADJUSTEN (Bitfield-Mask: 0x01) */ -#define CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Pos (20UL) /*!< CLKGEN BLEBUCKTONADJ: TONADJUSTPERIOD (Bit 20) */ -#define CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Msk (0x300000UL) /*!< CLKGEN BLEBUCKTONADJ: TONADJUSTPERIOD (Bitfield-Mask: 0x03) */ -#define CLKGEN_BLEBUCKTONADJ_TONHIGHTHRESHOLD_Pos (10UL) /*!< CLKGEN BLEBUCKTONADJ: TONHIGHTHRESHOLD (Bit 10) */ -#define CLKGEN_BLEBUCKTONADJ_TONHIGHTHRESHOLD_Msk (0xffc00UL) /*!< CLKGEN BLEBUCKTONADJ: TONHIGHTHRESHOLD (Bitfield-Mask: 0x3ff) */ -#define CLKGEN_BLEBUCKTONADJ_TONLOWTHRESHOLD_Pos (0UL) /*!< CLKGEN BLEBUCKTONADJ: TONLOWTHRESHOLD (Bit 0) */ -#define CLKGEN_BLEBUCKTONADJ_TONLOWTHRESHOLD_Msk (0x3ffUL) /*!< CLKGEN BLEBUCKTONADJ: TONLOWTHRESHOLD (Bitfield-Mask: 0x3ff) */ -/* ======================================================= INTRPTEN ======================================================== */ -#define CLKGEN_INTRPTEN_OF_Pos (2UL) /*!< CLKGEN INTRPTEN: OF (Bit 2) */ -#define CLKGEN_INTRPTEN_OF_Msk (0x4UL) /*!< CLKGEN INTRPTEN: OF (Bitfield-Mask: 0x01) */ -#define CLKGEN_INTRPTEN_ACC_Pos (1UL) /*!< CLKGEN INTRPTEN: ACC (Bit 1) */ -#define CLKGEN_INTRPTEN_ACC_Msk (0x2UL) /*!< CLKGEN INTRPTEN: ACC (Bitfield-Mask: 0x01) */ -#define CLKGEN_INTRPTEN_ACF_Pos (0UL) /*!< CLKGEN INTRPTEN: ACF (Bit 0) */ -#define CLKGEN_INTRPTEN_ACF_Msk (0x1UL) /*!< CLKGEN INTRPTEN: ACF (Bitfield-Mask: 0x01) */ -/* ====================================================== INTRPTSTAT ======================================================= */ -#define CLKGEN_INTRPTSTAT_OF_Pos (2UL) /*!< CLKGEN INTRPTSTAT: OF (Bit 2) */ -#define CLKGEN_INTRPTSTAT_OF_Msk (0x4UL) /*!< CLKGEN INTRPTSTAT: OF (Bitfield-Mask: 0x01) */ -#define CLKGEN_INTRPTSTAT_ACC_Pos (1UL) /*!< CLKGEN INTRPTSTAT: ACC (Bit 1) */ -#define CLKGEN_INTRPTSTAT_ACC_Msk (0x2UL) /*!< CLKGEN INTRPTSTAT: ACC (Bitfield-Mask: 0x01) */ -#define CLKGEN_INTRPTSTAT_ACF_Pos (0UL) /*!< CLKGEN INTRPTSTAT: ACF (Bit 0) */ -#define CLKGEN_INTRPTSTAT_ACF_Msk (0x1UL) /*!< CLKGEN INTRPTSTAT: ACF (Bitfield-Mask: 0x01) */ -/* ======================================================= INTRPTCLR ======================================================= */ -#define CLKGEN_INTRPTCLR_OF_Pos (2UL) /*!< CLKGEN INTRPTCLR: OF (Bit 2) */ -#define CLKGEN_INTRPTCLR_OF_Msk (0x4UL) /*!< CLKGEN INTRPTCLR: OF (Bitfield-Mask: 0x01) */ -#define CLKGEN_INTRPTCLR_ACC_Pos (1UL) /*!< CLKGEN INTRPTCLR: ACC (Bit 1) */ -#define CLKGEN_INTRPTCLR_ACC_Msk (0x2UL) /*!< CLKGEN INTRPTCLR: ACC (Bitfield-Mask: 0x01) */ -#define CLKGEN_INTRPTCLR_ACF_Pos (0UL) /*!< CLKGEN INTRPTCLR: ACF (Bit 0) */ -#define CLKGEN_INTRPTCLR_ACF_Msk (0x1UL) /*!< CLKGEN INTRPTCLR: ACF (Bitfield-Mask: 0x01) */ -/* ======================================================= INTRPTSET ======================================================= */ -#define CLKGEN_INTRPTSET_OF_Pos (2UL) /*!< CLKGEN INTRPTSET: OF (Bit 2) */ -#define CLKGEN_INTRPTSET_OF_Msk (0x4UL) /*!< CLKGEN INTRPTSET: OF (Bitfield-Mask: 0x01) */ -#define CLKGEN_INTRPTSET_ACC_Pos (1UL) /*!< CLKGEN INTRPTSET: ACC (Bit 1) */ -#define CLKGEN_INTRPTSET_ACC_Msk (0x2UL) /*!< CLKGEN INTRPTSET: ACC (Bitfield-Mask: 0x01) */ -#define CLKGEN_INTRPTSET_ACF_Pos (0UL) /*!< CLKGEN INTRPTSET: ACF (Bit 0) */ -#define CLKGEN_INTRPTSET_ACF_Msk (0x1UL) /*!< CLKGEN INTRPTSET: ACF (Bitfield-Mask: 0x01) */ - - -/* =========================================================================================================================== */ -/* ================ CTIMER ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= TMR0 ========================================================== */ -#define CTIMER_TMR0_CTTMRB0_Pos (16UL) /*!< CTIMER TMR0: CTTMRB0 (Bit 16) */ -#define CTIMER_TMR0_CTTMRB0_Msk (0xffff0000UL) /*!< CTIMER TMR0: CTTMRB0 (Bitfield-Mask: 0xffff) */ -#define CTIMER_TMR0_CTTMRA0_Pos (0UL) /*!< CTIMER TMR0: CTTMRA0 (Bit 0) */ -#define CTIMER_TMR0_CTTMRA0_Msk (0xffffUL) /*!< CTIMER TMR0: CTTMRA0 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRA0 ========================================================= */ -#define CTIMER_CMPRA0_CMPR1A0_Pos (16UL) /*!< CTIMER CMPRA0: CMPR1A0 (Bit 16) */ -#define CTIMER_CMPRA0_CMPR1A0_Msk (0xffff0000UL) /*!< CTIMER CMPRA0: CMPR1A0 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRA0_CMPR0A0_Pos (0UL) /*!< CTIMER CMPRA0: CMPR0A0 (Bit 0) */ -#define CTIMER_CMPRA0_CMPR0A0_Msk (0xffffUL) /*!< CTIMER CMPRA0: CMPR0A0 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRB0 ========================================================= */ -#define CTIMER_CMPRB0_CMPR1B0_Pos (16UL) /*!< CTIMER CMPRB0: CMPR1B0 (Bit 16) */ -#define CTIMER_CMPRB0_CMPR1B0_Msk (0xffff0000UL) /*!< CTIMER CMPRB0: CMPR1B0 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRB0_CMPR0B0_Pos (0UL) /*!< CTIMER CMPRB0: CMPR0B0 (Bit 0) */ -#define CTIMER_CMPRB0_CMPR0B0_Msk (0xffffUL) /*!< CTIMER CMPRB0: CMPR0B0 (Bitfield-Mask: 0xffff) */ -/* ========================================================= CTRL0 ========================================================= */ -#define CTIMER_CTRL0_CTLINK0_Pos (31UL) /*!< CTIMER CTRL0: CTLINK0 (Bit 31) */ -#define CTIMER_CTRL0_CTLINK0_Msk (0x80000000UL) /*!< CTIMER CTRL0: CTLINK0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL0_TMRB0POL_Pos (28UL) /*!< CTIMER CTRL0: TMRB0POL (Bit 28) */ -#define CTIMER_CTRL0_TMRB0POL_Msk (0x10000000UL) /*!< CTIMER CTRL0: TMRB0POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL0_TMRB0CLR_Pos (27UL) /*!< CTIMER CTRL0: TMRB0CLR (Bit 27) */ -#define CTIMER_CTRL0_TMRB0CLR_Msk (0x8000000UL) /*!< CTIMER CTRL0: TMRB0CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL0_TMRB0IE1_Pos (26UL) /*!< CTIMER CTRL0: TMRB0IE1 (Bit 26) */ -#define CTIMER_CTRL0_TMRB0IE1_Msk (0x4000000UL) /*!< CTIMER CTRL0: TMRB0IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL0_TMRB0IE0_Pos (25UL) /*!< CTIMER CTRL0: TMRB0IE0 (Bit 25) */ -#define CTIMER_CTRL0_TMRB0IE0_Msk (0x2000000UL) /*!< CTIMER CTRL0: TMRB0IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL0_TMRB0FN_Pos (22UL) /*!< CTIMER CTRL0: TMRB0FN (Bit 22) */ -#define CTIMER_CTRL0_TMRB0FN_Msk (0x1c00000UL) /*!< CTIMER CTRL0: TMRB0FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL0_TMRB0CLK_Pos (17UL) /*!< CTIMER CTRL0: TMRB0CLK (Bit 17) */ -#define CTIMER_CTRL0_TMRB0CLK_Msk (0x3e0000UL) /*!< CTIMER CTRL0: TMRB0CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL0_TMRB0EN_Pos (16UL) /*!< CTIMER CTRL0: TMRB0EN (Bit 16) */ -#define CTIMER_CTRL0_TMRB0EN_Msk (0x10000UL) /*!< CTIMER CTRL0: TMRB0EN (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL0_TMRA0POL_Pos (12UL) /*!< CTIMER CTRL0: TMRA0POL (Bit 12) */ -#define CTIMER_CTRL0_TMRA0POL_Msk (0x1000UL) /*!< CTIMER CTRL0: TMRA0POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL0_TMRA0CLR_Pos (11UL) /*!< CTIMER CTRL0: TMRA0CLR (Bit 11) */ -#define CTIMER_CTRL0_TMRA0CLR_Msk (0x800UL) /*!< CTIMER CTRL0: TMRA0CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL0_TMRA0IE1_Pos (10UL) /*!< CTIMER CTRL0: TMRA0IE1 (Bit 10) */ -#define CTIMER_CTRL0_TMRA0IE1_Msk (0x400UL) /*!< CTIMER CTRL0: TMRA0IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL0_TMRA0IE0_Pos (9UL) /*!< CTIMER CTRL0: TMRA0IE0 (Bit 9) */ -#define CTIMER_CTRL0_TMRA0IE0_Msk (0x200UL) /*!< CTIMER CTRL0: TMRA0IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL0_TMRA0FN_Pos (6UL) /*!< CTIMER CTRL0: TMRA0FN (Bit 6) */ -#define CTIMER_CTRL0_TMRA0FN_Msk (0x1c0UL) /*!< CTIMER CTRL0: TMRA0FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL0_TMRA0CLK_Pos (1UL) /*!< CTIMER CTRL0: TMRA0CLK (Bit 1) */ -#define CTIMER_CTRL0_TMRA0CLK_Msk (0x3eUL) /*!< CTIMER CTRL0: TMRA0CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL0_TMRA0EN_Pos (0UL) /*!< CTIMER CTRL0: TMRA0EN (Bit 0) */ -#define CTIMER_CTRL0_TMRA0EN_Msk (0x1UL) /*!< CTIMER CTRL0: TMRA0EN (Bitfield-Mask: 0x01) */ -/* ======================================================= CMPRAUXA0 ======================================================= */ -#define CTIMER_CMPRAUXA0_CMPR3A0_Pos (16UL) /*!< CTIMER CMPRAUXA0: CMPR3A0 (Bit 16) */ -#define CTIMER_CMPRAUXA0_CMPR3A0_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXA0: CMPR3A0 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXA0_CMPR2A0_Pos (0UL) /*!< CTIMER CMPRAUXA0: CMPR2A0 (Bit 0) */ -#define CTIMER_CMPRAUXA0_CMPR2A0_Msk (0xffffUL) /*!< CTIMER CMPRAUXA0: CMPR2A0 (Bitfield-Mask: 0xffff) */ -/* ======================================================= CMPRAUXB0 ======================================================= */ -#define CTIMER_CMPRAUXB0_CMPR3B0_Pos (16UL) /*!< CTIMER CMPRAUXB0: CMPR3B0 (Bit 16) */ -#define CTIMER_CMPRAUXB0_CMPR3B0_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXB0: CMPR3B0 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXB0_CMPR2B0_Pos (0UL) /*!< CTIMER CMPRAUXB0: CMPR2B0 (Bit 0) */ -#define CTIMER_CMPRAUXB0_CMPR2B0_Msk (0xffffUL) /*!< CTIMER CMPRAUXB0: CMPR2B0 (Bitfield-Mask: 0xffff) */ -/* ========================================================= AUX0 ========================================================== */ -#define CTIMER_AUX0_TMRB0EN23_Pos (30UL) /*!< CTIMER AUX0: TMRB0EN23 (Bit 30) */ -#define CTIMER_AUX0_TMRB0EN23_Msk (0x40000000UL) /*!< CTIMER AUX0: TMRB0EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX0_TMRB0POL23_Pos (29UL) /*!< CTIMER AUX0: TMRB0POL23 (Bit 29) */ -#define CTIMER_AUX0_TMRB0POL23_Msk (0x20000000UL) /*!< CTIMER AUX0: TMRB0POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX0_TMRB0TINV_Pos (28UL) /*!< CTIMER AUX0: TMRB0TINV (Bit 28) */ -#define CTIMER_AUX0_TMRB0TINV_Msk (0x10000000UL) /*!< CTIMER AUX0: TMRB0TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX0_TMRB0NOSYNC_Pos (27UL) /*!< CTIMER AUX0: TMRB0NOSYNC (Bit 27) */ -#define CTIMER_AUX0_TMRB0NOSYNC_Msk (0x8000000UL) /*!< CTIMER AUX0: TMRB0NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX0_TMRB0TRIG_Pos (23UL) /*!< CTIMER AUX0: TMRB0TRIG (Bit 23) */ -#define CTIMER_AUX0_TMRB0TRIG_Msk (0x7800000UL) /*!< CTIMER AUX0: TMRB0TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX0_TMRB0LMT_Pos (16UL) /*!< CTIMER AUX0: TMRB0LMT (Bit 16) */ -#define CTIMER_AUX0_TMRB0LMT_Msk (0x3f0000UL) /*!< CTIMER AUX0: TMRB0LMT (Bitfield-Mask: 0x3f) */ -#define CTIMER_AUX0_TMRA0EN23_Pos (14UL) /*!< CTIMER AUX0: TMRA0EN23 (Bit 14) */ -#define CTIMER_AUX0_TMRA0EN23_Msk (0x4000UL) /*!< CTIMER AUX0: TMRA0EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX0_TMRA0POL23_Pos (13UL) /*!< CTIMER AUX0: TMRA0POL23 (Bit 13) */ -#define CTIMER_AUX0_TMRA0POL23_Msk (0x2000UL) /*!< CTIMER AUX0: TMRA0POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX0_TMRA0TINV_Pos (12UL) /*!< CTIMER AUX0: TMRA0TINV (Bit 12) */ -#define CTIMER_AUX0_TMRA0TINV_Msk (0x1000UL) /*!< CTIMER AUX0: TMRA0TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX0_TMRA0NOSYNC_Pos (11UL) /*!< CTIMER AUX0: TMRA0NOSYNC (Bit 11) */ -#define CTIMER_AUX0_TMRA0NOSYNC_Msk (0x800UL) /*!< CTIMER AUX0: TMRA0NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX0_TMRA0TRIG_Pos (7UL) /*!< CTIMER AUX0: TMRA0TRIG (Bit 7) */ -#define CTIMER_AUX0_TMRA0TRIG_Msk (0x780UL) /*!< CTIMER AUX0: TMRA0TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX0_TMRA0LMT_Pos (0UL) /*!< CTIMER AUX0: TMRA0LMT (Bit 0) */ -#define CTIMER_AUX0_TMRA0LMT_Msk (0x7fUL) /*!< CTIMER AUX0: TMRA0LMT (Bitfield-Mask: 0x7f) */ -/* ========================================================= TMR1 ========================================================== */ -#define CTIMER_TMR1_CTTMRB1_Pos (16UL) /*!< CTIMER TMR1: CTTMRB1 (Bit 16) */ -#define CTIMER_TMR1_CTTMRB1_Msk (0xffff0000UL) /*!< CTIMER TMR1: CTTMRB1 (Bitfield-Mask: 0xffff) */ -#define CTIMER_TMR1_CTTMRA1_Pos (0UL) /*!< CTIMER TMR1: CTTMRA1 (Bit 0) */ -#define CTIMER_TMR1_CTTMRA1_Msk (0xffffUL) /*!< CTIMER TMR1: CTTMRA1 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRA1 ========================================================= */ -#define CTIMER_CMPRA1_CMPR1A1_Pos (16UL) /*!< CTIMER CMPRA1: CMPR1A1 (Bit 16) */ -#define CTIMER_CMPRA1_CMPR1A1_Msk (0xffff0000UL) /*!< CTIMER CMPRA1: CMPR1A1 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRA1_CMPR0A1_Pos (0UL) /*!< CTIMER CMPRA1: CMPR0A1 (Bit 0) */ -#define CTIMER_CMPRA1_CMPR0A1_Msk (0xffffUL) /*!< CTIMER CMPRA1: CMPR0A1 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRB1 ========================================================= */ -#define CTIMER_CMPRB1_CMPR1B1_Pos (16UL) /*!< CTIMER CMPRB1: CMPR1B1 (Bit 16) */ -#define CTIMER_CMPRB1_CMPR1B1_Msk (0xffff0000UL) /*!< CTIMER CMPRB1: CMPR1B1 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRB1_CMPR0B1_Pos (0UL) /*!< CTIMER CMPRB1: CMPR0B1 (Bit 0) */ -#define CTIMER_CMPRB1_CMPR0B1_Msk (0xffffUL) /*!< CTIMER CMPRB1: CMPR0B1 (Bitfield-Mask: 0xffff) */ -/* ========================================================= CTRL1 ========================================================= */ -#define CTIMER_CTRL1_CTLINK1_Pos (31UL) /*!< CTIMER CTRL1: CTLINK1 (Bit 31) */ -#define CTIMER_CTRL1_CTLINK1_Msk (0x80000000UL) /*!< CTIMER CTRL1: CTLINK1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL1_TMRB1POL_Pos (28UL) /*!< CTIMER CTRL1: TMRB1POL (Bit 28) */ -#define CTIMER_CTRL1_TMRB1POL_Msk (0x10000000UL) /*!< CTIMER CTRL1: TMRB1POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL1_TMRB1CLR_Pos (27UL) /*!< CTIMER CTRL1: TMRB1CLR (Bit 27) */ -#define CTIMER_CTRL1_TMRB1CLR_Msk (0x8000000UL) /*!< CTIMER CTRL1: TMRB1CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL1_TMRB1IE1_Pos (26UL) /*!< CTIMER CTRL1: TMRB1IE1 (Bit 26) */ -#define CTIMER_CTRL1_TMRB1IE1_Msk (0x4000000UL) /*!< CTIMER CTRL1: TMRB1IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL1_TMRB1IE0_Pos (25UL) /*!< CTIMER CTRL1: TMRB1IE0 (Bit 25) */ -#define CTIMER_CTRL1_TMRB1IE0_Msk (0x2000000UL) /*!< CTIMER CTRL1: TMRB1IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL1_TMRB1FN_Pos (22UL) /*!< CTIMER CTRL1: TMRB1FN (Bit 22) */ -#define CTIMER_CTRL1_TMRB1FN_Msk (0x1c00000UL) /*!< CTIMER CTRL1: TMRB1FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL1_TMRB1CLK_Pos (17UL) /*!< CTIMER CTRL1: TMRB1CLK (Bit 17) */ -#define CTIMER_CTRL1_TMRB1CLK_Msk (0x3e0000UL) /*!< CTIMER CTRL1: TMRB1CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL1_TMRB1EN_Pos (16UL) /*!< CTIMER CTRL1: TMRB1EN (Bit 16) */ -#define CTIMER_CTRL1_TMRB1EN_Msk (0x10000UL) /*!< CTIMER CTRL1: TMRB1EN (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL1_TMRA1POL_Pos (12UL) /*!< CTIMER CTRL1: TMRA1POL (Bit 12) */ -#define CTIMER_CTRL1_TMRA1POL_Msk (0x1000UL) /*!< CTIMER CTRL1: TMRA1POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL1_TMRA1CLR_Pos (11UL) /*!< CTIMER CTRL1: TMRA1CLR (Bit 11) */ -#define CTIMER_CTRL1_TMRA1CLR_Msk (0x800UL) /*!< CTIMER CTRL1: TMRA1CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL1_TMRA1IE1_Pos (10UL) /*!< CTIMER CTRL1: TMRA1IE1 (Bit 10) */ -#define CTIMER_CTRL1_TMRA1IE1_Msk (0x400UL) /*!< CTIMER CTRL1: TMRA1IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL1_TMRA1IE0_Pos (9UL) /*!< CTIMER CTRL1: TMRA1IE0 (Bit 9) */ -#define CTIMER_CTRL1_TMRA1IE0_Msk (0x200UL) /*!< CTIMER CTRL1: TMRA1IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL1_TMRA1FN_Pos (6UL) /*!< CTIMER CTRL1: TMRA1FN (Bit 6) */ -#define CTIMER_CTRL1_TMRA1FN_Msk (0x1c0UL) /*!< CTIMER CTRL1: TMRA1FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL1_TMRA1CLK_Pos (1UL) /*!< CTIMER CTRL1: TMRA1CLK (Bit 1) */ -#define CTIMER_CTRL1_TMRA1CLK_Msk (0x3eUL) /*!< CTIMER CTRL1: TMRA1CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL1_TMRA1EN_Pos (0UL) /*!< CTIMER CTRL1: TMRA1EN (Bit 0) */ -#define CTIMER_CTRL1_TMRA1EN_Msk (0x1UL) /*!< CTIMER CTRL1: TMRA1EN (Bitfield-Mask: 0x01) */ -/* ======================================================= CMPRAUXA1 ======================================================= */ -#define CTIMER_CMPRAUXA1_CMPR3A1_Pos (16UL) /*!< CTIMER CMPRAUXA1: CMPR3A1 (Bit 16) */ -#define CTIMER_CMPRAUXA1_CMPR3A1_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXA1: CMPR3A1 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXA1_CMPR2A1_Pos (0UL) /*!< CTIMER CMPRAUXA1: CMPR2A1 (Bit 0) */ -#define CTIMER_CMPRAUXA1_CMPR2A1_Msk (0xffffUL) /*!< CTIMER CMPRAUXA1: CMPR2A1 (Bitfield-Mask: 0xffff) */ -/* ======================================================= CMPRAUXB1 ======================================================= */ -#define CTIMER_CMPRAUXB1_CMPR3B1_Pos (16UL) /*!< CTIMER CMPRAUXB1: CMPR3B1 (Bit 16) */ -#define CTIMER_CMPRAUXB1_CMPR3B1_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXB1: CMPR3B1 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXB1_CMPR2B1_Pos (0UL) /*!< CTIMER CMPRAUXB1: CMPR2B1 (Bit 0) */ -#define CTIMER_CMPRAUXB1_CMPR2B1_Msk (0xffffUL) /*!< CTIMER CMPRAUXB1: CMPR2B1 (Bitfield-Mask: 0xffff) */ -/* ========================================================= AUX1 ========================================================== */ -#define CTIMER_AUX1_TMRB1EN23_Pos (30UL) /*!< CTIMER AUX1: TMRB1EN23 (Bit 30) */ -#define CTIMER_AUX1_TMRB1EN23_Msk (0x40000000UL) /*!< CTIMER AUX1: TMRB1EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX1_TMRB1POL23_Pos (29UL) /*!< CTIMER AUX1: TMRB1POL23 (Bit 29) */ -#define CTIMER_AUX1_TMRB1POL23_Msk (0x20000000UL) /*!< CTIMER AUX1: TMRB1POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX1_TMRB1TINV_Pos (28UL) /*!< CTIMER AUX1: TMRB1TINV (Bit 28) */ -#define CTIMER_AUX1_TMRB1TINV_Msk (0x10000000UL) /*!< CTIMER AUX1: TMRB1TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX1_TMRB1NOSYNC_Pos (27UL) /*!< CTIMER AUX1: TMRB1NOSYNC (Bit 27) */ -#define CTIMER_AUX1_TMRB1NOSYNC_Msk (0x8000000UL) /*!< CTIMER AUX1: TMRB1NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX1_TMRB1TRIG_Pos (23UL) /*!< CTIMER AUX1: TMRB1TRIG (Bit 23) */ -#define CTIMER_AUX1_TMRB1TRIG_Msk (0x7800000UL) /*!< CTIMER AUX1: TMRB1TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX1_TMRB1LMT_Pos (16UL) /*!< CTIMER AUX1: TMRB1LMT (Bit 16) */ -#define CTIMER_AUX1_TMRB1LMT_Msk (0x3f0000UL) /*!< CTIMER AUX1: TMRB1LMT (Bitfield-Mask: 0x3f) */ -#define CTIMER_AUX1_TMRA1EN23_Pos (14UL) /*!< CTIMER AUX1: TMRA1EN23 (Bit 14) */ -#define CTIMER_AUX1_TMRA1EN23_Msk (0x4000UL) /*!< CTIMER AUX1: TMRA1EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX1_TMRA1POL23_Pos (13UL) /*!< CTIMER AUX1: TMRA1POL23 (Bit 13) */ -#define CTIMER_AUX1_TMRA1POL23_Msk (0x2000UL) /*!< CTIMER AUX1: TMRA1POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX1_TMRA1TINV_Pos (12UL) /*!< CTIMER AUX1: TMRA1TINV (Bit 12) */ -#define CTIMER_AUX1_TMRA1TINV_Msk (0x1000UL) /*!< CTIMER AUX1: TMRA1TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX1_TMRA1NOSYNC_Pos (11UL) /*!< CTIMER AUX1: TMRA1NOSYNC (Bit 11) */ -#define CTIMER_AUX1_TMRA1NOSYNC_Msk (0x800UL) /*!< CTIMER AUX1: TMRA1NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX1_TMRA1TRIG_Pos (7UL) /*!< CTIMER AUX1: TMRA1TRIG (Bit 7) */ -#define CTIMER_AUX1_TMRA1TRIG_Msk (0x780UL) /*!< CTIMER AUX1: TMRA1TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX1_TMRA1LMT_Pos (0UL) /*!< CTIMER AUX1: TMRA1LMT (Bit 0) */ -#define CTIMER_AUX1_TMRA1LMT_Msk (0x7fUL) /*!< CTIMER AUX1: TMRA1LMT (Bitfield-Mask: 0x7f) */ -/* ========================================================= TMR2 ========================================================== */ -#define CTIMER_TMR2_CTTMRB2_Pos (16UL) /*!< CTIMER TMR2: CTTMRB2 (Bit 16) */ -#define CTIMER_TMR2_CTTMRB2_Msk (0xffff0000UL) /*!< CTIMER TMR2: CTTMRB2 (Bitfield-Mask: 0xffff) */ -#define CTIMER_TMR2_CTTMRA2_Pos (0UL) /*!< CTIMER TMR2: CTTMRA2 (Bit 0) */ -#define CTIMER_TMR2_CTTMRA2_Msk (0xffffUL) /*!< CTIMER TMR2: CTTMRA2 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRA2 ========================================================= */ -#define CTIMER_CMPRA2_CMPR1A2_Pos (16UL) /*!< CTIMER CMPRA2: CMPR1A2 (Bit 16) */ -#define CTIMER_CMPRA2_CMPR1A2_Msk (0xffff0000UL) /*!< CTIMER CMPRA2: CMPR1A2 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRA2_CMPR0A2_Pos (0UL) /*!< CTIMER CMPRA2: CMPR0A2 (Bit 0) */ -#define CTIMER_CMPRA2_CMPR0A2_Msk (0xffffUL) /*!< CTIMER CMPRA2: CMPR0A2 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRB2 ========================================================= */ -#define CTIMER_CMPRB2_CMPR1B2_Pos (16UL) /*!< CTIMER CMPRB2: CMPR1B2 (Bit 16) */ -#define CTIMER_CMPRB2_CMPR1B2_Msk (0xffff0000UL) /*!< CTIMER CMPRB2: CMPR1B2 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRB2_CMPR0B2_Pos (0UL) /*!< CTIMER CMPRB2: CMPR0B2 (Bit 0) */ -#define CTIMER_CMPRB2_CMPR0B2_Msk (0xffffUL) /*!< CTIMER CMPRB2: CMPR0B2 (Bitfield-Mask: 0xffff) */ -/* ========================================================= CTRL2 ========================================================= */ -#define CTIMER_CTRL2_CTLINK2_Pos (31UL) /*!< CTIMER CTRL2: CTLINK2 (Bit 31) */ -#define CTIMER_CTRL2_CTLINK2_Msk (0x80000000UL) /*!< CTIMER CTRL2: CTLINK2 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL2_TMRB2POL_Pos (28UL) /*!< CTIMER CTRL2: TMRB2POL (Bit 28) */ -#define CTIMER_CTRL2_TMRB2POL_Msk (0x10000000UL) /*!< CTIMER CTRL2: TMRB2POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL2_TMRB2CLR_Pos (27UL) /*!< CTIMER CTRL2: TMRB2CLR (Bit 27) */ -#define CTIMER_CTRL2_TMRB2CLR_Msk (0x8000000UL) /*!< CTIMER CTRL2: TMRB2CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL2_TMRB2IE1_Pos (26UL) /*!< CTIMER CTRL2: TMRB2IE1 (Bit 26) */ -#define CTIMER_CTRL2_TMRB2IE1_Msk (0x4000000UL) /*!< CTIMER CTRL2: TMRB2IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL2_TMRB2IE0_Pos (25UL) /*!< CTIMER CTRL2: TMRB2IE0 (Bit 25) */ -#define CTIMER_CTRL2_TMRB2IE0_Msk (0x2000000UL) /*!< CTIMER CTRL2: TMRB2IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL2_TMRB2FN_Pos (22UL) /*!< CTIMER CTRL2: TMRB2FN (Bit 22) */ -#define CTIMER_CTRL2_TMRB2FN_Msk (0x1c00000UL) /*!< CTIMER CTRL2: TMRB2FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL2_TMRB2CLK_Pos (17UL) /*!< CTIMER CTRL2: TMRB2CLK (Bit 17) */ -#define CTIMER_CTRL2_TMRB2CLK_Msk (0x3e0000UL) /*!< CTIMER CTRL2: TMRB2CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL2_TMRB2EN_Pos (16UL) /*!< CTIMER CTRL2: TMRB2EN (Bit 16) */ -#define CTIMER_CTRL2_TMRB2EN_Msk (0x10000UL) /*!< CTIMER CTRL2: TMRB2EN (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL2_TMRA2POL_Pos (12UL) /*!< CTIMER CTRL2: TMRA2POL (Bit 12) */ -#define CTIMER_CTRL2_TMRA2POL_Msk (0x1000UL) /*!< CTIMER CTRL2: TMRA2POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL2_TMRA2CLR_Pos (11UL) /*!< CTIMER CTRL2: TMRA2CLR (Bit 11) */ -#define CTIMER_CTRL2_TMRA2CLR_Msk (0x800UL) /*!< CTIMER CTRL2: TMRA2CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL2_TMRA2IE1_Pos (10UL) /*!< CTIMER CTRL2: TMRA2IE1 (Bit 10) */ -#define CTIMER_CTRL2_TMRA2IE1_Msk (0x400UL) /*!< CTIMER CTRL2: TMRA2IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL2_TMRA2IE0_Pos (9UL) /*!< CTIMER CTRL2: TMRA2IE0 (Bit 9) */ -#define CTIMER_CTRL2_TMRA2IE0_Msk (0x200UL) /*!< CTIMER CTRL2: TMRA2IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL2_TMRA2FN_Pos (6UL) /*!< CTIMER CTRL2: TMRA2FN (Bit 6) */ -#define CTIMER_CTRL2_TMRA2FN_Msk (0x1c0UL) /*!< CTIMER CTRL2: TMRA2FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL2_TMRA2CLK_Pos (1UL) /*!< CTIMER CTRL2: TMRA2CLK (Bit 1) */ -#define CTIMER_CTRL2_TMRA2CLK_Msk (0x3eUL) /*!< CTIMER CTRL2: TMRA2CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL2_TMRA2EN_Pos (0UL) /*!< CTIMER CTRL2: TMRA2EN (Bit 0) */ -#define CTIMER_CTRL2_TMRA2EN_Msk (0x1UL) /*!< CTIMER CTRL2: TMRA2EN (Bitfield-Mask: 0x01) */ -/* ======================================================= CMPRAUXA2 ======================================================= */ -#define CTIMER_CMPRAUXA2_CMPR3A2_Pos (16UL) /*!< CTIMER CMPRAUXA2: CMPR3A2 (Bit 16) */ -#define CTIMER_CMPRAUXA2_CMPR3A2_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXA2: CMPR3A2 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXA2_CMPR2A2_Pos (0UL) /*!< CTIMER CMPRAUXA2: CMPR2A2 (Bit 0) */ -#define CTIMER_CMPRAUXA2_CMPR2A2_Msk (0xffffUL) /*!< CTIMER CMPRAUXA2: CMPR2A2 (Bitfield-Mask: 0xffff) */ -/* ======================================================= CMPRAUXB2 ======================================================= */ -#define CTIMER_CMPRAUXB2_CMPR3B2_Pos (16UL) /*!< CTIMER CMPRAUXB2: CMPR3B2 (Bit 16) */ -#define CTIMER_CMPRAUXB2_CMPR3B2_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXB2: CMPR3B2 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXB2_CMPR2B2_Pos (0UL) /*!< CTIMER CMPRAUXB2: CMPR2B2 (Bit 0) */ -#define CTIMER_CMPRAUXB2_CMPR2B2_Msk (0xffffUL) /*!< CTIMER CMPRAUXB2: CMPR2B2 (Bitfield-Mask: 0xffff) */ -/* ========================================================= AUX2 ========================================================== */ -#define CTIMER_AUX2_TMRB2EN23_Pos (30UL) /*!< CTIMER AUX2: TMRB2EN23 (Bit 30) */ -#define CTIMER_AUX2_TMRB2EN23_Msk (0x40000000UL) /*!< CTIMER AUX2: TMRB2EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX2_TMRB2POL23_Pos (29UL) /*!< CTIMER AUX2: TMRB2POL23 (Bit 29) */ -#define CTIMER_AUX2_TMRB2POL23_Msk (0x20000000UL) /*!< CTIMER AUX2: TMRB2POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX2_TMRB2TINV_Pos (28UL) /*!< CTIMER AUX2: TMRB2TINV (Bit 28) */ -#define CTIMER_AUX2_TMRB2TINV_Msk (0x10000000UL) /*!< CTIMER AUX2: TMRB2TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX2_TMRB2NOSYNC_Pos (27UL) /*!< CTIMER AUX2: TMRB2NOSYNC (Bit 27) */ -#define CTIMER_AUX2_TMRB2NOSYNC_Msk (0x8000000UL) /*!< CTIMER AUX2: TMRB2NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX2_TMRB2TRIG_Pos (23UL) /*!< CTIMER AUX2: TMRB2TRIG (Bit 23) */ -#define CTIMER_AUX2_TMRB2TRIG_Msk (0x7800000UL) /*!< CTIMER AUX2: TMRB2TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX2_TMRB2LMT_Pos (16UL) /*!< CTIMER AUX2: TMRB2LMT (Bit 16) */ -#define CTIMER_AUX2_TMRB2LMT_Msk (0x3f0000UL) /*!< CTIMER AUX2: TMRB2LMT (Bitfield-Mask: 0x3f) */ -#define CTIMER_AUX2_TMRA2EN23_Pos (14UL) /*!< CTIMER AUX2: TMRA2EN23 (Bit 14) */ -#define CTIMER_AUX2_TMRA2EN23_Msk (0x4000UL) /*!< CTIMER AUX2: TMRA2EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX2_TMRA2POL23_Pos (13UL) /*!< CTIMER AUX2: TMRA2POL23 (Bit 13) */ -#define CTIMER_AUX2_TMRA2POL23_Msk (0x2000UL) /*!< CTIMER AUX2: TMRA2POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX2_TMRA2TINV_Pos (12UL) /*!< CTIMER AUX2: TMRA2TINV (Bit 12) */ -#define CTIMER_AUX2_TMRA2TINV_Msk (0x1000UL) /*!< CTIMER AUX2: TMRA2TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX2_TMRA2NOSYNC_Pos (11UL) /*!< CTIMER AUX2: TMRA2NOSYNC (Bit 11) */ -#define CTIMER_AUX2_TMRA2NOSYNC_Msk (0x800UL) /*!< CTIMER AUX2: TMRA2NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX2_TMRA2TRIG_Pos (7UL) /*!< CTIMER AUX2: TMRA2TRIG (Bit 7) */ -#define CTIMER_AUX2_TMRA2TRIG_Msk (0x780UL) /*!< CTIMER AUX2: TMRA2TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX2_TMRA2LMT_Pos (0UL) /*!< CTIMER AUX2: TMRA2LMT (Bit 0) */ -#define CTIMER_AUX2_TMRA2LMT_Msk (0x7fUL) /*!< CTIMER AUX2: TMRA2LMT (Bitfield-Mask: 0x7f) */ -/* ========================================================= TMR3 ========================================================== */ -#define CTIMER_TMR3_CTTMRB3_Pos (16UL) /*!< CTIMER TMR3: CTTMRB3 (Bit 16) */ -#define CTIMER_TMR3_CTTMRB3_Msk (0xffff0000UL) /*!< CTIMER TMR3: CTTMRB3 (Bitfield-Mask: 0xffff) */ -#define CTIMER_TMR3_CTTMRA3_Pos (0UL) /*!< CTIMER TMR3: CTTMRA3 (Bit 0) */ -#define CTIMER_TMR3_CTTMRA3_Msk (0xffffUL) /*!< CTIMER TMR3: CTTMRA3 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRA3 ========================================================= */ -#define CTIMER_CMPRA3_CMPR1A3_Pos (16UL) /*!< CTIMER CMPRA3: CMPR1A3 (Bit 16) */ -#define CTIMER_CMPRA3_CMPR1A3_Msk (0xffff0000UL) /*!< CTIMER CMPRA3: CMPR1A3 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRA3_CMPR0A3_Pos (0UL) /*!< CTIMER CMPRA3: CMPR0A3 (Bit 0) */ -#define CTIMER_CMPRA3_CMPR0A3_Msk (0xffffUL) /*!< CTIMER CMPRA3: CMPR0A3 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRB3 ========================================================= */ -#define CTIMER_CMPRB3_CMPR1B3_Pos (16UL) /*!< CTIMER CMPRB3: CMPR1B3 (Bit 16) */ -#define CTIMER_CMPRB3_CMPR1B3_Msk (0xffff0000UL) /*!< CTIMER CMPRB3: CMPR1B3 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRB3_CMPR0B3_Pos (0UL) /*!< CTIMER CMPRB3: CMPR0B3 (Bit 0) */ -#define CTIMER_CMPRB3_CMPR0B3_Msk (0xffffUL) /*!< CTIMER CMPRB3: CMPR0B3 (Bitfield-Mask: 0xffff) */ -/* ========================================================= CTRL3 ========================================================= */ -#define CTIMER_CTRL3_CTLINK3_Pos (31UL) /*!< CTIMER CTRL3: CTLINK3 (Bit 31) */ -#define CTIMER_CTRL3_CTLINK3_Msk (0x80000000UL) /*!< CTIMER CTRL3: CTLINK3 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL3_TMRB3POL_Pos (28UL) /*!< CTIMER CTRL3: TMRB3POL (Bit 28) */ -#define CTIMER_CTRL3_TMRB3POL_Msk (0x10000000UL) /*!< CTIMER CTRL3: TMRB3POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL3_TMRB3CLR_Pos (27UL) /*!< CTIMER CTRL3: TMRB3CLR (Bit 27) */ -#define CTIMER_CTRL3_TMRB3CLR_Msk (0x8000000UL) /*!< CTIMER CTRL3: TMRB3CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL3_TMRB3IE1_Pos (26UL) /*!< CTIMER CTRL3: TMRB3IE1 (Bit 26) */ -#define CTIMER_CTRL3_TMRB3IE1_Msk (0x4000000UL) /*!< CTIMER CTRL3: TMRB3IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL3_TMRB3IE0_Pos (25UL) /*!< CTIMER CTRL3: TMRB3IE0 (Bit 25) */ -#define CTIMER_CTRL3_TMRB3IE0_Msk (0x2000000UL) /*!< CTIMER CTRL3: TMRB3IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL3_TMRB3FN_Pos (22UL) /*!< CTIMER CTRL3: TMRB3FN (Bit 22) */ -#define CTIMER_CTRL3_TMRB3FN_Msk (0x1c00000UL) /*!< CTIMER CTRL3: TMRB3FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL3_TMRB3CLK_Pos (17UL) /*!< CTIMER CTRL3: TMRB3CLK (Bit 17) */ -#define CTIMER_CTRL3_TMRB3CLK_Msk (0x3e0000UL) /*!< CTIMER CTRL3: TMRB3CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL3_TMRB3EN_Pos (16UL) /*!< CTIMER CTRL3: TMRB3EN (Bit 16) */ -#define CTIMER_CTRL3_TMRB3EN_Msk (0x10000UL) /*!< CTIMER CTRL3: TMRB3EN (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL3_ADCEN_Pos (15UL) /*!< CTIMER CTRL3: ADCEN (Bit 15) */ -#define CTIMER_CTRL3_ADCEN_Msk (0x8000UL) /*!< CTIMER CTRL3: ADCEN (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL3_TMRA3POL_Pos (12UL) /*!< CTIMER CTRL3: TMRA3POL (Bit 12) */ -#define CTIMER_CTRL3_TMRA3POL_Msk (0x1000UL) /*!< CTIMER CTRL3: TMRA3POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL3_TMRA3CLR_Pos (11UL) /*!< CTIMER CTRL3: TMRA3CLR (Bit 11) */ -#define CTIMER_CTRL3_TMRA3CLR_Msk (0x800UL) /*!< CTIMER CTRL3: TMRA3CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL3_TMRA3IE1_Pos (10UL) /*!< CTIMER CTRL3: TMRA3IE1 (Bit 10) */ -#define CTIMER_CTRL3_TMRA3IE1_Msk (0x400UL) /*!< CTIMER CTRL3: TMRA3IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL3_TMRA3IE0_Pos (9UL) /*!< CTIMER CTRL3: TMRA3IE0 (Bit 9) */ -#define CTIMER_CTRL3_TMRA3IE0_Msk (0x200UL) /*!< CTIMER CTRL3: TMRA3IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL3_TMRA3FN_Pos (6UL) /*!< CTIMER CTRL3: TMRA3FN (Bit 6) */ -#define CTIMER_CTRL3_TMRA3FN_Msk (0x1c0UL) /*!< CTIMER CTRL3: TMRA3FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL3_TMRA3CLK_Pos (1UL) /*!< CTIMER CTRL3: TMRA3CLK (Bit 1) */ -#define CTIMER_CTRL3_TMRA3CLK_Msk (0x3eUL) /*!< CTIMER CTRL3: TMRA3CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL3_TMRA3EN_Pos (0UL) /*!< CTIMER CTRL3: TMRA3EN (Bit 0) */ -#define CTIMER_CTRL3_TMRA3EN_Msk (0x1UL) /*!< CTIMER CTRL3: TMRA3EN (Bitfield-Mask: 0x01) */ -/* ======================================================= CMPRAUXA3 ======================================================= */ -#define CTIMER_CMPRAUXA3_CMPR3A3_Pos (16UL) /*!< CTIMER CMPRAUXA3: CMPR3A3 (Bit 16) */ -#define CTIMER_CMPRAUXA3_CMPR3A3_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXA3: CMPR3A3 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXA3_CMPR2A3_Pos (0UL) /*!< CTIMER CMPRAUXA3: CMPR2A3 (Bit 0) */ -#define CTIMER_CMPRAUXA3_CMPR2A3_Msk (0xffffUL) /*!< CTIMER CMPRAUXA3: CMPR2A3 (Bitfield-Mask: 0xffff) */ -/* ======================================================= CMPRAUXB3 ======================================================= */ -#define CTIMER_CMPRAUXB3_CMPR3B3_Pos (16UL) /*!< CTIMER CMPRAUXB3: CMPR3B3 (Bit 16) */ -#define CTIMER_CMPRAUXB3_CMPR3B3_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXB3: CMPR3B3 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXB3_CMPR2B3_Pos (0UL) /*!< CTIMER CMPRAUXB3: CMPR2B3 (Bit 0) */ -#define CTIMER_CMPRAUXB3_CMPR2B3_Msk (0xffffUL) /*!< CTIMER CMPRAUXB3: CMPR2B3 (Bitfield-Mask: 0xffff) */ -/* ========================================================= AUX3 ========================================================== */ -#define CTIMER_AUX3_TMRB3EN23_Pos (30UL) /*!< CTIMER AUX3: TMRB3EN23 (Bit 30) */ -#define CTIMER_AUX3_TMRB3EN23_Msk (0x40000000UL) /*!< CTIMER AUX3: TMRB3EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX3_TMRB3POL23_Pos (29UL) /*!< CTIMER AUX3: TMRB3POL23 (Bit 29) */ -#define CTIMER_AUX3_TMRB3POL23_Msk (0x20000000UL) /*!< CTIMER AUX3: TMRB3POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX3_TMRB3TINV_Pos (28UL) /*!< CTIMER AUX3: TMRB3TINV (Bit 28) */ -#define CTIMER_AUX3_TMRB3TINV_Msk (0x10000000UL) /*!< CTIMER AUX3: TMRB3TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX3_TMRB3NOSYNC_Pos (27UL) /*!< CTIMER AUX3: TMRB3NOSYNC (Bit 27) */ -#define CTIMER_AUX3_TMRB3NOSYNC_Msk (0x8000000UL) /*!< CTIMER AUX3: TMRB3NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX3_TMRB3TRIG_Pos (23UL) /*!< CTIMER AUX3: TMRB3TRIG (Bit 23) */ -#define CTIMER_AUX3_TMRB3TRIG_Msk (0x7800000UL) /*!< CTIMER AUX3: TMRB3TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX3_TMRB3LMT_Pos (16UL) /*!< CTIMER AUX3: TMRB3LMT (Bit 16) */ -#define CTIMER_AUX3_TMRB3LMT_Msk (0x3f0000UL) /*!< CTIMER AUX3: TMRB3LMT (Bitfield-Mask: 0x3f) */ -#define CTIMER_AUX3_TMRA3EN23_Pos (14UL) /*!< CTIMER AUX3: TMRA3EN23 (Bit 14) */ -#define CTIMER_AUX3_TMRA3EN23_Msk (0x4000UL) /*!< CTIMER AUX3: TMRA3EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX3_TMRA3POL23_Pos (13UL) /*!< CTIMER AUX3: TMRA3POL23 (Bit 13) */ -#define CTIMER_AUX3_TMRA3POL23_Msk (0x2000UL) /*!< CTIMER AUX3: TMRA3POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX3_TMRA3TINV_Pos (12UL) /*!< CTIMER AUX3: TMRA3TINV (Bit 12) */ -#define CTIMER_AUX3_TMRA3TINV_Msk (0x1000UL) /*!< CTIMER AUX3: TMRA3TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX3_TMRA3NOSYNC_Pos (11UL) /*!< CTIMER AUX3: TMRA3NOSYNC (Bit 11) */ -#define CTIMER_AUX3_TMRA3NOSYNC_Msk (0x800UL) /*!< CTIMER AUX3: TMRA3NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX3_TMRA3TRIG_Pos (7UL) /*!< CTIMER AUX3: TMRA3TRIG (Bit 7) */ -#define CTIMER_AUX3_TMRA3TRIG_Msk (0x780UL) /*!< CTIMER AUX3: TMRA3TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX3_TMRA3LMT_Pos (0UL) /*!< CTIMER AUX3: TMRA3LMT (Bit 0) */ -#define CTIMER_AUX3_TMRA3LMT_Msk (0x7fUL) /*!< CTIMER AUX3: TMRA3LMT (Bitfield-Mask: 0x7f) */ -/* ========================================================= TMR4 ========================================================== */ -#define CTIMER_TMR4_CTTMRB4_Pos (16UL) /*!< CTIMER TMR4: CTTMRB4 (Bit 16) */ -#define CTIMER_TMR4_CTTMRB4_Msk (0xffff0000UL) /*!< CTIMER TMR4: CTTMRB4 (Bitfield-Mask: 0xffff) */ -#define CTIMER_TMR4_CTTMRA4_Pos (0UL) /*!< CTIMER TMR4: CTTMRA4 (Bit 0) */ -#define CTIMER_TMR4_CTTMRA4_Msk (0xffffUL) /*!< CTIMER TMR4: CTTMRA4 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRA4 ========================================================= */ -#define CTIMER_CMPRA4_CMPR1A4_Pos (16UL) /*!< CTIMER CMPRA4: CMPR1A4 (Bit 16) */ -#define CTIMER_CMPRA4_CMPR1A4_Msk (0xffff0000UL) /*!< CTIMER CMPRA4: CMPR1A4 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRA4_CMPR0A4_Pos (0UL) /*!< CTIMER CMPRA4: CMPR0A4 (Bit 0) */ -#define CTIMER_CMPRA4_CMPR0A4_Msk (0xffffUL) /*!< CTIMER CMPRA4: CMPR0A4 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRB4 ========================================================= */ -#define CTIMER_CMPRB4_CMPR1B4_Pos (16UL) /*!< CTIMER CMPRB4: CMPR1B4 (Bit 16) */ -#define CTIMER_CMPRB4_CMPR1B4_Msk (0xffff0000UL) /*!< CTIMER CMPRB4: CMPR1B4 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRB4_CMPR0B4_Pos (0UL) /*!< CTIMER CMPRB4: CMPR0B4 (Bit 0) */ -#define CTIMER_CMPRB4_CMPR0B4_Msk (0xffffUL) /*!< CTIMER CMPRB4: CMPR0B4 (Bitfield-Mask: 0xffff) */ -/* ========================================================= CTRL4 ========================================================= */ -#define CTIMER_CTRL4_CTLINK4_Pos (31UL) /*!< CTIMER CTRL4: CTLINK4 (Bit 31) */ -#define CTIMER_CTRL4_CTLINK4_Msk (0x80000000UL) /*!< CTIMER CTRL4: CTLINK4 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL4_TMRB4POL_Pos (28UL) /*!< CTIMER CTRL4: TMRB4POL (Bit 28) */ -#define CTIMER_CTRL4_TMRB4POL_Msk (0x10000000UL) /*!< CTIMER CTRL4: TMRB4POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL4_TMRB4CLR_Pos (27UL) /*!< CTIMER CTRL4: TMRB4CLR (Bit 27) */ -#define CTIMER_CTRL4_TMRB4CLR_Msk (0x8000000UL) /*!< CTIMER CTRL4: TMRB4CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL4_TMRB4IE1_Pos (26UL) /*!< CTIMER CTRL4: TMRB4IE1 (Bit 26) */ -#define CTIMER_CTRL4_TMRB4IE1_Msk (0x4000000UL) /*!< CTIMER CTRL4: TMRB4IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL4_TMRB4IE0_Pos (25UL) /*!< CTIMER CTRL4: TMRB4IE0 (Bit 25) */ -#define CTIMER_CTRL4_TMRB4IE0_Msk (0x2000000UL) /*!< CTIMER CTRL4: TMRB4IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL4_TMRB4FN_Pos (22UL) /*!< CTIMER CTRL4: TMRB4FN (Bit 22) */ -#define CTIMER_CTRL4_TMRB4FN_Msk (0x1c00000UL) /*!< CTIMER CTRL4: TMRB4FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL4_TMRB4CLK_Pos (17UL) /*!< CTIMER CTRL4: TMRB4CLK (Bit 17) */ -#define CTIMER_CTRL4_TMRB4CLK_Msk (0x3e0000UL) /*!< CTIMER CTRL4: TMRB4CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL4_TMRB4EN_Pos (16UL) /*!< CTIMER CTRL4: TMRB4EN (Bit 16) */ -#define CTIMER_CTRL4_TMRB4EN_Msk (0x10000UL) /*!< CTIMER CTRL4: TMRB4EN (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL4_TMRA4POL_Pos (12UL) /*!< CTIMER CTRL4: TMRA4POL (Bit 12) */ -#define CTIMER_CTRL4_TMRA4POL_Msk (0x1000UL) /*!< CTIMER CTRL4: TMRA4POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL4_TMRA4CLR_Pos (11UL) /*!< CTIMER CTRL4: TMRA4CLR (Bit 11) */ -#define CTIMER_CTRL4_TMRA4CLR_Msk (0x800UL) /*!< CTIMER CTRL4: TMRA4CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL4_TMRA4IE1_Pos (10UL) /*!< CTIMER CTRL4: TMRA4IE1 (Bit 10) */ -#define CTIMER_CTRL4_TMRA4IE1_Msk (0x400UL) /*!< CTIMER CTRL4: TMRA4IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL4_TMRA4IE0_Pos (9UL) /*!< CTIMER CTRL4: TMRA4IE0 (Bit 9) */ -#define CTIMER_CTRL4_TMRA4IE0_Msk (0x200UL) /*!< CTIMER CTRL4: TMRA4IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL4_TMRA4FN_Pos (6UL) /*!< CTIMER CTRL4: TMRA4FN (Bit 6) */ -#define CTIMER_CTRL4_TMRA4FN_Msk (0x1c0UL) /*!< CTIMER CTRL4: TMRA4FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL4_TMRA4CLK_Pos (1UL) /*!< CTIMER CTRL4: TMRA4CLK (Bit 1) */ -#define CTIMER_CTRL4_TMRA4CLK_Msk (0x3eUL) /*!< CTIMER CTRL4: TMRA4CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL4_TMRA4EN_Pos (0UL) /*!< CTIMER CTRL4: TMRA4EN (Bit 0) */ -#define CTIMER_CTRL4_TMRA4EN_Msk (0x1UL) /*!< CTIMER CTRL4: TMRA4EN (Bitfield-Mask: 0x01) */ -/* ======================================================= CMPRAUXA4 ======================================================= */ -#define CTIMER_CMPRAUXA4_CMPR3A4_Pos (16UL) /*!< CTIMER CMPRAUXA4: CMPR3A4 (Bit 16) */ -#define CTIMER_CMPRAUXA4_CMPR3A4_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXA4: CMPR3A4 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXA4_CMPR2A4_Pos (0UL) /*!< CTIMER CMPRAUXA4: CMPR2A4 (Bit 0) */ -#define CTIMER_CMPRAUXA4_CMPR2A4_Msk (0xffffUL) /*!< CTIMER CMPRAUXA4: CMPR2A4 (Bitfield-Mask: 0xffff) */ -/* ======================================================= CMPRAUXB4 ======================================================= */ -#define CTIMER_CMPRAUXB4_CMPR3B4_Pos (16UL) /*!< CTIMER CMPRAUXB4: CMPR3B4 (Bit 16) */ -#define CTIMER_CMPRAUXB4_CMPR3B4_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXB4: CMPR3B4 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXB4_CMPR2B4_Pos (0UL) /*!< CTIMER CMPRAUXB4: CMPR2B4 (Bit 0) */ -#define CTIMER_CMPRAUXB4_CMPR2B4_Msk (0xffffUL) /*!< CTIMER CMPRAUXB4: CMPR2B4 (Bitfield-Mask: 0xffff) */ -/* ========================================================= AUX4 ========================================================== */ -#define CTIMER_AUX4_TMRB4EN23_Pos (30UL) /*!< CTIMER AUX4: TMRB4EN23 (Bit 30) */ -#define CTIMER_AUX4_TMRB4EN23_Msk (0x40000000UL) /*!< CTIMER AUX4: TMRB4EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX4_TMRB4POL23_Pos (29UL) /*!< CTIMER AUX4: TMRB4POL23 (Bit 29) */ -#define CTIMER_AUX4_TMRB4POL23_Msk (0x20000000UL) /*!< CTIMER AUX4: TMRB4POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX4_TMRB4TINV_Pos (28UL) /*!< CTIMER AUX4: TMRB4TINV (Bit 28) */ -#define CTIMER_AUX4_TMRB4TINV_Msk (0x10000000UL) /*!< CTIMER AUX4: TMRB4TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX4_TMRB4NOSYNC_Pos (27UL) /*!< CTIMER AUX4: TMRB4NOSYNC (Bit 27) */ -#define CTIMER_AUX4_TMRB4NOSYNC_Msk (0x8000000UL) /*!< CTIMER AUX4: TMRB4NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX4_TMRB4TRIG_Pos (23UL) /*!< CTIMER AUX4: TMRB4TRIG (Bit 23) */ -#define CTIMER_AUX4_TMRB4TRIG_Msk (0x7800000UL) /*!< CTIMER AUX4: TMRB4TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX4_TMRB4LMT_Pos (16UL) /*!< CTIMER AUX4: TMRB4LMT (Bit 16) */ -#define CTIMER_AUX4_TMRB4LMT_Msk (0x3f0000UL) /*!< CTIMER AUX4: TMRB4LMT (Bitfield-Mask: 0x3f) */ -#define CTIMER_AUX4_TMRA4EN23_Pos (14UL) /*!< CTIMER AUX4: TMRA4EN23 (Bit 14) */ -#define CTIMER_AUX4_TMRA4EN23_Msk (0x4000UL) /*!< CTIMER AUX4: TMRA4EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX4_TMRA4POL23_Pos (13UL) /*!< CTIMER AUX4: TMRA4POL23 (Bit 13) */ -#define CTIMER_AUX4_TMRA4POL23_Msk (0x2000UL) /*!< CTIMER AUX4: TMRA4POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX4_TMRA4TINV_Pos (12UL) /*!< CTIMER AUX4: TMRA4TINV (Bit 12) */ -#define CTIMER_AUX4_TMRA4TINV_Msk (0x1000UL) /*!< CTIMER AUX4: TMRA4TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX4_TMRA4NOSYNC_Pos (11UL) /*!< CTIMER AUX4: TMRA4NOSYNC (Bit 11) */ -#define CTIMER_AUX4_TMRA4NOSYNC_Msk (0x800UL) /*!< CTIMER AUX4: TMRA4NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX4_TMRA4TRIG_Pos (7UL) /*!< CTIMER AUX4: TMRA4TRIG (Bit 7) */ -#define CTIMER_AUX4_TMRA4TRIG_Msk (0x780UL) /*!< CTIMER AUX4: TMRA4TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX4_TMRA4LMT_Pos (0UL) /*!< CTIMER AUX4: TMRA4LMT (Bit 0) */ -#define CTIMER_AUX4_TMRA4LMT_Msk (0x7fUL) /*!< CTIMER AUX4: TMRA4LMT (Bitfield-Mask: 0x7f) */ -/* ========================================================= TMR5 ========================================================== */ -#define CTIMER_TMR5_CTTMRB5_Pos (16UL) /*!< CTIMER TMR5: CTTMRB5 (Bit 16) */ -#define CTIMER_TMR5_CTTMRB5_Msk (0xffff0000UL) /*!< CTIMER TMR5: CTTMRB5 (Bitfield-Mask: 0xffff) */ -#define CTIMER_TMR5_CTTMRA5_Pos (0UL) /*!< CTIMER TMR5: CTTMRA5 (Bit 0) */ -#define CTIMER_TMR5_CTTMRA5_Msk (0xffffUL) /*!< CTIMER TMR5: CTTMRA5 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRA5 ========================================================= */ -#define CTIMER_CMPRA5_CMPR1A5_Pos (16UL) /*!< CTIMER CMPRA5: CMPR1A5 (Bit 16) */ -#define CTIMER_CMPRA5_CMPR1A5_Msk (0xffff0000UL) /*!< CTIMER CMPRA5: CMPR1A5 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRA5_CMPR0A5_Pos (0UL) /*!< CTIMER CMPRA5: CMPR0A5 (Bit 0) */ -#define CTIMER_CMPRA5_CMPR0A5_Msk (0xffffUL) /*!< CTIMER CMPRA5: CMPR0A5 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRB5 ========================================================= */ -#define CTIMER_CMPRB5_CMPR1B5_Pos (16UL) /*!< CTIMER CMPRB5: CMPR1B5 (Bit 16) */ -#define CTIMER_CMPRB5_CMPR1B5_Msk (0xffff0000UL) /*!< CTIMER CMPRB5: CMPR1B5 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRB5_CMPR0B5_Pos (0UL) /*!< CTIMER CMPRB5: CMPR0B5 (Bit 0) */ -#define CTIMER_CMPRB5_CMPR0B5_Msk (0xffffUL) /*!< CTIMER CMPRB5: CMPR0B5 (Bitfield-Mask: 0xffff) */ -/* ========================================================= CTRL5 ========================================================= */ -#define CTIMER_CTRL5_CTLINK5_Pos (31UL) /*!< CTIMER CTRL5: CTLINK5 (Bit 31) */ -#define CTIMER_CTRL5_CTLINK5_Msk (0x80000000UL) /*!< CTIMER CTRL5: CTLINK5 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL5_TMRB5POL_Pos (28UL) /*!< CTIMER CTRL5: TMRB5POL (Bit 28) */ -#define CTIMER_CTRL5_TMRB5POL_Msk (0x10000000UL) /*!< CTIMER CTRL5: TMRB5POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL5_TMRB5CLR_Pos (27UL) /*!< CTIMER CTRL5: TMRB5CLR (Bit 27) */ -#define CTIMER_CTRL5_TMRB5CLR_Msk (0x8000000UL) /*!< CTIMER CTRL5: TMRB5CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL5_TMRB5IE1_Pos (26UL) /*!< CTIMER CTRL5: TMRB5IE1 (Bit 26) */ -#define CTIMER_CTRL5_TMRB5IE1_Msk (0x4000000UL) /*!< CTIMER CTRL5: TMRB5IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL5_TMRB5IE0_Pos (25UL) /*!< CTIMER CTRL5: TMRB5IE0 (Bit 25) */ -#define CTIMER_CTRL5_TMRB5IE0_Msk (0x2000000UL) /*!< CTIMER CTRL5: TMRB5IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL5_TMRB5FN_Pos (22UL) /*!< CTIMER CTRL5: TMRB5FN (Bit 22) */ -#define CTIMER_CTRL5_TMRB5FN_Msk (0x1c00000UL) /*!< CTIMER CTRL5: TMRB5FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL5_TMRB5CLK_Pos (17UL) /*!< CTIMER CTRL5: TMRB5CLK (Bit 17) */ -#define CTIMER_CTRL5_TMRB5CLK_Msk (0x3e0000UL) /*!< CTIMER CTRL5: TMRB5CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL5_TMRB5EN_Pos (16UL) /*!< CTIMER CTRL5: TMRB5EN (Bit 16) */ -#define CTIMER_CTRL5_TMRB5EN_Msk (0x10000UL) /*!< CTIMER CTRL5: TMRB5EN (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL5_TMRA5POL_Pos (12UL) /*!< CTIMER CTRL5: TMRA5POL (Bit 12) */ -#define CTIMER_CTRL5_TMRA5POL_Msk (0x1000UL) /*!< CTIMER CTRL5: TMRA5POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL5_TMRA5CLR_Pos (11UL) /*!< CTIMER CTRL5: TMRA5CLR (Bit 11) */ -#define CTIMER_CTRL5_TMRA5CLR_Msk (0x800UL) /*!< CTIMER CTRL5: TMRA5CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL5_TMRA5IE1_Pos (10UL) /*!< CTIMER CTRL5: TMRA5IE1 (Bit 10) */ -#define CTIMER_CTRL5_TMRA5IE1_Msk (0x400UL) /*!< CTIMER CTRL5: TMRA5IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL5_TMRA5IE0_Pos (9UL) /*!< CTIMER CTRL5: TMRA5IE0 (Bit 9) */ -#define CTIMER_CTRL5_TMRA5IE0_Msk (0x200UL) /*!< CTIMER CTRL5: TMRA5IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL5_TMRA5FN_Pos (6UL) /*!< CTIMER CTRL5: TMRA5FN (Bit 6) */ -#define CTIMER_CTRL5_TMRA5FN_Msk (0x1c0UL) /*!< CTIMER CTRL5: TMRA5FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL5_TMRA5CLK_Pos (1UL) /*!< CTIMER CTRL5: TMRA5CLK (Bit 1) */ -#define CTIMER_CTRL5_TMRA5CLK_Msk (0x3eUL) /*!< CTIMER CTRL5: TMRA5CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL5_TMRA5EN_Pos (0UL) /*!< CTIMER CTRL5: TMRA5EN (Bit 0) */ -#define CTIMER_CTRL5_TMRA5EN_Msk (0x1UL) /*!< CTIMER CTRL5: TMRA5EN (Bitfield-Mask: 0x01) */ -/* ======================================================= CMPRAUXA5 ======================================================= */ -#define CTIMER_CMPRAUXA5_CMPR3A5_Pos (16UL) /*!< CTIMER CMPRAUXA5: CMPR3A5 (Bit 16) */ -#define CTIMER_CMPRAUXA5_CMPR3A5_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXA5: CMPR3A5 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXA5_CMPR2A5_Pos (0UL) /*!< CTIMER CMPRAUXA5: CMPR2A5 (Bit 0) */ -#define CTIMER_CMPRAUXA5_CMPR2A5_Msk (0xffffUL) /*!< CTIMER CMPRAUXA5: CMPR2A5 (Bitfield-Mask: 0xffff) */ -/* ======================================================= CMPRAUXB5 ======================================================= */ -#define CTIMER_CMPRAUXB5_CMPR3B5_Pos (16UL) /*!< CTIMER CMPRAUXB5: CMPR3B5 (Bit 16) */ -#define CTIMER_CMPRAUXB5_CMPR3B5_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXB5: CMPR3B5 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXB5_CMPR2B5_Pos (0UL) /*!< CTIMER CMPRAUXB5: CMPR2B5 (Bit 0) */ -#define CTIMER_CMPRAUXB5_CMPR2B5_Msk (0xffffUL) /*!< CTIMER CMPRAUXB5: CMPR2B5 (Bitfield-Mask: 0xffff) */ -/* ========================================================= AUX5 ========================================================== */ -#define CTIMER_AUX5_TMRB5EN23_Pos (30UL) /*!< CTIMER AUX5: TMRB5EN23 (Bit 30) */ -#define CTIMER_AUX5_TMRB5EN23_Msk (0x40000000UL) /*!< CTIMER AUX5: TMRB5EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX5_TMRB5POL23_Pos (29UL) /*!< CTIMER AUX5: TMRB5POL23 (Bit 29) */ -#define CTIMER_AUX5_TMRB5POL23_Msk (0x20000000UL) /*!< CTIMER AUX5: TMRB5POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX5_TMRB5TINV_Pos (28UL) /*!< CTIMER AUX5: TMRB5TINV (Bit 28) */ -#define CTIMER_AUX5_TMRB5TINV_Msk (0x10000000UL) /*!< CTIMER AUX5: TMRB5TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX5_TMRB5NOSYNC_Pos (27UL) /*!< CTIMER AUX5: TMRB5NOSYNC (Bit 27) */ -#define CTIMER_AUX5_TMRB5NOSYNC_Msk (0x8000000UL) /*!< CTIMER AUX5: TMRB5NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX5_TMRB5TRIG_Pos (23UL) /*!< CTIMER AUX5: TMRB5TRIG (Bit 23) */ -#define CTIMER_AUX5_TMRB5TRIG_Msk (0x7800000UL) /*!< CTIMER AUX5: TMRB5TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX5_TMRB5LMT_Pos (16UL) /*!< CTIMER AUX5: TMRB5LMT (Bit 16) */ -#define CTIMER_AUX5_TMRB5LMT_Msk (0x3f0000UL) /*!< CTIMER AUX5: TMRB5LMT (Bitfield-Mask: 0x3f) */ -#define CTIMER_AUX5_TMRA5EN23_Pos (14UL) /*!< CTIMER AUX5: TMRA5EN23 (Bit 14) */ -#define CTIMER_AUX5_TMRA5EN23_Msk (0x4000UL) /*!< CTIMER AUX5: TMRA5EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX5_TMRA5POL23_Pos (13UL) /*!< CTIMER AUX5: TMRA5POL23 (Bit 13) */ -#define CTIMER_AUX5_TMRA5POL23_Msk (0x2000UL) /*!< CTIMER AUX5: TMRA5POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX5_TMRA5TINV_Pos (12UL) /*!< CTIMER AUX5: TMRA5TINV (Bit 12) */ -#define CTIMER_AUX5_TMRA5TINV_Msk (0x1000UL) /*!< CTIMER AUX5: TMRA5TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX5_TMRA5NOSYNC_Pos (11UL) /*!< CTIMER AUX5: TMRA5NOSYNC (Bit 11) */ -#define CTIMER_AUX5_TMRA5NOSYNC_Msk (0x800UL) /*!< CTIMER AUX5: TMRA5NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX5_TMRA5TRIG_Pos (7UL) /*!< CTIMER AUX5: TMRA5TRIG (Bit 7) */ -#define CTIMER_AUX5_TMRA5TRIG_Msk (0x780UL) /*!< CTIMER AUX5: TMRA5TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX5_TMRA5LMT_Pos (0UL) /*!< CTIMER AUX5: TMRA5LMT (Bit 0) */ -#define CTIMER_AUX5_TMRA5LMT_Msk (0x7fUL) /*!< CTIMER AUX5: TMRA5LMT (Bitfield-Mask: 0x7f) */ -/* ========================================================= TMR6 ========================================================== */ -#define CTIMER_TMR6_CTTMRB6_Pos (16UL) /*!< CTIMER TMR6: CTTMRB6 (Bit 16) */ -#define CTIMER_TMR6_CTTMRB6_Msk (0xffff0000UL) /*!< CTIMER TMR6: CTTMRB6 (Bitfield-Mask: 0xffff) */ -#define CTIMER_TMR6_CTTMRA6_Pos (0UL) /*!< CTIMER TMR6: CTTMRA6 (Bit 0) */ -#define CTIMER_TMR6_CTTMRA6_Msk (0xffffUL) /*!< CTIMER TMR6: CTTMRA6 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRA6 ========================================================= */ -#define CTIMER_CMPRA6_CMPR1A6_Pos (16UL) /*!< CTIMER CMPRA6: CMPR1A6 (Bit 16) */ -#define CTIMER_CMPRA6_CMPR1A6_Msk (0xffff0000UL) /*!< CTIMER CMPRA6: CMPR1A6 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRA6_CMPR0A6_Pos (0UL) /*!< CTIMER CMPRA6: CMPR0A6 (Bit 0) */ -#define CTIMER_CMPRA6_CMPR0A6_Msk (0xffffUL) /*!< CTIMER CMPRA6: CMPR0A6 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRB6 ========================================================= */ -#define CTIMER_CMPRB6_CMPR1B6_Pos (16UL) /*!< CTIMER CMPRB6: CMPR1B6 (Bit 16) */ -#define CTIMER_CMPRB6_CMPR1B6_Msk (0xffff0000UL) /*!< CTIMER CMPRB6: CMPR1B6 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRB6_CMPR0B6_Pos (0UL) /*!< CTIMER CMPRB6: CMPR0B6 (Bit 0) */ -#define CTIMER_CMPRB6_CMPR0B6_Msk (0xffffUL) /*!< CTIMER CMPRB6: CMPR0B6 (Bitfield-Mask: 0xffff) */ -/* ========================================================= CTRL6 ========================================================= */ -#define CTIMER_CTRL6_CTLINK6_Pos (31UL) /*!< CTIMER CTRL6: CTLINK6 (Bit 31) */ -#define CTIMER_CTRL6_CTLINK6_Msk (0x80000000UL) /*!< CTIMER CTRL6: CTLINK6 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL6_TMRB6POL_Pos (28UL) /*!< CTIMER CTRL6: TMRB6POL (Bit 28) */ -#define CTIMER_CTRL6_TMRB6POL_Msk (0x10000000UL) /*!< CTIMER CTRL6: TMRB6POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL6_TMRB6CLR_Pos (27UL) /*!< CTIMER CTRL6: TMRB6CLR (Bit 27) */ -#define CTIMER_CTRL6_TMRB6CLR_Msk (0x8000000UL) /*!< CTIMER CTRL6: TMRB6CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL6_TMRB6IE1_Pos (26UL) /*!< CTIMER CTRL6: TMRB6IE1 (Bit 26) */ -#define CTIMER_CTRL6_TMRB6IE1_Msk (0x4000000UL) /*!< CTIMER CTRL6: TMRB6IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL6_TMRB6IE0_Pos (25UL) /*!< CTIMER CTRL6: TMRB6IE0 (Bit 25) */ -#define CTIMER_CTRL6_TMRB6IE0_Msk (0x2000000UL) /*!< CTIMER CTRL6: TMRB6IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL6_TMRB6FN_Pos (22UL) /*!< CTIMER CTRL6: TMRB6FN (Bit 22) */ -#define CTIMER_CTRL6_TMRB6FN_Msk (0x1c00000UL) /*!< CTIMER CTRL6: TMRB6FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL6_TMRB6CLK_Pos (17UL) /*!< CTIMER CTRL6: TMRB6CLK (Bit 17) */ -#define CTIMER_CTRL6_TMRB6CLK_Msk (0x3e0000UL) /*!< CTIMER CTRL6: TMRB6CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL6_TMRB6EN_Pos (16UL) /*!< CTIMER CTRL6: TMRB6EN (Bit 16) */ -#define CTIMER_CTRL6_TMRB6EN_Msk (0x10000UL) /*!< CTIMER CTRL6: TMRB6EN (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL6_TMRA6POL_Pos (12UL) /*!< CTIMER CTRL6: TMRA6POL (Bit 12) */ -#define CTIMER_CTRL6_TMRA6POL_Msk (0x1000UL) /*!< CTIMER CTRL6: TMRA6POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL6_TMRA6CLR_Pos (11UL) /*!< CTIMER CTRL6: TMRA6CLR (Bit 11) */ -#define CTIMER_CTRL6_TMRA6CLR_Msk (0x800UL) /*!< CTIMER CTRL6: TMRA6CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL6_TMRA6IE1_Pos (10UL) /*!< CTIMER CTRL6: TMRA6IE1 (Bit 10) */ -#define CTIMER_CTRL6_TMRA6IE1_Msk (0x400UL) /*!< CTIMER CTRL6: TMRA6IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL6_TMRA6IE0_Pos (9UL) /*!< CTIMER CTRL6: TMRA6IE0 (Bit 9) */ -#define CTIMER_CTRL6_TMRA6IE0_Msk (0x200UL) /*!< CTIMER CTRL6: TMRA6IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL6_TMRA6FN_Pos (6UL) /*!< CTIMER CTRL6: TMRA6FN (Bit 6) */ -#define CTIMER_CTRL6_TMRA6FN_Msk (0x1c0UL) /*!< CTIMER CTRL6: TMRA6FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL6_TMRA6CLK_Pos (1UL) /*!< CTIMER CTRL6: TMRA6CLK (Bit 1) */ -#define CTIMER_CTRL6_TMRA6CLK_Msk (0x3eUL) /*!< CTIMER CTRL6: TMRA6CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL6_TMRA6EN_Pos (0UL) /*!< CTIMER CTRL6: TMRA6EN (Bit 0) */ -#define CTIMER_CTRL6_TMRA6EN_Msk (0x1UL) /*!< CTIMER CTRL6: TMRA6EN (Bitfield-Mask: 0x01) */ -/* ======================================================= CMPRAUXA6 ======================================================= */ -#define CTIMER_CMPRAUXA6_CMPR3A6_Pos (16UL) /*!< CTIMER CMPRAUXA6: CMPR3A6 (Bit 16) */ -#define CTIMER_CMPRAUXA6_CMPR3A6_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXA6: CMPR3A6 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXA6_CMPR2A6_Pos (0UL) /*!< CTIMER CMPRAUXA6: CMPR2A6 (Bit 0) */ -#define CTIMER_CMPRAUXA6_CMPR2A6_Msk (0xffffUL) /*!< CTIMER CMPRAUXA6: CMPR2A6 (Bitfield-Mask: 0xffff) */ -/* ======================================================= CMPRAUXB6 ======================================================= */ -#define CTIMER_CMPRAUXB6_CMPR3B6_Pos (16UL) /*!< CTIMER CMPRAUXB6: CMPR3B6 (Bit 16) */ -#define CTIMER_CMPRAUXB6_CMPR3B6_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXB6: CMPR3B6 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXB6_CMPR2B6_Pos (0UL) /*!< CTIMER CMPRAUXB6: CMPR2B6 (Bit 0) */ -#define CTIMER_CMPRAUXB6_CMPR2B6_Msk (0xffffUL) /*!< CTIMER CMPRAUXB6: CMPR2B6 (Bitfield-Mask: 0xffff) */ -/* ========================================================= AUX6 ========================================================== */ -#define CTIMER_AUX6_TMRB6EN23_Pos (30UL) /*!< CTIMER AUX6: TMRB6EN23 (Bit 30) */ -#define CTIMER_AUX6_TMRB6EN23_Msk (0x40000000UL) /*!< CTIMER AUX6: TMRB6EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX6_TMRB6POL23_Pos (29UL) /*!< CTIMER AUX6: TMRB6POL23 (Bit 29) */ -#define CTIMER_AUX6_TMRB6POL23_Msk (0x20000000UL) /*!< CTIMER AUX6: TMRB6POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX6_TMRB6TINV_Pos (28UL) /*!< CTIMER AUX6: TMRB6TINV (Bit 28) */ -#define CTIMER_AUX6_TMRB6TINV_Msk (0x10000000UL) /*!< CTIMER AUX6: TMRB6TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX6_TMRB6NOSYNC_Pos (27UL) /*!< CTIMER AUX6: TMRB6NOSYNC (Bit 27) */ -#define CTIMER_AUX6_TMRB6NOSYNC_Msk (0x8000000UL) /*!< CTIMER AUX6: TMRB6NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX6_TMRB6TRIG_Pos (23UL) /*!< CTIMER AUX6: TMRB6TRIG (Bit 23) */ -#define CTIMER_AUX6_TMRB6TRIG_Msk (0x7800000UL) /*!< CTIMER AUX6: TMRB6TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX6_TMRB6LMT_Pos (16UL) /*!< CTIMER AUX6: TMRB6LMT (Bit 16) */ -#define CTIMER_AUX6_TMRB6LMT_Msk (0x3f0000UL) /*!< CTIMER AUX6: TMRB6LMT (Bitfield-Mask: 0x3f) */ -#define CTIMER_AUX6_TMRA6EN23_Pos (14UL) /*!< CTIMER AUX6: TMRA6EN23 (Bit 14) */ -#define CTIMER_AUX6_TMRA6EN23_Msk (0x4000UL) /*!< CTIMER AUX6: TMRA6EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX6_TMRA6POL23_Pos (13UL) /*!< CTIMER AUX6: TMRA6POL23 (Bit 13) */ -#define CTIMER_AUX6_TMRA6POL23_Msk (0x2000UL) /*!< CTIMER AUX6: TMRA6POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX6_TMRA6TINV_Pos (12UL) /*!< CTIMER AUX6: TMRA6TINV (Bit 12) */ -#define CTIMER_AUX6_TMRA6TINV_Msk (0x1000UL) /*!< CTIMER AUX6: TMRA6TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX6_TMRA6NOSYNC_Pos (11UL) /*!< CTIMER AUX6: TMRA6NOSYNC (Bit 11) */ -#define CTIMER_AUX6_TMRA6NOSYNC_Msk (0x800UL) /*!< CTIMER AUX6: TMRA6NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX6_TMRA6TRIG_Pos (7UL) /*!< CTIMER AUX6: TMRA6TRIG (Bit 7) */ -#define CTIMER_AUX6_TMRA6TRIG_Msk (0x780UL) /*!< CTIMER AUX6: TMRA6TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX6_TMRA6LMT_Pos (0UL) /*!< CTIMER AUX6: TMRA6LMT (Bit 0) */ -#define CTIMER_AUX6_TMRA6LMT_Msk (0x7fUL) /*!< CTIMER AUX6: TMRA6LMT (Bitfield-Mask: 0x7f) */ -/* ========================================================= TMR7 ========================================================== */ -#define CTIMER_TMR7_CTTMRB7_Pos (16UL) /*!< CTIMER TMR7: CTTMRB7 (Bit 16) */ -#define CTIMER_TMR7_CTTMRB7_Msk (0xffff0000UL) /*!< CTIMER TMR7: CTTMRB7 (Bitfield-Mask: 0xffff) */ -#define CTIMER_TMR7_CTTMRA7_Pos (0UL) /*!< CTIMER TMR7: CTTMRA7 (Bit 0) */ -#define CTIMER_TMR7_CTTMRA7_Msk (0xffffUL) /*!< CTIMER TMR7: CTTMRA7 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRA7 ========================================================= */ -#define CTIMER_CMPRA7_CMPR1A7_Pos (16UL) /*!< CTIMER CMPRA7: CMPR1A7 (Bit 16) */ -#define CTIMER_CMPRA7_CMPR1A7_Msk (0xffff0000UL) /*!< CTIMER CMPRA7: CMPR1A7 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRA7_CMPR0A7_Pos (0UL) /*!< CTIMER CMPRA7: CMPR0A7 (Bit 0) */ -#define CTIMER_CMPRA7_CMPR0A7_Msk (0xffffUL) /*!< CTIMER CMPRA7: CMPR0A7 (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMPRB7 ========================================================= */ -#define CTIMER_CMPRB7_CMPR1B7_Pos (16UL) /*!< CTIMER CMPRB7: CMPR1B7 (Bit 16) */ -#define CTIMER_CMPRB7_CMPR1B7_Msk (0xffff0000UL) /*!< CTIMER CMPRB7: CMPR1B7 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRB7_CMPR0B7_Pos (0UL) /*!< CTIMER CMPRB7: CMPR0B7 (Bit 0) */ -#define CTIMER_CMPRB7_CMPR0B7_Msk (0xffffUL) /*!< CTIMER CMPRB7: CMPR0B7 (Bitfield-Mask: 0xffff) */ -/* ========================================================= CTRL7 ========================================================= */ -#define CTIMER_CTRL7_CTLINK7_Pos (31UL) /*!< CTIMER CTRL7: CTLINK7 (Bit 31) */ -#define CTIMER_CTRL7_CTLINK7_Msk (0x80000000UL) /*!< CTIMER CTRL7: CTLINK7 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL7_TMRB7POL_Pos (28UL) /*!< CTIMER CTRL7: TMRB7POL (Bit 28) */ -#define CTIMER_CTRL7_TMRB7POL_Msk (0x10000000UL) /*!< CTIMER CTRL7: TMRB7POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL7_TMRB7CLR_Pos (27UL) /*!< CTIMER CTRL7: TMRB7CLR (Bit 27) */ -#define CTIMER_CTRL7_TMRB7CLR_Msk (0x8000000UL) /*!< CTIMER CTRL7: TMRB7CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL7_TMRB7IE1_Pos (26UL) /*!< CTIMER CTRL7: TMRB7IE1 (Bit 26) */ -#define CTIMER_CTRL7_TMRB7IE1_Msk (0x4000000UL) /*!< CTIMER CTRL7: TMRB7IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL7_TMRB7IE0_Pos (25UL) /*!< CTIMER CTRL7: TMRB7IE0 (Bit 25) */ -#define CTIMER_CTRL7_TMRB7IE0_Msk (0x2000000UL) /*!< CTIMER CTRL7: TMRB7IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL7_TMRB7FN_Pos (22UL) /*!< CTIMER CTRL7: TMRB7FN (Bit 22) */ -#define CTIMER_CTRL7_TMRB7FN_Msk (0x1c00000UL) /*!< CTIMER CTRL7: TMRB7FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL7_TMRB7CLK_Pos (17UL) /*!< CTIMER CTRL7: TMRB7CLK (Bit 17) */ -#define CTIMER_CTRL7_TMRB7CLK_Msk (0x3e0000UL) /*!< CTIMER CTRL7: TMRB7CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL7_TMRB7EN_Pos (16UL) /*!< CTIMER CTRL7: TMRB7EN (Bit 16) */ -#define CTIMER_CTRL7_TMRB7EN_Msk (0x10000UL) /*!< CTIMER CTRL7: TMRB7EN (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL7_TMRA7POL_Pos (12UL) /*!< CTIMER CTRL7: TMRA7POL (Bit 12) */ -#define CTIMER_CTRL7_TMRA7POL_Msk (0x1000UL) /*!< CTIMER CTRL7: TMRA7POL (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL7_TMRA7CLR_Pos (11UL) /*!< CTIMER CTRL7: TMRA7CLR (Bit 11) */ -#define CTIMER_CTRL7_TMRA7CLR_Msk (0x800UL) /*!< CTIMER CTRL7: TMRA7CLR (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL7_TMRA7IE1_Pos (10UL) /*!< CTIMER CTRL7: TMRA7IE1 (Bit 10) */ -#define CTIMER_CTRL7_TMRA7IE1_Msk (0x400UL) /*!< CTIMER CTRL7: TMRA7IE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL7_TMRA7IE0_Pos (9UL) /*!< CTIMER CTRL7: TMRA7IE0 (Bit 9) */ -#define CTIMER_CTRL7_TMRA7IE0_Msk (0x200UL) /*!< CTIMER CTRL7: TMRA7IE0 (Bitfield-Mask: 0x01) */ -#define CTIMER_CTRL7_TMRA7FN_Pos (6UL) /*!< CTIMER CTRL7: TMRA7FN (Bit 6) */ -#define CTIMER_CTRL7_TMRA7FN_Msk (0x1c0UL) /*!< CTIMER CTRL7: TMRA7FN (Bitfield-Mask: 0x07) */ -#define CTIMER_CTRL7_TMRA7CLK_Pos (1UL) /*!< CTIMER CTRL7: TMRA7CLK (Bit 1) */ -#define CTIMER_CTRL7_TMRA7CLK_Msk (0x3eUL) /*!< CTIMER CTRL7: TMRA7CLK (Bitfield-Mask: 0x1f) */ -#define CTIMER_CTRL7_TMRA7EN_Pos (0UL) /*!< CTIMER CTRL7: TMRA7EN (Bit 0) */ -#define CTIMER_CTRL7_TMRA7EN_Msk (0x1UL) /*!< CTIMER CTRL7: TMRA7EN (Bitfield-Mask: 0x01) */ -/* ======================================================= CMPRAUXA7 ======================================================= */ -#define CTIMER_CMPRAUXA7_CMPR3A7_Pos (16UL) /*!< CTIMER CMPRAUXA7: CMPR3A7 (Bit 16) */ -#define CTIMER_CMPRAUXA7_CMPR3A7_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXA7: CMPR3A7 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXA7_CMPR2A7_Pos (0UL) /*!< CTIMER CMPRAUXA7: CMPR2A7 (Bit 0) */ -#define CTIMER_CMPRAUXA7_CMPR2A7_Msk (0xffffUL) /*!< CTIMER CMPRAUXA7: CMPR2A7 (Bitfield-Mask: 0xffff) */ -/* ======================================================= CMPRAUXB7 ======================================================= */ -#define CTIMER_CMPRAUXB7_CMPR3B7_Pos (16UL) /*!< CTIMER CMPRAUXB7: CMPR3B7 (Bit 16) */ -#define CTIMER_CMPRAUXB7_CMPR3B7_Msk (0xffff0000UL) /*!< CTIMER CMPRAUXB7: CMPR3B7 (Bitfield-Mask: 0xffff) */ -#define CTIMER_CMPRAUXB7_CMPR2B7_Pos (0UL) /*!< CTIMER CMPRAUXB7: CMPR2B7 (Bit 0) */ -#define CTIMER_CMPRAUXB7_CMPR2B7_Msk (0xffffUL) /*!< CTIMER CMPRAUXB7: CMPR2B7 (Bitfield-Mask: 0xffff) */ -/* ========================================================= AUX7 ========================================================== */ -#define CTIMER_AUX7_TMRB7EN23_Pos (30UL) /*!< CTIMER AUX7: TMRB7EN23 (Bit 30) */ -#define CTIMER_AUX7_TMRB7EN23_Msk (0x40000000UL) /*!< CTIMER AUX7: TMRB7EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX7_TMRB7POL23_Pos (29UL) /*!< CTIMER AUX7: TMRB7POL23 (Bit 29) */ -#define CTIMER_AUX7_TMRB7POL23_Msk (0x20000000UL) /*!< CTIMER AUX7: TMRB7POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX7_TMRB7TINV_Pos (28UL) /*!< CTIMER AUX7: TMRB7TINV (Bit 28) */ -#define CTIMER_AUX7_TMRB7TINV_Msk (0x10000000UL) /*!< CTIMER AUX7: TMRB7TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX7_TMRB7NOSYNC_Pos (27UL) /*!< CTIMER AUX7: TMRB7NOSYNC (Bit 27) */ -#define CTIMER_AUX7_TMRB7NOSYNC_Msk (0x8000000UL) /*!< CTIMER AUX7: TMRB7NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX7_TMRB7TRIG_Pos (23UL) /*!< CTIMER AUX7: TMRB7TRIG (Bit 23) */ -#define CTIMER_AUX7_TMRB7TRIG_Msk (0x7800000UL) /*!< CTIMER AUX7: TMRB7TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX7_TMRB7LMT_Pos (16UL) /*!< CTIMER AUX7: TMRB7LMT (Bit 16) */ -#define CTIMER_AUX7_TMRB7LMT_Msk (0x3f0000UL) /*!< CTIMER AUX7: TMRB7LMT (Bitfield-Mask: 0x3f) */ -#define CTIMER_AUX7_TMRA7EN23_Pos (14UL) /*!< CTIMER AUX7: TMRA7EN23 (Bit 14) */ -#define CTIMER_AUX7_TMRA7EN23_Msk (0x4000UL) /*!< CTIMER AUX7: TMRA7EN23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX7_TMRA7POL23_Pos (13UL) /*!< CTIMER AUX7: TMRA7POL23 (Bit 13) */ -#define CTIMER_AUX7_TMRA7POL23_Msk (0x2000UL) /*!< CTIMER AUX7: TMRA7POL23 (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX7_TMRA7TINV_Pos (12UL) /*!< CTIMER AUX7: TMRA7TINV (Bit 12) */ -#define CTIMER_AUX7_TMRA7TINV_Msk (0x1000UL) /*!< CTIMER AUX7: TMRA7TINV (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX7_TMRA7NOSYNC_Pos (11UL) /*!< CTIMER AUX7: TMRA7NOSYNC (Bit 11) */ -#define CTIMER_AUX7_TMRA7NOSYNC_Msk (0x800UL) /*!< CTIMER AUX7: TMRA7NOSYNC (Bitfield-Mask: 0x01) */ -#define CTIMER_AUX7_TMRA7TRIG_Pos (7UL) /*!< CTIMER AUX7: TMRA7TRIG (Bit 7) */ -#define CTIMER_AUX7_TMRA7TRIG_Msk (0x780UL) /*!< CTIMER AUX7: TMRA7TRIG (Bitfield-Mask: 0x0f) */ -#define CTIMER_AUX7_TMRA7LMT_Pos (0UL) /*!< CTIMER AUX7: TMRA7LMT (Bit 0) */ -#define CTIMER_AUX7_TMRA7LMT_Msk (0x7fUL) /*!< CTIMER AUX7: TMRA7LMT (Bitfield-Mask: 0x7f) */ -/* ======================================================== GLOBEN ========================================================= */ -#define CTIMER_GLOBEN_ENB7_Pos (15UL) /*!< CTIMER GLOBEN: ENB7 (Bit 15) */ -#define CTIMER_GLOBEN_ENB7_Msk (0x8000UL) /*!< CTIMER GLOBEN: ENB7 (Bitfield-Mask: 0x01) */ -#define CTIMER_GLOBEN_ENA7_Pos (14UL) /*!< CTIMER GLOBEN: ENA7 (Bit 14) */ -#define CTIMER_GLOBEN_ENA7_Msk (0x4000UL) /*!< CTIMER GLOBEN: ENA7 (Bitfield-Mask: 0x01) */ -#define CTIMER_GLOBEN_ENB6_Pos (13UL) /*!< CTIMER GLOBEN: ENB6 (Bit 13) */ -#define CTIMER_GLOBEN_ENB6_Msk (0x2000UL) /*!< CTIMER GLOBEN: ENB6 (Bitfield-Mask: 0x01) */ -#define CTIMER_GLOBEN_ENA6_Pos (12UL) /*!< CTIMER GLOBEN: ENA6 (Bit 12) */ -#define CTIMER_GLOBEN_ENA6_Msk (0x1000UL) /*!< CTIMER GLOBEN: ENA6 (Bitfield-Mask: 0x01) */ -#define CTIMER_GLOBEN_ENB5_Pos (11UL) /*!< CTIMER GLOBEN: ENB5 (Bit 11) */ -#define CTIMER_GLOBEN_ENB5_Msk (0x800UL) /*!< CTIMER GLOBEN: ENB5 (Bitfield-Mask: 0x01) */ -#define CTIMER_GLOBEN_ENA5_Pos (10UL) /*!< CTIMER GLOBEN: ENA5 (Bit 10) */ -#define CTIMER_GLOBEN_ENA5_Msk (0x400UL) /*!< CTIMER GLOBEN: ENA5 (Bitfield-Mask: 0x01) */ -#define CTIMER_GLOBEN_ENB4_Pos (9UL) /*!< CTIMER GLOBEN: ENB4 (Bit 9) */ -#define CTIMER_GLOBEN_ENB4_Msk (0x200UL) /*!< CTIMER GLOBEN: ENB4 (Bitfield-Mask: 0x01) */ -#define CTIMER_GLOBEN_ENA4_Pos (8UL) /*!< CTIMER GLOBEN: ENA4 (Bit 8) */ -#define CTIMER_GLOBEN_ENA4_Msk (0x100UL) /*!< CTIMER GLOBEN: ENA4 (Bitfield-Mask: 0x01) */ -#define CTIMER_GLOBEN_ENB3_Pos (7UL) /*!< CTIMER GLOBEN: ENB3 (Bit 7) */ -#define CTIMER_GLOBEN_ENB3_Msk (0x80UL) /*!< CTIMER GLOBEN: ENB3 (Bitfield-Mask: 0x01) */ -#define CTIMER_GLOBEN_ENA3_Pos (6UL) /*!< CTIMER GLOBEN: ENA3 (Bit 6) */ -#define CTIMER_GLOBEN_ENA3_Msk (0x40UL) /*!< CTIMER GLOBEN: ENA3 (Bitfield-Mask: 0x01) */ -#define CTIMER_GLOBEN_ENB2_Pos (5UL) /*!< CTIMER GLOBEN: ENB2 (Bit 5) */ -#define CTIMER_GLOBEN_ENB2_Msk (0x20UL) /*!< CTIMER GLOBEN: ENB2 (Bitfield-Mask: 0x01) */ -#define CTIMER_GLOBEN_ENA2_Pos (4UL) /*!< CTIMER GLOBEN: ENA2 (Bit 4) */ -#define CTIMER_GLOBEN_ENA2_Msk (0x10UL) /*!< CTIMER GLOBEN: ENA2 (Bitfield-Mask: 0x01) */ -#define CTIMER_GLOBEN_ENB1_Pos (3UL) /*!< CTIMER GLOBEN: ENB1 (Bit 3) */ -#define CTIMER_GLOBEN_ENB1_Msk (0x8UL) /*!< CTIMER GLOBEN: ENB1 (Bitfield-Mask: 0x01) */ -#define CTIMER_GLOBEN_ENA1_Pos (2UL) /*!< CTIMER GLOBEN: ENA1 (Bit 2) */ -#define CTIMER_GLOBEN_ENA1_Msk (0x4UL) /*!< CTIMER GLOBEN: ENA1 (Bitfield-Mask: 0x01) */ -#define CTIMER_GLOBEN_ENB0_Pos (1UL) /*!< CTIMER GLOBEN: ENB0 (Bit 1) */ -#define CTIMER_GLOBEN_ENB0_Msk (0x2UL) /*!< CTIMER GLOBEN: ENB0 (Bitfield-Mask: 0x01) */ -#define CTIMER_GLOBEN_ENA0_Pos (0UL) /*!< CTIMER GLOBEN: ENA0 (Bit 0) */ -#define CTIMER_GLOBEN_ENA0_Msk (0x1UL) /*!< CTIMER GLOBEN: ENA0 (Bitfield-Mask: 0x01) */ -/* ======================================================== OUTCFG0 ======================================================== */ -#define CTIMER_OUTCFG0_CFG9_Pos (28UL) /*!< CTIMER OUTCFG0: CFG9 (Bit 28) */ -#define CTIMER_OUTCFG0_CFG9_Msk (0x70000000UL) /*!< CTIMER OUTCFG0: CFG9 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG0_CFG8_Pos (25UL) /*!< CTIMER OUTCFG0: CFG8 (Bit 25) */ -#define CTIMER_OUTCFG0_CFG8_Msk (0xe000000UL) /*!< CTIMER OUTCFG0: CFG8 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG0_CFG7_Pos (22UL) /*!< CTIMER OUTCFG0: CFG7 (Bit 22) */ -#define CTIMER_OUTCFG0_CFG7_Msk (0x1c00000UL) /*!< CTIMER OUTCFG0: CFG7 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG0_CFG6_Pos (19UL) /*!< CTIMER OUTCFG0: CFG6 (Bit 19) */ -#define CTIMER_OUTCFG0_CFG6_Msk (0x380000UL) /*!< CTIMER OUTCFG0: CFG6 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG0_CFG5_Pos (16UL) /*!< CTIMER OUTCFG0: CFG5 (Bit 16) */ -#define CTIMER_OUTCFG0_CFG5_Msk (0x70000UL) /*!< CTIMER OUTCFG0: CFG5 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG0_CFG4_Pos (12UL) /*!< CTIMER OUTCFG0: CFG4 (Bit 12) */ -#define CTIMER_OUTCFG0_CFG4_Msk (0x7000UL) /*!< CTIMER OUTCFG0: CFG4 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG0_CFG3_Pos (9UL) /*!< CTIMER OUTCFG0: CFG3 (Bit 9) */ -#define CTIMER_OUTCFG0_CFG3_Msk (0xe00UL) /*!< CTIMER OUTCFG0: CFG3 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG0_CFG2_Pos (6UL) /*!< CTIMER OUTCFG0: CFG2 (Bit 6) */ -#define CTIMER_OUTCFG0_CFG2_Msk (0x1c0UL) /*!< CTIMER OUTCFG0: CFG2 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG0_CFG1_Pos (3UL) /*!< CTIMER OUTCFG0: CFG1 (Bit 3) */ -#define CTIMER_OUTCFG0_CFG1_Msk (0x38UL) /*!< CTIMER OUTCFG0: CFG1 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG0_CFG0_Pos (0UL) /*!< CTIMER OUTCFG0: CFG0 (Bit 0) */ -#define CTIMER_OUTCFG0_CFG0_Msk (0x7UL) /*!< CTIMER OUTCFG0: CFG0 (Bitfield-Mask: 0x07) */ -/* ======================================================== OUTCFG1 ======================================================== */ -#define CTIMER_OUTCFG1_CFG19_Pos (28UL) /*!< CTIMER OUTCFG1: CFG19 (Bit 28) */ -#define CTIMER_OUTCFG1_CFG19_Msk (0x70000000UL) /*!< CTIMER OUTCFG1: CFG19 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG1_CFG18_Pos (25UL) /*!< CTIMER OUTCFG1: CFG18 (Bit 25) */ -#define CTIMER_OUTCFG1_CFG18_Msk (0xe000000UL) /*!< CTIMER OUTCFG1: CFG18 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG1_CFG17_Pos (22UL) /*!< CTIMER OUTCFG1: CFG17 (Bit 22) */ -#define CTIMER_OUTCFG1_CFG17_Msk (0x1c00000UL) /*!< CTIMER OUTCFG1: CFG17 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG1_CFG16_Pos (19UL) /*!< CTIMER OUTCFG1: CFG16 (Bit 19) */ -#define CTIMER_OUTCFG1_CFG16_Msk (0x380000UL) /*!< CTIMER OUTCFG1: CFG16 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG1_CFG15_Pos (16UL) /*!< CTIMER OUTCFG1: CFG15 (Bit 16) */ -#define CTIMER_OUTCFG1_CFG15_Msk (0x70000UL) /*!< CTIMER OUTCFG1: CFG15 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG1_CFG14_Pos (12UL) /*!< CTIMER OUTCFG1: CFG14 (Bit 12) */ -#define CTIMER_OUTCFG1_CFG14_Msk (0x7000UL) /*!< CTIMER OUTCFG1: CFG14 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG1_CFG13_Pos (9UL) /*!< CTIMER OUTCFG1: CFG13 (Bit 9) */ -#define CTIMER_OUTCFG1_CFG13_Msk (0xe00UL) /*!< CTIMER OUTCFG1: CFG13 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG1_CFG12_Pos (6UL) /*!< CTIMER OUTCFG1: CFG12 (Bit 6) */ -#define CTIMER_OUTCFG1_CFG12_Msk (0x1c0UL) /*!< CTIMER OUTCFG1: CFG12 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG1_CFG11_Pos (3UL) /*!< CTIMER OUTCFG1: CFG11 (Bit 3) */ -#define CTIMER_OUTCFG1_CFG11_Msk (0x38UL) /*!< CTIMER OUTCFG1: CFG11 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG1_CFG10_Pos (0UL) /*!< CTIMER OUTCFG1: CFG10 (Bit 0) */ -#define CTIMER_OUTCFG1_CFG10_Msk (0x7UL) /*!< CTIMER OUTCFG1: CFG10 (Bitfield-Mask: 0x07) */ -/* ======================================================== OUTCFG2 ======================================================== */ -#define CTIMER_OUTCFG2_CFG29_Pos (28UL) /*!< CTIMER OUTCFG2: CFG29 (Bit 28) */ -#define CTIMER_OUTCFG2_CFG29_Msk (0x70000000UL) /*!< CTIMER OUTCFG2: CFG29 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG2_CFG28_Pos (25UL) /*!< CTIMER OUTCFG2: CFG28 (Bit 25) */ -#define CTIMER_OUTCFG2_CFG28_Msk (0xe000000UL) /*!< CTIMER OUTCFG2: CFG28 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG2_CFG27_Pos (22UL) /*!< CTIMER OUTCFG2: CFG27 (Bit 22) */ -#define CTIMER_OUTCFG2_CFG27_Msk (0x1c00000UL) /*!< CTIMER OUTCFG2: CFG27 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG2_CFG26_Pos (19UL) /*!< CTIMER OUTCFG2: CFG26 (Bit 19) */ -#define CTIMER_OUTCFG2_CFG26_Msk (0x380000UL) /*!< CTIMER OUTCFG2: CFG26 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG2_CFG25_Pos (16UL) /*!< CTIMER OUTCFG2: CFG25 (Bit 16) */ -#define CTIMER_OUTCFG2_CFG25_Msk (0x70000UL) /*!< CTIMER OUTCFG2: CFG25 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG2_CFG24_Pos (12UL) /*!< CTIMER OUTCFG2: CFG24 (Bit 12) */ -#define CTIMER_OUTCFG2_CFG24_Msk (0x7000UL) /*!< CTIMER OUTCFG2: CFG24 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG2_CFG23_Pos (9UL) /*!< CTIMER OUTCFG2: CFG23 (Bit 9) */ -#define CTIMER_OUTCFG2_CFG23_Msk (0xe00UL) /*!< CTIMER OUTCFG2: CFG23 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG2_CFG22_Pos (6UL) /*!< CTIMER OUTCFG2: CFG22 (Bit 6) */ -#define CTIMER_OUTCFG2_CFG22_Msk (0x1c0UL) /*!< CTIMER OUTCFG2: CFG22 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG2_CFG21_Pos (3UL) /*!< CTIMER OUTCFG2: CFG21 (Bit 3) */ -#define CTIMER_OUTCFG2_CFG21_Msk (0x38UL) /*!< CTIMER OUTCFG2: CFG21 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG2_CFG20_Pos (0UL) /*!< CTIMER OUTCFG2: CFG20 (Bit 0) */ -#define CTIMER_OUTCFG2_CFG20_Msk (0x7UL) /*!< CTIMER OUTCFG2: CFG20 (Bitfield-Mask: 0x07) */ -/* ======================================================== OUTCFG3 ======================================================== */ -#define CTIMER_OUTCFG3_CFG31_Pos (3UL) /*!< CTIMER OUTCFG3: CFG31 (Bit 3) */ -#define CTIMER_OUTCFG3_CFG31_Msk (0x38UL) /*!< CTIMER OUTCFG3: CFG31 (Bitfield-Mask: 0x07) */ -#define CTIMER_OUTCFG3_CFG30_Pos (0UL) /*!< CTIMER OUTCFG3: CFG30 (Bit 0) */ -#define CTIMER_OUTCFG3_CFG30_Msk (0x7UL) /*!< CTIMER OUTCFG3: CFG30 (Bitfield-Mask: 0x07) */ -/* ========================================================= INCFG ========================================================= */ -#define CTIMER_INCFG_CFGB7_Pos (15UL) /*!< CTIMER INCFG: CFGB7 (Bit 15) */ -#define CTIMER_INCFG_CFGB7_Msk (0x8000UL) /*!< CTIMER INCFG: CFGB7 (Bitfield-Mask: 0x01) */ -#define CTIMER_INCFG_CFGA7_Pos (14UL) /*!< CTIMER INCFG: CFGA7 (Bit 14) */ -#define CTIMER_INCFG_CFGA7_Msk (0x4000UL) /*!< CTIMER INCFG: CFGA7 (Bitfield-Mask: 0x01) */ -#define CTIMER_INCFG_CFGB6_Pos (13UL) /*!< CTIMER INCFG: CFGB6 (Bit 13) */ -#define CTIMER_INCFG_CFGB6_Msk (0x2000UL) /*!< CTIMER INCFG: CFGB6 (Bitfield-Mask: 0x01) */ -#define CTIMER_INCFG_CFGA6_Pos (12UL) /*!< CTIMER INCFG: CFGA6 (Bit 12) */ -#define CTIMER_INCFG_CFGA6_Msk (0x1000UL) /*!< CTIMER INCFG: CFGA6 (Bitfield-Mask: 0x01) */ -#define CTIMER_INCFG_CFGB5_Pos (11UL) /*!< CTIMER INCFG: CFGB5 (Bit 11) */ -#define CTIMER_INCFG_CFGB5_Msk (0x800UL) /*!< CTIMER INCFG: CFGB5 (Bitfield-Mask: 0x01) */ -#define CTIMER_INCFG_CFGA5_Pos (10UL) /*!< CTIMER INCFG: CFGA5 (Bit 10) */ -#define CTIMER_INCFG_CFGA5_Msk (0x400UL) /*!< CTIMER INCFG: CFGA5 (Bitfield-Mask: 0x01) */ -#define CTIMER_INCFG_CFGB4_Pos (9UL) /*!< CTIMER INCFG: CFGB4 (Bit 9) */ -#define CTIMER_INCFG_CFGB4_Msk (0x200UL) /*!< CTIMER INCFG: CFGB4 (Bitfield-Mask: 0x01) */ -#define CTIMER_INCFG_CFGA4_Pos (8UL) /*!< CTIMER INCFG: CFGA4 (Bit 8) */ -#define CTIMER_INCFG_CFGA4_Msk (0x100UL) /*!< CTIMER INCFG: CFGA4 (Bitfield-Mask: 0x01) */ -#define CTIMER_INCFG_CFGB3_Pos (7UL) /*!< CTIMER INCFG: CFGB3 (Bit 7) */ -#define CTIMER_INCFG_CFGB3_Msk (0x80UL) /*!< CTIMER INCFG: CFGB3 (Bitfield-Mask: 0x01) */ -#define CTIMER_INCFG_CFGA3_Pos (6UL) /*!< CTIMER INCFG: CFGA3 (Bit 6) */ -#define CTIMER_INCFG_CFGA3_Msk (0x40UL) /*!< CTIMER INCFG: CFGA3 (Bitfield-Mask: 0x01) */ -#define CTIMER_INCFG_CFGB2_Pos (5UL) /*!< CTIMER INCFG: CFGB2 (Bit 5) */ -#define CTIMER_INCFG_CFGB2_Msk (0x20UL) /*!< CTIMER INCFG: CFGB2 (Bitfield-Mask: 0x01) */ -#define CTIMER_INCFG_CFGA2_Pos (4UL) /*!< CTIMER INCFG: CFGA2 (Bit 4) */ -#define CTIMER_INCFG_CFGA2_Msk (0x10UL) /*!< CTIMER INCFG: CFGA2 (Bitfield-Mask: 0x01) */ -#define CTIMER_INCFG_CFGB1_Pos (3UL) /*!< CTIMER INCFG: CFGB1 (Bit 3) */ -#define CTIMER_INCFG_CFGB1_Msk (0x8UL) /*!< CTIMER INCFG: CFGB1 (Bitfield-Mask: 0x01) */ -#define CTIMER_INCFG_CFGA1_Pos (2UL) /*!< CTIMER INCFG: CFGA1 (Bit 2) */ -#define CTIMER_INCFG_CFGA1_Msk (0x4UL) /*!< CTIMER INCFG: CFGA1 (Bitfield-Mask: 0x01) */ -#define CTIMER_INCFG_CFGB0_Pos (1UL) /*!< CTIMER INCFG: CFGB0 (Bit 1) */ -#define CTIMER_INCFG_CFGB0_Msk (0x2UL) /*!< CTIMER INCFG: CFGB0 (Bitfield-Mask: 0x01) */ -#define CTIMER_INCFG_CFGA0_Pos (0UL) /*!< CTIMER INCFG: CFGA0 (Bit 0) */ -#define CTIMER_INCFG_CFGA0_Msk (0x1UL) /*!< CTIMER INCFG: CFGA0 (Bitfield-Mask: 0x01) */ -/* ========================================================= STCFG ========================================================= */ -#define CTIMER_STCFG_FREEZE_Pos (31UL) /*!< CTIMER STCFG: FREEZE (Bit 31) */ -#define CTIMER_STCFG_FREEZE_Msk (0x80000000UL) /*!< CTIMER STCFG: FREEZE (Bitfield-Mask: 0x01) */ -#define CTIMER_STCFG_CLEAR_Pos (30UL) /*!< CTIMER STCFG: CLEAR (Bit 30) */ -#define CTIMER_STCFG_CLEAR_Msk (0x40000000UL) /*!< CTIMER STCFG: CLEAR (Bitfield-Mask: 0x01) */ -#define CTIMER_STCFG_COMPARE_H_EN_Pos (15UL) /*!< CTIMER STCFG: COMPARE_H_EN (Bit 15) */ -#define CTIMER_STCFG_COMPARE_H_EN_Msk (0x8000UL) /*!< CTIMER STCFG: COMPARE_H_EN (Bitfield-Mask: 0x01) */ -#define CTIMER_STCFG_COMPARE_G_EN_Pos (14UL) /*!< CTIMER STCFG: COMPARE_G_EN (Bit 14) */ -#define CTIMER_STCFG_COMPARE_G_EN_Msk (0x4000UL) /*!< CTIMER STCFG: COMPARE_G_EN (Bitfield-Mask: 0x01) */ -#define CTIMER_STCFG_COMPARE_F_EN_Pos (13UL) /*!< CTIMER STCFG: COMPARE_F_EN (Bit 13) */ -#define CTIMER_STCFG_COMPARE_F_EN_Msk (0x2000UL) /*!< CTIMER STCFG: COMPARE_F_EN (Bitfield-Mask: 0x01) */ -#define CTIMER_STCFG_COMPARE_E_EN_Pos (12UL) /*!< CTIMER STCFG: COMPARE_E_EN (Bit 12) */ -#define CTIMER_STCFG_COMPARE_E_EN_Msk (0x1000UL) /*!< CTIMER STCFG: COMPARE_E_EN (Bitfield-Mask: 0x01) */ -#define CTIMER_STCFG_COMPARE_D_EN_Pos (11UL) /*!< CTIMER STCFG: COMPARE_D_EN (Bit 11) */ -#define CTIMER_STCFG_COMPARE_D_EN_Msk (0x800UL) /*!< CTIMER STCFG: COMPARE_D_EN (Bitfield-Mask: 0x01) */ -#define CTIMER_STCFG_COMPARE_C_EN_Pos (10UL) /*!< CTIMER STCFG: COMPARE_C_EN (Bit 10) */ -#define CTIMER_STCFG_COMPARE_C_EN_Msk (0x400UL) /*!< CTIMER STCFG: COMPARE_C_EN (Bitfield-Mask: 0x01) */ -#define CTIMER_STCFG_COMPARE_B_EN_Pos (9UL) /*!< CTIMER STCFG: COMPARE_B_EN (Bit 9) */ -#define CTIMER_STCFG_COMPARE_B_EN_Msk (0x200UL) /*!< CTIMER STCFG: COMPARE_B_EN (Bitfield-Mask: 0x01) */ -#define CTIMER_STCFG_COMPARE_A_EN_Pos (8UL) /*!< CTIMER STCFG: COMPARE_A_EN (Bit 8) */ -#define CTIMER_STCFG_COMPARE_A_EN_Msk (0x100UL) /*!< CTIMER STCFG: COMPARE_A_EN (Bitfield-Mask: 0x01) */ -#define CTIMER_STCFG_CLKSEL_Pos (0UL) /*!< CTIMER STCFG: CLKSEL (Bit 0) */ -#define CTIMER_STCFG_CLKSEL_Msk (0xfUL) /*!< CTIMER STCFG: CLKSEL (Bitfield-Mask: 0x0f) */ -/* ========================================================= STTMR ========================================================= */ -#define CTIMER_STTMR_STTMR_Pos (0UL) /*!< CTIMER STTMR: STTMR (Bit 0) */ -#define CTIMER_STTMR_STTMR_Msk (0xffffffffUL) /*!< CTIMER STTMR: STTMR (Bitfield-Mask: 0xffffffff) */ -/* ==================================================== CAPTURECONTROL ===================================================== */ -#define CTIMER_CAPTURECONTROL_CAPTURE3_Pos (3UL) /*!< CTIMER CAPTURECONTROL: CAPTURE3 (Bit 3) */ -#define CTIMER_CAPTURECONTROL_CAPTURE3_Msk (0x8UL) /*!< CTIMER CAPTURECONTROL: CAPTURE3 (Bitfield-Mask: 0x01) */ -#define CTIMER_CAPTURECONTROL_CAPTURE2_Pos (2UL) /*!< CTIMER CAPTURECONTROL: CAPTURE2 (Bit 2) */ -#define CTIMER_CAPTURECONTROL_CAPTURE2_Msk (0x4UL) /*!< CTIMER CAPTURECONTROL: CAPTURE2 (Bitfield-Mask: 0x01) */ -#define CTIMER_CAPTURECONTROL_CAPTURE1_Pos (1UL) /*!< CTIMER CAPTURECONTROL: CAPTURE1 (Bit 1) */ -#define CTIMER_CAPTURECONTROL_CAPTURE1_Msk (0x2UL) /*!< CTIMER CAPTURECONTROL: CAPTURE1 (Bitfield-Mask: 0x01) */ -#define CTIMER_CAPTURECONTROL_CAPTURE0_Pos (0UL) /*!< CTIMER CAPTURECONTROL: CAPTURE0 (Bit 0) */ -#define CTIMER_CAPTURECONTROL_CAPTURE0_Msk (0x1UL) /*!< CTIMER CAPTURECONTROL: CAPTURE0 (Bitfield-Mask: 0x01) */ -/* ======================================================== SCMPR0 ========================================================= */ -#define CTIMER_SCMPR0_SCMPR0_Pos (0UL) /*!< CTIMER SCMPR0: SCMPR0 (Bit 0) */ -#define CTIMER_SCMPR0_SCMPR0_Msk (0xffffffffUL) /*!< CTIMER SCMPR0: SCMPR0 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SCMPR1 ========================================================= */ -#define CTIMER_SCMPR1_SCMPR1_Pos (0UL) /*!< CTIMER SCMPR1: SCMPR1 (Bit 0) */ -#define CTIMER_SCMPR1_SCMPR1_Msk (0xffffffffUL) /*!< CTIMER SCMPR1: SCMPR1 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SCMPR2 ========================================================= */ -#define CTIMER_SCMPR2_SCMPR2_Pos (0UL) /*!< CTIMER SCMPR2: SCMPR2 (Bit 0) */ -#define CTIMER_SCMPR2_SCMPR2_Msk (0xffffffffUL) /*!< CTIMER SCMPR2: SCMPR2 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SCMPR3 ========================================================= */ -#define CTIMER_SCMPR3_SCMPR3_Pos (0UL) /*!< CTIMER SCMPR3: SCMPR3 (Bit 0) */ -#define CTIMER_SCMPR3_SCMPR3_Msk (0xffffffffUL) /*!< CTIMER SCMPR3: SCMPR3 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SCMPR4 ========================================================= */ -#define CTIMER_SCMPR4_SCMPR4_Pos (0UL) /*!< CTIMER SCMPR4: SCMPR4 (Bit 0) */ -#define CTIMER_SCMPR4_SCMPR4_Msk (0xffffffffUL) /*!< CTIMER SCMPR4: SCMPR4 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SCMPR5 ========================================================= */ -#define CTIMER_SCMPR5_SCMPR5_Pos (0UL) /*!< CTIMER SCMPR5: SCMPR5 (Bit 0) */ -#define CTIMER_SCMPR5_SCMPR5_Msk (0xffffffffUL) /*!< CTIMER SCMPR5: SCMPR5 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SCMPR6 ========================================================= */ -#define CTIMER_SCMPR6_SCMPR6_Pos (0UL) /*!< CTIMER SCMPR6: SCMPR6 (Bit 0) */ -#define CTIMER_SCMPR6_SCMPR6_Msk (0xffffffffUL) /*!< CTIMER SCMPR6: SCMPR6 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SCMPR7 ========================================================= */ -#define CTIMER_SCMPR7_SCMPR7_Pos (0UL) /*!< CTIMER SCMPR7: SCMPR7 (Bit 0) */ -#define CTIMER_SCMPR7_SCMPR7_Msk (0xffffffffUL) /*!< CTIMER SCMPR7: SCMPR7 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SCAPT0 ========================================================= */ -#define CTIMER_SCAPT0_SCAPT0_Pos (0UL) /*!< CTIMER SCAPT0: SCAPT0 (Bit 0) */ -#define CTIMER_SCAPT0_SCAPT0_Msk (0xffffffffUL) /*!< CTIMER SCAPT0: SCAPT0 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SCAPT1 ========================================================= */ -#define CTIMER_SCAPT1_SCAPT1_Pos (0UL) /*!< CTIMER SCAPT1: SCAPT1 (Bit 0) */ -#define CTIMER_SCAPT1_SCAPT1_Msk (0xffffffffUL) /*!< CTIMER SCAPT1: SCAPT1 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SCAPT2 ========================================================= */ -#define CTIMER_SCAPT2_SCAPT2_Pos (0UL) /*!< CTIMER SCAPT2: SCAPT2 (Bit 0) */ -#define CTIMER_SCAPT2_SCAPT2_Msk (0xffffffffUL) /*!< CTIMER SCAPT2: SCAPT2 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== SCAPT3 ========================================================= */ -#define CTIMER_SCAPT3_SCAPT3_Pos (0UL) /*!< CTIMER SCAPT3: SCAPT3 (Bit 0) */ -#define CTIMER_SCAPT3_SCAPT3_Msk (0xffffffffUL) /*!< CTIMER SCAPT3: SCAPT3 (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= SNVR0 ========================================================= */ -#define CTIMER_SNVR0_SNVR0_Pos (0UL) /*!< CTIMER SNVR0: SNVR0 (Bit 0) */ -#define CTIMER_SNVR0_SNVR0_Msk (0xffffffffUL) /*!< CTIMER SNVR0: SNVR0 (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= SNVR1 ========================================================= */ -#define CTIMER_SNVR1_SNVR1_Pos (0UL) /*!< CTIMER SNVR1: SNVR1 (Bit 0) */ -#define CTIMER_SNVR1_SNVR1_Msk (0xffffffffUL) /*!< CTIMER SNVR1: SNVR1 (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= SNVR2 ========================================================= */ -#define CTIMER_SNVR2_SNVR2_Pos (0UL) /*!< CTIMER SNVR2: SNVR2 (Bit 0) */ -#define CTIMER_SNVR2_SNVR2_Msk (0xffffffffUL) /*!< CTIMER SNVR2: SNVR2 (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= SNVR3 ========================================================= */ -#define CTIMER_SNVR3_SNVR3_Pos (0UL) /*!< CTIMER SNVR3: SNVR3 (Bit 0) */ -#define CTIMER_SNVR3_SNVR3_Msk (0xffffffffUL) /*!< CTIMER SNVR3: SNVR3 (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= INTEN ========================================================= */ -#define CTIMER_INTEN_CTMRB7C1INT_Pos (31UL) /*!< CTIMER INTEN: CTMRB7C1INT (Bit 31) */ -#define CTIMER_INTEN_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTIMER INTEN: CTMRB7C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA7C1INT_Pos (30UL) /*!< CTIMER INTEN: CTMRA7C1INT (Bit 30) */ -#define CTIMER_INTEN_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTIMER INTEN: CTMRA7C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRB6C1INT_Pos (29UL) /*!< CTIMER INTEN: CTMRB6C1INT (Bit 29) */ -#define CTIMER_INTEN_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTIMER INTEN: CTMRB6C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA6C1INT_Pos (28UL) /*!< CTIMER INTEN: CTMRA6C1INT (Bit 28) */ -#define CTIMER_INTEN_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTIMER INTEN: CTMRA6C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRB5C1INT_Pos (27UL) /*!< CTIMER INTEN: CTMRB5C1INT (Bit 27) */ -#define CTIMER_INTEN_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTIMER INTEN: CTMRB5C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA5C1INT_Pos (26UL) /*!< CTIMER INTEN: CTMRA5C1INT (Bit 26) */ -#define CTIMER_INTEN_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTIMER INTEN: CTMRA5C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRB4C1INT_Pos (25UL) /*!< CTIMER INTEN: CTMRB4C1INT (Bit 25) */ -#define CTIMER_INTEN_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTIMER INTEN: CTMRB4C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA4C1INT_Pos (24UL) /*!< CTIMER INTEN: CTMRA4C1INT (Bit 24) */ -#define CTIMER_INTEN_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTIMER INTEN: CTMRA4C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRB3C1INT_Pos (23UL) /*!< CTIMER INTEN: CTMRB3C1INT (Bit 23) */ -#define CTIMER_INTEN_CTMRB3C1INT_Msk (0x800000UL) /*!< CTIMER INTEN: CTMRB3C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA3C1INT_Pos (22UL) /*!< CTIMER INTEN: CTMRA3C1INT (Bit 22) */ -#define CTIMER_INTEN_CTMRA3C1INT_Msk (0x400000UL) /*!< CTIMER INTEN: CTMRA3C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRB2C1INT_Pos (21UL) /*!< CTIMER INTEN: CTMRB2C1INT (Bit 21) */ -#define CTIMER_INTEN_CTMRB2C1INT_Msk (0x200000UL) /*!< CTIMER INTEN: CTMRB2C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA2C1INT_Pos (20UL) /*!< CTIMER INTEN: CTMRA2C1INT (Bit 20) */ -#define CTIMER_INTEN_CTMRA2C1INT_Msk (0x100000UL) /*!< CTIMER INTEN: CTMRA2C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRB1C1INT_Pos (19UL) /*!< CTIMER INTEN: CTMRB1C1INT (Bit 19) */ -#define CTIMER_INTEN_CTMRB1C1INT_Msk (0x80000UL) /*!< CTIMER INTEN: CTMRB1C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA1C1INT_Pos (18UL) /*!< CTIMER INTEN: CTMRA1C1INT (Bit 18) */ -#define CTIMER_INTEN_CTMRA1C1INT_Msk (0x40000UL) /*!< CTIMER INTEN: CTMRA1C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRB0C1INT_Pos (17UL) /*!< CTIMER INTEN: CTMRB0C1INT (Bit 17) */ -#define CTIMER_INTEN_CTMRB0C1INT_Msk (0x20000UL) /*!< CTIMER INTEN: CTMRB0C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA0C1INT_Pos (16UL) /*!< CTIMER INTEN: CTMRA0C1INT (Bit 16) */ -#define CTIMER_INTEN_CTMRA0C1INT_Msk (0x10000UL) /*!< CTIMER INTEN: CTMRA0C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRB7C0INT_Pos (15UL) /*!< CTIMER INTEN: CTMRB7C0INT (Bit 15) */ -#define CTIMER_INTEN_CTMRB7C0INT_Msk (0x8000UL) /*!< CTIMER INTEN: CTMRB7C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA7C0INT_Pos (14UL) /*!< CTIMER INTEN: CTMRA7C0INT (Bit 14) */ -#define CTIMER_INTEN_CTMRA7C0INT_Msk (0x4000UL) /*!< CTIMER INTEN: CTMRA7C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRB6C0INT_Pos (13UL) /*!< CTIMER INTEN: CTMRB6C0INT (Bit 13) */ -#define CTIMER_INTEN_CTMRB6C0INT_Msk (0x2000UL) /*!< CTIMER INTEN: CTMRB6C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA6C0INT_Pos (12UL) /*!< CTIMER INTEN: CTMRA6C0INT (Bit 12) */ -#define CTIMER_INTEN_CTMRA6C0INT_Msk (0x1000UL) /*!< CTIMER INTEN: CTMRA6C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRB5C0INT_Pos (11UL) /*!< CTIMER INTEN: CTMRB5C0INT (Bit 11) */ -#define CTIMER_INTEN_CTMRB5C0INT_Msk (0x800UL) /*!< CTIMER INTEN: CTMRB5C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA5C0INT_Pos (10UL) /*!< CTIMER INTEN: CTMRA5C0INT (Bit 10) */ -#define CTIMER_INTEN_CTMRA5C0INT_Msk (0x400UL) /*!< CTIMER INTEN: CTMRA5C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRB4C0INT_Pos (9UL) /*!< CTIMER INTEN: CTMRB4C0INT (Bit 9) */ -#define CTIMER_INTEN_CTMRB4C0INT_Msk (0x200UL) /*!< CTIMER INTEN: CTMRB4C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA4C0INT_Pos (8UL) /*!< CTIMER INTEN: CTMRA4C0INT (Bit 8) */ -#define CTIMER_INTEN_CTMRA4C0INT_Msk (0x100UL) /*!< CTIMER INTEN: CTMRA4C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRB3C0INT_Pos (7UL) /*!< CTIMER INTEN: CTMRB3C0INT (Bit 7) */ -#define CTIMER_INTEN_CTMRB3C0INT_Msk (0x80UL) /*!< CTIMER INTEN: CTMRB3C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA3C0INT_Pos (6UL) /*!< CTIMER INTEN: CTMRA3C0INT (Bit 6) */ -#define CTIMER_INTEN_CTMRA3C0INT_Msk (0x40UL) /*!< CTIMER INTEN: CTMRA3C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRB2C0INT_Pos (5UL) /*!< CTIMER INTEN: CTMRB2C0INT (Bit 5) */ -#define CTIMER_INTEN_CTMRB2C0INT_Msk (0x20UL) /*!< CTIMER INTEN: CTMRB2C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA2C0INT_Pos (4UL) /*!< CTIMER INTEN: CTMRA2C0INT (Bit 4) */ -#define CTIMER_INTEN_CTMRA2C0INT_Msk (0x10UL) /*!< CTIMER INTEN: CTMRA2C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRB1C0INT_Pos (3UL) /*!< CTIMER INTEN: CTMRB1C0INT (Bit 3) */ -#define CTIMER_INTEN_CTMRB1C0INT_Msk (0x8UL) /*!< CTIMER INTEN: CTMRB1C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA1C0INT_Pos (2UL) /*!< CTIMER INTEN: CTMRA1C0INT (Bit 2) */ -#define CTIMER_INTEN_CTMRA1C0INT_Msk (0x4UL) /*!< CTIMER INTEN: CTMRA1C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRB0C0INT_Pos (1UL) /*!< CTIMER INTEN: CTMRB0C0INT (Bit 1) */ -#define CTIMER_INTEN_CTMRB0C0INT_Msk (0x2UL) /*!< CTIMER INTEN: CTMRB0C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTEN_CTMRA0C0INT_Pos (0UL) /*!< CTIMER INTEN: CTMRA0C0INT (Bit 0) */ -#define CTIMER_INTEN_CTMRA0C0INT_Msk (0x1UL) /*!< CTIMER INTEN: CTMRA0C0INT (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTAT ======================================================== */ -#define CTIMER_INTSTAT_CTMRB7C1INT_Pos (31UL) /*!< CTIMER INTSTAT: CTMRB7C1INT (Bit 31) */ -#define CTIMER_INTSTAT_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTIMER INTSTAT: CTMRB7C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA7C1INT_Pos (30UL) /*!< CTIMER INTSTAT: CTMRA7C1INT (Bit 30) */ -#define CTIMER_INTSTAT_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTIMER INTSTAT: CTMRA7C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRB6C1INT_Pos (29UL) /*!< CTIMER INTSTAT: CTMRB6C1INT (Bit 29) */ -#define CTIMER_INTSTAT_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTIMER INTSTAT: CTMRB6C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA6C1INT_Pos (28UL) /*!< CTIMER INTSTAT: CTMRA6C1INT (Bit 28) */ -#define CTIMER_INTSTAT_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTIMER INTSTAT: CTMRA6C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRB5C1INT_Pos (27UL) /*!< CTIMER INTSTAT: CTMRB5C1INT (Bit 27) */ -#define CTIMER_INTSTAT_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTIMER INTSTAT: CTMRB5C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA5C1INT_Pos (26UL) /*!< CTIMER INTSTAT: CTMRA5C1INT (Bit 26) */ -#define CTIMER_INTSTAT_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTIMER INTSTAT: CTMRA5C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRB4C1INT_Pos (25UL) /*!< CTIMER INTSTAT: CTMRB4C1INT (Bit 25) */ -#define CTIMER_INTSTAT_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTIMER INTSTAT: CTMRB4C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA4C1INT_Pos (24UL) /*!< CTIMER INTSTAT: CTMRA4C1INT (Bit 24) */ -#define CTIMER_INTSTAT_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTIMER INTSTAT: CTMRA4C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRB3C1INT_Pos (23UL) /*!< CTIMER INTSTAT: CTMRB3C1INT (Bit 23) */ -#define CTIMER_INTSTAT_CTMRB3C1INT_Msk (0x800000UL) /*!< CTIMER INTSTAT: CTMRB3C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA3C1INT_Pos (22UL) /*!< CTIMER INTSTAT: CTMRA3C1INT (Bit 22) */ -#define CTIMER_INTSTAT_CTMRA3C1INT_Msk (0x400000UL) /*!< CTIMER INTSTAT: CTMRA3C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRB2C1INT_Pos (21UL) /*!< CTIMER INTSTAT: CTMRB2C1INT (Bit 21) */ -#define CTIMER_INTSTAT_CTMRB2C1INT_Msk (0x200000UL) /*!< CTIMER INTSTAT: CTMRB2C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA2C1INT_Pos (20UL) /*!< CTIMER INTSTAT: CTMRA2C1INT (Bit 20) */ -#define CTIMER_INTSTAT_CTMRA2C1INT_Msk (0x100000UL) /*!< CTIMER INTSTAT: CTMRA2C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRB1C1INT_Pos (19UL) /*!< CTIMER INTSTAT: CTMRB1C1INT (Bit 19) */ -#define CTIMER_INTSTAT_CTMRB1C1INT_Msk (0x80000UL) /*!< CTIMER INTSTAT: CTMRB1C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA1C1INT_Pos (18UL) /*!< CTIMER INTSTAT: CTMRA1C1INT (Bit 18) */ -#define CTIMER_INTSTAT_CTMRA1C1INT_Msk (0x40000UL) /*!< CTIMER INTSTAT: CTMRA1C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRB0C1INT_Pos (17UL) /*!< CTIMER INTSTAT: CTMRB0C1INT (Bit 17) */ -#define CTIMER_INTSTAT_CTMRB0C1INT_Msk (0x20000UL) /*!< CTIMER INTSTAT: CTMRB0C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA0C1INT_Pos (16UL) /*!< CTIMER INTSTAT: CTMRA0C1INT (Bit 16) */ -#define CTIMER_INTSTAT_CTMRA0C1INT_Msk (0x10000UL) /*!< CTIMER INTSTAT: CTMRA0C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRB7C0INT_Pos (15UL) /*!< CTIMER INTSTAT: CTMRB7C0INT (Bit 15) */ -#define CTIMER_INTSTAT_CTMRB7C0INT_Msk (0x8000UL) /*!< CTIMER INTSTAT: CTMRB7C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA7C0INT_Pos (14UL) /*!< CTIMER INTSTAT: CTMRA7C0INT (Bit 14) */ -#define CTIMER_INTSTAT_CTMRA7C0INT_Msk (0x4000UL) /*!< CTIMER INTSTAT: CTMRA7C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRB6C0INT_Pos (13UL) /*!< CTIMER INTSTAT: CTMRB6C0INT (Bit 13) */ -#define CTIMER_INTSTAT_CTMRB6C0INT_Msk (0x2000UL) /*!< CTIMER INTSTAT: CTMRB6C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA6C0INT_Pos (12UL) /*!< CTIMER INTSTAT: CTMRA6C0INT (Bit 12) */ -#define CTIMER_INTSTAT_CTMRA6C0INT_Msk (0x1000UL) /*!< CTIMER INTSTAT: CTMRA6C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRB5C0INT_Pos (11UL) /*!< CTIMER INTSTAT: CTMRB5C0INT (Bit 11) */ -#define CTIMER_INTSTAT_CTMRB5C0INT_Msk (0x800UL) /*!< CTIMER INTSTAT: CTMRB5C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA5C0INT_Pos (10UL) /*!< CTIMER INTSTAT: CTMRA5C0INT (Bit 10) */ -#define CTIMER_INTSTAT_CTMRA5C0INT_Msk (0x400UL) /*!< CTIMER INTSTAT: CTMRA5C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRB4C0INT_Pos (9UL) /*!< CTIMER INTSTAT: CTMRB4C0INT (Bit 9) */ -#define CTIMER_INTSTAT_CTMRB4C0INT_Msk (0x200UL) /*!< CTIMER INTSTAT: CTMRB4C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA4C0INT_Pos (8UL) /*!< CTIMER INTSTAT: CTMRA4C0INT (Bit 8) */ -#define CTIMER_INTSTAT_CTMRA4C0INT_Msk (0x100UL) /*!< CTIMER INTSTAT: CTMRA4C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRB3C0INT_Pos (7UL) /*!< CTIMER INTSTAT: CTMRB3C0INT (Bit 7) */ -#define CTIMER_INTSTAT_CTMRB3C0INT_Msk (0x80UL) /*!< CTIMER INTSTAT: CTMRB3C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA3C0INT_Pos (6UL) /*!< CTIMER INTSTAT: CTMRA3C0INT (Bit 6) */ -#define CTIMER_INTSTAT_CTMRA3C0INT_Msk (0x40UL) /*!< CTIMER INTSTAT: CTMRA3C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRB2C0INT_Pos (5UL) /*!< CTIMER INTSTAT: CTMRB2C0INT (Bit 5) */ -#define CTIMER_INTSTAT_CTMRB2C0INT_Msk (0x20UL) /*!< CTIMER INTSTAT: CTMRB2C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA2C0INT_Pos (4UL) /*!< CTIMER INTSTAT: CTMRA2C0INT (Bit 4) */ -#define CTIMER_INTSTAT_CTMRA2C0INT_Msk (0x10UL) /*!< CTIMER INTSTAT: CTMRA2C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRB1C0INT_Pos (3UL) /*!< CTIMER INTSTAT: CTMRB1C0INT (Bit 3) */ -#define CTIMER_INTSTAT_CTMRB1C0INT_Msk (0x8UL) /*!< CTIMER INTSTAT: CTMRB1C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA1C0INT_Pos (2UL) /*!< CTIMER INTSTAT: CTMRA1C0INT (Bit 2) */ -#define CTIMER_INTSTAT_CTMRA1C0INT_Msk (0x4UL) /*!< CTIMER INTSTAT: CTMRA1C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRB0C0INT_Pos (1UL) /*!< CTIMER INTSTAT: CTMRB0C0INT (Bit 1) */ -#define CTIMER_INTSTAT_CTMRB0C0INT_Msk (0x2UL) /*!< CTIMER INTSTAT: CTMRB0C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSTAT_CTMRA0C0INT_Pos (0UL) /*!< CTIMER INTSTAT: CTMRA0C0INT (Bit 0) */ -#define CTIMER_INTSTAT_CTMRA0C0INT_Msk (0x1UL) /*!< CTIMER INTSTAT: CTMRA0C0INT (Bitfield-Mask: 0x01) */ -/* ======================================================== INTCLR ========================================================= */ -#define CTIMER_INTCLR_CTMRB7C1INT_Pos (31UL) /*!< CTIMER INTCLR: CTMRB7C1INT (Bit 31) */ -#define CTIMER_INTCLR_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTIMER INTCLR: CTMRB7C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA7C1INT_Pos (30UL) /*!< CTIMER INTCLR: CTMRA7C1INT (Bit 30) */ -#define CTIMER_INTCLR_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTIMER INTCLR: CTMRA7C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRB6C1INT_Pos (29UL) /*!< CTIMER INTCLR: CTMRB6C1INT (Bit 29) */ -#define CTIMER_INTCLR_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTIMER INTCLR: CTMRB6C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA6C1INT_Pos (28UL) /*!< CTIMER INTCLR: CTMRA6C1INT (Bit 28) */ -#define CTIMER_INTCLR_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTIMER INTCLR: CTMRA6C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRB5C1INT_Pos (27UL) /*!< CTIMER INTCLR: CTMRB5C1INT (Bit 27) */ -#define CTIMER_INTCLR_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTIMER INTCLR: CTMRB5C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA5C1INT_Pos (26UL) /*!< CTIMER INTCLR: CTMRA5C1INT (Bit 26) */ -#define CTIMER_INTCLR_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTIMER INTCLR: CTMRA5C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRB4C1INT_Pos (25UL) /*!< CTIMER INTCLR: CTMRB4C1INT (Bit 25) */ -#define CTIMER_INTCLR_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTIMER INTCLR: CTMRB4C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA4C1INT_Pos (24UL) /*!< CTIMER INTCLR: CTMRA4C1INT (Bit 24) */ -#define CTIMER_INTCLR_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTIMER INTCLR: CTMRA4C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRB3C1INT_Pos (23UL) /*!< CTIMER INTCLR: CTMRB3C1INT (Bit 23) */ -#define CTIMER_INTCLR_CTMRB3C1INT_Msk (0x800000UL) /*!< CTIMER INTCLR: CTMRB3C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA3C1INT_Pos (22UL) /*!< CTIMER INTCLR: CTMRA3C1INT (Bit 22) */ -#define CTIMER_INTCLR_CTMRA3C1INT_Msk (0x400000UL) /*!< CTIMER INTCLR: CTMRA3C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRB2C1INT_Pos (21UL) /*!< CTIMER INTCLR: CTMRB2C1INT (Bit 21) */ -#define CTIMER_INTCLR_CTMRB2C1INT_Msk (0x200000UL) /*!< CTIMER INTCLR: CTMRB2C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA2C1INT_Pos (20UL) /*!< CTIMER INTCLR: CTMRA2C1INT (Bit 20) */ -#define CTIMER_INTCLR_CTMRA2C1INT_Msk (0x100000UL) /*!< CTIMER INTCLR: CTMRA2C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRB1C1INT_Pos (19UL) /*!< CTIMER INTCLR: CTMRB1C1INT (Bit 19) */ -#define CTIMER_INTCLR_CTMRB1C1INT_Msk (0x80000UL) /*!< CTIMER INTCLR: CTMRB1C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA1C1INT_Pos (18UL) /*!< CTIMER INTCLR: CTMRA1C1INT (Bit 18) */ -#define CTIMER_INTCLR_CTMRA1C1INT_Msk (0x40000UL) /*!< CTIMER INTCLR: CTMRA1C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRB0C1INT_Pos (17UL) /*!< CTIMER INTCLR: CTMRB0C1INT (Bit 17) */ -#define CTIMER_INTCLR_CTMRB0C1INT_Msk (0x20000UL) /*!< CTIMER INTCLR: CTMRB0C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA0C1INT_Pos (16UL) /*!< CTIMER INTCLR: CTMRA0C1INT (Bit 16) */ -#define CTIMER_INTCLR_CTMRA0C1INT_Msk (0x10000UL) /*!< CTIMER INTCLR: CTMRA0C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRB7C0INT_Pos (15UL) /*!< CTIMER INTCLR: CTMRB7C0INT (Bit 15) */ -#define CTIMER_INTCLR_CTMRB7C0INT_Msk (0x8000UL) /*!< CTIMER INTCLR: CTMRB7C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA7C0INT_Pos (14UL) /*!< CTIMER INTCLR: CTMRA7C0INT (Bit 14) */ -#define CTIMER_INTCLR_CTMRA7C0INT_Msk (0x4000UL) /*!< CTIMER INTCLR: CTMRA7C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRB6C0INT_Pos (13UL) /*!< CTIMER INTCLR: CTMRB6C0INT (Bit 13) */ -#define CTIMER_INTCLR_CTMRB6C0INT_Msk (0x2000UL) /*!< CTIMER INTCLR: CTMRB6C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA6C0INT_Pos (12UL) /*!< CTIMER INTCLR: CTMRA6C0INT (Bit 12) */ -#define CTIMER_INTCLR_CTMRA6C0INT_Msk (0x1000UL) /*!< CTIMER INTCLR: CTMRA6C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRB5C0INT_Pos (11UL) /*!< CTIMER INTCLR: CTMRB5C0INT (Bit 11) */ -#define CTIMER_INTCLR_CTMRB5C0INT_Msk (0x800UL) /*!< CTIMER INTCLR: CTMRB5C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA5C0INT_Pos (10UL) /*!< CTIMER INTCLR: CTMRA5C0INT (Bit 10) */ -#define CTIMER_INTCLR_CTMRA5C0INT_Msk (0x400UL) /*!< CTIMER INTCLR: CTMRA5C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRB4C0INT_Pos (9UL) /*!< CTIMER INTCLR: CTMRB4C0INT (Bit 9) */ -#define CTIMER_INTCLR_CTMRB4C0INT_Msk (0x200UL) /*!< CTIMER INTCLR: CTMRB4C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA4C0INT_Pos (8UL) /*!< CTIMER INTCLR: CTMRA4C0INT (Bit 8) */ -#define CTIMER_INTCLR_CTMRA4C0INT_Msk (0x100UL) /*!< CTIMER INTCLR: CTMRA4C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRB3C0INT_Pos (7UL) /*!< CTIMER INTCLR: CTMRB3C0INT (Bit 7) */ -#define CTIMER_INTCLR_CTMRB3C0INT_Msk (0x80UL) /*!< CTIMER INTCLR: CTMRB3C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA3C0INT_Pos (6UL) /*!< CTIMER INTCLR: CTMRA3C0INT (Bit 6) */ -#define CTIMER_INTCLR_CTMRA3C0INT_Msk (0x40UL) /*!< CTIMER INTCLR: CTMRA3C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRB2C0INT_Pos (5UL) /*!< CTIMER INTCLR: CTMRB2C0INT (Bit 5) */ -#define CTIMER_INTCLR_CTMRB2C0INT_Msk (0x20UL) /*!< CTIMER INTCLR: CTMRB2C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA2C0INT_Pos (4UL) /*!< CTIMER INTCLR: CTMRA2C0INT (Bit 4) */ -#define CTIMER_INTCLR_CTMRA2C0INT_Msk (0x10UL) /*!< CTIMER INTCLR: CTMRA2C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRB1C0INT_Pos (3UL) /*!< CTIMER INTCLR: CTMRB1C0INT (Bit 3) */ -#define CTIMER_INTCLR_CTMRB1C0INT_Msk (0x8UL) /*!< CTIMER INTCLR: CTMRB1C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA1C0INT_Pos (2UL) /*!< CTIMER INTCLR: CTMRA1C0INT (Bit 2) */ -#define CTIMER_INTCLR_CTMRA1C0INT_Msk (0x4UL) /*!< CTIMER INTCLR: CTMRA1C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRB0C0INT_Pos (1UL) /*!< CTIMER INTCLR: CTMRB0C0INT (Bit 1) */ -#define CTIMER_INTCLR_CTMRB0C0INT_Msk (0x2UL) /*!< CTIMER INTCLR: CTMRB0C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTCLR_CTMRA0C0INT_Pos (0UL) /*!< CTIMER INTCLR: CTMRA0C0INT (Bit 0) */ -#define CTIMER_INTCLR_CTMRA0C0INT_Msk (0x1UL) /*!< CTIMER INTCLR: CTMRA0C0INT (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSET ========================================================= */ -#define CTIMER_INTSET_CTMRB7C1INT_Pos (31UL) /*!< CTIMER INTSET: CTMRB7C1INT (Bit 31) */ -#define CTIMER_INTSET_CTMRB7C1INT_Msk (0x80000000UL) /*!< CTIMER INTSET: CTMRB7C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA7C1INT_Pos (30UL) /*!< CTIMER INTSET: CTMRA7C1INT (Bit 30) */ -#define CTIMER_INTSET_CTMRA7C1INT_Msk (0x40000000UL) /*!< CTIMER INTSET: CTMRA7C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRB6C1INT_Pos (29UL) /*!< CTIMER INTSET: CTMRB6C1INT (Bit 29) */ -#define CTIMER_INTSET_CTMRB6C1INT_Msk (0x20000000UL) /*!< CTIMER INTSET: CTMRB6C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA6C1INT_Pos (28UL) /*!< CTIMER INTSET: CTMRA6C1INT (Bit 28) */ -#define CTIMER_INTSET_CTMRA6C1INT_Msk (0x10000000UL) /*!< CTIMER INTSET: CTMRA6C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRB5C1INT_Pos (27UL) /*!< CTIMER INTSET: CTMRB5C1INT (Bit 27) */ -#define CTIMER_INTSET_CTMRB5C1INT_Msk (0x8000000UL) /*!< CTIMER INTSET: CTMRB5C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA5C1INT_Pos (26UL) /*!< CTIMER INTSET: CTMRA5C1INT (Bit 26) */ -#define CTIMER_INTSET_CTMRA5C1INT_Msk (0x4000000UL) /*!< CTIMER INTSET: CTMRA5C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRB4C1INT_Pos (25UL) /*!< CTIMER INTSET: CTMRB4C1INT (Bit 25) */ -#define CTIMER_INTSET_CTMRB4C1INT_Msk (0x2000000UL) /*!< CTIMER INTSET: CTMRB4C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA4C1INT_Pos (24UL) /*!< CTIMER INTSET: CTMRA4C1INT (Bit 24) */ -#define CTIMER_INTSET_CTMRA4C1INT_Msk (0x1000000UL) /*!< CTIMER INTSET: CTMRA4C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRB3C1INT_Pos (23UL) /*!< CTIMER INTSET: CTMRB3C1INT (Bit 23) */ -#define CTIMER_INTSET_CTMRB3C1INT_Msk (0x800000UL) /*!< CTIMER INTSET: CTMRB3C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA3C1INT_Pos (22UL) /*!< CTIMER INTSET: CTMRA3C1INT (Bit 22) */ -#define CTIMER_INTSET_CTMRA3C1INT_Msk (0x400000UL) /*!< CTIMER INTSET: CTMRA3C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRB2C1INT_Pos (21UL) /*!< CTIMER INTSET: CTMRB2C1INT (Bit 21) */ -#define CTIMER_INTSET_CTMRB2C1INT_Msk (0x200000UL) /*!< CTIMER INTSET: CTMRB2C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA2C1INT_Pos (20UL) /*!< CTIMER INTSET: CTMRA2C1INT (Bit 20) */ -#define CTIMER_INTSET_CTMRA2C1INT_Msk (0x100000UL) /*!< CTIMER INTSET: CTMRA2C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRB1C1INT_Pos (19UL) /*!< CTIMER INTSET: CTMRB1C1INT (Bit 19) */ -#define CTIMER_INTSET_CTMRB1C1INT_Msk (0x80000UL) /*!< CTIMER INTSET: CTMRB1C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA1C1INT_Pos (18UL) /*!< CTIMER INTSET: CTMRA1C1INT (Bit 18) */ -#define CTIMER_INTSET_CTMRA1C1INT_Msk (0x40000UL) /*!< CTIMER INTSET: CTMRA1C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRB0C1INT_Pos (17UL) /*!< CTIMER INTSET: CTMRB0C1INT (Bit 17) */ -#define CTIMER_INTSET_CTMRB0C1INT_Msk (0x20000UL) /*!< CTIMER INTSET: CTMRB0C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA0C1INT_Pos (16UL) /*!< CTIMER INTSET: CTMRA0C1INT (Bit 16) */ -#define CTIMER_INTSET_CTMRA0C1INT_Msk (0x10000UL) /*!< CTIMER INTSET: CTMRA0C1INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRB7C0INT_Pos (15UL) /*!< CTIMER INTSET: CTMRB7C0INT (Bit 15) */ -#define CTIMER_INTSET_CTMRB7C0INT_Msk (0x8000UL) /*!< CTIMER INTSET: CTMRB7C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA7C0INT_Pos (14UL) /*!< CTIMER INTSET: CTMRA7C0INT (Bit 14) */ -#define CTIMER_INTSET_CTMRA7C0INT_Msk (0x4000UL) /*!< CTIMER INTSET: CTMRA7C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRB6C0INT_Pos (13UL) /*!< CTIMER INTSET: CTMRB6C0INT (Bit 13) */ -#define CTIMER_INTSET_CTMRB6C0INT_Msk (0x2000UL) /*!< CTIMER INTSET: CTMRB6C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA6C0INT_Pos (12UL) /*!< CTIMER INTSET: CTMRA6C0INT (Bit 12) */ -#define CTIMER_INTSET_CTMRA6C0INT_Msk (0x1000UL) /*!< CTIMER INTSET: CTMRA6C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRB5C0INT_Pos (11UL) /*!< CTIMER INTSET: CTMRB5C0INT (Bit 11) */ -#define CTIMER_INTSET_CTMRB5C0INT_Msk (0x800UL) /*!< CTIMER INTSET: CTMRB5C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA5C0INT_Pos (10UL) /*!< CTIMER INTSET: CTMRA5C0INT (Bit 10) */ -#define CTIMER_INTSET_CTMRA5C0INT_Msk (0x400UL) /*!< CTIMER INTSET: CTMRA5C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRB4C0INT_Pos (9UL) /*!< CTIMER INTSET: CTMRB4C0INT (Bit 9) */ -#define CTIMER_INTSET_CTMRB4C0INT_Msk (0x200UL) /*!< CTIMER INTSET: CTMRB4C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA4C0INT_Pos (8UL) /*!< CTIMER INTSET: CTMRA4C0INT (Bit 8) */ -#define CTIMER_INTSET_CTMRA4C0INT_Msk (0x100UL) /*!< CTIMER INTSET: CTMRA4C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRB3C0INT_Pos (7UL) /*!< CTIMER INTSET: CTMRB3C0INT (Bit 7) */ -#define CTIMER_INTSET_CTMRB3C0INT_Msk (0x80UL) /*!< CTIMER INTSET: CTMRB3C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA3C0INT_Pos (6UL) /*!< CTIMER INTSET: CTMRA3C0INT (Bit 6) */ -#define CTIMER_INTSET_CTMRA3C0INT_Msk (0x40UL) /*!< CTIMER INTSET: CTMRA3C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRB2C0INT_Pos (5UL) /*!< CTIMER INTSET: CTMRB2C0INT (Bit 5) */ -#define CTIMER_INTSET_CTMRB2C0INT_Msk (0x20UL) /*!< CTIMER INTSET: CTMRB2C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA2C0INT_Pos (4UL) /*!< CTIMER INTSET: CTMRA2C0INT (Bit 4) */ -#define CTIMER_INTSET_CTMRA2C0INT_Msk (0x10UL) /*!< CTIMER INTSET: CTMRA2C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRB1C0INT_Pos (3UL) /*!< CTIMER INTSET: CTMRB1C0INT (Bit 3) */ -#define CTIMER_INTSET_CTMRB1C0INT_Msk (0x8UL) /*!< CTIMER INTSET: CTMRB1C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA1C0INT_Pos (2UL) /*!< CTIMER INTSET: CTMRA1C0INT (Bit 2) */ -#define CTIMER_INTSET_CTMRA1C0INT_Msk (0x4UL) /*!< CTIMER INTSET: CTMRA1C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRB0C0INT_Pos (1UL) /*!< CTIMER INTSET: CTMRB0C0INT (Bit 1) */ -#define CTIMER_INTSET_CTMRB0C0INT_Msk (0x2UL) /*!< CTIMER INTSET: CTMRB0C0INT (Bitfield-Mask: 0x01) */ -#define CTIMER_INTSET_CTMRA0C0INT_Pos (0UL) /*!< CTIMER INTSET: CTMRA0C0INT (Bit 0) */ -#define CTIMER_INTSET_CTMRA0C0INT_Msk (0x1UL) /*!< CTIMER INTSET: CTMRA0C0INT (Bitfield-Mask: 0x01) */ -/* ======================================================= STMINTEN ======================================================== */ -#define CTIMER_STMINTEN_CAPTURED_Pos (12UL) /*!< CTIMER STMINTEN: CAPTURED (Bit 12) */ -#define CTIMER_STMINTEN_CAPTURED_Msk (0x1000UL) /*!< CTIMER STMINTEN: CAPTURED (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTEN_CAPTUREC_Pos (11UL) /*!< CTIMER STMINTEN: CAPTUREC (Bit 11) */ -#define CTIMER_STMINTEN_CAPTUREC_Msk (0x800UL) /*!< CTIMER STMINTEN: CAPTUREC (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTEN_CAPTUREB_Pos (10UL) /*!< CTIMER STMINTEN: CAPTUREB (Bit 10) */ -#define CTIMER_STMINTEN_CAPTUREB_Msk (0x400UL) /*!< CTIMER STMINTEN: CAPTUREB (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTEN_CAPTUREA_Pos (9UL) /*!< CTIMER STMINTEN: CAPTUREA (Bit 9) */ -#define CTIMER_STMINTEN_CAPTUREA_Msk (0x200UL) /*!< CTIMER STMINTEN: CAPTUREA (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTEN_OVERFLOW_Pos (8UL) /*!< CTIMER STMINTEN: OVERFLOW (Bit 8) */ -#define CTIMER_STMINTEN_OVERFLOW_Msk (0x100UL) /*!< CTIMER STMINTEN: OVERFLOW (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTEN_COMPAREH_Pos (7UL) /*!< CTIMER STMINTEN: COMPAREH (Bit 7) */ -#define CTIMER_STMINTEN_COMPAREH_Msk (0x80UL) /*!< CTIMER STMINTEN: COMPAREH (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTEN_COMPAREG_Pos (6UL) /*!< CTIMER STMINTEN: COMPAREG (Bit 6) */ -#define CTIMER_STMINTEN_COMPAREG_Msk (0x40UL) /*!< CTIMER STMINTEN: COMPAREG (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTEN_COMPAREF_Pos (5UL) /*!< CTIMER STMINTEN: COMPAREF (Bit 5) */ -#define CTIMER_STMINTEN_COMPAREF_Msk (0x20UL) /*!< CTIMER STMINTEN: COMPAREF (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTEN_COMPAREE_Pos (4UL) /*!< CTIMER STMINTEN: COMPAREE (Bit 4) */ -#define CTIMER_STMINTEN_COMPAREE_Msk (0x10UL) /*!< CTIMER STMINTEN: COMPAREE (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTEN_COMPARED_Pos (3UL) /*!< CTIMER STMINTEN: COMPARED (Bit 3) */ -#define CTIMER_STMINTEN_COMPARED_Msk (0x8UL) /*!< CTIMER STMINTEN: COMPARED (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTEN_COMPAREC_Pos (2UL) /*!< CTIMER STMINTEN: COMPAREC (Bit 2) */ -#define CTIMER_STMINTEN_COMPAREC_Msk (0x4UL) /*!< CTIMER STMINTEN: COMPAREC (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTEN_COMPAREB_Pos (1UL) /*!< CTIMER STMINTEN: COMPAREB (Bit 1) */ -#define CTIMER_STMINTEN_COMPAREB_Msk (0x2UL) /*!< CTIMER STMINTEN: COMPAREB (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTEN_COMPAREA_Pos (0UL) /*!< CTIMER STMINTEN: COMPAREA (Bit 0) */ -#define CTIMER_STMINTEN_COMPAREA_Msk (0x1UL) /*!< CTIMER STMINTEN: COMPAREA (Bitfield-Mask: 0x01) */ -/* ====================================================== STMINTSTAT ======================================================= */ -#define CTIMER_STMINTSTAT_CAPTURED_Pos (12UL) /*!< CTIMER STMINTSTAT: CAPTURED (Bit 12) */ -#define CTIMER_STMINTSTAT_CAPTURED_Msk (0x1000UL) /*!< CTIMER STMINTSTAT: CAPTURED (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSTAT_CAPTUREC_Pos (11UL) /*!< CTIMER STMINTSTAT: CAPTUREC (Bit 11) */ -#define CTIMER_STMINTSTAT_CAPTUREC_Msk (0x800UL) /*!< CTIMER STMINTSTAT: CAPTUREC (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSTAT_CAPTUREB_Pos (10UL) /*!< CTIMER STMINTSTAT: CAPTUREB (Bit 10) */ -#define CTIMER_STMINTSTAT_CAPTUREB_Msk (0x400UL) /*!< CTIMER STMINTSTAT: CAPTUREB (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSTAT_CAPTUREA_Pos (9UL) /*!< CTIMER STMINTSTAT: CAPTUREA (Bit 9) */ -#define CTIMER_STMINTSTAT_CAPTUREA_Msk (0x200UL) /*!< CTIMER STMINTSTAT: CAPTUREA (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSTAT_OVERFLOW_Pos (8UL) /*!< CTIMER STMINTSTAT: OVERFLOW (Bit 8) */ -#define CTIMER_STMINTSTAT_OVERFLOW_Msk (0x100UL) /*!< CTIMER STMINTSTAT: OVERFLOW (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSTAT_COMPAREH_Pos (7UL) /*!< CTIMER STMINTSTAT: COMPAREH (Bit 7) */ -#define CTIMER_STMINTSTAT_COMPAREH_Msk (0x80UL) /*!< CTIMER STMINTSTAT: COMPAREH (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSTAT_COMPAREG_Pos (6UL) /*!< CTIMER STMINTSTAT: COMPAREG (Bit 6) */ -#define CTIMER_STMINTSTAT_COMPAREG_Msk (0x40UL) /*!< CTIMER STMINTSTAT: COMPAREG (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSTAT_COMPAREF_Pos (5UL) /*!< CTIMER STMINTSTAT: COMPAREF (Bit 5) */ -#define CTIMER_STMINTSTAT_COMPAREF_Msk (0x20UL) /*!< CTIMER STMINTSTAT: COMPAREF (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSTAT_COMPAREE_Pos (4UL) /*!< CTIMER STMINTSTAT: COMPAREE (Bit 4) */ -#define CTIMER_STMINTSTAT_COMPAREE_Msk (0x10UL) /*!< CTIMER STMINTSTAT: COMPAREE (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSTAT_COMPARED_Pos (3UL) /*!< CTIMER STMINTSTAT: COMPARED (Bit 3) */ -#define CTIMER_STMINTSTAT_COMPARED_Msk (0x8UL) /*!< CTIMER STMINTSTAT: COMPARED (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSTAT_COMPAREC_Pos (2UL) /*!< CTIMER STMINTSTAT: COMPAREC (Bit 2) */ -#define CTIMER_STMINTSTAT_COMPAREC_Msk (0x4UL) /*!< CTIMER STMINTSTAT: COMPAREC (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSTAT_COMPAREB_Pos (1UL) /*!< CTIMER STMINTSTAT: COMPAREB (Bit 1) */ -#define CTIMER_STMINTSTAT_COMPAREB_Msk (0x2UL) /*!< CTIMER STMINTSTAT: COMPAREB (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSTAT_COMPAREA_Pos (0UL) /*!< CTIMER STMINTSTAT: COMPAREA (Bit 0) */ -#define CTIMER_STMINTSTAT_COMPAREA_Msk (0x1UL) /*!< CTIMER STMINTSTAT: COMPAREA (Bitfield-Mask: 0x01) */ -/* ======================================================= STMINTCLR ======================================================= */ -#define CTIMER_STMINTCLR_CAPTURED_Pos (12UL) /*!< CTIMER STMINTCLR: CAPTURED (Bit 12) */ -#define CTIMER_STMINTCLR_CAPTURED_Msk (0x1000UL) /*!< CTIMER STMINTCLR: CAPTURED (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTCLR_CAPTUREC_Pos (11UL) /*!< CTIMER STMINTCLR: CAPTUREC (Bit 11) */ -#define CTIMER_STMINTCLR_CAPTUREC_Msk (0x800UL) /*!< CTIMER STMINTCLR: CAPTUREC (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTCLR_CAPTUREB_Pos (10UL) /*!< CTIMER STMINTCLR: CAPTUREB (Bit 10) */ -#define CTIMER_STMINTCLR_CAPTUREB_Msk (0x400UL) /*!< CTIMER STMINTCLR: CAPTUREB (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTCLR_CAPTUREA_Pos (9UL) /*!< CTIMER STMINTCLR: CAPTUREA (Bit 9) */ -#define CTIMER_STMINTCLR_CAPTUREA_Msk (0x200UL) /*!< CTIMER STMINTCLR: CAPTUREA (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTCLR_OVERFLOW_Pos (8UL) /*!< CTIMER STMINTCLR: OVERFLOW (Bit 8) */ -#define CTIMER_STMINTCLR_OVERFLOW_Msk (0x100UL) /*!< CTIMER STMINTCLR: OVERFLOW (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTCLR_COMPAREH_Pos (7UL) /*!< CTIMER STMINTCLR: COMPAREH (Bit 7) */ -#define CTIMER_STMINTCLR_COMPAREH_Msk (0x80UL) /*!< CTIMER STMINTCLR: COMPAREH (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTCLR_COMPAREG_Pos (6UL) /*!< CTIMER STMINTCLR: COMPAREG (Bit 6) */ -#define CTIMER_STMINTCLR_COMPAREG_Msk (0x40UL) /*!< CTIMER STMINTCLR: COMPAREG (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTCLR_COMPAREF_Pos (5UL) /*!< CTIMER STMINTCLR: COMPAREF (Bit 5) */ -#define CTIMER_STMINTCLR_COMPAREF_Msk (0x20UL) /*!< CTIMER STMINTCLR: COMPAREF (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTCLR_COMPAREE_Pos (4UL) /*!< CTIMER STMINTCLR: COMPAREE (Bit 4) */ -#define CTIMER_STMINTCLR_COMPAREE_Msk (0x10UL) /*!< CTIMER STMINTCLR: COMPAREE (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTCLR_COMPARED_Pos (3UL) /*!< CTIMER STMINTCLR: COMPARED (Bit 3) */ -#define CTIMER_STMINTCLR_COMPARED_Msk (0x8UL) /*!< CTIMER STMINTCLR: COMPARED (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTCLR_COMPAREC_Pos (2UL) /*!< CTIMER STMINTCLR: COMPAREC (Bit 2) */ -#define CTIMER_STMINTCLR_COMPAREC_Msk (0x4UL) /*!< CTIMER STMINTCLR: COMPAREC (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTCLR_COMPAREB_Pos (1UL) /*!< CTIMER STMINTCLR: COMPAREB (Bit 1) */ -#define CTIMER_STMINTCLR_COMPAREB_Msk (0x2UL) /*!< CTIMER STMINTCLR: COMPAREB (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTCLR_COMPAREA_Pos (0UL) /*!< CTIMER STMINTCLR: COMPAREA (Bit 0) */ -#define CTIMER_STMINTCLR_COMPAREA_Msk (0x1UL) /*!< CTIMER STMINTCLR: COMPAREA (Bitfield-Mask: 0x01) */ -/* ======================================================= STMINTSET ======================================================= */ -#define CTIMER_STMINTSET_CAPTURED_Pos (12UL) /*!< CTIMER STMINTSET: CAPTURED (Bit 12) */ -#define CTIMER_STMINTSET_CAPTURED_Msk (0x1000UL) /*!< CTIMER STMINTSET: CAPTURED (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSET_CAPTUREC_Pos (11UL) /*!< CTIMER STMINTSET: CAPTUREC (Bit 11) */ -#define CTIMER_STMINTSET_CAPTUREC_Msk (0x800UL) /*!< CTIMER STMINTSET: CAPTUREC (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSET_CAPTUREB_Pos (10UL) /*!< CTIMER STMINTSET: CAPTUREB (Bit 10) */ -#define CTIMER_STMINTSET_CAPTUREB_Msk (0x400UL) /*!< CTIMER STMINTSET: CAPTUREB (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSET_CAPTUREA_Pos (9UL) /*!< CTIMER STMINTSET: CAPTUREA (Bit 9) */ -#define CTIMER_STMINTSET_CAPTUREA_Msk (0x200UL) /*!< CTIMER STMINTSET: CAPTUREA (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSET_OVERFLOW_Pos (8UL) /*!< CTIMER STMINTSET: OVERFLOW (Bit 8) */ -#define CTIMER_STMINTSET_OVERFLOW_Msk (0x100UL) /*!< CTIMER STMINTSET: OVERFLOW (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSET_COMPAREH_Pos (7UL) /*!< CTIMER STMINTSET: COMPAREH (Bit 7) */ -#define CTIMER_STMINTSET_COMPAREH_Msk (0x80UL) /*!< CTIMER STMINTSET: COMPAREH (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSET_COMPAREG_Pos (6UL) /*!< CTIMER STMINTSET: COMPAREG (Bit 6) */ -#define CTIMER_STMINTSET_COMPAREG_Msk (0x40UL) /*!< CTIMER STMINTSET: COMPAREG (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSET_COMPAREF_Pos (5UL) /*!< CTIMER STMINTSET: COMPAREF (Bit 5) */ -#define CTIMER_STMINTSET_COMPAREF_Msk (0x20UL) /*!< CTIMER STMINTSET: COMPAREF (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSET_COMPAREE_Pos (4UL) /*!< CTIMER STMINTSET: COMPAREE (Bit 4) */ -#define CTIMER_STMINTSET_COMPAREE_Msk (0x10UL) /*!< CTIMER STMINTSET: COMPAREE (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSET_COMPARED_Pos (3UL) /*!< CTIMER STMINTSET: COMPARED (Bit 3) */ -#define CTIMER_STMINTSET_COMPARED_Msk (0x8UL) /*!< CTIMER STMINTSET: COMPARED (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSET_COMPAREC_Pos (2UL) /*!< CTIMER STMINTSET: COMPAREC (Bit 2) */ -#define CTIMER_STMINTSET_COMPAREC_Msk (0x4UL) /*!< CTIMER STMINTSET: COMPAREC (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSET_COMPAREB_Pos (1UL) /*!< CTIMER STMINTSET: COMPAREB (Bit 1) */ -#define CTIMER_STMINTSET_COMPAREB_Msk (0x2UL) /*!< CTIMER STMINTSET: COMPAREB (Bitfield-Mask: 0x01) */ -#define CTIMER_STMINTSET_COMPAREA_Pos (0UL) /*!< CTIMER STMINTSET: COMPAREA (Bit 0) */ -#define CTIMER_STMINTSET_COMPAREA_Msk (0x1UL) /*!< CTIMER STMINTSET: COMPAREA (Bitfield-Mask: 0x01) */ - - -/* =========================================================================================================================== */ -/* ================ GPIO ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PADREGA ======================================================== */ -#define GPIO_PADREGA_PAD3PWRUP_Pos (30UL) /*!< GPIO PADREGA: PAD3PWRUP (Bit 30) */ -#define GPIO_PADREGA_PAD3PWRUP_Msk (0x40000000UL) /*!< GPIO PADREGA: PAD3PWRUP (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGA_PAD3FNCSEL_Pos (27UL) /*!< GPIO PADREGA: PAD3FNCSEL (Bit 27) */ -#define GPIO_PADREGA_PAD3FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGA: PAD3FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGA_PAD3STRNG_Pos (26UL) /*!< GPIO PADREGA: PAD3STRNG (Bit 26) */ -#define GPIO_PADREGA_PAD3STRNG_Msk (0x4000000UL) /*!< GPIO PADREGA: PAD3STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGA_PAD3INPEN_Pos (25UL) /*!< GPIO PADREGA: PAD3INPEN (Bit 25) */ -#define GPIO_PADREGA_PAD3INPEN_Msk (0x2000000UL) /*!< GPIO PADREGA: PAD3INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGA_PAD3PULL_Pos (24UL) /*!< GPIO PADREGA: PAD3PULL (Bit 24) */ -#define GPIO_PADREGA_PAD3PULL_Msk (0x1000000UL) /*!< GPIO PADREGA: PAD3PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGA_PAD2FNCSEL_Pos (19UL) /*!< GPIO PADREGA: PAD2FNCSEL (Bit 19) */ -#define GPIO_PADREGA_PAD2FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGA: PAD2FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGA_PAD2STRNG_Pos (18UL) /*!< GPIO PADREGA: PAD2STRNG (Bit 18) */ -#define GPIO_PADREGA_PAD2STRNG_Msk (0x40000UL) /*!< GPIO PADREGA: PAD2STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGA_PAD2INPEN_Pos (17UL) /*!< GPIO PADREGA: PAD2INPEN (Bit 17) */ -#define GPIO_PADREGA_PAD2INPEN_Msk (0x20000UL) /*!< GPIO PADREGA: PAD2INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGA_PAD2PULL_Pos (16UL) /*!< GPIO PADREGA: PAD2PULL (Bit 16) */ -#define GPIO_PADREGA_PAD2PULL_Msk (0x10000UL) /*!< GPIO PADREGA: PAD2PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGA_PAD1RSEL_Pos (14UL) /*!< GPIO PADREGA: PAD1RSEL (Bit 14) */ -#define GPIO_PADREGA_PAD1RSEL_Msk (0xc000UL) /*!< GPIO PADREGA: PAD1RSEL (Bitfield-Mask: 0x03) */ -#define GPIO_PADREGA_PAD1FNCSEL_Pos (11UL) /*!< GPIO PADREGA: PAD1FNCSEL (Bit 11) */ -#define GPIO_PADREGA_PAD1FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGA: PAD1FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGA_PAD1STRNG_Pos (10UL) /*!< GPIO PADREGA: PAD1STRNG (Bit 10) */ -#define GPIO_PADREGA_PAD1STRNG_Msk (0x400UL) /*!< GPIO PADREGA: PAD1STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGA_PAD1INPEN_Pos (9UL) /*!< GPIO PADREGA: PAD1INPEN (Bit 9) */ -#define GPIO_PADREGA_PAD1INPEN_Msk (0x200UL) /*!< GPIO PADREGA: PAD1INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGA_PAD1PULL_Pos (8UL) /*!< GPIO PADREGA: PAD1PULL (Bit 8) */ -#define GPIO_PADREGA_PAD1PULL_Msk (0x100UL) /*!< GPIO PADREGA: PAD1PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGA_PAD0RSEL_Pos (6UL) /*!< GPIO PADREGA: PAD0RSEL (Bit 6) */ -#define GPIO_PADREGA_PAD0RSEL_Msk (0xc0UL) /*!< GPIO PADREGA: PAD0RSEL (Bitfield-Mask: 0x03) */ -#define GPIO_PADREGA_PAD0FNCSEL_Pos (3UL) /*!< GPIO PADREGA: PAD0FNCSEL (Bit 3) */ -#define GPIO_PADREGA_PAD0FNCSEL_Msk (0x38UL) /*!< GPIO PADREGA: PAD0FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGA_PAD0STRNG_Pos (2UL) /*!< GPIO PADREGA: PAD0STRNG (Bit 2) */ -#define GPIO_PADREGA_PAD0STRNG_Msk (0x4UL) /*!< GPIO PADREGA: PAD0STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGA_PAD0INPEN_Pos (1UL) /*!< GPIO PADREGA: PAD0INPEN (Bit 1) */ -#define GPIO_PADREGA_PAD0INPEN_Msk (0x2UL) /*!< GPIO PADREGA: PAD0INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGA_PAD0PULL_Pos (0UL) /*!< GPIO PADREGA: PAD0PULL (Bit 0) */ -#define GPIO_PADREGA_PAD0PULL_Msk (0x1UL) /*!< GPIO PADREGA: PAD0PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGB ======================================================== */ -#define GPIO_PADREGB_PAD7FNCSEL_Pos (27UL) /*!< GPIO PADREGB: PAD7FNCSEL (Bit 27) */ -#define GPIO_PADREGB_PAD7FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGB: PAD7FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGB_PAD7STRNG_Pos (26UL) /*!< GPIO PADREGB: PAD7STRNG (Bit 26) */ -#define GPIO_PADREGB_PAD7STRNG_Msk (0x4000000UL) /*!< GPIO PADREGB: PAD7STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGB_PAD7INPEN_Pos (25UL) /*!< GPIO PADREGB: PAD7INPEN (Bit 25) */ -#define GPIO_PADREGB_PAD7INPEN_Msk (0x2000000UL) /*!< GPIO PADREGB: PAD7INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGB_PAD7PULL_Pos (24UL) /*!< GPIO PADREGB: PAD7PULL (Bit 24) */ -#define GPIO_PADREGB_PAD7PULL_Msk (0x1000000UL) /*!< GPIO PADREGB: PAD7PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGB_PAD6RSEL_Pos (22UL) /*!< GPIO PADREGB: PAD6RSEL (Bit 22) */ -#define GPIO_PADREGB_PAD6RSEL_Msk (0xc00000UL) /*!< GPIO PADREGB: PAD6RSEL (Bitfield-Mask: 0x03) */ -#define GPIO_PADREGB_PAD6FNCSEL_Pos (19UL) /*!< GPIO PADREGB: PAD6FNCSEL (Bit 19) */ -#define GPIO_PADREGB_PAD6FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGB: PAD6FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGB_PAD6STRNG_Pos (18UL) /*!< GPIO PADREGB: PAD6STRNG (Bit 18) */ -#define GPIO_PADREGB_PAD6STRNG_Msk (0x40000UL) /*!< GPIO PADREGB: PAD6STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGB_PAD6INPEN_Pos (17UL) /*!< GPIO PADREGB: PAD6INPEN (Bit 17) */ -#define GPIO_PADREGB_PAD6INPEN_Msk (0x20000UL) /*!< GPIO PADREGB: PAD6INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGB_PAD6PULL_Pos (16UL) /*!< GPIO PADREGB: PAD6PULL (Bit 16) */ -#define GPIO_PADREGB_PAD6PULL_Msk (0x10000UL) /*!< GPIO PADREGB: PAD6PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGB_PAD5RSEL_Pos (14UL) /*!< GPIO PADREGB: PAD5RSEL (Bit 14) */ -#define GPIO_PADREGB_PAD5RSEL_Msk (0xc000UL) /*!< GPIO PADREGB: PAD5RSEL (Bitfield-Mask: 0x03) */ -#define GPIO_PADREGB_PAD5FNCSEL_Pos (11UL) /*!< GPIO PADREGB: PAD5FNCSEL (Bit 11) */ -#define GPIO_PADREGB_PAD5FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGB: PAD5FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGB_PAD5STRNG_Pos (10UL) /*!< GPIO PADREGB: PAD5STRNG (Bit 10) */ -#define GPIO_PADREGB_PAD5STRNG_Msk (0x400UL) /*!< GPIO PADREGB: PAD5STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGB_PAD5INPEN_Pos (9UL) /*!< GPIO PADREGB: PAD5INPEN (Bit 9) */ -#define GPIO_PADREGB_PAD5INPEN_Msk (0x200UL) /*!< GPIO PADREGB: PAD5INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGB_PAD5PULL_Pos (8UL) /*!< GPIO PADREGB: PAD5PULL (Bit 8) */ -#define GPIO_PADREGB_PAD5PULL_Msk (0x100UL) /*!< GPIO PADREGB: PAD5PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGB_PAD4FNCSEL_Pos (3UL) /*!< GPIO PADREGB: PAD4FNCSEL (Bit 3) */ -#define GPIO_PADREGB_PAD4FNCSEL_Msk (0x38UL) /*!< GPIO PADREGB: PAD4FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGB_PAD4STRNG_Pos (2UL) /*!< GPIO PADREGB: PAD4STRNG (Bit 2) */ -#define GPIO_PADREGB_PAD4STRNG_Msk (0x4UL) /*!< GPIO PADREGB: PAD4STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGB_PAD4INPEN_Pos (1UL) /*!< GPIO PADREGB: PAD4INPEN (Bit 1) */ -#define GPIO_PADREGB_PAD4INPEN_Msk (0x2UL) /*!< GPIO PADREGB: PAD4INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGB_PAD4PULL_Pos (0UL) /*!< GPIO PADREGB: PAD4PULL (Bit 0) */ -#define GPIO_PADREGB_PAD4PULL_Msk (0x1UL) /*!< GPIO PADREGB: PAD4PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGC ======================================================== */ -#define GPIO_PADREGC_PAD11FNCSEL_Pos (27UL) /*!< GPIO PADREGC: PAD11FNCSEL (Bit 27) */ -#define GPIO_PADREGC_PAD11FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGC: PAD11FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGC_PAD11STRNG_Pos (26UL) /*!< GPIO PADREGC: PAD11STRNG (Bit 26) */ -#define GPIO_PADREGC_PAD11STRNG_Msk (0x4000000UL) /*!< GPIO PADREGC: PAD11STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGC_PAD11INPEN_Pos (25UL) /*!< GPIO PADREGC: PAD11INPEN (Bit 25) */ -#define GPIO_PADREGC_PAD11INPEN_Msk (0x2000000UL) /*!< GPIO PADREGC: PAD11INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGC_PAD11PULL_Pos (24UL) /*!< GPIO PADREGC: PAD11PULL (Bit 24) */ -#define GPIO_PADREGC_PAD11PULL_Msk (0x1000000UL) /*!< GPIO PADREGC: PAD11PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGC_PAD10FNCSEL_Pos (19UL) /*!< GPIO PADREGC: PAD10FNCSEL (Bit 19) */ -#define GPIO_PADREGC_PAD10FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGC: PAD10FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGC_PAD10STRNG_Pos (18UL) /*!< GPIO PADREGC: PAD10STRNG (Bit 18) */ -#define GPIO_PADREGC_PAD10STRNG_Msk (0x40000UL) /*!< GPIO PADREGC: PAD10STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGC_PAD10INPEN_Pos (17UL) /*!< GPIO PADREGC: PAD10INPEN (Bit 17) */ -#define GPIO_PADREGC_PAD10INPEN_Msk (0x20000UL) /*!< GPIO PADREGC: PAD10INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGC_PAD10PULL_Pos (16UL) /*!< GPIO PADREGC: PAD10PULL (Bit 16) */ -#define GPIO_PADREGC_PAD10PULL_Msk (0x10000UL) /*!< GPIO PADREGC: PAD10PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGC_PAD9RSEL_Pos (14UL) /*!< GPIO PADREGC: PAD9RSEL (Bit 14) */ -#define GPIO_PADREGC_PAD9RSEL_Msk (0xc000UL) /*!< GPIO PADREGC: PAD9RSEL (Bitfield-Mask: 0x03) */ -#define GPIO_PADREGC_PAD9FNCSEL_Pos (11UL) /*!< GPIO PADREGC: PAD9FNCSEL (Bit 11) */ -#define GPIO_PADREGC_PAD9FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGC: PAD9FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGC_PAD9STRNG_Pos (10UL) /*!< GPIO PADREGC: PAD9STRNG (Bit 10) */ -#define GPIO_PADREGC_PAD9STRNG_Msk (0x400UL) /*!< GPIO PADREGC: PAD9STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGC_PAD9INPEN_Pos (9UL) /*!< GPIO PADREGC: PAD9INPEN (Bit 9) */ -#define GPIO_PADREGC_PAD9INPEN_Msk (0x200UL) /*!< GPIO PADREGC: PAD9INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGC_PAD9PULL_Pos (8UL) /*!< GPIO PADREGC: PAD9PULL (Bit 8) */ -#define GPIO_PADREGC_PAD9PULL_Msk (0x100UL) /*!< GPIO PADREGC: PAD9PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGC_PAD8RSEL_Pos (6UL) /*!< GPIO PADREGC: PAD8RSEL (Bit 6) */ -#define GPIO_PADREGC_PAD8RSEL_Msk (0xc0UL) /*!< GPIO PADREGC: PAD8RSEL (Bitfield-Mask: 0x03) */ -#define GPIO_PADREGC_PAD8FNCSEL_Pos (3UL) /*!< GPIO PADREGC: PAD8FNCSEL (Bit 3) */ -#define GPIO_PADREGC_PAD8FNCSEL_Msk (0x38UL) /*!< GPIO PADREGC: PAD8FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGC_PAD8STRNG_Pos (2UL) /*!< GPIO PADREGC: PAD8STRNG (Bit 2) */ -#define GPIO_PADREGC_PAD8STRNG_Msk (0x4UL) /*!< GPIO PADREGC: PAD8STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGC_PAD8INPEN_Pos (1UL) /*!< GPIO PADREGC: PAD8INPEN (Bit 1) */ -#define GPIO_PADREGC_PAD8INPEN_Msk (0x2UL) /*!< GPIO PADREGC: PAD8INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGC_PAD8PULL_Pos (0UL) /*!< GPIO PADREGC: PAD8PULL (Bit 0) */ -#define GPIO_PADREGC_PAD8PULL_Msk (0x1UL) /*!< GPIO PADREGC: PAD8PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGD ======================================================== */ -#define GPIO_PADREGD_PAD15FNCSEL_Pos (27UL) /*!< GPIO PADREGD: PAD15FNCSEL (Bit 27) */ -#define GPIO_PADREGD_PAD15FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGD: PAD15FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGD_PAD15STRNG_Pos (26UL) /*!< GPIO PADREGD: PAD15STRNG (Bit 26) */ -#define GPIO_PADREGD_PAD15STRNG_Msk (0x4000000UL) /*!< GPIO PADREGD: PAD15STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGD_PAD15INPEN_Pos (25UL) /*!< GPIO PADREGD: PAD15INPEN (Bit 25) */ -#define GPIO_PADREGD_PAD15INPEN_Msk (0x2000000UL) /*!< GPIO PADREGD: PAD15INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGD_PAD15PULL_Pos (24UL) /*!< GPIO PADREGD: PAD15PULL (Bit 24) */ -#define GPIO_PADREGD_PAD15PULL_Msk (0x1000000UL) /*!< GPIO PADREGD: PAD15PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGD_PAD14FNCSEL_Pos (19UL) /*!< GPIO PADREGD: PAD14FNCSEL (Bit 19) */ -#define GPIO_PADREGD_PAD14FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGD: PAD14FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGD_PAD14STRNG_Pos (18UL) /*!< GPIO PADREGD: PAD14STRNG (Bit 18) */ -#define GPIO_PADREGD_PAD14STRNG_Msk (0x40000UL) /*!< GPIO PADREGD: PAD14STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGD_PAD14INPEN_Pos (17UL) /*!< GPIO PADREGD: PAD14INPEN (Bit 17) */ -#define GPIO_PADREGD_PAD14INPEN_Msk (0x20000UL) /*!< GPIO PADREGD: PAD14INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGD_PAD14PULL_Pos (16UL) /*!< GPIO PADREGD: PAD14PULL (Bit 16) */ -#define GPIO_PADREGD_PAD14PULL_Msk (0x10000UL) /*!< GPIO PADREGD: PAD14PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGD_PAD13FNCSEL_Pos (11UL) /*!< GPIO PADREGD: PAD13FNCSEL (Bit 11) */ -#define GPIO_PADREGD_PAD13FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGD: PAD13FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGD_PAD13STRNG_Pos (10UL) /*!< GPIO PADREGD: PAD13STRNG (Bit 10) */ -#define GPIO_PADREGD_PAD13STRNG_Msk (0x400UL) /*!< GPIO PADREGD: PAD13STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGD_PAD13INPEN_Pos (9UL) /*!< GPIO PADREGD: PAD13INPEN (Bit 9) */ -#define GPIO_PADREGD_PAD13INPEN_Msk (0x200UL) /*!< GPIO PADREGD: PAD13INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGD_PAD13PULL_Pos (8UL) /*!< GPIO PADREGD: PAD13PULL (Bit 8) */ -#define GPIO_PADREGD_PAD13PULL_Msk (0x100UL) /*!< GPIO PADREGD: PAD13PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGD_PAD12FNCSEL_Pos (3UL) /*!< GPIO PADREGD: PAD12FNCSEL (Bit 3) */ -#define GPIO_PADREGD_PAD12FNCSEL_Msk (0x38UL) /*!< GPIO PADREGD: PAD12FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGD_PAD12STRNG_Pos (2UL) /*!< GPIO PADREGD: PAD12STRNG (Bit 2) */ -#define GPIO_PADREGD_PAD12STRNG_Msk (0x4UL) /*!< GPIO PADREGD: PAD12STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGD_PAD12INPEN_Pos (1UL) /*!< GPIO PADREGD: PAD12INPEN (Bit 1) */ -#define GPIO_PADREGD_PAD12INPEN_Msk (0x2UL) /*!< GPIO PADREGD: PAD12INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGD_PAD12PULL_Pos (0UL) /*!< GPIO PADREGD: PAD12PULL (Bit 0) */ -#define GPIO_PADREGD_PAD12PULL_Msk (0x1UL) /*!< GPIO PADREGD: PAD12PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGE ======================================================== */ -#define GPIO_PADREGE_PAD19FNCSEL_Pos (27UL) /*!< GPIO PADREGE: PAD19FNCSEL (Bit 27) */ -#define GPIO_PADREGE_PAD19FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGE: PAD19FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGE_PAD19STRNG_Pos (26UL) /*!< GPIO PADREGE: PAD19STRNG (Bit 26) */ -#define GPIO_PADREGE_PAD19STRNG_Msk (0x4000000UL) /*!< GPIO PADREGE: PAD19STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGE_PAD19INPEN_Pos (25UL) /*!< GPIO PADREGE: PAD19INPEN (Bit 25) */ -#define GPIO_PADREGE_PAD19INPEN_Msk (0x2000000UL) /*!< GPIO PADREGE: PAD19INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGE_PAD19PULL_Pos (24UL) /*!< GPIO PADREGE: PAD19PULL (Bit 24) */ -#define GPIO_PADREGE_PAD19PULL_Msk (0x1000000UL) /*!< GPIO PADREGE: PAD19PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGE_PAD18FNCSEL_Pos (19UL) /*!< GPIO PADREGE: PAD18FNCSEL (Bit 19) */ -#define GPIO_PADREGE_PAD18FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGE: PAD18FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGE_PAD18STRNG_Pos (18UL) /*!< GPIO PADREGE: PAD18STRNG (Bit 18) */ -#define GPIO_PADREGE_PAD18STRNG_Msk (0x40000UL) /*!< GPIO PADREGE: PAD18STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGE_PAD18INPEN_Pos (17UL) /*!< GPIO PADREGE: PAD18INPEN (Bit 17) */ -#define GPIO_PADREGE_PAD18INPEN_Msk (0x20000UL) /*!< GPIO PADREGE: PAD18INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGE_PAD18PULL_Pos (16UL) /*!< GPIO PADREGE: PAD18PULL (Bit 16) */ -#define GPIO_PADREGE_PAD18PULL_Msk (0x10000UL) /*!< GPIO PADREGE: PAD18PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGE_PAD17FNCSEL_Pos (11UL) /*!< GPIO PADREGE: PAD17FNCSEL (Bit 11) */ -#define GPIO_PADREGE_PAD17FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGE: PAD17FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGE_PAD17STRNG_Pos (10UL) /*!< GPIO PADREGE: PAD17STRNG (Bit 10) */ -#define GPIO_PADREGE_PAD17STRNG_Msk (0x400UL) /*!< GPIO PADREGE: PAD17STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGE_PAD17INPEN_Pos (9UL) /*!< GPIO PADREGE: PAD17INPEN (Bit 9) */ -#define GPIO_PADREGE_PAD17INPEN_Msk (0x200UL) /*!< GPIO PADREGE: PAD17INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGE_PAD17PULL_Pos (8UL) /*!< GPIO PADREGE: PAD17PULL (Bit 8) */ -#define GPIO_PADREGE_PAD17PULL_Msk (0x100UL) /*!< GPIO PADREGE: PAD17PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGE_PAD16FNCSEL_Pos (3UL) /*!< GPIO PADREGE: PAD16FNCSEL (Bit 3) */ -#define GPIO_PADREGE_PAD16FNCSEL_Msk (0x38UL) /*!< GPIO PADREGE: PAD16FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGE_PAD16STRNG_Pos (2UL) /*!< GPIO PADREGE: PAD16STRNG (Bit 2) */ -#define GPIO_PADREGE_PAD16STRNG_Msk (0x4UL) /*!< GPIO PADREGE: PAD16STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGE_PAD16INPEN_Pos (1UL) /*!< GPIO PADREGE: PAD16INPEN (Bit 1) */ -#define GPIO_PADREGE_PAD16INPEN_Msk (0x2UL) /*!< GPIO PADREGE: PAD16INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGE_PAD16PULL_Pos (0UL) /*!< GPIO PADREGE: PAD16PULL (Bit 0) */ -#define GPIO_PADREGE_PAD16PULL_Msk (0x1UL) /*!< GPIO PADREGE: PAD16PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGF ======================================================== */ -#define GPIO_PADREGF_PAD23FNCSEL_Pos (27UL) /*!< GPIO PADREGF: PAD23FNCSEL (Bit 27) */ -#define GPIO_PADREGF_PAD23FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGF: PAD23FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGF_PAD23STRNG_Pos (26UL) /*!< GPIO PADREGF: PAD23STRNG (Bit 26) */ -#define GPIO_PADREGF_PAD23STRNG_Msk (0x4000000UL) /*!< GPIO PADREGF: PAD23STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGF_PAD23INPEN_Pos (25UL) /*!< GPIO PADREGF: PAD23INPEN (Bit 25) */ -#define GPIO_PADREGF_PAD23INPEN_Msk (0x2000000UL) /*!< GPIO PADREGF: PAD23INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGF_PAD23PULL_Pos (24UL) /*!< GPIO PADREGF: PAD23PULL (Bit 24) */ -#define GPIO_PADREGF_PAD23PULL_Msk (0x1000000UL) /*!< GPIO PADREGF: PAD23PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGF_PAD22FNCSEL_Pos (19UL) /*!< GPIO PADREGF: PAD22FNCSEL (Bit 19) */ -#define GPIO_PADREGF_PAD22FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGF: PAD22FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGF_PAD22STRNG_Pos (18UL) /*!< GPIO PADREGF: PAD22STRNG (Bit 18) */ -#define GPIO_PADREGF_PAD22STRNG_Msk (0x40000UL) /*!< GPIO PADREGF: PAD22STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGF_PAD22INPEN_Pos (17UL) /*!< GPIO PADREGF: PAD22INPEN (Bit 17) */ -#define GPIO_PADREGF_PAD22INPEN_Msk (0x20000UL) /*!< GPIO PADREGF: PAD22INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGF_PAD22PULL_Pos (16UL) /*!< GPIO PADREGF: PAD22PULL (Bit 16) */ -#define GPIO_PADREGF_PAD22PULL_Msk (0x10000UL) /*!< GPIO PADREGF: PAD22PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGF_PAD21FNCSEL_Pos (11UL) /*!< GPIO PADREGF: PAD21FNCSEL (Bit 11) */ -#define GPIO_PADREGF_PAD21FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGF: PAD21FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGF_PAD21STRNG_Pos (10UL) /*!< GPIO PADREGF: PAD21STRNG (Bit 10) */ -#define GPIO_PADREGF_PAD21STRNG_Msk (0x400UL) /*!< GPIO PADREGF: PAD21STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGF_PAD21INPEN_Pos (9UL) /*!< GPIO PADREGF: PAD21INPEN (Bit 9) */ -#define GPIO_PADREGF_PAD21INPEN_Msk (0x200UL) /*!< GPIO PADREGF: PAD21INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGF_PAD21PULL_Pos (8UL) /*!< GPIO PADREGF: PAD21PULL (Bit 8) */ -#define GPIO_PADREGF_PAD21PULL_Msk (0x100UL) /*!< GPIO PADREGF: PAD21PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGF_PAD20FNCSEL_Pos (3UL) /*!< GPIO PADREGF: PAD20FNCSEL (Bit 3) */ -#define GPIO_PADREGF_PAD20FNCSEL_Msk (0x38UL) /*!< GPIO PADREGF: PAD20FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGF_PAD20STRNG_Pos (2UL) /*!< GPIO PADREGF: PAD20STRNG (Bit 2) */ -#define GPIO_PADREGF_PAD20STRNG_Msk (0x4UL) /*!< GPIO PADREGF: PAD20STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGF_PAD20INPEN_Pos (1UL) /*!< GPIO PADREGF: PAD20INPEN (Bit 1) */ -#define GPIO_PADREGF_PAD20INPEN_Msk (0x2UL) /*!< GPIO PADREGF: PAD20INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGF_PAD20PULL_Pos (0UL) /*!< GPIO PADREGF: PAD20PULL (Bit 0) */ -#define GPIO_PADREGF_PAD20PULL_Msk (0x1UL) /*!< GPIO PADREGF: PAD20PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGG ======================================================== */ -#define GPIO_PADREGG_PAD27RSEL_Pos (30UL) /*!< GPIO PADREGG: PAD27RSEL (Bit 30) */ -#define GPIO_PADREGG_PAD27RSEL_Msk (0xc0000000UL) /*!< GPIO PADREGG: PAD27RSEL (Bitfield-Mask: 0x03) */ -#define GPIO_PADREGG_PAD27FNCSEL_Pos (27UL) /*!< GPIO PADREGG: PAD27FNCSEL (Bit 27) */ -#define GPIO_PADREGG_PAD27FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGG: PAD27FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGG_PAD27STRNG_Pos (26UL) /*!< GPIO PADREGG: PAD27STRNG (Bit 26) */ -#define GPIO_PADREGG_PAD27STRNG_Msk (0x4000000UL) /*!< GPIO PADREGG: PAD27STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGG_PAD27INPEN_Pos (25UL) /*!< GPIO PADREGG: PAD27INPEN (Bit 25) */ -#define GPIO_PADREGG_PAD27INPEN_Msk (0x2000000UL) /*!< GPIO PADREGG: PAD27INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGG_PAD27PULL_Pos (24UL) /*!< GPIO PADREGG: PAD27PULL (Bit 24) */ -#define GPIO_PADREGG_PAD27PULL_Msk (0x1000000UL) /*!< GPIO PADREGG: PAD27PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGG_PAD26FNCSEL_Pos (19UL) /*!< GPIO PADREGG: PAD26FNCSEL (Bit 19) */ -#define GPIO_PADREGG_PAD26FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGG: PAD26FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGG_PAD26STRNG_Pos (18UL) /*!< GPIO PADREGG: PAD26STRNG (Bit 18) */ -#define GPIO_PADREGG_PAD26STRNG_Msk (0x40000UL) /*!< GPIO PADREGG: PAD26STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGG_PAD26INPEN_Pos (17UL) /*!< GPIO PADREGG: PAD26INPEN (Bit 17) */ -#define GPIO_PADREGG_PAD26INPEN_Msk (0x20000UL) /*!< GPIO PADREGG: PAD26INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGG_PAD26PULL_Pos (16UL) /*!< GPIO PADREGG: PAD26PULL (Bit 16) */ -#define GPIO_PADREGG_PAD26PULL_Msk (0x10000UL) /*!< GPIO PADREGG: PAD26PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGG_PAD25RSEL_Pos (14UL) /*!< GPIO PADREGG: PAD25RSEL (Bit 14) */ -#define GPIO_PADREGG_PAD25RSEL_Msk (0xc000UL) /*!< GPIO PADREGG: PAD25RSEL (Bitfield-Mask: 0x03) */ -#define GPIO_PADREGG_PAD25FNCSEL_Pos (11UL) /*!< GPIO PADREGG: PAD25FNCSEL (Bit 11) */ -#define GPIO_PADREGG_PAD25FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGG: PAD25FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGG_PAD25STRNG_Pos (10UL) /*!< GPIO PADREGG: PAD25STRNG (Bit 10) */ -#define GPIO_PADREGG_PAD25STRNG_Msk (0x400UL) /*!< GPIO PADREGG: PAD25STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGG_PAD25INPEN_Pos (9UL) /*!< GPIO PADREGG: PAD25INPEN (Bit 9) */ -#define GPIO_PADREGG_PAD25INPEN_Msk (0x200UL) /*!< GPIO PADREGG: PAD25INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGG_PAD25PULL_Pos (8UL) /*!< GPIO PADREGG: PAD25PULL (Bit 8) */ -#define GPIO_PADREGG_PAD25PULL_Msk (0x100UL) /*!< GPIO PADREGG: PAD25PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGG_PAD24FNCSEL_Pos (3UL) /*!< GPIO PADREGG: PAD24FNCSEL (Bit 3) */ -#define GPIO_PADREGG_PAD24FNCSEL_Msk (0x38UL) /*!< GPIO PADREGG: PAD24FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGG_PAD24STRNG_Pos (2UL) /*!< GPIO PADREGG: PAD24STRNG (Bit 2) */ -#define GPIO_PADREGG_PAD24STRNG_Msk (0x4UL) /*!< GPIO PADREGG: PAD24STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGG_PAD24INPEN_Pos (1UL) /*!< GPIO PADREGG: PAD24INPEN (Bit 1) */ -#define GPIO_PADREGG_PAD24INPEN_Msk (0x2UL) /*!< GPIO PADREGG: PAD24INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGG_PAD24PULL_Pos (0UL) /*!< GPIO PADREGG: PAD24PULL (Bit 0) */ -#define GPIO_PADREGG_PAD24PULL_Msk (0x1UL) /*!< GPIO PADREGG: PAD24PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGH ======================================================== */ -#define GPIO_PADREGH_PAD31FNCSEL_Pos (27UL) /*!< GPIO PADREGH: PAD31FNCSEL (Bit 27) */ -#define GPIO_PADREGH_PAD31FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGH: PAD31FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGH_PAD31STRNG_Pos (26UL) /*!< GPIO PADREGH: PAD31STRNG (Bit 26) */ -#define GPIO_PADREGH_PAD31STRNG_Msk (0x4000000UL) /*!< GPIO PADREGH: PAD31STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGH_PAD31INPEN_Pos (25UL) /*!< GPIO PADREGH: PAD31INPEN (Bit 25) */ -#define GPIO_PADREGH_PAD31INPEN_Msk (0x2000000UL) /*!< GPIO PADREGH: PAD31INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGH_PAD31PULL_Pos (24UL) /*!< GPIO PADREGH: PAD31PULL (Bit 24) */ -#define GPIO_PADREGH_PAD31PULL_Msk (0x1000000UL) /*!< GPIO PADREGH: PAD31PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGH_PAD30FNCSEL_Pos (19UL) /*!< GPIO PADREGH: PAD30FNCSEL (Bit 19) */ -#define GPIO_PADREGH_PAD30FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGH: PAD30FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGH_PAD30STRNG_Pos (18UL) /*!< GPIO PADREGH: PAD30STRNG (Bit 18) */ -#define GPIO_PADREGH_PAD30STRNG_Msk (0x40000UL) /*!< GPIO PADREGH: PAD30STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGH_PAD30INPEN_Pos (17UL) /*!< GPIO PADREGH: PAD30INPEN (Bit 17) */ -#define GPIO_PADREGH_PAD30INPEN_Msk (0x20000UL) /*!< GPIO PADREGH: PAD30INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGH_PAD30PULL_Pos (16UL) /*!< GPIO PADREGH: PAD30PULL (Bit 16) */ -#define GPIO_PADREGH_PAD30PULL_Msk (0x10000UL) /*!< GPIO PADREGH: PAD30PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGH_PAD29FNCSEL_Pos (11UL) /*!< GPIO PADREGH: PAD29FNCSEL (Bit 11) */ -#define GPIO_PADREGH_PAD29FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGH: PAD29FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGH_PAD29STRNG_Pos (10UL) /*!< GPIO PADREGH: PAD29STRNG (Bit 10) */ -#define GPIO_PADREGH_PAD29STRNG_Msk (0x400UL) /*!< GPIO PADREGH: PAD29STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGH_PAD29INPEN_Pos (9UL) /*!< GPIO PADREGH: PAD29INPEN (Bit 9) */ -#define GPIO_PADREGH_PAD29INPEN_Msk (0x200UL) /*!< GPIO PADREGH: PAD29INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGH_PAD29PULL_Pos (8UL) /*!< GPIO PADREGH: PAD29PULL (Bit 8) */ -#define GPIO_PADREGH_PAD29PULL_Msk (0x100UL) /*!< GPIO PADREGH: PAD29PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGH_PAD28FNCSEL_Pos (3UL) /*!< GPIO PADREGH: PAD28FNCSEL (Bit 3) */ -#define GPIO_PADREGH_PAD28FNCSEL_Msk (0x38UL) /*!< GPIO PADREGH: PAD28FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGH_PAD28STRNG_Pos (2UL) /*!< GPIO PADREGH: PAD28STRNG (Bit 2) */ -#define GPIO_PADREGH_PAD28STRNG_Msk (0x4UL) /*!< GPIO PADREGH: PAD28STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGH_PAD28INPEN_Pos (1UL) /*!< GPIO PADREGH: PAD28INPEN (Bit 1) */ -#define GPIO_PADREGH_PAD28INPEN_Msk (0x2UL) /*!< GPIO PADREGH: PAD28INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGH_PAD28PULL_Pos (0UL) /*!< GPIO PADREGH: PAD28PULL (Bit 0) */ -#define GPIO_PADREGH_PAD28PULL_Msk (0x1UL) /*!< GPIO PADREGH: PAD28PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGI ======================================================== */ -#define GPIO_PADREGI_PAD35FNCSEL_Pos (27UL) /*!< GPIO PADREGI: PAD35FNCSEL (Bit 27) */ -#define GPIO_PADREGI_PAD35FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGI: PAD35FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGI_PAD35STRNG_Pos (26UL) /*!< GPIO PADREGI: PAD35STRNG (Bit 26) */ -#define GPIO_PADREGI_PAD35STRNG_Msk (0x4000000UL) /*!< GPIO PADREGI: PAD35STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGI_PAD35INPEN_Pos (25UL) /*!< GPIO PADREGI: PAD35INPEN (Bit 25) */ -#define GPIO_PADREGI_PAD35INPEN_Msk (0x2000000UL) /*!< GPIO PADREGI: PAD35INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGI_PAD35PULL_Pos (24UL) /*!< GPIO PADREGI: PAD35PULL (Bit 24) */ -#define GPIO_PADREGI_PAD35PULL_Msk (0x1000000UL) /*!< GPIO PADREGI: PAD35PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGI_PAD34FNCSEL_Pos (19UL) /*!< GPIO PADREGI: PAD34FNCSEL (Bit 19) */ -#define GPIO_PADREGI_PAD34FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGI: PAD34FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGI_PAD34STRNG_Pos (18UL) /*!< GPIO PADREGI: PAD34STRNG (Bit 18) */ -#define GPIO_PADREGI_PAD34STRNG_Msk (0x40000UL) /*!< GPIO PADREGI: PAD34STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGI_PAD34INPEN_Pos (17UL) /*!< GPIO PADREGI: PAD34INPEN (Bit 17) */ -#define GPIO_PADREGI_PAD34INPEN_Msk (0x20000UL) /*!< GPIO PADREGI: PAD34INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGI_PAD34PULL_Pos (16UL) /*!< GPIO PADREGI: PAD34PULL (Bit 16) */ -#define GPIO_PADREGI_PAD34PULL_Msk (0x10000UL) /*!< GPIO PADREGI: PAD34PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGI_PAD33FNCSEL_Pos (11UL) /*!< GPIO PADREGI: PAD33FNCSEL (Bit 11) */ -#define GPIO_PADREGI_PAD33FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGI: PAD33FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGI_PAD33STRNG_Pos (10UL) /*!< GPIO PADREGI: PAD33STRNG (Bit 10) */ -#define GPIO_PADREGI_PAD33STRNG_Msk (0x400UL) /*!< GPIO PADREGI: PAD33STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGI_PAD33INPEN_Pos (9UL) /*!< GPIO PADREGI: PAD33INPEN (Bit 9) */ -#define GPIO_PADREGI_PAD33INPEN_Msk (0x200UL) /*!< GPIO PADREGI: PAD33INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGI_PAD33PULL_Pos (8UL) /*!< GPIO PADREGI: PAD33PULL (Bit 8) */ -#define GPIO_PADREGI_PAD33PULL_Msk (0x100UL) /*!< GPIO PADREGI: PAD33PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGI_PAD32FNCSEL_Pos (3UL) /*!< GPIO PADREGI: PAD32FNCSEL (Bit 3) */ -#define GPIO_PADREGI_PAD32FNCSEL_Msk (0x38UL) /*!< GPIO PADREGI: PAD32FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGI_PAD32STRNG_Pos (2UL) /*!< GPIO PADREGI: PAD32STRNG (Bit 2) */ -#define GPIO_PADREGI_PAD32STRNG_Msk (0x4UL) /*!< GPIO PADREGI: PAD32STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGI_PAD32INPEN_Pos (1UL) /*!< GPIO PADREGI: PAD32INPEN (Bit 1) */ -#define GPIO_PADREGI_PAD32INPEN_Msk (0x2UL) /*!< GPIO PADREGI: PAD32INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGI_PAD32PULL_Pos (0UL) /*!< GPIO PADREGI: PAD32PULL (Bit 0) */ -#define GPIO_PADREGI_PAD32PULL_Msk (0x1UL) /*!< GPIO PADREGI: PAD32PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGJ ======================================================== */ -#define GPIO_PADREGJ_PAD39RSEL_Pos (30UL) /*!< GPIO PADREGJ: PAD39RSEL (Bit 30) */ -#define GPIO_PADREGJ_PAD39RSEL_Msk (0xc0000000UL) /*!< GPIO PADREGJ: PAD39RSEL (Bitfield-Mask: 0x03) */ -#define GPIO_PADREGJ_PAD39FNCSEL_Pos (27UL) /*!< GPIO PADREGJ: PAD39FNCSEL (Bit 27) */ -#define GPIO_PADREGJ_PAD39FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGJ: PAD39FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGJ_PAD39STRNG_Pos (26UL) /*!< GPIO PADREGJ: PAD39STRNG (Bit 26) */ -#define GPIO_PADREGJ_PAD39STRNG_Msk (0x4000000UL) /*!< GPIO PADREGJ: PAD39STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGJ_PAD39INPEN_Pos (25UL) /*!< GPIO PADREGJ: PAD39INPEN (Bit 25) */ -#define GPIO_PADREGJ_PAD39INPEN_Msk (0x2000000UL) /*!< GPIO PADREGJ: PAD39INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGJ_PAD39PULL_Pos (24UL) /*!< GPIO PADREGJ: PAD39PULL (Bit 24) */ -#define GPIO_PADREGJ_PAD39PULL_Msk (0x1000000UL) /*!< GPIO PADREGJ: PAD39PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGJ_PAD38FNCSEL_Pos (19UL) /*!< GPIO PADREGJ: PAD38FNCSEL (Bit 19) */ -#define GPIO_PADREGJ_PAD38FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGJ: PAD38FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGJ_PAD38STRNG_Pos (18UL) /*!< GPIO PADREGJ: PAD38STRNG (Bit 18) */ -#define GPIO_PADREGJ_PAD38STRNG_Msk (0x40000UL) /*!< GPIO PADREGJ: PAD38STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGJ_PAD38INPEN_Pos (17UL) /*!< GPIO PADREGJ: PAD38INPEN (Bit 17) */ -#define GPIO_PADREGJ_PAD38INPEN_Msk (0x20000UL) /*!< GPIO PADREGJ: PAD38INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGJ_PAD38PULL_Pos (16UL) /*!< GPIO PADREGJ: PAD38PULL (Bit 16) */ -#define GPIO_PADREGJ_PAD38PULL_Msk (0x10000UL) /*!< GPIO PADREGJ: PAD38PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGJ_PAD37PWRDN_Pos (15UL) /*!< GPIO PADREGJ: PAD37PWRDN (Bit 15) */ -#define GPIO_PADREGJ_PAD37PWRDN_Msk (0x8000UL) /*!< GPIO PADREGJ: PAD37PWRDN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGJ_PAD37FNCSEL_Pos (11UL) /*!< GPIO PADREGJ: PAD37FNCSEL (Bit 11) */ -#define GPIO_PADREGJ_PAD37FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGJ: PAD37FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGJ_PAD37STRNG_Pos (10UL) /*!< GPIO PADREGJ: PAD37STRNG (Bit 10) */ -#define GPIO_PADREGJ_PAD37STRNG_Msk (0x400UL) /*!< GPIO PADREGJ: PAD37STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGJ_PAD37INPEN_Pos (9UL) /*!< GPIO PADREGJ: PAD37INPEN (Bit 9) */ -#define GPIO_PADREGJ_PAD37INPEN_Msk (0x200UL) /*!< GPIO PADREGJ: PAD37INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGJ_PAD37PULL_Pos (8UL) /*!< GPIO PADREGJ: PAD37PULL (Bit 8) */ -#define GPIO_PADREGJ_PAD37PULL_Msk (0x100UL) /*!< GPIO PADREGJ: PAD37PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGJ_PAD36FNCSEL_Pos (3UL) /*!< GPIO PADREGJ: PAD36FNCSEL (Bit 3) */ -#define GPIO_PADREGJ_PAD36FNCSEL_Msk (0x38UL) /*!< GPIO PADREGJ: PAD36FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGJ_PAD36STRNG_Pos (2UL) /*!< GPIO PADREGJ: PAD36STRNG (Bit 2) */ -#define GPIO_PADREGJ_PAD36STRNG_Msk (0x4UL) /*!< GPIO PADREGJ: PAD36STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGJ_PAD36INPEN_Pos (1UL) /*!< GPIO PADREGJ: PAD36INPEN (Bit 1) */ -#define GPIO_PADREGJ_PAD36INPEN_Msk (0x2UL) /*!< GPIO PADREGJ: PAD36INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGJ_PAD36PULL_Pos (0UL) /*!< GPIO PADREGJ: PAD36PULL (Bit 0) */ -#define GPIO_PADREGJ_PAD36PULL_Msk (0x1UL) /*!< GPIO PADREGJ: PAD36PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGK ======================================================== */ -#define GPIO_PADREGK_PAD43RSEL_Pos (30UL) /*!< GPIO PADREGK: PAD43RSEL (Bit 30) */ -#define GPIO_PADREGK_PAD43RSEL_Msk (0xc0000000UL) /*!< GPIO PADREGK: PAD43RSEL (Bitfield-Mask: 0x03) */ -#define GPIO_PADREGK_PAD43FNCSEL_Pos (27UL) /*!< GPIO PADREGK: PAD43FNCSEL (Bit 27) */ -#define GPIO_PADREGK_PAD43FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGK: PAD43FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGK_PAD43STRNG_Pos (26UL) /*!< GPIO PADREGK: PAD43STRNG (Bit 26) */ -#define GPIO_PADREGK_PAD43STRNG_Msk (0x4000000UL) /*!< GPIO PADREGK: PAD43STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGK_PAD43INPEN_Pos (25UL) /*!< GPIO PADREGK: PAD43INPEN (Bit 25) */ -#define GPIO_PADREGK_PAD43INPEN_Msk (0x2000000UL) /*!< GPIO PADREGK: PAD43INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGK_PAD43PULL_Pos (24UL) /*!< GPIO PADREGK: PAD43PULL (Bit 24) */ -#define GPIO_PADREGK_PAD43PULL_Msk (0x1000000UL) /*!< GPIO PADREGK: PAD43PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGK_PAD42RSEL_Pos (22UL) /*!< GPIO PADREGK: PAD42RSEL (Bit 22) */ -#define GPIO_PADREGK_PAD42RSEL_Msk (0xc00000UL) /*!< GPIO PADREGK: PAD42RSEL (Bitfield-Mask: 0x03) */ -#define GPIO_PADREGK_PAD42FNCSEL_Pos (19UL) /*!< GPIO PADREGK: PAD42FNCSEL (Bit 19) */ -#define GPIO_PADREGK_PAD42FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGK: PAD42FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGK_PAD42STRNG_Pos (18UL) /*!< GPIO PADREGK: PAD42STRNG (Bit 18) */ -#define GPIO_PADREGK_PAD42STRNG_Msk (0x40000UL) /*!< GPIO PADREGK: PAD42STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGK_PAD42INPEN_Pos (17UL) /*!< GPIO PADREGK: PAD42INPEN (Bit 17) */ -#define GPIO_PADREGK_PAD42INPEN_Msk (0x20000UL) /*!< GPIO PADREGK: PAD42INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGK_PAD42PULL_Pos (16UL) /*!< GPIO PADREGK: PAD42PULL (Bit 16) */ -#define GPIO_PADREGK_PAD42PULL_Msk (0x10000UL) /*!< GPIO PADREGK: PAD42PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGK_PAD41PWRDN_Pos (15UL) /*!< GPIO PADREGK: PAD41PWRDN (Bit 15) */ -#define GPIO_PADREGK_PAD41PWRDN_Msk (0x8000UL) /*!< GPIO PADREGK: PAD41PWRDN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGK_PAD41FNCSEL_Pos (11UL) /*!< GPIO PADREGK: PAD41FNCSEL (Bit 11) */ -#define GPIO_PADREGK_PAD41FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGK: PAD41FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGK_PAD41STRNG_Pos (10UL) /*!< GPIO PADREGK: PAD41STRNG (Bit 10) */ -#define GPIO_PADREGK_PAD41STRNG_Msk (0x400UL) /*!< GPIO PADREGK: PAD41STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGK_PAD41INPEN_Pos (9UL) /*!< GPIO PADREGK: PAD41INPEN (Bit 9) */ -#define GPIO_PADREGK_PAD41INPEN_Msk (0x200UL) /*!< GPIO PADREGK: PAD41INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGK_PAD41PULL_Pos (8UL) /*!< GPIO PADREGK: PAD41PULL (Bit 8) */ -#define GPIO_PADREGK_PAD41PULL_Msk (0x100UL) /*!< GPIO PADREGK: PAD41PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGK_PAD40RSEL_Pos (6UL) /*!< GPIO PADREGK: PAD40RSEL (Bit 6) */ -#define GPIO_PADREGK_PAD40RSEL_Msk (0xc0UL) /*!< GPIO PADREGK: PAD40RSEL (Bitfield-Mask: 0x03) */ -#define GPIO_PADREGK_PAD40FNCSEL_Pos (3UL) /*!< GPIO PADREGK: PAD40FNCSEL (Bit 3) */ -#define GPIO_PADREGK_PAD40FNCSEL_Msk (0x38UL) /*!< GPIO PADREGK: PAD40FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGK_PAD40STRNG_Pos (2UL) /*!< GPIO PADREGK: PAD40STRNG (Bit 2) */ -#define GPIO_PADREGK_PAD40STRNG_Msk (0x4UL) /*!< GPIO PADREGK: PAD40STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGK_PAD40INPEN_Pos (1UL) /*!< GPIO PADREGK: PAD40INPEN (Bit 1) */ -#define GPIO_PADREGK_PAD40INPEN_Msk (0x2UL) /*!< GPIO PADREGK: PAD40INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGK_PAD40PULL_Pos (0UL) /*!< GPIO PADREGK: PAD40PULL (Bit 0) */ -#define GPIO_PADREGK_PAD40PULL_Msk (0x1UL) /*!< GPIO PADREGK: PAD40PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGL ======================================================== */ -#define GPIO_PADREGL_PAD47FNCSEL_Pos (27UL) /*!< GPIO PADREGL: PAD47FNCSEL (Bit 27) */ -#define GPIO_PADREGL_PAD47FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGL: PAD47FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGL_PAD47STRNG_Pos (26UL) /*!< GPIO PADREGL: PAD47STRNG (Bit 26) */ -#define GPIO_PADREGL_PAD47STRNG_Msk (0x4000000UL) /*!< GPIO PADREGL: PAD47STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGL_PAD47INPEN_Pos (25UL) /*!< GPIO PADREGL: PAD47INPEN (Bit 25) */ -#define GPIO_PADREGL_PAD47INPEN_Msk (0x2000000UL) /*!< GPIO PADREGL: PAD47INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGL_PAD47PULL_Pos (24UL) /*!< GPIO PADREGL: PAD47PULL (Bit 24) */ -#define GPIO_PADREGL_PAD47PULL_Msk (0x1000000UL) /*!< GPIO PADREGL: PAD47PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGL_PAD46FNCSEL_Pos (19UL) /*!< GPIO PADREGL: PAD46FNCSEL (Bit 19) */ -#define GPIO_PADREGL_PAD46FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGL: PAD46FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGL_PAD46STRNG_Pos (18UL) /*!< GPIO PADREGL: PAD46STRNG (Bit 18) */ -#define GPIO_PADREGL_PAD46STRNG_Msk (0x40000UL) /*!< GPIO PADREGL: PAD46STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGL_PAD46INPEN_Pos (17UL) /*!< GPIO PADREGL: PAD46INPEN (Bit 17) */ -#define GPIO_PADREGL_PAD46INPEN_Msk (0x20000UL) /*!< GPIO PADREGL: PAD46INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGL_PAD46PULL_Pos (16UL) /*!< GPIO PADREGL: PAD46PULL (Bit 16) */ -#define GPIO_PADREGL_PAD46PULL_Msk (0x10000UL) /*!< GPIO PADREGL: PAD46PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGL_PAD45FNCSEL_Pos (11UL) /*!< GPIO PADREGL: PAD45FNCSEL (Bit 11) */ -#define GPIO_PADREGL_PAD45FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGL: PAD45FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGL_PAD45STRNG_Pos (10UL) /*!< GPIO PADREGL: PAD45STRNG (Bit 10) */ -#define GPIO_PADREGL_PAD45STRNG_Msk (0x400UL) /*!< GPIO PADREGL: PAD45STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGL_PAD45INPEN_Pos (9UL) /*!< GPIO PADREGL: PAD45INPEN (Bit 9) */ -#define GPIO_PADREGL_PAD45INPEN_Msk (0x200UL) /*!< GPIO PADREGL: PAD45INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGL_PAD45PULL_Pos (8UL) /*!< GPIO PADREGL: PAD45PULL (Bit 8) */ -#define GPIO_PADREGL_PAD45PULL_Msk (0x100UL) /*!< GPIO PADREGL: PAD45PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGL_PAD44FNCSEL_Pos (3UL) /*!< GPIO PADREGL: PAD44FNCSEL (Bit 3) */ -#define GPIO_PADREGL_PAD44FNCSEL_Msk (0x38UL) /*!< GPIO PADREGL: PAD44FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGL_PAD44STRNG_Pos (2UL) /*!< GPIO PADREGL: PAD44STRNG (Bit 2) */ -#define GPIO_PADREGL_PAD44STRNG_Msk (0x4UL) /*!< GPIO PADREGL: PAD44STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGL_PAD44INPEN_Pos (1UL) /*!< GPIO PADREGL: PAD44INPEN (Bit 1) */ -#define GPIO_PADREGL_PAD44INPEN_Msk (0x2UL) /*!< GPIO PADREGL: PAD44INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGL_PAD44PULL_Pos (0UL) /*!< GPIO PADREGL: PAD44PULL (Bit 0) */ -#define GPIO_PADREGL_PAD44PULL_Msk (0x1UL) /*!< GPIO PADREGL: PAD44PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGM ======================================================== */ -#define GPIO_PADREGM_PAD51FNCSEL_Pos (27UL) /*!< GPIO PADREGM: PAD51FNCSEL (Bit 27) */ -#define GPIO_PADREGM_PAD51FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGM: PAD51FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGM_PAD51STRNG_Pos (26UL) /*!< GPIO PADREGM: PAD51STRNG (Bit 26) */ -#define GPIO_PADREGM_PAD51STRNG_Msk (0x4000000UL) /*!< GPIO PADREGM: PAD51STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGM_PAD51INPEN_Pos (25UL) /*!< GPIO PADREGM: PAD51INPEN (Bit 25) */ -#define GPIO_PADREGM_PAD51INPEN_Msk (0x2000000UL) /*!< GPIO PADREGM: PAD51INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGM_PAD51PULL_Pos (24UL) /*!< GPIO PADREGM: PAD51PULL (Bit 24) */ -#define GPIO_PADREGM_PAD51PULL_Msk (0x1000000UL) /*!< GPIO PADREGM: PAD51PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGM_PAD50FNCSEL_Pos (19UL) /*!< GPIO PADREGM: PAD50FNCSEL (Bit 19) */ -#define GPIO_PADREGM_PAD50FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGM: PAD50FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGM_PAD50STRNG_Pos (18UL) /*!< GPIO PADREGM: PAD50STRNG (Bit 18) */ -#define GPIO_PADREGM_PAD50STRNG_Msk (0x40000UL) /*!< GPIO PADREGM: PAD50STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGM_PAD50INPEN_Pos (17UL) /*!< GPIO PADREGM: PAD50INPEN (Bit 17) */ -#define GPIO_PADREGM_PAD50INPEN_Msk (0x20000UL) /*!< GPIO PADREGM: PAD50INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGM_PAD50PULL_Pos (16UL) /*!< GPIO PADREGM: PAD50PULL (Bit 16) */ -#define GPIO_PADREGM_PAD50PULL_Msk (0x10000UL) /*!< GPIO PADREGM: PAD50PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGM_PAD49RSEL_Pos (14UL) /*!< GPIO PADREGM: PAD49RSEL (Bit 14) */ -#define GPIO_PADREGM_PAD49RSEL_Msk (0xc000UL) /*!< GPIO PADREGM: PAD49RSEL (Bitfield-Mask: 0x03) */ -#define GPIO_PADREGM_PAD49FNCSEL_Pos (11UL) /*!< GPIO PADREGM: PAD49FNCSEL (Bit 11) */ -#define GPIO_PADREGM_PAD49FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGM: PAD49FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGM_PAD49STRNG_Pos (10UL) /*!< GPIO PADREGM: PAD49STRNG (Bit 10) */ -#define GPIO_PADREGM_PAD49STRNG_Msk (0x400UL) /*!< GPIO PADREGM: PAD49STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGM_PAD49INPEN_Pos (9UL) /*!< GPIO PADREGM: PAD49INPEN (Bit 9) */ -#define GPIO_PADREGM_PAD49INPEN_Msk (0x200UL) /*!< GPIO PADREGM: PAD49INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGM_PAD49PULL_Pos (8UL) /*!< GPIO PADREGM: PAD49PULL (Bit 8) */ -#define GPIO_PADREGM_PAD49PULL_Msk (0x100UL) /*!< GPIO PADREGM: PAD49PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGM_PAD48RSEL_Pos (6UL) /*!< GPIO PADREGM: PAD48RSEL (Bit 6) */ -#define GPIO_PADREGM_PAD48RSEL_Msk (0xc0UL) /*!< GPIO PADREGM: PAD48RSEL (Bitfield-Mask: 0x03) */ -#define GPIO_PADREGM_PAD48FNCSEL_Pos (3UL) /*!< GPIO PADREGM: PAD48FNCSEL (Bit 3) */ -#define GPIO_PADREGM_PAD48FNCSEL_Msk (0x38UL) /*!< GPIO PADREGM: PAD48FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGM_PAD48STRNG_Pos (2UL) /*!< GPIO PADREGM: PAD48STRNG (Bit 2) */ -#define GPIO_PADREGM_PAD48STRNG_Msk (0x4UL) /*!< GPIO PADREGM: PAD48STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGM_PAD48INPEN_Pos (1UL) /*!< GPIO PADREGM: PAD48INPEN (Bit 1) */ -#define GPIO_PADREGM_PAD48INPEN_Msk (0x2UL) /*!< GPIO PADREGM: PAD48INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGM_PAD48PULL_Pos (0UL) /*!< GPIO PADREGM: PAD48PULL (Bit 0) */ -#define GPIO_PADREGM_PAD48PULL_Msk (0x1UL) /*!< GPIO PADREGM: PAD48PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGN ======================================================== */ -#define GPIO_PADREGN_PAD55FNCSEL_Pos (27UL) /*!< GPIO PADREGN: PAD55FNCSEL (Bit 27) */ -#define GPIO_PADREGN_PAD55FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGN: PAD55FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGN_PAD55STRNG_Pos (26UL) /*!< GPIO PADREGN: PAD55STRNG (Bit 26) */ -#define GPIO_PADREGN_PAD55STRNG_Msk (0x4000000UL) /*!< GPIO PADREGN: PAD55STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGN_PAD55INPEN_Pos (25UL) /*!< GPIO PADREGN: PAD55INPEN (Bit 25) */ -#define GPIO_PADREGN_PAD55INPEN_Msk (0x2000000UL) /*!< GPIO PADREGN: PAD55INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGN_PAD55PULL_Pos (24UL) /*!< GPIO PADREGN: PAD55PULL (Bit 24) */ -#define GPIO_PADREGN_PAD55PULL_Msk (0x1000000UL) /*!< GPIO PADREGN: PAD55PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGN_PAD54FNCSEL_Pos (19UL) /*!< GPIO PADREGN: PAD54FNCSEL (Bit 19) */ -#define GPIO_PADREGN_PAD54FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGN: PAD54FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGN_PAD54STRNG_Pos (18UL) /*!< GPIO PADREGN: PAD54STRNG (Bit 18) */ -#define GPIO_PADREGN_PAD54STRNG_Msk (0x40000UL) /*!< GPIO PADREGN: PAD54STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGN_PAD54INPEN_Pos (17UL) /*!< GPIO PADREGN: PAD54INPEN (Bit 17) */ -#define GPIO_PADREGN_PAD54INPEN_Msk (0x20000UL) /*!< GPIO PADREGN: PAD54INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGN_PAD54PULL_Pos (16UL) /*!< GPIO PADREGN: PAD54PULL (Bit 16) */ -#define GPIO_PADREGN_PAD54PULL_Msk (0x10000UL) /*!< GPIO PADREGN: PAD54PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGN_PAD53FNCSEL_Pos (11UL) /*!< GPIO PADREGN: PAD53FNCSEL (Bit 11) */ -#define GPIO_PADREGN_PAD53FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGN: PAD53FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGN_PAD53STRNG_Pos (10UL) /*!< GPIO PADREGN: PAD53STRNG (Bit 10) */ -#define GPIO_PADREGN_PAD53STRNG_Msk (0x400UL) /*!< GPIO PADREGN: PAD53STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGN_PAD53INPEN_Pos (9UL) /*!< GPIO PADREGN: PAD53INPEN (Bit 9) */ -#define GPIO_PADREGN_PAD53INPEN_Msk (0x200UL) /*!< GPIO PADREGN: PAD53INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGN_PAD53PULL_Pos (8UL) /*!< GPIO PADREGN: PAD53PULL (Bit 8) */ -#define GPIO_PADREGN_PAD53PULL_Msk (0x100UL) /*!< GPIO PADREGN: PAD53PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGN_PAD52FNCSEL_Pos (3UL) /*!< GPIO PADREGN: PAD52FNCSEL (Bit 3) */ -#define GPIO_PADREGN_PAD52FNCSEL_Msk (0x38UL) /*!< GPIO PADREGN: PAD52FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGN_PAD52STRNG_Pos (2UL) /*!< GPIO PADREGN: PAD52STRNG (Bit 2) */ -#define GPIO_PADREGN_PAD52STRNG_Msk (0x4UL) /*!< GPIO PADREGN: PAD52STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGN_PAD52INPEN_Pos (1UL) /*!< GPIO PADREGN: PAD52INPEN (Bit 1) */ -#define GPIO_PADREGN_PAD52INPEN_Msk (0x2UL) /*!< GPIO PADREGN: PAD52INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGN_PAD52PULL_Pos (0UL) /*!< GPIO PADREGN: PAD52PULL (Bit 0) */ -#define GPIO_PADREGN_PAD52PULL_Msk (0x1UL) /*!< GPIO PADREGN: PAD52PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGO ======================================================== */ -#define GPIO_PADREGO_PAD59FNCSEL_Pos (27UL) /*!< GPIO PADREGO: PAD59FNCSEL (Bit 27) */ -#define GPIO_PADREGO_PAD59FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGO: PAD59FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGO_PAD59STRNG_Pos (26UL) /*!< GPIO PADREGO: PAD59STRNG (Bit 26) */ -#define GPIO_PADREGO_PAD59STRNG_Msk (0x4000000UL) /*!< GPIO PADREGO: PAD59STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGO_PAD59INPEN_Pos (25UL) /*!< GPIO PADREGO: PAD59INPEN (Bit 25) */ -#define GPIO_PADREGO_PAD59INPEN_Msk (0x2000000UL) /*!< GPIO PADREGO: PAD59INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGO_PAD59PULL_Pos (24UL) /*!< GPIO PADREGO: PAD59PULL (Bit 24) */ -#define GPIO_PADREGO_PAD59PULL_Msk (0x1000000UL) /*!< GPIO PADREGO: PAD59PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGO_PAD58FNCSEL_Pos (19UL) /*!< GPIO PADREGO: PAD58FNCSEL (Bit 19) */ -#define GPIO_PADREGO_PAD58FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGO: PAD58FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGO_PAD58STRNG_Pos (18UL) /*!< GPIO PADREGO: PAD58STRNG (Bit 18) */ -#define GPIO_PADREGO_PAD58STRNG_Msk (0x40000UL) /*!< GPIO PADREGO: PAD58STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGO_PAD58INPEN_Pos (17UL) /*!< GPIO PADREGO: PAD58INPEN (Bit 17) */ -#define GPIO_PADREGO_PAD58INPEN_Msk (0x20000UL) /*!< GPIO PADREGO: PAD58INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGO_PAD58PULL_Pos (16UL) /*!< GPIO PADREGO: PAD58PULL (Bit 16) */ -#define GPIO_PADREGO_PAD58PULL_Msk (0x10000UL) /*!< GPIO PADREGO: PAD58PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGO_PAD57FNCSEL_Pos (11UL) /*!< GPIO PADREGO: PAD57FNCSEL (Bit 11) */ -#define GPIO_PADREGO_PAD57FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGO: PAD57FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGO_PAD57STRNG_Pos (10UL) /*!< GPIO PADREGO: PAD57STRNG (Bit 10) */ -#define GPIO_PADREGO_PAD57STRNG_Msk (0x400UL) /*!< GPIO PADREGO: PAD57STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGO_PAD57INPEN_Pos (9UL) /*!< GPIO PADREGO: PAD57INPEN (Bit 9) */ -#define GPIO_PADREGO_PAD57INPEN_Msk (0x200UL) /*!< GPIO PADREGO: PAD57INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGO_PAD57PULL_Pos (8UL) /*!< GPIO PADREGO: PAD57PULL (Bit 8) */ -#define GPIO_PADREGO_PAD57PULL_Msk (0x100UL) /*!< GPIO PADREGO: PAD57PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGO_PAD56FNCSEL_Pos (3UL) /*!< GPIO PADREGO: PAD56FNCSEL (Bit 3) */ -#define GPIO_PADREGO_PAD56FNCSEL_Msk (0x38UL) /*!< GPIO PADREGO: PAD56FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGO_PAD56STRNG_Pos (2UL) /*!< GPIO PADREGO: PAD56STRNG (Bit 2) */ -#define GPIO_PADREGO_PAD56STRNG_Msk (0x4UL) /*!< GPIO PADREGO: PAD56STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGO_PAD56INPEN_Pos (1UL) /*!< GPIO PADREGO: PAD56INPEN (Bit 1) */ -#define GPIO_PADREGO_PAD56INPEN_Msk (0x2UL) /*!< GPIO PADREGO: PAD56INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGO_PAD56PULL_Pos (0UL) /*!< GPIO PADREGO: PAD56PULL (Bit 0) */ -#define GPIO_PADREGO_PAD56PULL_Msk (0x1UL) /*!< GPIO PADREGO: PAD56PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGP ======================================================== */ -#define GPIO_PADREGP_PAD63FNCSEL_Pos (27UL) /*!< GPIO PADREGP: PAD63FNCSEL (Bit 27) */ -#define GPIO_PADREGP_PAD63FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGP: PAD63FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGP_PAD63STRNG_Pos (26UL) /*!< GPIO PADREGP: PAD63STRNG (Bit 26) */ -#define GPIO_PADREGP_PAD63STRNG_Msk (0x4000000UL) /*!< GPIO PADREGP: PAD63STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGP_PAD63INPEN_Pos (25UL) /*!< GPIO PADREGP: PAD63INPEN (Bit 25) */ -#define GPIO_PADREGP_PAD63INPEN_Msk (0x2000000UL) /*!< GPIO PADREGP: PAD63INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGP_PAD63PULL_Pos (24UL) /*!< GPIO PADREGP: PAD63PULL (Bit 24) */ -#define GPIO_PADREGP_PAD63PULL_Msk (0x1000000UL) /*!< GPIO PADREGP: PAD63PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGP_PAD62FNCSEL_Pos (19UL) /*!< GPIO PADREGP: PAD62FNCSEL (Bit 19) */ -#define GPIO_PADREGP_PAD62FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGP: PAD62FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGP_PAD62STRNG_Pos (18UL) /*!< GPIO PADREGP: PAD62STRNG (Bit 18) */ -#define GPIO_PADREGP_PAD62STRNG_Msk (0x40000UL) /*!< GPIO PADREGP: PAD62STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGP_PAD62INPEN_Pos (17UL) /*!< GPIO PADREGP: PAD62INPEN (Bit 17) */ -#define GPIO_PADREGP_PAD62INPEN_Msk (0x20000UL) /*!< GPIO PADREGP: PAD62INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGP_PAD62PULL_Pos (16UL) /*!< GPIO PADREGP: PAD62PULL (Bit 16) */ -#define GPIO_PADREGP_PAD62PULL_Msk (0x10000UL) /*!< GPIO PADREGP: PAD62PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGP_PAD61FNCSEL_Pos (11UL) /*!< GPIO PADREGP: PAD61FNCSEL (Bit 11) */ -#define GPIO_PADREGP_PAD61FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGP: PAD61FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGP_PAD61STRNG_Pos (10UL) /*!< GPIO PADREGP: PAD61STRNG (Bit 10) */ -#define GPIO_PADREGP_PAD61STRNG_Msk (0x400UL) /*!< GPIO PADREGP: PAD61STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGP_PAD61INPEN_Pos (9UL) /*!< GPIO PADREGP: PAD61INPEN (Bit 9) */ -#define GPIO_PADREGP_PAD61INPEN_Msk (0x200UL) /*!< GPIO PADREGP: PAD61INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGP_PAD61PULL_Pos (8UL) /*!< GPIO PADREGP: PAD61PULL (Bit 8) */ -#define GPIO_PADREGP_PAD61PULL_Msk (0x100UL) /*!< GPIO PADREGP: PAD61PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGP_PAD60FNCSEL_Pos (3UL) /*!< GPIO PADREGP: PAD60FNCSEL (Bit 3) */ -#define GPIO_PADREGP_PAD60FNCSEL_Msk (0x38UL) /*!< GPIO PADREGP: PAD60FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGP_PAD60STRNG_Pos (2UL) /*!< GPIO PADREGP: PAD60STRNG (Bit 2) */ -#define GPIO_PADREGP_PAD60STRNG_Msk (0x4UL) /*!< GPIO PADREGP: PAD60STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGP_PAD60INPEN_Pos (1UL) /*!< GPIO PADREGP: PAD60INPEN (Bit 1) */ -#define GPIO_PADREGP_PAD60INPEN_Msk (0x2UL) /*!< GPIO PADREGP: PAD60INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGP_PAD60PULL_Pos (0UL) /*!< GPIO PADREGP: PAD60PULL (Bit 0) */ -#define GPIO_PADREGP_PAD60PULL_Msk (0x1UL) /*!< GPIO PADREGP: PAD60PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGQ ======================================================== */ -#define GPIO_PADREGQ_PAD67FNCSEL_Pos (27UL) /*!< GPIO PADREGQ: PAD67FNCSEL (Bit 27) */ -#define GPIO_PADREGQ_PAD67FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGQ: PAD67FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGQ_PAD67STRNG_Pos (26UL) /*!< GPIO PADREGQ: PAD67STRNG (Bit 26) */ -#define GPIO_PADREGQ_PAD67STRNG_Msk (0x4000000UL) /*!< GPIO PADREGQ: PAD67STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGQ_PAD67INPEN_Pos (25UL) /*!< GPIO PADREGQ: PAD67INPEN (Bit 25) */ -#define GPIO_PADREGQ_PAD67INPEN_Msk (0x2000000UL) /*!< GPIO PADREGQ: PAD67INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGQ_PAD67PULL_Pos (24UL) /*!< GPIO PADREGQ: PAD67PULL (Bit 24) */ -#define GPIO_PADREGQ_PAD67PULL_Msk (0x1000000UL) /*!< GPIO PADREGQ: PAD67PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGQ_PAD66FNCSEL_Pos (19UL) /*!< GPIO PADREGQ: PAD66FNCSEL (Bit 19) */ -#define GPIO_PADREGQ_PAD66FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGQ: PAD66FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGQ_PAD66STRNG_Pos (18UL) /*!< GPIO PADREGQ: PAD66STRNG (Bit 18) */ -#define GPIO_PADREGQ_PAD66STRNG_Msk (0x40000UL) /*!< GPIO PADREGQ: PAD66STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGQ_PAD66INPEN_Pos (17UL) /*!< GPIO PADREGQ: PAD66INPEN (Bit 17) */ -#define GPIO_PADREGQ_PAD66INPEN_Msk (0x20000UL) /*!< GPIO PADREGQ: PAD66INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGQ_PAD66PULL_Pos (16UL) /*!< GPIO PADREGQ: PAD66PULL (Bit 16) */ -#define GPIO_PADREGQ_PAD66PULL_Msk (0x10000UL) /*!< GPIO PADREGQ: PAD66PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGQ_PAD65FNCSEL_Pos (11UL) /*!< GPIO PADREGQ: PAD65FNCSEL (Bit 11) */ -#define GPIO_PADREGQ_PAD65FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGQ: PAD65FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGQ_PAD65STRNG_Pos (10UL) /*!< GPIO PADREGQ: PAD65STRNG (Bit 10) */ -#define GPIO_PADREGQ_PAD65STRNG_Msk (0x400UL) /*!< GPIO PADREGQ: PAD65STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGQ_PAD65INPEN_Pos (9UL) /*!< GPIO PADREGQ: PAD65INPEN (Bit 9) */ -#define GPIO_PADREGQ_PAD65INPEN_Msk (0x200UL) /*!< GPIO PADREGQ: PAD65INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGQ_PAD65PULL_Pos (8UL) /*!< GPIO PADREGQ: PAD65PULL (Bit 8) */ -#define GPIO_PADREGQ_PAD65PULL_Msk (0x100UL) /*!< GPIO PADREGQ: PAD65PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGQ_PAD64FNCSEL_Pos (3UL) /*!< GPIO PADREGQ: PAD64FNCSEL (Bit 3) */ -#define GPIO_PADREGQ_PAD64FNCSEL_Msk (0x38UL) /*!< GPIO PADREGQ: PAD64FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGQ_PAD64STRNG_Pos (2UL) /*!< GPIO PADREGQ: PAD64STRNG (Bit 2) */ -#define GPIO_PADREGQ_PAD64STRNG_Msk (0x4UL) /*!< GPIO PADREGQ: PAD64STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGQ_PAD64INPEN_Pos (1UL) /*!< GPIO PADREGQ: PAD64INPEN (Bit 1) */ -#define GPIO_PADREGQ_PAD64INPEN_Msk (0x2UL) /*!< GPIO PADREGQ: PAD64INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGQ_PAD64PULL_Pos (0UL) /*!< GPIO PADREGQ: PAD64PULL (Bit 0) */ -#define GPIO_PADREGQ_PAD64PULL_Msk (0x1UL) /*!< GPIO PADREGQ: PAD64PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGR ======================================================== */ -#define GPIO_PADREGR_PAD71FNCSEL_Pos (27UL) /*!< GPIO PADREGR: PAD71FNCSEL (Bit 27) */ -#define GPIO_PADREGR_PAD71FNCSEL_Msk (0x38000000UL) /*!< GPIO PADREGR: PAD71FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGR_PAD71STRNG_Pos (26UL) /*!< GPIO PADREGR: PAD71STRNG (Bit 26) */ -#define GPIO_PADREGR_PAD71STRNG_Msk (0x4000000UL) /*!< GPIO PADREGR: PAD71STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGR_PAD71INPEN_Pos (25UL) /*!< GPIO PADREGR: PAD71INPEN (Bit 25) */ -#define GPIO_PADREGR_PAD71INPEN_Msk (0x2000000UL) /*!< GPIO PADREGR: PAD71INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGR_PAD71PULL_Pos (24UL) /*!< GPIO PADREGR: PAD71PULL (Bit 24) */ -#define GPIO_PADREGR_PAD71PULL_Msk (0x1000000UL) /*!< GPIO PADREGR: PAD71PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGR_PAD70FNCSEL_Pos (19UL) /*!< GPIO PADREGR: PAD70FNCSEL (Bit 19) */ -#define GPIO_PADREGR_PAD70FNCSEL_Msk (0x380000UL) /*!< GPIO PADREGR: PAD70FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGR_PAD70STRNG_Pos (18UL) /*!< GPIO PADREGR: PAD70STRNG (Bit 18) */ -#define GPIO_PADREGR_PAD70STRNG_Msk (0x40000UL) /*!< GPIO PADREGR: PAD70STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGR_PAD70INPEN_Pos (17UL) /*!< GPIO PADREGR: PAD70INPEN (Bit 17) */ -#define GPIO_PADREGR_PAD70INPEN_Msk (0x20000UL) /*!< GPIO PADREGR: PAD70INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGR_PAD70PULL_Pos (16UL) /*!< GPIO PADREGR: PAD70PULL (Bit 16) */ -#define GPIO_PADREGR_PAD70PULL_Msk (0x10000UL) /*!< GPIO PADREGR: PAD70PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGR_PAD69FNCSEL_Pos (11UL) /*!< GPIO PADREGR: PAD69FNCSEL (Bit 11) */ -#define GPIO_PADREGR_PAD69FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGR: PAD69FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGR_PAD69STRNG_Pos (10UL) /*!< GPIO PADREGR: PAD69STRNG (Bit 10) */ -#define GPIO_PADREGR_PAD69STRNG_Msk (0x400UL) /*!< GPIO PADREGR: PAD69STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGR_PAD69INPEN_Pos (9UL) /*!< GPIO PADREGR: PAD69INPEN (Bit 9) */ -#define GPIO_PADREGR_PAD69INPEN_Msk (0x200UL) /*!< GPIO PADREGR: PAD69INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGR_PAD69PULL_Pos (8UL) /*!< GPIO PADREGR: PAD69PULL (Bit 8) */ -#define GPIO_PADREGR_PAD69PULL_Msk (0x100UL) /*!< GPIO PADREGR: PAD69PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGR_PAD68FNCSEL_Pos (3UL) /*!< GPIO PADREGR: PAD68FNCSEL (Bit 3) */ -#define GPIO_PADREGR_PAD68FNCSEL_Msk (0x38UL) /*!< GPIO PADREGR: PAD68FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGR_PAD68STRNG_Pos (2UL) /*!< GPIO PADREGR: PAD68STRNG (Bit 2) */ -#define GPIO_PADREGR_PAD68STRNG_Msk (0x4UL) /*!< GPIO PADREGR: PAD68STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGR_PAD68INPEN_Pos (1UL) /*!< GPIO PADREGR: PAD68INPEN (Bit 1) */ -#define GPIO_PADREGR_PAD68INPEN_Msk (0x2UL) /*!< GPIO PADREGR: PAD68INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGR_PAD68PULL_Pos (0UL) /*!< GPIO PADREGR: PAD68PULL (Bit 0) */ -#define GPIO_PADREGR_PAD68PULL_Msk (0x1UL) /*!< GPIO PADREGR: PAD68PULL (Bitfield-Mask: 0x01) */ -/* ======================================================== PADREGS ======================================================== */ -#define GPIO_PADREGS_PAD73FNCSEL_Pos (11UL) /*!< GPIO PADREGS: PAD73FNCSEL (Bit 11) */ -#define GPIO_PADREGS_PAD73FNCSEL_Msk (0x3800UL) /*!< GPIO PADREGS: PAD73FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGS_PAD73STRNG_Pos (10UL) /*!< GPIO PADREGS: PAD73STRNG (Bit 10) */ -#define GPIO_PADREGS_PAD73STRNG_Msk (0x400UL) /*!< GPIO PADREGS: PAD73STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGS_PAD73INPEN_Pos (9UL) /*!< GPIO PADREGS: PAD73INPEN (Bit 9) */ -#define GPIO_PADREGS_PAD73INPEN_Msk (0x200UL) /*!< GPIO PADREGS: PAD73INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGS_PAD73PULL_Pos (8UL) /*!< GPIO PADREGS: PAD73PULL (Bit 8) */ -#define GPIO_PADREGS_PAD73PULL_Msk (0x100UL) /*!< GPIO PADREGS: PAD73PULL (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGS_PAD72FNCSEL_Pos (3UL) /*!< GPIO PADREGS: PAD72FNCSEL (Bit 3) */ -#define GPIO_PADREGS_PAD72FNCSEL_Msk (0x38UL) /*!< GPIO PADREGS: PAD72FNCSEL (Bitfield-Mask: 0x07) */ -#define GPIO_PADREGS_PAD72STRNG_Pos (2UL) /*!< GPIO PADREGS: PAD72STRNG (Bit 2) */ -#define GPIO_PADREGS_PAD72STRNG_Msk (0x4UL) /*!< GPIO PADREGS: PAD72STRNG (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGS_PAD72INPEN_Pos (1UL) /*!< GPIO PADREGS: PAD72INPEN (Bit 1) */ -#define GPIO_PADREGS_PAD72INPEN_Msk (0x2UL) /*!< GPIO PADREGS: PAD72INPEN (Bitfield-Mask: 0x01) */ -#define GPIO_PADREGS_PAD72PULL_Pos (0UL) /*!< GPIO PADREGS: PAD72PULL (Bit 0) */ -#define GPIO_PADREGS_PAD72PULL_Msk (0x1UL) /*!< GPIO PADREGS: PAD72PULL (Bitfield-Mask: 0x01) */ -/* ========================================================= CFGA ========================================================== */ -#define GPIO_CFGA_GPIO7INTD_Pos (31UL) /*!< GPIO CFGA: GPIO7INTD (Bit 31) */ -#define GPIO_CFGA_GPIO7INTD_Msk (0x80000000UL) /*!< GPIO CFGA: GPIO7INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGA_GPIO7OUTCFG_Pos (29UL) /*!< GPIO CFGA: GPIO7OUTCFG (Bit 29) */ -#define GPIO_CFGA_GPIO7OUTCFG_Msk (0x60000000UL) /*!< GPIO CFGA: GPIO7OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGA_GPIO7INCFG_Pos (28UL) /*!< GPIO CFGA: GPIO7INCFG (Bit 28) */ -#define GPIO_CFGA_GPIO7INCFG_Msk (0x10000000UL) /*!< GPIO CFGA: GPIO7INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGA_GPIO6INTD_Pos (27UL) /*!< GPIO CFGA: GPIO6INTD (Bit 27) */ -#define GPIO_CFGA_GPIO6INTD_Msk (0x8000000UL) /*!< GPIO CFGA: GPIO6INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGA_GPIO6OUTCFG_Pos (25UL) /*!< GPIO CFGA: GPIO6OUTCFG (Bit 25) */ -#define GPIO_CFGA_GPIO6OUTCFG_Msk (0x6000000UL) /*!< GPIO CFGA: GPIO6OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGA_GPIO6INCFG_Pos (24UL) /*!< GPIO CFGA: GPIO6INCFG (Bit 24) */ -#define GPIO_CFGA_GPIO6INCFG_Msk (0x1000000UL) /*!< GPIO CFGA: GPIO6INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGA_GPIO5INTD_Pos (23UL) /*!< GPIO CFGA: GPIO5INTD (Bit 23) */ -#define GPIO_CFGA_GPIO5INTD_Msk (0x800000UL) /*!< GPIO CFGA: GPIO5INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGA_GPIO5OUTCFG_Pos (21UL) /*!< GPIO CFGA: GPIO5OUTCFG (Bit 21) */ -#define GPIO_CFGA_GPIO5OUTCFG_Msk (0x600000UL) /*!< GPIO CFGA: GPIO5OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGA_GPIO5INCFG_Pos (20UL) /*!< GPIO CFGA: GPIO5INCFG (Bit 20) */ -#define GPIO_CFGA_GPIO5INCFG_Msk (0x100000UL) /*!< GPIO CFGA: GPIO5INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGA_GPIO4INTD_Pos (19UL) /*!< GPIO CFGA: GPIO4INTD (Bit 19) */ -#define GPIO_CFGA_GPIO4INTD_Msk (0x80000UL) /*!< GPIO CFGA: GPIO4INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGA_GPIO4OUTCFG_Pos (17UL) /*!< GPIO CFGA: GPIO4OUTCFG (Bit 17) */ -#define GPIO_CFGA_GPIO4OUTCFG_Msk (0x60000UL) /*!< GPIO CFGA: GPIO4OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGA_GPIO4INCFG_Pos (16UL) /*!< GPIO CFGA: GPIO4INCFG (Bit 16) */ -#define GPIO_CFGA_GPIO4INCFG_Msk (0x10000UL) /*!< GPIO CFGA: GPIO4INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGA_GPIO3INTD_Pos (15UL) /*!< GPIO CFGA: GPIO3INTD (Bit 15) */ -#define GPIO_CFGA_GPIO3INTD_Msk (0x8000UL) /*!< GPIO CFGA: GPIO3INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGA_GPIO3OUTCFG_Pos (13UL) /*!< GPIO CFGA: GPIO3OUTCFG (Bit 13) */ -#define GPIO_CFGA_GPIO3OUTCFG_Msk (0x6000UL) /*!< GPIO CFGA: GPIO3OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGA_GPIO3INCFG_Pos (12UL) /*!< GPIO CFGA: GPIO3INCFG (Bit 12) */ -#define GPIO_CFGA_GPIO3INCFG_Msk (0x1000UL) /*!< GPIO CFGA: GPIO3INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGA_GPIO2INTD_Pos (11UL) /*!< GPIO CFGA: GPIO2INTD (Bit 11) */ -#define GPIO_CFGA_GPIO2INTD_Msk (0x800UL) /*!< GPIO CFGA: GPIO2INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGA_GPIO2OUTCFG_Pos (9UL) /*!< GPIO CFGA: GPIO2OUTCFG (Bit 9) */ -#define GPIO_CFGA_GPIO2OUTCFG_Msk (0x600UL) /*!< GPIO CFGA: GPIO2OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGA_GPIO2INCFG_Pos (8UL) /*!< GPIO CFGA: GPIO2INCFG (Bit 8) */ -#define GPIO_CFGA_GPIO2INCFG_Msk (0x100UL) /*!< GPIO CFGA: GPIO2INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGA_GPIO1INTD_Pos (7UL) /*!< GPIO CFGA: GPIO1INTD (Bit 7) */ -#define GPIO_CFGA_GPIO1INTD_Msk (0x80UL) /*!< GPIO CFGA: GPIO1INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGA_GPIO1OUTCFG_Pos (5UL) /*!< GPIO CFGA: GPIO1OUTCFG (Bit 5) */ -#define GPIO_CFGA_GPIO1OUTCFG_Msk (0x60UL) /*!< GPIO CFGA: GPIO1OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGA_GPIO1INCFG_Pos (4UL) /*!< GPIO CFGA: GPIO1INCFG (Bit 4) */ -#define GPIO_CFGA_GPIO1INCFG_Msk (0x10UL) /*!< GPIO CFGA: GPIO1INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGA_GPIO0INTD_Pos (3UL) /*!< GPIO CFGA: GPIO0INTD (Bit 3) */ -#define GPIO_CFGA_GPIO0INTD_Msk (0x8UL) /*!< GPIO CFGA: GPIO0INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGA_GPIO0OUTCFG_Pos (1UL) /*!< GPIO CFGA: GPIO0OUTCFG (Bit 1) */ -#define GPIO_CFGA_GPIO0OUTCFG_Msk (0x6UL) /*!< GPIO CFGA: GPIO0OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGA_GPIO0INCFG_Pos (0UL) /*!< GPIO CFGA: GPIO0INCFG (Bit 0) */ -#define GPIO_CFGA_GPIO0INCFG_Msk (0x1UL) /*!< GPIO CFGA: GPIO0INCFG (Bitfield-Mask: 0x01) */ -/* ========================================================= CFGB ========================================================== */ -#define GPIO_CFGB_GPIO15INTD_Pos (31UL) /*!< GPIO CFGB: GPIO15INTD (Bit 31) */ -#define GPIO_CFGB_GPIO15INTD_Msk (0x80000000UL) /*!< GPIO CFGB: GPIO15INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGB_GPIO15OUTCFG_Pos (29UL) /*!< GPIO CFGB: GPIO15OUTCFG (Bit 29) */ -#define GPIO_CFGB_GPIO15OUTCFG_Msk (0x60000000UL) /*!< GPIO CFGB: GPIO15OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGB_GPIO15INCFG_Pos (28UL) /*!< GPIO CFGB: GPIO15INCFG (Bit 28) */ -#define GPIO_CFGB_GPIO15INCFG_Msk (0x10000000UL) /*!< GPIO CFGB: GPIO15INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGB_GPIO14INTD_Pos (27UL) /*!< GPIO CFGB: GPIO14INTD (Bit 27) */ -#define GPIO_CFGB_GPIO14INTD_Msk (0x8000000UL) /*!< GPIO CFGB: GPIO14INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGB_GPIO14OUTCFG_Pos (25UL) /*!< GPIO CFGB: GPIO14OUTCFG (Bit 25) */ -#define GPIO_CFGB_GPIO14OUTCFG_Msk (0x6000000UL) /*!< GPIO CFGB: GPIO14OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGB_GPIO14INCFG_Pos (24UL) /*!< GPIO CFGB: GPIO14INCFG (Bit 24) */ -#define GPIO_CFGB_GPIO14INCFG_Msk (0x1000000UL) /*!< GPIO CFGB: GPIO14INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGB_GPIO13INTD_Pos (23UL) /*!< GPIO CFGB: GPIO13INTD (Bit 23) */ -#define GPIO_CFGB_GPIO13INTD_Msk (0x800000UL) /*!< GPIO CFGB: GPIO13INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGB_GPIO13OUTCFG_Pos (21UL) /*!< GPIO CFGB: GPIO13OUTCFG (Bit 21) */ -#define GPIO_CFGB_GPIO13OUTCFG_Msk (0x600000UL) /*!< GPIO CFGB: GPIO13OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGB_GPIO13INCFG_Pos (20UL) /*!< GPIO CFGB: GPIO13INCFG (Bit 20) */ -#define GPIO_CFGB_GPIO13INCFG_Msk (0x100000UL) /*!< GPIO CFGB: GPIO13INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGB_GPIO12INTD_Pos (19UL) /*!< GPIO CFGB: GPIO12INTD (Bit 19) */ -#define GPIO_CFGB_GPIO12INTD_Msk (0x80000UL) /*!< GPIO CFGB: GPIO12INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGB_GPIO12OUTCFG_Pos (17UL) /*!< GPIO CFGB: GPIO12OUTCFG (Bit 17) */ -#define GPIO_CFGB_GPIO12OUTCFG_Msk (0x60000UL) /*!< GPIO CFGB: GPIO12OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGB_GPIO12INCFG_Pos (16UL) /*!< GPIO CFGB: GPIO12INCFG (Bit 16) */ -#define GPIO_CFGB_GPIO12INCFG_Msk (0x10000UL) /*!< GPIO CFGB: GPIO12INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGB_GPIO11INTD_Pos (15UL) /*!< GPIO CFGB: GPIO11INTD (Bit 15) */ -#define GPIO_CFGB_GPIO11INTD_Msk (0x8000UL) /*!< GPIO CFGB: GPIO11INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGB_GPIO11OUTCFG_Pos (13UL) /*!< GPIO CFGB: GPIO11OUTCFG (Bit 13) */ -#define GPIO_CFGB_GPIO11OUTCFG_Msk (0x6000UL) /*!< GPIO CFGB: GPIO11OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGB_GPIO11INCFG_Pos (12UL) /*!< GPIO CFGB: GPIO11INCFG (Bit 12) */ -#define GPIO_CFGB_GPIO11INCFG_Msk (0x1000UL) /*!< GPIO CFGB: GPIO11INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGB_GPIO10INTD_Pos (11UL) /*!< GPIO CFGB: GPIO10INTD (Bit 11) */ -#define GPIO_CFGB_GPIO10INTD_Msk (0x800UL) /*!< GPIO CFGB: GPIO10INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGB_GPIO10OUTCFG_Pos (9UL) /*!< GPIO CFGB: GPIO10OUTCFG (Bit 9) */ -#define GPIO_CFGB_GPIO10OUTCFG_Msk (0x600UL) /*!< GPIO CFGB: GPIO10OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGB_GPIO10INCFG_Pos (8UL) /*!< GPIO CFGB: GPIO10INCFG (Bit 8) */ -#define GPIO_CFGB_GPIO10INCFG_Msk (0x100UL) /*!< GPIO CFGB: GPIO10INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGB_GPIO9INTD_Pos (7UL) /*!< GPIO CFGB: GPIO9INTD (Bit 7) */ -#define GPIO_CFGB_GPIO9INTD_Msk (0x80UL) /*!< GPIO CFGB: GPIO9INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGB_GPIO9OUTCFG_Pos (5UL) /*!< GPIO CFGB: GPIO9OUTCFG (Bit 5) */ -#define GPIO_CFGB_GPIO9OUTCFG_Msk (0x60UL) /*!< GPIO CFGB: GPIO9OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGB_GPIO9INCFG_Pos (4UL) /*!< GPIO CFGB: GPIO9INCFG (Bit 4) */ -#define GPIO_CFGB_GPIO9INCFG_Msk (0x10UL) /*!< GPIO CFGB: GPIO9INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGB_GPIO8INTD_Pos (3UL) /*!< GPIO CFGB: GPIO8INTD (Bit 3) */ -#define GPIO_CFGB_GPIO8INTD_Msk (0x8UL) /*!< GPIO CFGB: GPIO8INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGB_GPIO8OUTCFG_Pos (1UL) /*!< GPIO CFGB: GPIO8OUTCFG (Bit 1) */ -#define GPIO_CFGB_GPIO8OUTCFG_Msk (0x6UL) /*!< GPIO CFGB: GPIO8OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGB_GPIO8INCFG_Pos (0UL) /*!< GPIO CFGB: GPIO8INCFG (Bit 0) */ -#define GPIO_CFGB_GPIO8INCFG_Msk (0x1UL) /*!< GPIO CFGB: GPIO8INCFG (Bitfield-Mask: 0x01) */ -/* ========================================================= CFGC ========================================================== */ -#define GPIO_CFGC_GPIO23INTD_Pos (31UL) /*!< GPIO CFGC: GPIO23INTD (Bit 31) */ -#define GPIO_CFGC_GPIO23INTD_Msk (0x80000000UL) /*!< GPIO CFGC: GPIO23INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGC_GPIO23OUTCFG_Pos (29UL) /*!< GPIO CFGC: GPIO23OUTCFG (Bit 29) */ -#define GPIO_CFGC_GPIO23OUTCFG_Msk (0x60000000UL) /*!< GPIO CFGC: GPIO23OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGC_GPIO23INCFG_Pos (28UL) /*!< GPIO CFGC: GPIO23INCFG (Bit 28) */ -#define GPIO_CFGC_GPIO23INCFG_Msk (0x10000000UL) /*!< GPIO CFGC: GPIO23INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGC_GPIO22INTD_Pos (27UL) /*!< GPIO CFGC: GPIO22INTD (Bit 27) */ -#define GPIO_CFGC_GPIO22INTD_Msk (0x8000000UL) /*!< GPIO CFGC: GPIO22INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGC_GPIO22OUTCFG_Pos (25UL) /*!< GPIO CFGC: GPIO22OUTCFG (Bit 25) */ -#define GPIO_CFGC_GPIO22OUTCFG_Msk (0x6000000UL) /*!< GPIO CFGC: GPIO22OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGC_GPIO22INCFG_Pos (24UL) /*!< GPIO CFGC: GPIO22INCFG (Bit 24) */ -#define GPIO_CFGC_GPIO22INCFG_Msk (0x1000000UL) /*!< GPIO CFGC: GPIO22INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGC_GPIO21INTD_Pos (23UL) /*!< GPIO CFGC: GPIO21INTD (Bit 23) */ -#define GPIO_CFGC_GPIO21INTD_Msk (0x800000UL) /*!< GPIO CFGC: GPIO21INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGC_GPIO21OUTCFG_Pos (21UL) /*!< GPIO CFGC: GPIO21OUTCFG (Bit 21) */ -#define GPIO_CFGC_GPIO21OUTCFG_Msk (0x600000UL) /*!< GPIO CFGC: GPIO21OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGC_GPIO21INCFG_Pos (20UL) /*!< GPIO CFGC: GPIO21INCFG (Bit 20) */ -#define GPIO_CFGC_GPIO21INCFG_Msk (0x100000UL) /*!< GPIO CFGC: GPIO21INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGC_GPIO20INTD_Pos (19UL) /*!< GPIO CFGC: GPIO20INTD (Bit 19) */ -#define GPIO_CFGC_GPIO20INTD_Msk (0x80000UL) /*!< GPIO CFGC: GPIO20INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGC_GPIO20OUTCFG_Pos (17UL) /*!< GPIO CFGC: GPIO20OUTCFG (Bit 17) */ -#define GPIO_CFGC_GPIO20OUTCFG_Msk (0x60000UL) /*!< GPIO CFGC: GPIO20OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGC_GPIO20INCFG_Pos (16UL) /*!< GPIO CFGC: GPIO20INCFG (Bit 16) */ -#define GPIO_CFGC_GPIO20INCFG_Msk (0x10000UL) /*!< GPIO CFGC: GPIO20INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGC_GPIO19INTD_Pos (15UL) /*!< GPIO CFGC: GPIO19INTD (Bit 15) */ -#define GPIO_CFGC_GPIO19INTD_Msk (0x8000UL) /*!< GPIO CFGC: GPIO19INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGC_GPIO19OUTCFG_Pos (13UL) /*!< GPIO CFGC: GPIO19OUTCFG (Bit 13) */ -#define GPIO_CFGC_GPIO19OUTCFG_Msk (0x6000UL) /*!< GPIO CFGC: GPIO19OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGC_GPIO19INCFG_Pos (12UL) /*!< GPIO CFGC: GPIO19INCFG (Bit 12) */ -#define GPIO_CFGC_GPIO19INCFG_Msk (0x1000UL) /*!< GPIO CFGC: GPIO19INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGC_GPIO18INTD_Pos (11UL) /*!< GPIO CFGC: GPIO18INTD (Bit 11) */ -#define GPIO_CFGC_GPIO18INTD_Msk (0x800UL) /*!< GPIO CFGC: GPIO18INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGC_GPIO18OUTCFG_Pos (9UL) /*!< GPIO CFGC: GPIO18OUTCFG (Bit 9) */ -#define GPIO_CFGC_GPIO18OUTCFG_Msk (0x600UL) /*!< GPIO CFGC: GPIO18OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGC_GPIO18INCFG_Pos (8UL) /*!< GPIO CFGC: GPIO18INCFG (Bit 8) */ -#define GPIO_CFGC_GPIO18INCFG_Msk (0x100UL) /*!< GPIO CFGC: GPIO18INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGC_GPIO17INTD_Pos (7UL) /*!< GPIO CFGC: GPIO17INTD (Bit 7) */ -#define GPIO_CFGC_GPIO17INTD_Msk (0x80UL) /*!< GPIO CFGC: GPIO17INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGC_GPIO17OUTCFG_Pos (5UL) /*!< GPIO CFGC: GPIO17OUTCFG (Bit 5) */ -#define GPIO_CFGC_GPIO17OUTCFG_Msk (0x60UL) /*!< GPIO CFGC: GPIO17OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGC_GPIO17INCFG_Pos (4UL) /*!< GPIO CFGC: GPIO17INCFG (Bit 4) */ -#define GPIO_CFGC_GPIO17INCFG_Msk (0x10UL) /*!< GPIO CFGC: GPIO17INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGC_GPIO16INTD_Pos (3UL) /*!< GPIO CFGC: GPIO16INTD (Bit 3) */ -#define GPIO_CFGC_GPIO16INTD_Msk (0x8UL) /*!< GPIO CFGC: GPIO16INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGC_GPIO16OUTCFG_Pos (1UL) /*!< GPIO CFGC: GPIO16OUTCFG (Bit 1) */ -#define GPIO_CFGC_GPIO16OUTCFG_Msk (0x6UL) /*!< GPIO CFGC: GPIO16OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGC_GPIO16INCFG_Pos (0UL) /*!< GPIO CFGC: GPIO16INCFG (Bit 0) */ -#define GPIO_CFGC_GPIO16INCFG_Msk (0x1UL) /*!< GPIO CFGC: GPIO16INCFG (Bitfield-Mask: 0x01) */ -/* ========================================================= CFGD ========================================================== */ -#define GPIO_CFGD_GPIO31INTD_Pos (31UL) /*!< GPIO CFGD: GPIO31INTD (Bit 31) */ -#define GPIO_CFGD_GPIO31INTD_Msk (0x80000000UL) /*!< GPIO CFGD: GPIO31INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGD_GPIO31OUTCFG_Pos (29UL) /*!< GPIO CFGD: GPIO31OUTCFG (Bit 29) */ -#define GPIO_CFGD_GPIO31OUTCFG_Msk (0x60000000UL) /*!< GPIO CFGD: GPIO31OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGD_GPIO31INCFG_Pos (28UL) /*!< GPIO CFGD: GPIO31INCFG (Bit 28) */ -#define GPIO_CFGD_GPIO31INCFG_Msk (0x10000000UL) /*!< GPIO CFGD: GPIO31INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGD_GPIO30INTD_Pos (27UL) /*!< GPIO CFGD: GPIO30INTD (Bit 27) */ -#define GPIO_CFGD_GPIO30INTD_Msk (0x8000000UL) /*!< GPIO CFGD: GPIO30INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGD_GPIO30OUTCFG_Pos (25UL) /*!< GPIO CFGD: GPIO30OUTCFG (Bit 25) */ -#define GPIO_CFGD_GPIO30OUTCFG_Msk (0x6000000UL) /*!< GPIO CFGD: GPIO30OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGD_GPIO30INCFG_Pos (24UL) /*!< GPIO CFGD: GPIO30INCFG (Bit 24) */ -#define GPIO_CFGD_GPIO30INCFG_Msk (0x1000000UL) /*!< GPIO CFGD: GPIO30INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGD_GPIO29INTD_Pos (23UL) /*!< GPIO CFGD: GPIO29INTD (Bit 23) */ -#define GPIO_CFGD_GPIO29INTD_Msk (0x800000UL) /*!< GPIO CFGD: GPIO29INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGD_GPIO29OUTCFG_Pos (21UL) /*!< GPIO CFGD: GPIO29OUTCFG (Bit 21) */ -#define GPIO_CFGD_GPIO29OUTCFG_Msk (0x600000UL) /*!< GPIO CFGD: GPIO29OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGD_GPIO29INCFG_Pos (20UL) /*!< GPIO CFGD: GPIO29INCFG (Bit 20) */ -#define GPIO_CFGD_GPIO29INCFG_Msk (0x100000UL) /*!< GPIO CFGD: GPIO29INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGD_GPIO28INTD_Pos (19UL) /*!< GPIO CFGD: GPIO28INTD (Bit 19) */ -#define GPIO_CFGD_GPIO28INTD_Msk (0x80000UL) /*!< GPIO CFGD: GPIO28INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGD_GPIO28OUTCFG_Pos (17UL) /*!< GPIO CFGD: GPIO28OUTCFG (Bit 17) */ -#define GPIO_CFGD_GPIO28OUTCFG_Msk (0x60000UL) /*!< GPIO CFGD: GPIO28OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGD_GPIO28INCFG_Pos (16UL) /*!< GPIO CFGD: GPIO28INCFG (Bit 16) */ -#define GPIO_CFGD_GPIO28INCFG_Msk (0x10000UL) /*!< GPIO CFGD: GPIO28INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGD_GPIO27INTD_Pos (15UL) /*!< GPIO CFGD: GPIO27INTD (Bit 15) */ -#define GPIO_CFGD_GPIO27INTD_Msk (0x8000UL) /*!< GPIO CFGD: GPIO27INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGD_GPIO27OUTCFG_Pos (13UL) /*!< GPIO CFGD: GPIO27OUTCFG (Bit 13) */ -#define GPIO_CFGD_GPIO27OUTCFG_Msk (0x6000UL) /*!< GPIO CFGD: GPIO27OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGD_GPIO27INCFG_Pos (12UL) /*!< GPIO CFGD: GPIO27INCFG (Bit 12) */ -#define GPIO_CFGD_GPIO27INCFG_Msk (0x1000UL) /*!< GPIO CFGD: GPIO27INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGD_GPIO26INTD_Pos (11UL) /*!< GPIO CFGD: GPIO26INTD (Bit 11) */ -#define GPIO_CFGD_GPIO26INTD_Msk (0x800UL) /*!< GPIO CFGD: GPIO26INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGD_GPIO26OUTCFG_Pos (9UL) /*!< GPIO CFGD: GPIO26OUTCFG (Bit 9) */ -#define GPIO_CFGD_GPIO26OUTCFG_Msk (0x600UL) /*!< GPIO CFGD: GPIO26OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGD_GPIO26INCFG_Pos (8UL) /*!< GPIO CFGD: GPIO26INCFG (Bit 8) */ -#define GPIO_CFGD_GPIO26INCFG_Msk (0x100UL) /*!< GPIO CFGD: GPIO26INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGD_GPIO25INTD_Pos (7UL) /*!< GPIO CFGD: GPIO25INTD (Bit 7) */ -#define GPIO_CFGD_GPIO25INTD_Msk (0x80UL) /*!< GPIO CFGD: GPIO25INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGD_GPIO25OUTCFG_Pos (5UL) /*!< GPIO CFGD: GPIO25OUTCFG (Bit 5) */ -#define GPIO_CFGD_GPIO25OUTCFG_Msk (0x60UL) /*!< GPIO CFGD: GPIO25OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGD_GPIO25INCFG_Pos (4UL) /*!< GPIO CFGD: GPIO25INCFG (Bit 4) */ -#define GPIO_CFGD_GPIO25INCFG_Msk (0x10UL) /*!< GPIO CFGD: GPIO25INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGD_GPIO24INTD_Pos (3UL) /*!< GPIO CFGD: GPIO24INTD (Bit 3) */ -#define GPIO_CFGD_GPIO24INTD_Msk (0x8UL) /*!< GPIO CFGD: GPIO24INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGD_GPIO24OUTCFG_Pos (1UL) /*!< GPIO CFGD: GPIO24OUTCFG (Bit 1) */ -#define GPIO_CFGD_GPIO24OUTCFG_Msk (0x6UL) /*!< GPIO CFGD: GPIO24OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGD_GPIO24INCFG_Pos (0UL) /*!< GPIO CFGD: GPIO24INCFG (Bit 0) */ -#define GPIO_CFGD_GPIO24INCFG_Msk (0x1UL) /*!< GPIO CFGD: GPIO24INCFG (Bitfield-Mask: 0x01) */ -/* ========================================================= CFGE ========================================================== */ -#define GPIO_CFGE_GPIO39INTD_Pos (31UL) /*!< GPIO CFGE: GPIO39INTD (Bit 31) */ -#define GPIO_CFGE_GPIO39INTD_Msk (0x80000000UL) /*!< GPIO CFGE: GPIO39INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGE_GPIO39OUTCFG_Pos (29UL) /*!< GPIO CFGE: GPIO39OUTCFG (Bit 29) */ -#define GPIO_CFGE_GPIO39OUTCFG_Msk (0x60000000UL) /*!< GPIO CFGE: GPIO39OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGE_GPIO39INCFG_Pos (28UL) /*!< GPIO CFGE: GPIO39INCFG (Bit 28) */ -#define GPIO_CFGE_GPIO39INCFG_Msk (0x10000000UL) /*!< GPIO CFGE: GPIO39INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGE_GPIO38INTD_Pos (27UL) /*!< GPIO CFGE: GPIO38INTD (Bit 27) */ -#define GPIO_CFGE_GPIO38INTD_Msk (0x8000000UL) /*!< GPIO CFGE: GPIO38INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGE_GPIO38OUTCFG_Pos (25UL) /*!< GPIO CFGE: GPIO38OUTCFG (Bit 25) */ -#define GPIO_CFGE_GPIO38OUTCFG_Msk (0x6000000UL) /*!< GPIO CFGE: GPIO38OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGE_GPIO38INCFG_Pos (24UL) /*!< GPIO CFGE: GPIO38INCFG (Bit 24) */ -#define GPIO_CFGE_GPIO38INCFG_Msk (0x1000000UL) /*!< GPIO CFGE: GPIO38INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGE_GPIO37INTD_Pos (23UL) /*!< GPIO CFGE: GPIO37INTD (Bit 23) */ -#define GPIO_CFGE_GPIO37INTD_Msk (0x800000UL) /*!< GPIO CFGE: GPIO37INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGE_GPIO37OUTCFG_Pos (21UL) /*!< GPIO CFGE: GPIO37OUTCFG (Bit 21) */ -#define GPIO_CFGE_GPIO37OUTCFG_Msk (0x600000UL) /*!< GPIO CFGE: GPIO37OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGE_GPIO37INCFG_Pos (20UL) /*!< GPIO CFGE: GPIO37INCFG (Bit 20) */ -#define GPIO_CFGE_GPIO37INCFG_Msk (0x100000UL) /*!< GPIO CFGE: GPIO37INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGE_GPIO36INTD_Pos (19UL) /*!< GPIO CFGE: GPIO36INTD (Bit 19) */ -#define GPIO_CFGE_GPIO36INTD_Msk (0x80000UL) /*!< GPIO CFGE: GPIO36INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGE_GPIO36OUTCFG_Pos (17UL) /*!< GPIO CFGE: GPIO36OUTCFG (Bit 17) */ -#define GPIO_CFGE_GPIO36OUTCFG_Msk (0x60000UL) /*!< GPIO CFGE: GPIO36OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGE_GPIO36INCFG_Pos (16UL) /*!< GPIO CFGE: GPIO36INCFG (Bit 16) */ -#define GPIO_CFGE_GPIO36INCFG_Msk (0x10000UL) /*!< GPIO CFGE: GPIO36INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGE_GPIO35INTD_Pos (15UL) /*!< GPIO CFGE: GPIO35INTD (Bit 15) */ -#define GPIO_CFGE_GPIO35INTD_Msk (0x8000UL) /*!< GPIO CFGE: GPIO35INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGE_GPIO35OUTCFG_Pos (13UL) /*!< GPIO CFGE: GPIO35OUTCFG (Bit 13) */ -#define GPIO_CFGE_GPIO35OUTCFG_Msk (0x6000UL) /*!< GPIO CFGE: GPIO35OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGE_GPIO35INCFG_Pos (12UL) /*!< GPIO CFGE: GPIO35INCFG (Bit 12) */ -#define GPIO_CFGE_GPIO35INCFG_Msk (0x1000UL) /*!< GPIO CFGE: GPIO35INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGE_GPIO34INTD_Pos (11UL) /*!< GPIO CFGE: GPIO34INTD (Bit 11) */ -#define GPIO_CFGE_GPIO34INTD_Msk (0x800UL) /*!< GPIO CFGE: GPIO34INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGE_GPIO34OUTCFG_Pos (9UL) /*!< GPIO CFGE: GPIO34OUTCFG (Bit 9) */ -#define GPIO_CFGE_GPIO34OUTCFG_Msk (0x600UL) /*!< GPIO CFGE: GPIO34OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGE_GPIO34INCFG_Pos (8UL) /*!< GPIO CFGE: GPIO34INCFG (Bit 8) */ -#define GPIO_CFGE_GPIO34INCFG_Msk (0x100UL) /*!< GPIO CFGE: GPIO34INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGE_GPIO33INTD_Pos (7UL) /*!< GPIO CFGE: GPIO33INTD (Bit 7) */ -#define GPIO_CFGE_GPIO33INTD_Msk (0x80UL) /*!< GPIO CFGE: GPIO33INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGE_GPIO33OUTCFG_Pos (5UL) /*!< GPIO CFGE: GPIO33OUTCFG (Bit 5) */ -#define GPIO_CFGE_GPIO33OUTCFG_Msk (0x60UL) /*!< GPIO CFGE: GPIO33OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGE_GPIO33INCFG_Pos (4UL) /*!< GPIO CFGE: GPIO33INCFG (Bit 4) */ -#define GPIO_CFGE_GPIO33INCFG_Msk (0x10UL) /*!< GPIO CFGE: GPIO33INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGE_GPIO32INTD_Pos (3UL) /*!< GPIO CFGE: GPIO32INTD (Bit 3) */ -#define GPIO_CFGE_GPIO32INTD_Msk (0x8UL) /*!< GPIO CFGE: GPIO32INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGE_GPIO32OUTCFG_Pos (1UL) /*!< GPIO CFGE: GPIO32OUTCFG (Bit 1) */ -#define GPIO_CFGE_GPIO32OUTCFG_Msk (0x6UL) /*!< GPIO CFGE: GPIO32OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGE_GPIO32INCFG_Pos (0UL) /*!< GPIO CFGE: GPIO32INCFG (Bit 0) */ -#define GPIO_CFGE_GPIO32INCFG_Msk (0x1UL) /*!< GPIO CFGE: GPIO32INCFG (Bitfield-Mask: 0x01) */ -/* ========================================================= CFGF ========================================================== */ -#define GPIO_CFGF_GPIO47INTD_Pos (31UL) /*!< GPIO CFGF: GPIO47INTD (Bit 31) */ -#define GPIO_CFGF_GPIO47INTD_Msk (0x80000000UL) /*!< GPIO CFGF: GPIO47INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGF_GPIO47OUTCFG_Pos (29UL) /*!< GPIO CFGF: GPIO47OUTCFG (Bit 29) */ -#define GPIO_CFGF_GPIO47OUTCFG_Msk (0x60000000UL) /*!< GPIO CFGF: GPIO47OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGF_GPIO47INCFG_Pos (28UL) /*!< GPIO CFGF: GPIO47INCFG (Bit 28) */ -#define GPIO_CFGF_GPIO47INCFG_Msk (0x10000000UL) /*!< GPIO CFGF: GPIO47INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGF_GPIO46INTD_Pos (27UL) /*!< GPIO CFGF: GPIO46INTD (Bit 27) */ -#define GPIO_CFGF_GPIO46INTD_Msk (0x8000000UL) /*!< GPIO CFGF: GPIO46INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGF_GPIO46OUTCFG_Pos (25UL) /*!< GPIO CFGF: GPIO46OUTCFG (Bit 25) */ -#define GPIO_CFGF_GPIO46OUTCFG_Msk (0x6000000UL) /*!< GPIO CFGF: GPIO46OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGF_GPIO46INCFG_Pos (24UL) /*!< GPIO CFGF: GPIO46INCFG (Bit 24) */ -#define GPIO_CFGF_GPIO46INCFG_Msk (0x1000000UL) /*!< GPIO CFGF: GPIO46INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGF_GPIO45INTD_Pos (23UL) /*!< GPIO CFGF: GPIO45INTD (Bit 23) */ -#define GPIO_CFGF_GPIO45INTD_Msk (0x800000UL) /*!< GPIO CFGF: GPIO45INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGF_GPIO45OUTCFG_Pos (21UL) /*!< GPIO CFGF: GPIO45OUTCFG (Bit 21) */ -#define GPIO_CFGF_GPIO45OUTCFG_Msk (0x600000UL) /*!< GPIO CFGF: GPIO45OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGF_GPIO45INCFG_Pos (20UL) /*!< GPIO CFGF: GPIO45INCFG (Bit 20) */ -#define GPIO_CFGF_GPIO45INCFG_Msk (0x100000UL) /*!< GPIO CFGF: GPIO45INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGF_GPIO44INTD_Pos (19UL) /*!< GPIO CFGF: GPIO44INTD (Bit 19) */ -#define GPIO_CFGF_GPIO44INTD_Msk (0x80000UL) /*!< GPIO CFGF: GPIO44INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGF_GPIO44OUTCFG_Pos (17UL) /*!< GPIO CFGF: GPIO44OUTCFG (Bit 17) */ -#define GPIO_CFGF_GPIO44OUTCFG_Msk (0x60000UL) /*!< GPIO CFGF: GPIO44OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGF_GPIO44INCFG_Pos (16UL) /*!< GPIO CFGF: GPIO44INCFG (Bit 16) */ -#define GPIO_CFGF_GPIO44INCFG_Msk (0x10000UL) /*!< GPIO CFGF: GPIO44INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGF_GPIO43INTD_Pos (15UL) /*!< GPIO CFGF: GPIO43INTD (Bit 15) */ -#define GPIO_CFGF_GPIO43INTD_Msk (0x8000UL) /*!< GPIO CFGF: GPIO43INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGF_GPIO43OUTCFG_Pos (13UL) /*!< GPIO CFGF: GPIO43OUTCFG (Bit 13) */ -#define GPIO_CFGF_GPIO43OUTCFG_Msk (0x6000UL) /*!< GPIO CFGF: GPIO43OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGF_GPIO43INCFG_Pos (12UL) /*!< GPIO CFGF: GPIO43INCFG (Bit 12) */ -#define GPIO_CFGF_GPIO43INCFG_Msk (0x1000UL) /*!< GPIO CFGF: GPIO43INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGF_GPIO42INTD_Pos (11UL) /*!< GPIO CFGF: GPIO42INTD (Bit 11) */ -#define GPIO_CFGF_GPIO42INTD_Msk (0x800UL) /*!< GPIO CFGF: GPIO42INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGF_GPIO42OUTCFG_Pos (9UL) /*!< GPIO CFGF: GPIO42OUTCFG (Bit 9) */ -#define GPIO_CFGF_GPIO42OUTCFG_Msk (0x600UL) /*!< GPIO CFGF: GPIO42OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGF_GPIO42INCFG_Pos (8UL) /*!< GPIO CFGF: GPIO42INCFG (Bit 8) */ -#define GPIO_CFGF_GPIO42INCFG_Msk (0x100UL) /*!< GPIO CFGF: GPIO42INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGF_GPIO41INTD_Pos (7UL) /*!< GPIO CFGF: GPIO41INTD (Bit 7) */ -#define GPIO_CFGF_GPIO41INTD_Msk (0x80UL) /*!< GPIO CFGF: GPIO41INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGF_GPIO41OUTCFG_Pos (5UL) /*!< GPIO CFGF: GPIO41OUTCFG (Bit 5) */ -#define GPIO_CFGF_GPIO41OUTCFG_Msk (0x60UL) /*!< GPIO CFGF: GPIO41OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGF_GPIO41INCFG_Pos (4UL) /*!< GPIO CFGF: GPIO41INCFG (Bit 4) */ -#define GPIO_CFGF_GPIO41INCFG_Msk (0x10UL) /*!< GPIO CFGF: GPIO41INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGF_GPIO40INTD_Pos (3UL) /*!< GPIO CFGF: GPIO40INTD (Bit 3) */ -#define GPIO_CFGF_GPIO40INTD_Msk (0x8UL) /*!< GPIO CFGF: GPIO40INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGF_GPIO40OUTCFG_Pos (1UL) /*!< GPIO CFGF: GPIO40OUTCFG (Bit 1) */ -#define GPIO_CFGF_GPIO40OUTCFG_Msk (0x6UL) /*!< GPIO CFGF: GPIO40OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGF_GPIO40INCFG_Pos (0UL) /*!< GPIO CFGF: GPIO40INCFG (Bit 0) */ -#define GPIO_CFGF_GPIO40INCFG_Msk (0x1UL) /*!< GPIO CFGF: GPIO40INCFG (Bitfield-Mask: 0x01) */ -/* ========================================================= CFGG ========================================================== */ -#define GPIO_CFGG_GPIO55INTD_Pos (31UL) /*!< GPIO CFGG: GPIO55INTD (Bit 31) */ -#define GPIO_CFGG_GPIO55INTD_Msk (0x80000000UL) /*!< GPIO CFGG: GPIO55INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGG_GPIO55OUTCFG_Pos (29UL) /*!< GPIO CFGG: GPIO55OUTCFG (Bit 29) */ -#define GPIO_CFGG_GPIO55OUTCFG_Msk (0x60000000UL) /*!< GPIO CFGG: GPIO55OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGG_GPIO55INCFG_Pos (28UL) /*!< GPIO CFGG: GPIO55INCFG (Bit 28) */ -#define GPIO_CFGG_GPIO55INCFG_Msk (0x10000000UL) /*!< GPIO CFGG: GPIO55INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGG_GPIO54INTD_Pos (27UL) /*!< GPIO CFGG: GPIO54INTD (Bit 27) */ -#define GPIO_CFGG_GPIO54INTD_Msk (0x8000000UL) /*!< GPIO CFGG: GPIO54INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGG_GPIO54OUTCFG_Pos (25UL) /*!< GPIO CFGG: GPIO54OUTCFG (Bit 25) */ -#define GPIO_CFGG_GPIO54OUTCFG_Msk (0x6000000UL) /*!< GPIO CFGG: GPIO54OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGG_GPIO54INCFG_Pos (24UL) /*!< GPIO CFGG: GPIO54INCFG (Bit 24) */ -#define GPIO_CFGG_GPIO54INCFG_Msk (0x1000000UL) /*!< GPIO CFGG: GPIO54INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGG_GPIO53INTD_Pos (23UL) /*!< GPIO CFGG: GPIO53INTD (Bit 23) */ -#define GPIO_CFGG_GPIO53INTD_Msk (0x800000UL) /*!< GPIO CFGG: GPIO53INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGG_GPIO53OUTCFG_Pos (21UL) /*!< GPIO CFGG: GPIO53OUTCFG (Bit 21) */ -#define GPIO_CFGG_GPIO53OUTCFG_Msk (0x600000UL) /*!< GPIO CFGG: GPIO53OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGG_GPIO53INCFG_Pos (20UL) /*!< GPIO CFGG: GPIO53INCFG (Bit 20) */ -#define GPIO_CFGG_GPIO53INCFG_Msk (0x100000UL) /*!< GPIO CFGG: GPIO53INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGG_GPIO52INTD_Pos (19UL) /*!< GPIO CFGG: GPIO52INTD (Bit 19) */ -#define GPIO_CFGG_GPIO52INTD_Msk (0x80000UL) /*!< GPIO CFGG: GPIO52INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGG_GPIO52OUTCFG_Pos (17UL) /*!< GPIO CFGG: GPIO52OUTCFG (Bit 17) */ -#define GPIO_CFGG_GPIO52OUTCFG_Msk (0x60000UL) /*!< GPIO CFGG: GPIO52OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGG_GPIO52INCFG_Pos (16UL) /*!< GPIO CFGG: GPIO52INCFG (Bit 16) */ -#define GPIO_CFGG_GPIO52INCFG_Msk (0x10000UL) /*!< GPIO CFGG: GPIO52INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGG_GPIO51INTD_Pos (15UL) /*!< GPIO CFGG: GPIO51INTD (Bit 15) */ -#define GPIO_CFGG_GPIO51INTD_Msk (0x8000UL) /*!< GPIO CFGG: GPIO51INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGG_GPIO51OUTCFG_Pos (13UL) /*!< GPIO CFGG: GPIO51OUTCFG (Bit 13) */ -#define GPIO_CFGG_GPIO51OUTCFG_Msk (0x6000UL) /*!< GPIO CFGG: GPIO51OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGG_GPIO51INCFG_Pos (12UL) /*!< GPIO CFGG: GPIO51INCFG (Bit 12) */ -#define GPIO_CFGG_GPIO51INCFG_Msk (0x1000UL) /*!< GPIO CFGG: GPIO51INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGG_GPIO50INTD_Pos (11UL) /*!< GPIO CFGG: GPIO50INTD (Bit 11) */ -#define GPIO_CFGG_GPIO50INTD_Msk (0x800UL) /*!< GPIO CFGG: GPIO50INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGG_GPIO50OUTCFG_Pos (9UL) /*!< GPIO CFGG: GPIO50OUTCFG (Bit 9) */ -#define GPIO_CFGG_GPIO50OUTCFG_Msk (0x600UL) /*!< GPIO CFGG: GPIO50OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGG_GPIO50INCFG_Pos (8UL) /*!< GPIO CFGG: GPIO50INCFG (Bit 8) */ -#define GPIO_CFGG_GPIO50INCFG_Msk (0x100UL) /*!< GPIO CFGG: GPIO50INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGG_GPIO49INTD_Pos (7UL) /*!< GPIO CFGG: GPIO49INTD (Bit 7) */ -#define GPIO_CFGG_GPIO49INTD_Msk (0x80UL) /*!< GPIO CFGG: GPIO49INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGG_GPIO49OUTCFG_Pos (5UL) /*!< GPIO CFGG: GPIO49OUTCFG (Bit 5) */ -#define GPIO_CFGG_GPIO49OUTCFG_Msk (0x60UL) /*!< GPIO CFGG: GPIO49OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGG_GPIO49INCFG_Pos (4UL) /*!< GPIO CFGG: GPIO49INCFG (Bit 4) */ -#define GPIO_CFGG_GPIO49INCFG_Msk (0x10UL) /*!< GPIO CFGG: GPIO49INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGG_GPIO48INTD_Pos (3UL) /*!< GPIO CFGG: GPIO48INTD (Bit 3) */ -#define GPIO_CFGG_GPIO48INTD_Msk (0x8UL) /*!< GPIO CFGG: GPIO48INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGG_GPIO48OUTCFG_Pos (1UL) /*!< GPIO CFGG: GPIO48OUTCFG (Bit 1) */ -#define GPIO_CFGG_GPIO48OUTCFG_Msk (0x6UL) /*!< GPIO CFGG: GPIO48OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGG_GPIO48INCFG_Pos (0UL) /*!< GPIO CFGG: GPIO48INCFG (Bit 0) */ -#define GPIO_CFGG_GPIO48INCFG_Msk (0x1UL) /*!< GPIO CFGG: GPIO48INCFG (Bitfield-Mask: 0x01) */ -/* ========================================================= CFGH ========================================================== */ -#define GPIO_CFGH_GPIO63INTD_Pos (31UL) /*!< GPIO CFGH: GPIO63INTD (Bit 31) */ -#define GPIO_CFGH_GPIO63INTD_Msk (0x80000000UL) /*!< GPIO CFGH: GPIO63INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGH_GPIO63OUTCFG_Pos (29UL) /*!< GPIO CFGH: GPIO63OUTCFG (Bit 29) */ -#define GPIO_CFGH_GPIO63OUTCFG_Msk (0x60000000UL) /*!< GPIO CFGH: GPIO63OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGH_GPIO63INCFG_Pos (28UL) /*!< GPIO CFGH: GPIO63INCFG (Bit 28) */ -#define GPIO_CFGH_GPIO63INCFG_Msk (0x10000000UL) /*!< GPIO CFGH: GPIO63INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGH_GPIO62INTD_Pos (27UL) /*!< GPIO CFGH: GPIO62INTD (Bit 27) */ -#define GPIO_CFGH_GPIO62INTD_Msk (0x8000000UL) /*!< GPIO CFGH: GPIO62INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGH_GPIO62OUTCFG_Pos (25UL) /*!< GPIO CFGH: GPIO62OUTCFG (Bit 25) */ -#define GPIO_CFGH_GPIO62OUTCFG_Msk (0x6000000UL) /*!< GPIO CFGH: GPIO62OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGH_GPIO62INCFG_Pos (24UL) /*!< GPIO CFGH: GPIO62INCFG (Bit 24) */ -#define GPIO_CFGH_GPIO62INCFG_Msk (0x1000000UL) /*!< GPIO CFGH: GPIO62INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGH_GPIO61INTD_Pos (23UL) /*!< GPIO CFGH: GPIO61INTD (Bit 23) */ -#define GPIO_CFGH_GPIO61INTD_Msk (0x800000UL) /*!< GPIO CFGH: GPIO61INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGH_GPIO61OUTCFG_Pos (21UL) /*!< GPIO CFGH: GPIO61OUTCFG (Bit 21) */ -#define GPIO_CFGH_GPIO61OUTCFG_Msk (0x600000UL) /*!< GPIO CFGH: GPIO61OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGH_GPIO61INCFG_Pos (20UL) /*!< GPIO CFGH: GPIO61INCFG (Bit 20) */ -#define GPIO_CFGH_GPIO61INCFG_Msk (0x100000UL) /*!< GPIO CFGH: GPIO61INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGH_GPIO60INTD_Pos (19UL) /*!< GPIO CFGH: GPIO60INTD (Bit 19) */ -#define GPIO_CFGH_GPIO60INTD_Msk (0x80000UL) /*!< GPIO CFGH: GPIO60INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGH_GPIO60OUTCFG_Pos (17UL) /*!< GPIO CFGH: GPIO60OUTCFG (Bit 17) */ -#define GPIO_CFGH_GPIO60OUTCFG_Msk (0x60000UL) /*!< GPIO CFGH: GPIO60OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGH_GPIO60INCFG_Pos (16UL) /*!< GPIO CFGH: GPIO60INCFG (Bit 16) */ -#define GPIO_CFGH_GPIO60INCFG_Msk (0x10000UL) /*!< GPIO CFGH: GPIO60INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGH_GPIO59INTD_Pos (15UL) /*!< GPIO CFGH: GPIO59INTD (Bit 15) */ -#define GPIO_CFGH_GPIO59INTD_Msk (0x8000UL) /*!< GPIO CFGH: GPIO59INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGH_GPIO59OUTCFG_Pos (13UL) /*!< GPIO CFGH: GPIO59OUTCFG (Bit 13) */ -#define GPIO_CFGH_GPIO59OUTCFG_Msk (0x6000UL) /*!< GPIO CFGH: GPIO59OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGH_GPIO59INCFG_Pos (12UL) /*!< GPIO CFGH: GPIO59INCFG (Bit 12) */ -#define GPIO_CFGH_GPIO59INCFG_Msk (0x1000UL) /*!< GPIO CFGH: GPIO59INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGH_GPIO58INTD_Pos (11UL) /*!< GPIO CFGH: GPIO58INTD (Bit 11) */ -#define GPIO_CFGH_GPIO58INTD_Msk (0x800UL) /*!< GPIO CFGH: GPIO58INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGH_GPIO58OUTCFG_Pos (9UL) /*!< GPIO CFGH: GPIO58OUTCFG (Bit 9) */ -#define GPIO_CFGH_GPIO58OUTCFG_Msk (0x600UL) /*!< GPIO CFGH: GPIO58OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGH_GPIO58INCFG_Pos (8UL) /*!< GPIO CFGH: GPIO58INCFG (Bit 8) */ -#define GPIO_CFGH_GPIO58INCFG_Msk (0x100UL) /*!< GPIO CFGH: GPIO58INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGH_GPIO57INTD_Pos (7UL) /*!< GPIO CFGH: GPIO57INTD (Bit 7) */ -#define GPIO_CFGH_GPIO57INTD_Msk (0x80UL) /*!< GPIO CFGH: GPIO57INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGH_GPIO57OUTCFG_Pos (5UL) /*!< GPIO CFGH: GPIO57OUTCFG (Bit 5) */ -#define GPIO_CFGH_GPIO57OUTCFG_Msk (0x60UL) /*!< GPIO CFGH: GPIO57OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGH_GPIO57INCFG_Pos (4UL) /*!< GPIO CFGH: GPIO57INCFG (Bit 4) */ -#define GPIO_CFGH_GPIO57INCFG_Msk (0x10UL) /*!< GPIO CFGH: GPIO57INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGH_GPIO56INTD_Pos (3UL) /*!< GPIO CFGH: GPIO56INTD (Bit 3) */ -#define GPIO_CFGH_GPIO56INTD_Msk (0x8UL) /*!< GPIO CFGH: GPIO56INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGH_GPIO56OUTCFG_Pos (1UL) /*!< GPIO CFGH: GPIO56OUTCFG (Bit 1) */ -#define GPIO_CFGH_GPIO56OUTCFG_Msk (0x6UL) /*!< GPIO CFGH: GPIO56OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGH_GPIO56INCFG_Pos (0UL) /*!< GPIO CFGH: GPIO56INCFG (Bit 0) */ -#define GPIO_CFGH_GPIO56INCFG_Msk (0x1UL) /*!< GPIO CFGH: GPIO56INCFG (Bitfield-Mask: 0x01) */ -/* ========================================================= CFGI ========================================================== */ -#define GPIO_CFGI_GPIO71INTD_Pos (31UL) /*!< GPIO CFGI: GPIO71INTD (Bit 31) */ -#define GPIO_CFGI_GPIO71INTD_Msk (0x80000000UL) /*!< GPIO CFGI: GPIO71INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGI_GPIO71OUTCFG_Pos (29UL) /*!< GPIO CFGI: GPIO71OUTCFG (Bit 29) */ -#define GPIO_CFGI_GPIO71OUTCFG_Msk (0x60000000UL) /*!< GPIO CFGI: GPIO71OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGI_GPIO71INCFG_Pos (28UL) /*!< GPIO CFGI: GPIO71INCFG (Bit 28) */ -#define GPIO_CFGI_GPIO71INCFG_Msk (0x10000000UL) /*!< GPIO CFGI: GPIO71INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGI_GPIO70INTD_Pos (27UL) /*!< GPIO CFGI: GPIO70INTD (Bit 27) */ -#define GPIO_CFGI_GPIO70INTD_Msk (0x8000000UL) /*!< GPIO CFGI: GPIO70INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGI_GPIO70OUTCFG_Pos (25UL) /*!< GPIO CFGI: GPIO70OUTCFG (Bit 25) */ -#define GPIO_CFGI_GPIO70OUTCFG_Msk (0x6000000UL) /*!< GPIO CFGI: GPIO70OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGI_GPIO70INCFG_Pos (24UL) /*!< GPIO CFGI: GPIO70INCFG (Bit 24) */ -#define GPIO_CFGI_GPIO70INCFG_Msk (0x1000000UL) /*!< GPIO CFGI: GPIO70INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGI_GPIO69INTD_Pos (23UL) /*!< GPIO CFGI: GPIO69INTD (Bit 23) */ -#define GPIO_CFGI_GPIO69INTD_Msk (0x800000UL) /*!< GPIO CFGI: GPIO69INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGI_GPIO69OUTCFG_Pos (21UL) /*!< GPIO CFGI: GPIO69OUTCFG (Bit 21) */ -#define GPIO_CFGI_GPIO69OUTCFG_Msk (0x600000UL) /*!< GPIO CFGI: GPIO69OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGI_GPIO69INCFG_Pos (20UL) /*!< GPIO CFGI: GPIO69INCFG (Bit 20) */ -#define GPIO_CFGI_GPIO69INCFG_Msk (0x100000UL) /*!< GPIO CFGI: GPIO69INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGI_GPIO68INTD_Pos (19UL) /*!< GPIO CFGI: GPIO68INTD (Bit 19) */ -#define GPIO_CFGI_GPIO68INTD_Msk (0x80000UL) /*!< GPIO CFGI: GPIO68INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGI_GPIO68OUTCFG_Pos (17UL) /*!< GPIO CFGI: GPIO68OUTCFG (Bit 17) */ -#define GPIO_CFGI_GPIO68OUTCFG_Msk (0x60000UL) /*!< GPIO CFGI: GPIO68OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGI_GPIO68INCFG_Pos (16UL) /*!< GPIO CFGI: GPIO68INCFG (Bit 16) */ -#define GPIO_CFGI_GPIO68INCFG_Msk (0x10000UL) /*!< GPIO CFGI: GPIO68INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGI_GPIO67INTD_Pos (15UL) /*!< GPIO CFGI: GPIO67INTD (Bit 15) */ -#define GPIO_CFGI_GPIO67INTD_Msk (0x8000UL) /*!< GPIO CFGI: GPIO67INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGI_GPIO67OUTCFG_Pos (13UL) /*!< GPIO CFGI: GPIO67OUTCFG (Bit 13) */ -#define GPIO_CFGI_GPIO67OUTCFG_Msk (0x6000UL) /*!< GPIO CFGI: GPIO67OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGI_GPIO67INCFG_Pos (12UL) /*!< GPIO CFGI: GPIO67INCFG (Bit 12) */ -#define GPIO_CFGI_GPIO67INCFG_Msk (0x1000UL) /*!< GPIO CFGI: GPIO67INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGI_GPIO66INTD_Pos (11UL) /*!< GPIO CFGI: GPIO66INTD (Bit 11) */ -#define GPIO_CFGI_GPIO66INTD_Msk (0x800UL) /*!< GPIO CFGI: GPIO66INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGI_GPIO66OUTCFG_Pos (9UL) /*!< GPIO CFGI: GPIO66OUTCFG (Bit 9) */ -#define GPIO_CFGI_GPIO66OUTCFG_Msk (0x600UL) /*!< GPIO CFGI: GPIO66OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGI_GPIO66INCFG_Pos (8UL) /*!< GPIO CFGI: GPIO66INCFG (Bit 8) */ -#define GPIO_CFGI_GPIO66INCFG_Msk (0x100UL) /*!< GPIO CFGI: GPIO66INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGI_GPIO65INTD_Pos (7UL) /*!< GPIO CFGI: GPIO65INTD (Bit 7) */ -#define GPIO_CFGI_GPIO65INTD_Msk (0x80UL) /*!< GPIO CFGI: GPIO65INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGI_GPIO65OUTCFG_Pos (5UL) /*!< GPIO CFGI: GPIO65OUTCFG (Bit 5) */ -#define GPIO_CFGI_GPIO65OUTCFG_Msk (0x60UL) /*!< GPIO CFGI: GPIO65OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGI_GPIO65INCFG_Pos (4UL) /*!< GPIO CFGI: GPIO65INCFG (Bit 4) */ -#define GPIO_CFGI_GPIO65INCFG_Msk (0x10UL) /*!< GPIO CFGI: GPIO65INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGI_GPIO64INTD_Pos (3UL) /*!< GPIO CFGI: GPIO64INTD (Bit 3) */ -#define GPIO_CFGI_GPIO64INTD_Msk (0x8UL) /*!< GPIO CFGI: GPIO64INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGI_GPIO64OUTCFG_Pos (1UL) /*!< GPIO CFGI: GPIO64OUTCFG (Bit 1) */ -#define GPIO_CFGI_GPIO64OUTCFG_Msk (0x6UL) /*!< GPIO CFGI: GPIO64OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGI_GPIO64INCFG_Pos (0UL) /*!< GPIO CFGI: GPIO64INCFG (Bit 0) */ -#define GPIO_CFGI_GPIO64INCFG_Msk (0x1UL) /*!< GPIO CFGI: GPIO64INCFG (Bitfield-Mask: 0x01) */ -/* ========================================================= CFGJ ========================================================== */ -#define GPIO_CFGJ_GPIO73INTD_Pos (7UL) /*!< GPIO CFGJ: GPIO73INTD (Bit 7) */ -#define GPIO_CFGJ_GPIO73INTD_Msk (0x80UL) /*!< GPIO CFGJ: GPIO73INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGJ_GPIO73OUTCFG_Pos (5UL) /*!< GPIO CFGJ: GPIO73OUTCFG (Bit 5) */ -#define GPIO_CFGJ_GPIO73OUTCFG_Msk (0x60UL) /*!< GPIO CFGJ: GPIO73OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGJ_GPIO73INCFG_Pos (4UL) /*!< GPIO CFGJ: GPIO73INCFG (Bit 4) */ -#define GPIO_CFGJ_GPIO73INCFG_Msk (0x10UL) /*!< GPIO CFGJ: GPIO73INCFG (Bitfield-Mask: 0x01) */ -#define GPIO_CFGJ_GPIO72INTD_Pos (3UL) /*!< GPIO CFGJ: GPIO72INTD (Bit 3) */ -#define GPIO_CFGJ_GPIO72INTD_Msk (0x8UL) /*!< GPIO CFGJ: GPIO72INTD (Bitfield-Mask: 0x01) */ -#define GPIO_CFGJ_GPIO72OUTCFG_Pos (1UL) /*!< GPIO CFGJ: GPIO72OUTCFG (Bit 1) */ -#define GPIO_CFGJ_GPIO72OUTCFG_Msk (0x6UL) /*!< GPIO CFGJ: GPIO72OUTCFG (Bitfield-Mask: 0x03) */ -#define GPIO_CFGJ_GPIO72INCFG_Pos (0UL) /*!< GPIO CFGJ: GPIO72INCFG (Bit 0) */ -#define GPIO_CFGJ_GPIO72INCFG_Msk (0x1UL) /*!< GPIO CFGJ: GPIO72INCFG (Bitfield-Mask: 0x01) */ -/* ======================================================== PADKEY ========================================================= */ -#define GPIO_PADKEY_PADKEY_Pos (0UL) /*!< GPIO PADKEY: PADKEY (Bit 0) */ -#define GPIO_PADKEY_PADKEY_Msk (0xffffffffUL) /*!< GPIO PADKEY: PADKEY (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== RDA ========================================================== */ -#define GPIO_RDA_RDA_Pos (0UL) /*!< GPIO RDA: RDA (Bit 0) */ -#define GPIO_RDA_RDA_Msk (0xffffffffUL) /*!< GPIO RDA: RDA (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== RDB ========================================================== */ -#define GPIO_RDB_RDB_Pos (0UL) /*!< GPIO RDB: RDB (Bit 0) */ -#define GPIO_RDB_RDB_Msk (0xffffffffUL) /*!< GPIO RDB: RDB (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== RDC ========================================================== */ -#define GPIO_RDC_RDC_Pos (0UL) /*!< GPIO RDC: RDC (Bit 0) */ -#define GPIO_RDC_RDC_Msk (0x3ffUL) /*!< GPIO RDC: RDC (Bitfield-Mask: 0x3ff) */ -/* ========================================================== WTA ========================================================== */ -#define GPIO_WTA_WTA_Pos (0UL) /*!< GPIO WTA: WTA (Bit 0) */ -#define GPIO_WTA_WTA_Msk (0xffffffffUL) /*!< GPIO WTA: WTA (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== WTB ========================================================== */ -#define GPIO_WTB_WTB_Pos (0UL) /*!< GPIO WTB: WTB (Bit 0) */ -#define GPIO_WTB_WTB_Msk (0xffffffffUL) /*!< GPIO WTB: WTB (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== WTC ========================================================== */ -#define GPIO_WTC_WTC_Pos (0UL) /*!< GPIO WTC: WTC (Bit 0) */ -#define GPIO_WTC_WTC_Msk (0x3ffUL) /*!< GPIO WTC: WTC (Bitfield-Mask: 0x3ff) */ -/* ========================================================= WTSA ========================================================== */ -#define GPIO_WTSA_WTSA_Pos (0UL) /*!< GPIO WTSA: WTSA (Bit 0) */ -#define GPIO_WTSA_WTSA_Msk (0xffffffffUL) /*!< GPIO WTSA: WTSA (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= WTSB ========================================================== */ -#define GPIO_WTSB_WTSB_Pos (0UL) /*!< GPIO WTSB: WTSB (Bit 0) */ -#define GPIO_WTSB_WTSB_Msk (0xffffffffUL) /*!< GPIO WTSB: WTSB (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= WTSC ========================================================== */ -#define GPIO_WTSC_WTSC_Pos (0UL) /*!< GPIO WTSC: WTSC (Bit 0) */ -#define GPIO_WTSC_WTSC_Msk (0x3ffUL) /*!< GPIO WTSC: WTSC (Bitfield-Mask: 0x3ff) */ -/* ========================================================= WTCA ========================================================== */ -#define GPIO_WTCA_WTCA_Pos (0UL) /*!< GPIO WTCA: WTCA (Bit 0) */ -#define GPIO_WTCA_WTCA_Msk (0xffffffffUL) /*!< GPIO WTCA: WTCA (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= WTCB ========================================================== */ -#define GPIO_WTCB_WTCB_Pos (0UL) /*!< GPIO WTCB: WTCB (Bit 0) */ -#define GPIO_WTCB_WTCB_Msk (0xffffffffUL) /*!< GPIO WTCB: WTCB (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= WTCC ========================================================== */ -#define GPIO_WTCC_WTCB_Pos (0UL) /*!< GPIO WTCC: WTCB (Bit 0) */ -#define GPIO_WTCC_WTCB_Msk (0x3ffUL) /*!< GPIO WTCC: WTCB (Bitfield-Mask: 0x3ff) */ -/* ========================================================== ENA ========================================================== */ -#define GPIO_ENA_ENA_Pos (0UL) /*!< GPIO ENA: ENA (Bit 0) */ -#define GPIO_ENA_ENA_Msk (0xffffffffUL) /*!< GPIO ENA: ENA (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== ENB ========================================================== */ -#define GPIO_ENB_ENB_Pos (0UL) /*!< GPIO ENB: ENB (Bit 0) */ -#define GPIO_ENB_ENB_Msk (0xffffffffUL) /*!< GPIO ENB: ENB (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== ENC ========================================================== */ -#define GPIO_ENC_ENC_Pos (0UL) /*!< GPIO ENC: ENC (Bit 0) */ -#define GPIO_ENC_ENC_Msk (0x3ffUL) /*!< GPIO ENC: ENC (Bitfield-Mask: 0x3ff) */ -/* ========================================================= ENSA ========================================================== */ -#define GPIO_ENSA_ENSA_Pos (0UL) /*!< GPIO ENSA: ENSA (Bit 0) */ -#define GPIO_ENSA_ENSA_Msk (0xffffffffUL) /*!< GPIO ENSA: ENSA (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ENSB ========================================================== */ -#define GPIO_ENSB_ENSB_Pos (0UL) /*!< GPIO ENSB: ENSB (Bit 0) */ -#define GPIO_ENSB_ENSB_Msk (0xffffffffUL) /*!< GPIO ENSB: ENSB (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ENSC ========================================================== */ -#define GPIO_ENSC_ENSC_Pos (0UL) /*!< GPIO ENSC: ENSC (Bit 0) */ -#define GPIO_ENSC_ENSC_Msk (0x3ffUL) /*!< GPIO ENSC: ENSC (Bitfield-Mask: 0x3ff) */ -/* ========================================================= ENCA ========================================================== */ -#define GPIO_ENCA_ENCA_Pos (0UL) /*!< GPIO ENCA: ENCA (Bit 0) */ -#define GPIO_ENCA_ENCA_Msk (0xffffffffUL) /*!< GPIO ENCA: ENCA (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ENCB ========================================================== */ -#define GPIO_ENCB_ENCB_Pos (0UL) /*!< GPIO ENCB: ENCB (Bit 0) */ -#define GPIO_ENCB_ENCB_Msk (0xffffffffUL) /*!< GPIO ENCB: ENCB (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= ENCC ========================================================== */ -#define GPIO_ENCC_ENCC_Pos (0UL) /*!< GPIO ENCC: ENCC (Bit 0) */ -#define GPIO_ENCC_ENCC_Msk (0x3ffUL) /*!< GPIO ENCC: ENCC (Bitfield-Mask: 0x3ff) */ -/* ======================================================== STMRCAP ======================================================== */ -#define GPIO_STMRCAP_STPOL3_Pos (31UL) /*!< GPIO STMRCAP: STPOL3 (Bit 31) */ -#define GPIO_STMRCAP_STPOL3_Msk (0x80000000UL) /*!< GPIO STMRCAP: STPOL3 (Bitfield-Mask: 0x01) */ -#define GPIO_STMRCAP_STSEL3_Pos (24UL) /*!< GPIO STMRCAP: STSEL3 (Bit 24) */ -#define GPIO_STMRCAP_STSEL3_Msk (0x7f000000UL) /*!< GPIO STMRCAP: STSEL3 (Bitfield-Mask: 0x7f) */ -#define GPIO_STMRCAP_STPOL2_Pos (23UL) /*!< GPIO STMRCAP: STPOL2 (Bit 23) */ -#define GPIO_STMRCAP_STPOL2_Msk (0x800000UL) /*!< GPIO STMRCAP: STPOL2 (Bitfield-Mask: 0x01) */ -#define GPIO_STMRCAP_STSEL2_Pos (16UL) /*!< GPIO STMRCAP: STSEL2 (Bit 16) */ -#define GPIO_STMRCAP_STSEL2_Msk (0x7f0000UL) /*!< GPIO STMRCAP: STSEL2 (Bitfield-Mask: 0x7f) */ -#define GPIO_STMRCAP_STPOL1_Pos (15UL) /*!< GPIO STMRCAP: STPOL1 (Bit 15) */ -#define GPIO_STMRCAP_STPOL1_Msk (0x8000UL) /*!< GPIO STMRCAP: STPOL1 (Bitfield-Mask: 0x01) */ -#define GPIO_STMRCAP_STSEL1_Pos (8UL) /*!< GPIO STMRCAP: STSEL1 (Bit 8) */ -#define GPIO_STMRCAP_STSEL1_Msk (0x7f00UL) /*!< GPIO STMRCAP: STSEL1 (Bitfield-Mask: 0x7f) */ -#define GPIO_STMRCAP_STPOL0_Pos (7UL) /*!< GPIO STMRCAP: STPOL0 (Bit 7) */ -#define GPIO_STMRCAP_STPOL0_Msk (0x80UL) /*!< GPIO STMRCAP: STPOL0 (Bitfield-Mask: 0x01) */ -#define GPIO_STMRCAP_STSEL0_Pos (0UL) /*!< GPIO STMRCAP: STSEL0 (Bit 0) */ -#define GPIO_STMRCAP_STSEL0_Msk (0x7fUL) /*!< GPIO STMRCAP: STSEL0 (Bitfield-Mask: 0x7f) */ -/* ======================================================== IOM0IRQ ======================================================== */ -#define GPIO_IOM0IRQ_IOM0IRQ_Pos (0UL) /*!< GPIO IOM0IRQ: IOM0IRQ (Bit 0) */ -#define GPIO_IOM0IRQ_IOM0IRQ_Msk (0x7fUL) /*!< GPIO IOM0IRQ: IOM0IRQ (Bitfield-Mask: 0x7f) */ -/* ======================================================== IOM1IRQ ======================================================== */ -#define GPIO_IOM1IRQ_IOM1IRQ_Pos (0UL) /*!< GPIO IOM1IRQ: IOM1IRQ (Bit 0) */ -#define GPIO_IOM1IRQ_IOM1IRQ_Msk (0x7fUL) /*!< GPIO IOM1IRQ: IOM1IRQ (Bitfield-Mask: 0x7f) */ -/* ======================================================== IOM2IRQ ======================================================== */ -#define GPIO_IOM2IRQ_IOM2IRQ_Pos (0UL) /*!< GPIO IOM2IRQ: IOM2IRQ (Bit 0) */ -#define GPIO_IOM2IRQ_IOM2IRQ_Msk (0x7fUL) /*!< GPIO IOM2IRQ: IOM2IRQ (Bitfield-Mask: 0x7f) */ -/* ======================================================== IOM3IRQ ======================================================== */ -#define GPIO_IOM3IRQ_IOM3IRQ_Pos (0UL) /*!< GPIO IOM3IRQ: IOM3IRQ (Bit 0) */ -#define GPIO_IOM3IRQ_IOM3IRQ_Msk (0x7fUL) /*!< GPIO IOM3IRQ: IOM3IRQ (Bitfield-Mask: 0x7f) */ -/* ======================================================== IOM4IRQ ======================================================== */ -#define GPIO_IOM4IRQ_IOM4IRQ_Pos (0UL) /*!< GPIO IOM4IRQ: IOM4IRQ (Bit 0) */ -#define GPIO_IOM4IRQ_IOM4IRQ_Msk (0x7fUL) /*!< GPIO IOM4IRQ: IOM4IRQ (Bitfield-Mask: 0x7f) */ -/* ======================================================== IOM5IRQ ======================================================== */ -#define GPIO_IOM5IRQ_IOM5IRQ_Pos (0UL) /*!< GPIO IOM5IRQ: IOM5IRQ (Bit 0) */ -#define GPIO_IOM5IRQ_IOM5IRQ_Msk (0x7fUL) /*!< GPIO IOM5IRQ: IOM5IRQ (Bitfield-Mask: 0x7f) */ -/* ======================================================= BLEIFIRQ ======================================================== */ -#define GPIO_BLEIFIRQ_BLEIFIRQ_Pos (0UL) /*!< GPIO BLEIFIRQ: BLEIFIRQ (Bit 0) */ -#define GPIO_BLEIFIRQ_BLEIFIRQ_Msk (0x7fUL) /*!< GPIO BLEIFIRQ: BLEIFIRQ (Bitfield-Mask: 0x7f) */ -/* ======================================================== GPIOOBS ======================================================== */ -#define GPIO_GPIOOBS_OBS_DATA_Pos (0UL) /*!< GPIO GPIOOBS: OBS_DATA (Bit 0) */ -#define GPIO_GPIOOBS_OBS_DATA_Msk (0xffffUL) /*!< GPIO GPIOOBS: OBS_DATA (Bitfield-Mask: 0xffff) */ -/* ====================================================== ALTPADCFGA ======================================================= */ -#define GPIO_ALTPADCFGA_PAD3_SR_Pos (28UL) /*!< GPIO ALTPADCFGA: PAD3_SR (Bit 28) */ -#define GPIO_ALTPADCFGA_PAD3_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGA: PAD3_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGA_PAD3_DS1_Pos (24UL) /*!< GPIO ALTPADCFGA: PAD3_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGA_PAD3_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGA: PAD3_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGA_PAD2_SR_Pos (20UL) /*!< GPIO ALTPADCFGA: PAD2_SR (Bit 20) */ -#define GPIO_ALTPADCFGA_PAD2_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGA: PAD2_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGA_PAD2_DS1_Pos (16UL) /*!< GPIO ALTPADCFGA: PAD2_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGA_PAD2_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGA: PAD2_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGA_PAD1_SR_Pos (12UL) /*!< GPIO ALTPADCFGA: PAD1_SR (Bit 12) */ -#define GPIO_ALTPADCFGA_PAD1_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGA: PAD1_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGA_PAD1_DS1_Pos (8UL) /*!< GPIO ALTPADCFGA: PAD1_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGA_PAD1_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGA: PAD1_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGA_PAD0_SR_Pos (4UL) /*!< GPIO ALTPADCFGA: PAD0_SR (Bit 4) */ -#define GPIO_ALTPADCFGA_PAD0_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGA: PAD0_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGA_PAD0_DS1_Pos (0UL) /*!< GPIO ALTPADCFGA: PAD0_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGA_PAD0_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGA: PAD0_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGB ======================================================= */ -#define GPIO_ALTPADCFGB_PAD7_SR_Pos (28UL) /*!< GPIO ALTPADCFGB: PAD7_SR (Bit 28) */ -#define GPIO_ALTPADCFGB_PAD7_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGB: PAD7_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGB_PAD7_DS1_Pos (24UL) /*!< GPIO ALTPADCFGB: PAD7_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGB_PAD7_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGB: PAD7_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGB_PAD6_SR_Pos (20UL) /*!< GPIO ALTPADCFGB: PAD6_SR (Bit 20) */ -#define GPIO_ALTPADCFGB_PAD6_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGB: PAD6_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGB_PAD6_DS1_Pos (16UL) /*!< GPIO ALTPADCFGB: PAD6_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGB_PAD6_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGB: PAD6_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGB_PAD5_SR_Pos (12UL) /*!< GPIO ALTPADCFGB: PAD5_SR (Bit 12) */ -#define GPIO_ALTPADCFGB_PAD5_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGB: PAD5_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGB_PAD5_DS1_Pos (8UL) /*!< GPIO ALTPADCFGB: PAD5_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGB_PAD5_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGB: PAD5_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGB_PAD4_SR_Pos (4UL) /*!< GPIO ALTPADCFGB: PAD4_SR (Bit 4) */ -#define GPIO_ALTPADCFGB_PAD4_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGB: PAD4_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGB_PAD4_DS1_Pos (0UL) /*!< GPIO ALTPADCFGB: PAD4_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGB_PAD4_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGB: PAD4_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGC ======================================================= */ -#define GPIO_ALTPADCFGC_PAD11_SR_Pos (28UL) /*!< GPIO ALTPADCFGC: PAD11_SR (Bit 28) */ -#define GPIO_ALTPADCFGC_PAD11_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGC: PAD11_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGC_PAD11_DS1_Pos (24UL) /*!< GPIO ALTPADCFGC: PAD11_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGC_PAD11_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGC: PAD11_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGC_PAD10_SR_Pos (20UL) /*!< GPIO ALTPADCFGC: PAD10_SR (Bit 20) */ -#define GPIO_ALTPADCFGC_PAD10_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGC: PAD10_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGC_PAD10_DS1_Pos (16UL) /*!< GPIO ALTPADCFGC: PAD10_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGC_PAD10_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGC: PAD10_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGC_PAD9_SR_Pos (12UL) /*!< GPIO ALTPADCFGC: PAD9_SR (Bit 12) */ -#define GPIO_ALTPADCFGC_PAD9_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGC: PAD9_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGC_PAD9_DS1_Pos (8UL) /*!< GPIO ALTPADCFGC: PAD9_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGC_PAD9_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGC: PAD9_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGC_PAD8_SR_Pos (4UL) /*!< GPIO ALTPADCFGC: PAD8_SR (Bit 4) */ -#define GPIO_ALTPADCFGC_PAD8_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGC: PAD8_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGC_PAD8_DS1_Pos (0UL) /*!< GPIO ALTPADCFGC: PAD8_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGC_PAD8_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGC: PAD8_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGD ======================================================= */ -#define GPIO_ALTPADCFGD_PAD15_SR_Pos (28UL) /*!< GPIO ALTPADCFGD: PAD15_SR (Bit 28) */ -#define GPIO_ALTPADCFGD_PAD15_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGD: PAD15_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGD_PAD15_DS1_Pos (24UL) /*!< GPIO ALTPADCFGD: PAD15_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGD_PAD15_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGD: PAD15_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGD_PAD14_SR_Pos (20UL) /*!< GPIO ALTPADCFGD: PAD14_SR (Bit 20) */ -#define GPIO_ALTPADCFGD_PAD14_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGD: PAD14_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGD_PAD14_DS1_Pos (16UL) /*!< GPIO ALTPADCFGD: PAD14_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGD_PAD14_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGD: PAD14_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGD_PAD13_SR_Pos (12UL) /*!< GPIO ALTPADCFGD: PAD13_SR (Bit 12) */ -#define GPIO_ALTPADCFGD_PAD13_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGD: PAD13_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGD_PAD13_DS1_Pos (8UL) /*!< GPIO ALTPADCFGD: PAD13_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGD_PAD13_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGD: PAD13_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGD_PAD12_SR_Pos (4UL) /*!< GPIO ALTPADCFGD: PAD12_SR (Bit 4) */ -#define GPIO_ALTPADCFGD_PAD12_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGD: PAD12_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGD_PAD12_DS1_Pos (0UL) /*!< GPIO ALTPADCFGD: PAD12_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGD_PAD12_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGD: PAD12_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGE ======================================================= */ -#define GPIO_ALTPADCFGE_PAD19_SR_Pos (28UL) /*!< GPIO ALTPADCFGE: PAD19_SR (Bit 28) */ -#define GPIO_ALTPADCFGE_PAD19_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGE: PAD19_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGE_PAD19_DS1_Pos (24UL) /*!< GPIO ALTPADCFGE: PAD19_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGE_PAD19_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGE: PAD19_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGE_PAD18_SR_Pos (20UL) /*!< GPIO ALTPADCFGE: PAD18_SR (Bit 20) */ -#define GPIO_ALTPADCFGE_PAD18_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGE: PAD18_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGE_PAD18_DS1_Pos (16UL) /*!< GPIO ALTPADCFGE: PAD18_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGE_PAD18_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGE: PAD18_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGE_PAD17_SR_Pos (12UL) /*!< GPIO ALTPADCFGE: PAD17_SR (Bit 12) */ -#define GPIO_ALTPADCFGE_PAD17_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGE: PAD17_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGE_PAD17_DS1_Pos (8UL) /*!< GPIO ALTPADCFGE: PAD17_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGE_PAD17_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGE: PAD17_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGE_PAD16_SR_Pos (4UL) /*!< GPIO ALTPADCFGE: PAD16_SR (Bit 4) */ -#define GPIO_ALTPADCFGE_PAD16_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGE: PAD16_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGE_PAD16_DS1_Pos (0UL) /*!< GPIO ALTPADCFGE: PAD16_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGE_PAD16_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGE: PAD16_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGF ======================================================= */ -#define GPIO_ALTPADCFGF_PAD23_SR_Pos (28UL) /*!< GPIO ALTPADCFGF: PAD23_SR (Bit 28) */ -#define GPIO_ALTPADCFGF_PAD23_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGF: PAD23_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGF_PAD23_DS1_Pos (24UL) /*!< GPIO ALTPADCFGF: PAD23_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGF_PAD23_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGF: PAD23_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGF_PAD22_SR_Pos (20UL) /*!< GPIO ALTPADCFGF: PAD22_SR (Bit 20) */ -#define GPIO_ALTPADCFGF_PAD22_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGF: PAD22_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGF_PAD22_DS1_Pos (16UL) /*!< GPIO ALTPADCFGF: PAD22_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGF_PAD22_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGF: PAD22_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGF_PAD21_SR_Pos (12UL) /*!< GPIO ALTPADCFGF: PAD21_SR (Bit 12) */ -#define GPIO_ALTPADCFGF_PAD21_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGF: PAD21_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGF_PAD21_DS1_Pos (8UL) /*!< GPIO ALTPADCFGF: PAD21_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGF_PAD21_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGF: PAD21_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGF_PAD20_SR_Pos (4UL) /*!< GPIO ALTPADCFGF: PAD20_SR (Bit 4) */ -#define GPIO_ALTPADCFGF_PAD20_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGF: PAD20_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGF_PAD20_DS1_Pos (0UL) /*!< GPIO ALTPADCFGF: PAD20_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGF_PAD20_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGF: PAD20_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGG ======================================================= */ -#define GPIO_ALTPADCFGG_PAD27_SR_Pos (28UL) /*!< GPIO ALTPADCFGG: PAD27_SR (Bit 28) */ -#define GPIO_ALTPADCFGG_PAD27_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGG: PAD27_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGG_PAD27_DS1_Pos (24UL) /*!< GPIO ALTPADCFGG: PAD27_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGG_PAD27_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGG: PAD27_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGG_PAD26_SR_Pos (20UL) /*!< GPIO ALTPADCFGG: PAD26_SR (Bit 20) */ -#define GPIO_ALTPADCFGG_PAD26_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGG: PAD26_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGG_PAD26_DS1_Pos (16UL) /*!< GPIO ALTPADCFGG: PAD26_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGG_PAD26_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGG: PAD26_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGG_PAD25_SR_Pos (12UL) /*!< GPIO ALTPADCFGG: PAD25_SR (Bit 12) */ -#define GPIO_ALTPADCFGG_PAD25_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGG: PAD25_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGG_PAD25_DS1_Pos (8UL) /*!< GPIO ALTPADCFGG: PAD25_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGG_PAD25_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGG: PAD25_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGG_PAD24_SR_Pos (4UL) /*!< GPIO ALTPADCFGG: PAD24_SR (Bit 4) */ -#define GPIO_ALTPADCFGG_PAD24_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGG: PAD24_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGG_PAD24_DS1_Pos (0UL) /*!< GPIO ALTPADCFGG: PAD24_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGG_PAD24_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGG: PAD24_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGH ======================================================= */ -#define GPIO_ALTPADCFGH_PAD31_SR_Pos (28UL) /*!< GPIO ALTPADCFGH: PAD31_SR (Bit 28) */ -#define GPIO_ALTPADCFGH_PAD31_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGH: PAD31_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGH_PAD31_DS1_Pos (24UL) /*!< GPIO ALTPADCFGH: PAD31_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGH_PAD31_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGH: PAD31_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGH_PAD30_SR_Pos (20UL) /*!< GPIO ALTPADCFGH: PAD30_SR (Bit 20) */ -#define GPIO_ALTPADCFGH_PAD30_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGH: PAD30_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGH_PAD30_DS1_Pos (16UL) /*!< GPIO ALTPADCFGH: PAD30_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGH_PAD30_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGH: PAD30_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGH_PAD29_SR_Pos (12UL) /*!< GPIO ALTPADCFGH: PAD29_SR (Bit 12) */ -#define GPIO_ALTPADCFGH_PAD29_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGH: PAD29_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGH_PAD29_DS1_Pos (8UL) /*!< GPIO ALTPADCFGH: PAD29_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGH_PAD29_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGH: PAD29_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGH_PAD28_SR_Pos (4UL) /*!< GPIO ALTPADCFGH: PAD28_SR (Bit 4) */ -#define GPIO_ALTPADCFGH_PAD28_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGH: PAD28_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGH_PAD28_DS1_Pos (0UL) /*!< GPIO ALTPADCFGH: PAD28_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGH_PAD28_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGH: PAD28_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGI ======================================================= */ -#define GPIO_ALTPADCFGI_PAD35_SR_Pos (28UL) /*!< GPIO ALTPADCFGI: PAD35_SR (Bit 28) */ -#define GPIO_ALTPADCFGI_PAD35_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGI: PAD35_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGI_PAD35_DS1_Pos (24UL) /*!< GPIO ALTPADCFGI: PAD35_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGI_PAD35_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGI: PAD35_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGI_PAD34_SR_Pos (20UL) /*!< GPIO ALTPADCFGI: PAD34_SR (Bit 20) */ -#define GPIO_ALTPADCFGI_PAD34_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGI: PAD34_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGI_PAD34_DS1_Pos (16UL) /*!< GPIO ALTPADCFGI: PAD34_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGI_PAD34_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGI: PAD34_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGI_PAD33_SR_Pos (12UL) /*!< GPIO ALTPADCFGI: PAD33_SR (Bit 12) */ -#define GPIO_ALTPADCFGI_PAD33_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGI: PAD33_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGI_PAD33_DS1_Pos (8UL) /*!< GPIO ALTPADCFGI: PAD33_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGI_PAD33_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGI: PAD33_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGI_PAD32_SR_Pos (4UL) /*!< GPIO ALTPADCFGI: PAD32_SR (Bit 4) */ -#define GPIO_ALTPADCFGI_PAD32_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGI: PAD32_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGI_PAD32_DS1_Pos (0UL) /*!< GPIO ALTPADCFGI: PAD32_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGI_PAD32_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGI: PAD32_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGJ ======================================================= */ -#define GPIO_ALTPADCFGJ_PAD39_SR_Pos (28UL) /*!< GPIO ALTPADCFGJ: PAD39_SR (Bit 28) */ -#define GPIO_ALTPADCFGJ_PAD39_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGJ: PAD39_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGJ_PAD39_DS1_Pos (24UL) /*!< GPIO ALTPADCFGJ: PAD39_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGJ_PAD39_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGJ: PAD39_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGJ_PAD38_SR_Pos (20UL) /*!< GPIO ALTPADCFGJ: PAD38_SR (Bit 20) */ -#define GPIO_ALTPADCFGJ_PAD38_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGJ: PAD38_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGJ_PAD38_DS1_Pos (16UL) /*!< GPIO ALTPADCFGJ: PAD38_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGJ_PAD38_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGJ: PAD38_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGJ_PAD37_SR_Pos (12UL) /*!< GPIO ALTPADCFGJ: PAD37_SR (Bit 12) */ -#define GPIO_ALTPADCFGJ_PAD37_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGJ: PAD37_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGJ_PAD37_DS1_Pos (8UL) /*!< GPIO ALTPADCFGJ: PAD37_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGJ_PAD37_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGJ: PAD37_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGJ_PAD36_SR_Pos (4UL) /*!< GPIO ALTPADCFGJ: PAD36_SR (Bit 4) */ -#define GPIO_ALTPADCFGJ_PAD36_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGJ: PAD36_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGJ_PAD36_DS1_Pos (0UL) /*!< GPIO ALTPADCFGJ: PAD36_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGJ_PAD36_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGJ: PAD36_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGK ======================================================= */ -#define GPIO_ALTPADCFGK_PAD43_SR_Pos (28UL) /*!< GPIO ALTPADCFGK: PAD43_SR (Bit 28) */ -#define GPIO_ALTPADCFGK_PAD43_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGK: PAD43_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGK_PAD43_DS1_Pos (24UL) /*!< GPIO ALTPADCFGK: PAD43_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGK_PAD43_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGK: PAD43_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGK_PAD42_SR_Pos (20UL) /*!< GPIO ALTPADCFGK: PAD42_SR (Bit 20) */ -#define GPIO_ALTPADCFGK_PAD42_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGK: PAD42_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGK_PAD42_DS1_Pos (16UL) /*!< GPIO ALTPADCFGK: PAD42_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGK_PAD42_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGK: PAD42_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGK_PAD41_SR_Pos (12UL) /*!< GPIO ALTPADCFGK: PAD41_SR (Bit 12) */ -#define GPIO_ALTPADCFGK_PAD41_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGK: PAD41_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGK_PAD41_DS1_Pos (8UL) /*!< GPIO ALTPADCFGK: PAD41_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGK_PAD41_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGK: PAD41_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGK_PAD40_SR_Pos (4UL) /*!< GPIO ALTPADCFGK: PAD40_SR (Bit 4) */ -#define GPIO_ALTPADCFGK_PAD40_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGK: PAD40_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGK_PAD40_DS1_Pos (0UL) /*!< GPIO ALTPADCFGK: PAD40_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGK_PAD40_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGK: PAD40_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGL ======================================================= */ -#define GPIO_ALTPADCFGL_PAD47_SR_Pos (28UL) /*!< GPIO ALTPADCFGL: PAD47_SR (Bit 28) */ -#define GPIO_ALTPADCFGL_PAD47_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGL: PAD47_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGL_PAD47_DS1_Pos (24UL) /*!< GPIO ALTPADCFGL: PAD47_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGL_PAD47_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGL: PAD47_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGL_PAD46_SR_Pos (20UL) /*!< GPIO ALTPADCFGL: PAD46_SR (Bit 20) */ -#define GPIO_ALTPADCFGL_PAD46_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGL: PAD46_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGL_PAD46_DS1_Pos (16UL) /*!< GPIO ALTPADCFGL: PAD46_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGL_PAD46_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGL: PAD46_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGL_PAD45_SR_Pos (12UL) /*!< GPIO ALTPADCFGL: PAD45_SR (Bit 12) */ -#define GPIO_ALTPADCFGL_PAD45_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGL: PAD45_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGL_PAD45_DS1_Pos (8UL) /*!< GPIO ALTPADCFGL: PAD45_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGL_PAD45_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGL: PAD45_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGL_PAD44_SR_Pos (4UL) /*!< GPIO ALTPADCFGL: PAD44_SR (Bit 4) */ -#define GPIO_ALTPADCFGL_PAD44_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGL: PAD44_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGL_PAD44_DS1_Pos (0UL) /*!< GPIO ALTPADCFGL: PAD44_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGL_PAD44_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGL: PAD44_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGM ======================================================= */ -#define GPIO_ALTPADCFGM_PAD51_SR_Pos (28UL) /*!< GPIO ALTPADCFGM: PAD51_SR (Bit 28) */ -#define GPIO_ALTPADCFGM_PAD51_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGM: PAD51_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGM_PAD51_DS1_Pos (24UL) /*!< GPIO ALTPADCFGM: PAD51_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGM_PAD51_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGM: PAD51_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGM_PAD50_SR_Pos (20UL) /*!< GPIO ALTPADCFGM: PAD50_SR (Bit 20) */ -#define GPIO_ALTPADCFGM_PAD50_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGM: PAD50_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGM_PAD50_DS1_Pos (16UL) /*!< GPIO ALTPADCFGM: PAD50_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGM_PAD50_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGM: PAD50_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGM_PAD49_SR_Pos (12UL) /*!< GPIO ALTPADCFGM: PAD49_SR (Bit 12) */ -#define GPIO_ALTPADCFGM_PAD49_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGM: PAD49_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGM_PAD49_DS1_Pos (8UL) /*!< GPIO ALTPADCFGM: PAD49_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGM_PAD49_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGM: PAD49_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGM_PAD48_SR_Pos (4UL) /*!< GPIO ALTPADCFGM: PAD48_SR (Bit 4) */ -#define GPIO_ALTPADCFGM_PAD48_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGM: PAD48_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGM_PAD48_DS1_Pos (0UL) /*!< GPIO ALTPADCFGM: PAD48_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGM_PAD48_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGM: PAD48_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGN ======================================================= */ -#define GPIO_ALTPADCFGN_PAD55_SR_Pos (28UL) /*!< GPIO ALTPADCFGN: PAD55_SR (Bit 28) */ -#define GPIO_ALTPADCFGN_PAD55_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGN: PAD55_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGN_PAD55_DS1_Pos (24UL) /*!< GPIO ALTPADCFGN: PAD55_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGN_PAD55_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGN: PAD55_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGN_PAD54_SR_Pos (20UL) /*!< GPIO ALTPADCFGN: PAD54_SR (Bit 20) */ -#define GPIO_ALTPADCFGN_PAD54_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGN: PAD54_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGN_PAD54_DS1_Pos (16UL) /*!< GPIO ALTPADCFGN: PAD54_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGN_PAD54_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGN: PAD54_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGN_PAD53_SR_Pos (12UL) /*!< GPIO ALTPADCFGN: PAD53_SR (Bit 12) */ -#define GPIO_ALTPADCFGN_PAD53_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGN: PAD53_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGN_PAD53_DS1_Pos (8UL) /*!< GPIO ALTPADCFGN: PAD53_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGN_PAD53_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGN: PAD53_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGN_PAD52_SR_Pos (4UL) /*!< GPIO ALTPADCFGN: PAD52_SR (Bit 4) */ -#define GPIO_ALTPADCFGN_PAD52_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGN: PAD52_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGN_PAD52_DS1_Pos (0UL) /*!< GPIO ALTPADCFGN: PAD52_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGN_PAD52_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGN: PAD52_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGO ======================================================= */ -#define GPIO_ALTPADCFGO_PAD59_SR_Pos (28UL) /*!< GPIO ALTPADCFGO: PAD59_SR (Bit 28) */ -#define GPIO_ALTPADCFGO_PAD59_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGO: PAD59_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGO_PAD59_DS1_Pos (24UL) /*!< GPIO ALTPADCFGO: PAD59_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGO_PAD59_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGO: PAD59_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGO_PAD58_SR_Pos (20UL) /*!< GPIO ALTPADCFGO: PAD58_SR (Bit 20) */ -#define GPIO_ALTPADCFGO_PAD58_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGO: PAD58_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGO_PAD58_DS1_Pos (16UL) /*!< GPIO ALTPADCFGO: PAD58_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGO_PAD58_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGO: PAD58_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGO_PAD57_SR_Pos (12UL) /*!< GPIO ALTPADCFGO: PAD57_SR (Bit 12) */ -#define GPIO_ALTPADCFGO_PAD57_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGO: PAD57_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGO_PAD57_DS1_Pos (8UL) /*!< GPIO ALTPADCFGO: PAD57_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGO_PAD57_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGO: PAD57_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGO_PAD56_SR_Pos (4UL) /*!< GPIO ALTPADCFGO: PAD56_SR (Bit 4) */ -#define GPIO_ALTPADCFGO_PAD56_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGO: PAD56_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGO_PAD56_DS1_Pos (0UL) /*!< GPIO ALTPADCFGO: PAD56_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGO_PAD56_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGO: PAD56_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGP ======================================================= */ -#define GPIO_ALTPADCFGP_PAD63_SR_Pos (28UL) /*!< GPIO ALTPADCFGP: PAD63_SR (Bit 28) */ -#define GPIO_ALTPADCFGP_PAD63_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGP: PAD63_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGP_PAD63_DS1_Pos (24UL) /*!< GPIO ALTPADCFGP: PAD63_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGP_PAD63_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGP: PAD63_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGP_PAD62_SR_Pos (20UL) /*!< GPIO ALTPADCFGP: PAD62_SR (Bit 20) */ -#define GPIO_ALTPADCFGP_PAD62_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGP: PAD62_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGP_PAD62_DS1_Pos (16UL) /*!< GPIO ALTPADCFGP: PAD62_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGP_PAD62_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGP: PAD62_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGP_PAD61_SR_Pos (12UL) /*!< GPIO ALTPADCFGP: PAD61_SR (Bit 12) */ -#define GPIO_ALTPADCFGP_PAD61_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGP: PAD61_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGP_PAD61_DS1_Pos (8UL) /*!< GPIO ALTPADCFGP: PAD61_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGP_PAD61_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGP: PAD61_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGP_PAD60_SR_Pos (4UL) /*!< GPIO ALTPADCFGP: PAD60_SR (Bit 4) */ -#define GPIO_ALTPADCFGP_PAD60_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGP: PAD60_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGP_PAD60_DS1_Pos (0UL) /*!< GPIO ALTPADCFGP: PAD60_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGP_PAD60_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGP: PAD60_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGQ ======================================================= */ -#define GPIO_ALTPADCFGQ_PAD67_SR_Pos (28UL) /*!< GPIO ALTPADCFGQ: PAD67_SR (Bit 28) */ -#define GPIO_ALTPADCFGQ_PAD67_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGQ: PAD67_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGQ_PAD67_DS1_Pos (24UL) /*!< GPIO ALTPADCFGQ: PAD67_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGQ_PAD67_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGQ: PAD67_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGQ_PAD66_SR_Pos (20UL) /*!< GPIO ALTPADCFGQ: PAD66_SR (Bit 20) */ -#define GPIO_ALTPADCFGQ_PAD66_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGQ: PAD66_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGQ_PAD66_DS1_Pos (16UL) /*!< GPIO ALTPADCFGQ: PAD66_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGQ_PAD66_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGQ: PAD66_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGQ_PAD65_SR_Pos (12UL) /*!< GPIO ALTPADCFGQ: PAD65_SR (Bit 12) */ -#define GPIO_ALTPADCFGQ_PAD65_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGQ: PAD65_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGQ_PAD65_DS1_Pos (8UL) /*!< GPIO ALTPADCFGQ: PAD65_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGQ_PAD65_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGQ: PAD65_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGQ_PAD64_SR_Pos (4UL) /*!< GPIO ALTPADCFGQ: PAD64_SR (Bit 4) */ -#define GPIO_ALTPADCFGQ_PAD64_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGQ: PAD64_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGQ_PAD64_DS1_Pos (0UL) /*!< GPIO ALTPADCFGQ: PAD64_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGQ_PAD64_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGQ: PAD64_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGR ======================================================= */ -#define GPIO_ALTPADCFGR_PAD71_SR_Pos (28UL) /*!< GPIO ALTPADCFGR: PAD71_SR (Bit 28) */ -#define GPIO_ALTPADCFGR_PAD71_SR_Msk (0x10000000UL) /*!< GPIO ALTPADCFGR: PAD71_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGR_PAD71_DS1_Pos (24UL) /*!< GPIO ALTPADCFGR: PAD71_DS1 (Bit 24) */ -#define GPIO_ALTPADCFGR_PAD71_DS1_Msk (0x1000000UL) /*!< GPIO ALTPADCFGR: PAD71_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGR_PAD70_SR_Pos (20UL) /*!< GPIO ALTPADCFGR: PAD70_SR (Bit 20) */ -#define GPIO_ALTPADCFGR_PAD70_SR_Msk (0x100000UL) /*!< GPIO ALTPADCFGR: PAD70_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGR_PAD70_DS1_Pos (16UL) /*!< GPIO ALTPADCFGR: PAD70_DS1 (Bit 16) */ -#define GPIO_ALTPADCFGR_PAD70_DS1_Msk (0x10000UL) /*!< GPIO ALTPADCFGR: PAD70_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGR_PAD69_SR_Pos (12UL) /*!< GPIO ALTPADCFGR: PAD69_SR (Bit 12) */ -#define GPIO_ALTPADCFGR_PAD69_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGR: PAD69_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGR_PAD69_DS1_Pos (8UL) /*!< GPIO ALTPADCFGR: PAD69_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGR_PAD69_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGR: PAD69_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGR_PAD68_SR_Pos (4UL) /*!< GPIO ALTPADCFGR: PAD68_SR (Bit 4) */ -#define GPIO_ALTPADCFGR_PAD68_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGR: PAD68_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGR_PAD68_DS1_Pos (0UL) /*!< GPIO ALTPADCFGR: PAD68_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGR_PAD68_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGR: PAD68_DS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== ALTPADCFGS ======================================================= */ -#define GPIO_ALTPADCFGS_PAD73_SR_Pos (12UL) /*!< GPIO ALTPADCFGS: PAD73_SR (Bit 12) */ -#define GPIO_ALTPADCFGS_PAD73_SR_Msk (0x1000UL) /*!< GPIO ALTPADCFGS: PAD73_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGS_PAD73_DS1_Pos (8UL) /*!< GPIO ALTPADCFGS: PAD73_DS1 (Bit 8) */ -#define GPIO_ALTPADCFGS_PAD73_DS1_Msk (0x100UL) /*!< GPIO ALTPADCFGS: PAD73_DS1 (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGS_PAD72_SR_Pos (4UL) /*!< GPIO ALTPADCFGS: PAD72_SR (Bit 4) */ -#define GPIO_ALTPADCFGS_PAD72_SR_Msk (0x10UL) /*!< GPIO ALTPADCFGS: PAD72_SR (Bitfield-Mask: 0x01) */ -#define GPIO_ALTPADCFGS_PAD72_DS1_Pos (0UL) /*!< GPIO ALTPADCFGS: PAD72_DS1 (Bit 0) */ -#define GPIO_ALTPADCFGS_PAD72_DS1_Msk (0x1UL) /*!< GPIO ALTPADCFGS: PAD72_DS1 (Bitfield-Mask: 0x01) */ -/* ========================================================= SCDET ========================================================= */ -#define GPIO_SCDET_SCDET_Pos (0UL) /*!< GPIO SCDET: SCDET (Bit 0) */ -#define GPIO_SCDET_SCDET_Msk (0x7fUL) /*!< GPIO SCDET: SCDET (Bitfield-Mask: 0x7f) */ -/* ======================================================== CTENCFG ======================================================== */ -#define GPIO_CTENCFG_EN31_Pos (31UL) /*!< GPIO CTENCFG: EN31 (Bit 31) */ -#define GPIO_CTENCFG_EN31_Msk (0x80000000UL) /*!< GPIO CTENCFG: EN31 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN30_Pos (30UL) /*!< GPIO CTENCFG: EN30 (Bit 30) */ -#define GPIO_CTENCFG_EN30_Msk (0x40000000UL) /*!< GPIO CTENCFG: EN30 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN29_Pos (29UL) /*!< GPIO CTENCFG: EN29 (Bit 29) */ -#define GPIO_CTENCFG_EN29_Msk (0x20000000UL) /*!< GPIO CTENCFG: EN29 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN28_Pos (28UL) /*!< GPIO CTENCFG: EN28 (Bit 28) */ -#define GPIO_CTENCFG_EN28_Msk (0x10000000UL) /*!< GPIO CTENCFG: EN28 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN27_Pos (27UL) /*!< GPIO CTENCFG: EN27 (Bit 27) */ -#define GPIO_CTENCFG_EN27_Msk (0x8000000UL) /*!< GPIO CTENCFG: EN27 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN26_Pos (26UL) /*!< GPIO CTENCFG: EN26 (Bit 26) */ -#define GPIO_CTENCFG_EN26_Msk (0x4000000UL) /*!< GPIO CTENCFG: EN26 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN25_Pos (25UL) /*!< GPIO CTENCFG: EN25 (Bit 25) */ -#define GPIO_CTENCFG_EN25_Msk (0x2000000UL) /*!< GPIO CTENCFG: EN25 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN24_Pos (24UL) /*!< GPIO CTENCFG: EN24 (Bit 24) */ -#define GPIO_CTENCFG_EN24_Msk (0x1000000UL) /*!< GPIO CTENCFG: EN24 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN23_Pos (23UL) /*!< GPIO CTENCFG: EN23 (Bit 23) */ -#define GPIO_CTENCFG_EN23_Msk (0x800000UL) /*!< GPIO CTENCFG: EN23 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN22_Pos (22UL) /*!< GPIO CTENCFG: EN22 (Bit 22) */ -#define GPIO_CTENCFG_EN22_Msk (0x400000UL) /*!< GPIO CTENCFG: EN22 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN21_Pos (21UL) /*!< GPIO CTENCFG: EN21 (Bit 21) */ -#define GPIO_CTENCFG_EN21_Msk (0x200000UL) /*!< GPIO CTENCFG: EN21 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN20_Pos (20UL) /*!< GPIO CTENCFG: EN20 (Bit 20) */ -#define GPIO_CTENCFG_EN20_Msk (0x100000UL) /*!< GPIO CTENCFG: EN20 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN19_Pos (19UL) /*!< GPIO CTENCFG: EN19 (Bit 19) */ -#define GPIO_CTENCFG_EN19_Msk (0x80000UL) /*!< GPIO CTENCFG: EN19 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN18_Pos (18UL) /*!< GPIO CTENCFG: EN18 (Bit 18) */ -#define GPIO_CTENCFG_EN18_Msk (0x40000UL) /*!< GPIO CTENCFG: EN18 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN17_Pos (17UL) /*!< GPIO CTENCFG: EN17 (Bit 17) */ -#define GPIO_CTENCFG_EN17_Msk (0x20000UL) /*!< GPIO CTENCFG: EN17 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN16_Pos (16UL) /*!< GPIO CTENCFG: EN16 (Bit 16) */ -#define GPIO_CTENCFG_EN16_Msk (0x10000UL) /*!< GPIO CTENCFG: EN16 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN15_Pos (15UL) /*!< GPIO CTENCFG: EN15 (Bit 15) */ -#define GPIO_CTENCFG_EN15_Msk (0x8000UL) /*!< GPIO CTENCFG: EN15 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN14_Pos (14UL) /*!< GPIO CTENCFG: EN14 (Bit 14) */ -#define GPIO_CTENCFG_EN14_Msk (0x4000UL) /*!< GPIO CTENCFG: EN14 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN13_Pos (13UL) /*!< GPIO CTENCFG: EN13 (Bit 13) */ -#define GPIO_CTENCFG_EN13_Msk (0x2000UL) /*!< GPIO CTENCFG: EN13 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN12_Pos (12UL) /*!< GPIO CTENCFG: EN12 (Bit 12) */ -#define GPIO_CTENCFG_EN12_Msk (0x1000UL) /*!< GPIO CTENCFG: EN12 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN11_Pos (11UL) /*!< GPIO CTENCFG: EN11 (Bit 11) */ -#define GPIO_CTENCFG_EN11_Msk (0x800UL) /*!< GPIO CTENCFG: EN11 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN10_Pos (10UL) /*!< GPIO CTENCFG: EN10 (Bit 10) */ -#define GPIO_CTENCFG_EN10_Msk (0x400UL) /*!< GPIO CTENCFG: EN10 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN9_Pos (9UL) /*!< GPIO CTENCFG: EN9 (Bit 9) */ -#define GPIO_CTENCFG_EN9_Msk (0x200UL) /*!< GPIO CTENCFG: EN9 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN8_Pos (8UL) /*!< GPIO CTENCFG: EN8 (Bit 8) */ -#define GPIO_CTENCFG_EN8_Msk (0x100UL) /*!< GPIO CTENCFG: EN8 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN7_Pos (7UL) /*!< GPIO CTENCFG: EN7 (Bit 7) */ -#define GPIO_CTENCFG_EN7_Msk (0x80UL) /*!< GPIO CTENCFG: EN7 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN6_Pos (6UL) /*!< GPIO CTENCFG: EN6 (Bit 6) */ -#define GPIO_CTENCFG_EN6_Msk (0x40UL) /*!< GPIO CTENCFG: EN6 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN5_Pos (5UL) /*!< GPIO CTENCFG: EN5 (Bit 5) */ -#define GPIO_CTENCFG_EN5_Msk (0x20UL) /*!< GPIO CTENCFG: EN5 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN4_Pos (4UL) /*!< GPIO CTENCFG: EN4 (Bit 4) */ -#define GPIO_CTENCFG_EN4_Msk (0x10UL) /*!< GPIO CTENCFG: EN4 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN3_Pos (3UL) /*!< GPIO CTENCFG: EN3 (Bit 3) */ -#define GPIO_CTENCFG_EN3_Msk (0x8UL) /*!< GPIO CTENCFG: EN3 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN2_Pos (2UL) /*!< GPIO CTENCFG: EN2 (Bit 2) */ -#define GPIO_CTENCFG_EN2_Msk (0x4UL) /*!< GPIO CTENCFG: EN2 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN1_Pos (1UL) /*!< GPIO CTENCFG: EN1 (Bit 1) */ -#define GPIO_CTENCFG_EN1_Msk (0x2UL) /*!< GPIO CTENCFG: EN1 (Bitfield-Mask: 0x01) */ -#define GPIO_CTENCFG_EN0_Pos (0UL) /*!< GPIO CTENCFG: EN0 (Bit 0) */ -#define GPIO_CTENCFG_EN0_Msk (0x1UL) /*!< GPIO CTENCFG: EN0 (Bitfield-Mask: 0x01) */ -/* ======================================================== INT0EN ========================================================= */ -#define GPIO_INT0EN_GPIO31_Pos (31UL) /*!< GPIO INT0EN: GPIO31 (Bit 31) */ -#define GPIO_INT0EN_GPIO31_Msk (0x80000000UL) /*!< GPIO INT0EN: GPIO31 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO30_Pos (30UL) /*!< GPIO INT0EN: GPIO30 (Bit 30) */ -#define GPIO_INT0EN_GPIO30_Msk (0x40000000UL) /*!< GPIO INT0EN: GPIO30 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO29_Pos (29UL) /*!< GPIO INT0EN: GPIO29 (Bit 29) */ -#define GPIO_INT0EN_GPIO29_Msk (0x20000000UL) /*!< GPIO INT0EN: GPIO29 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO28_Pos (28UL) /*!< GPIO INT0EN: GPIO28 (Bit 28) */ -#define GPIO_INT0EN_GPIO28_Msk (0x10000000UL) /*!< GPIO INT0EN: GPIO28 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO27_Pos (27UL) /*!< GPIO INT0EN: GPIO27 (Bit 27) */ -#define GPIO_INT0EN_GPIO27_Msk (0x8000000UL) /*!< GPIO INT0EN: GPIO27 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO26_Pos (26UL) /*!< GPIO INT0EN: GPIO26 (Bit 26) */ -#define GPIO_INT0EN_GPIO26_Msk (0x4000000UL) /*!< GPIO INT0EN: GPIO26 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO25_Pos (25UL) /*!< GPIO INT0EN: GPIO25 (Bit 25) */ -#define GPIO_INT0EN_GPIO25_Msk (0x2000000UL) /*!< GPIO INT0EN: GPIO25 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO24_Pos (24UL) /*!< GPIO INT0EN: GPIO24 (Bit 24) */ -#define GPIO_INT0EN_GPIO24_Msk (0x1000000UL) /*!< GPIO INT0EN: GPIO24 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO23_Pos (23UL) /*!< GPIO INT0EN: GPIO23 (Bit 23) */ -#define GPIO_INT0EN_GPIO23_Msk (0x800000UL) /*!< GPIO INT0EN: GPIO23 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO22_Pos (22UL) /*!< GPIO INT0EN: GPIO22 (Bit 22) */ -#define GPIO_INT0EN_GPIO22_Msk (0x400000UL) /*!< GPIO INT0EN: GPIO22 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO21_Pos (21UL) /*!< GPIO INT0EN: GPIO21 (Bit 21) */ -#define GPIO_INT0EN_GPIO21_Msk (0x200000UL) /*!< GPIO INT0EN: GPIO21 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO20_Pos (20UL) /*!< GPIO INT0EN: GPIO20 (Bit 20) */ -#define GPIO_INT0EN_GPIO20_Msk (0x100000UL) /*!< GPIO INT0EN: GPIO20 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO19_Pos (19UL) /*!< GPIO INT0EN: GPIO19 (Bit 19) */ -#define GPIO_INT0EN_GPIO19_Msk (0x80000UL) /*!< GPIO INT0EN: GPIO19 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO18_Pos (18UL) /*!< GPIO INT0EN: GPIO18 (Bit 18) */ -#define GPIO_INT0EN_GPIO18_Msk (0x40000UL) /*!< GPIO INT0EN: GPIO18 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO17_Pos (17UL) /*!< GPIO INT0EN: GPIO17 (Bit 17) */ -#define GPIO_INT0EN_GPIO17_Msk (0x20000UL) /*!< GPIO INT0EN: GPIO17 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO16_Pos (16UL) /*!< GPIO INT0EN: GPIO16 (Bit 16) */ -#define GPIO_INT0EN_GPIO16_Msk (0x10000UL) /*!< GPIO INT0EN: GPIO16 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO15_Pos (15UL) /*!< GPIO INT0EN: GPIO15 (Bit 15) */ -#define GPIO_INT0EN_GPIO15_Msk (0x8000UL) /*!< GPIO INT0EN: GPIO15 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO14_Pos (14UL) /*!< GPIO INT0EN: GPIO14 (Bit 14) */ -#define GPIO_INT0EN_GPIO14_Msk (0x4000UL) /*!< GPIO INT0EN: GPIO14 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO13_Pos (13UL) /*!< GPIO INT0EN: GPIO13 (Bit 13) */ -#define GPIO_INT0EN_GPIO13_Msk (0x2000UL) /*!< GPIO INT0EN: GPIO13 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO12_Pos (12UL) /*!< GPIO INT0EN: GPIO12 (Bit 12) */ -#define GPIO_INT0EN_GPIO12_Msk (0x1000UL) /*!< GPIO INT0EN: GPIO12 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO11_Pos (11UL) /*!< GPIO INT0EN: GPIO11 (Bit 11) */ -#define GPIO_INT0EN_GPIO11_Msk (0x800UL) /*!< GPIO INT0EN: GPIO11 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO10_Pos (10UL) /*!< GPIO INT0EN: GPIO10 (Bit 10) */ -#define GPIO_INT0EN_GPIO10_Msk (0x400UL) /*!< GPIO INT0EN: GPIO10 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO9_Pos (9UL) /*!< GPIO INT0EN: GPIO9 (Bit 9) */ -#define GPIO_INT0EN_GPIO9_Msk (0x200UL) /*!< GPIO INT0EN: GPIO9 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO8_Pos (8UL) /*!< GPIO INT0EN: GPIO8 (Bit 8) */ -#define GPIO_INT0EN_GPIO8_Msk (0x100UL) /*!< GPIO INT0EN: GPIO8 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO7_Pos (7UL) /*!< GPIO INT0EN: GPIO7 (Bit 7) */ -#define GPIO_INT0EN_GPIO7_Msk (0x80UL) /*!< GPIO INT0EN: GPIO7 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO6_Pos (6UL) /*!< GPIO INT0EN: GPIO6 (Bit 6) */ -#define GPIO_INT0EN_GPIO6_Msk (0x40UL) /*!< GPIO INT0EN: GPIO6 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO5_Pos (5UL) /*!< GPIO INT0EN: GPIO5 (Bit 5) */ -#define GPIO_INT0EN_GPIO5_Msk (0x20UL) /*!< GPIO INT0EN: GPIO5 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO4_Pos (4UL) /*!< GPIO INT0EN: GPIO4 (Bit 4) */ -#define GPIO_INT0EN_GPIO4_Msk (0x10UL) /*!< GPIO INT0EN: GPIO4 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO3_Pos (3UL) /*!< GPIO INT0EN: GPIO3 (Bit 3) */ -#define GPIO_INT0EN_GPIO3_Msk (0x8UL) /*!< GPIO INT0EN: GPIO3 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO2_Pos (2UL) /*!< GPIO INT0EN: GPIO2 (Bit 2) */ -#define GPIO_INT0EN_GPIO2_Msk (0x4UL) /*!< GPIO INT0EN: GPIO2 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO1_Pos (1UL) /*!< GPIO INT0EN: GPIO1 (Bit 1) */ -#define GPIO_INT0EN_GPIO1_Msk (0x2UL) /*!< GPIO INT0EN: GPIO1 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0EN_GPIO0_Pos (0UL) /*!< GPIO INT0EN: GPIO0 (Bit 0) */ -#define GPIO_INT0EN_GPIO0_Msk (0x1UL) /*!< GPIO INT0EN: GPIO0 (Bitfield-Mask: 0x01) */ -/* ======================================================= INT0STAT ======================================================== */ -#define GPIO_INT0STAT_GPIO31_Pos (31UL) /*!< GPIO INT0STAT: GPIO31 (Bit 31) */ -#define GPIO_INT0STAT_GPIO31_Msk (0x80000000UL) /*!< GPIO INT0STAT: GPIO31 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO30_Pos (30UL) /*!< GPIO INT0STAT: GPIO30 (Bit 30) */ -#define GPIO_INT0STAT_GPIO30_Msk (0x40000000UL) /*!< GPIO INT0STAT: GPIO30 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO29_Pos (29UL) /*!< GPIO INT0STAT: GPIO29 (Bit 29) */ -#define GPIO_INT0STAT_GPIO29_Msk (0x20000000UL) /*!< GPIO INT0STAT: GPIO29 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO28_Pos (28UL) /*!< GPIO INT0STAT: GPIO28 (Bit 28) */ -#define GPIO_INT0STAT_GPIO28_Msk (0x10000000UL) /*!< GPIO INT0STAT: GPIO28 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO27_Pos (27UL) /*!< GPIO INT0STAT: GPIO27 (Bit 27) */ -#define GPIO_INT0STAT_GPIO27_Msk (0x8000000UL) /*!< GPIO INT0STAT: GPIO27 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO26_Pos (26UL) /*!< GPIO INT0STAT: GPIO26 (Bit 26) */ -#define GPIO_INT0STAT_GPIO26_Msk (0x4000000UL) /*!< GPIO INT0STAT: GPIO26 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO25_Pos (25UL) /*!< GPIO INT0STAT: GPIO25 (Bit 25) */ -#define GPIO_INT0STAT_GPIO25_Msk (0x2000000UL) /*!< GPIO INT0STAT: GPIO25 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO24_Pos (24UL) /*!< GPIO INT0STAT: GPIO24 (Bit 24) */ -#define GPIO_INT0STAT_GPIO24_Msk (0x1000000UL) /*!< GPIO INT0STAT: GPIO24 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO23_Pos (23UL) /*!< GPIO INT0STAT: GPIO23 (Bit 23) */ -#define GPIO_INT0STAT_GPIO23_Msk (0x800000UL) /*!< GPIO INT0STAT: GPIO23 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO22_Pos (22UL) /*!< GPIO INT0STAT: GPIO22 (Bit 22) */ -#define GPIO_INT0STAT_GPIO22_Msk (0x400000UL) /*!< GPIO INT0STAT: GPIO22 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO21_Pos (21UL) /*!< GPIO INT0STAT: GPIO21 (Bit 21) */ -#define GPIO_INT0STAT_GPIO21_Msk (0x200000UL) /*!< GPIO INT0STAT: GPIO21 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO20_Pos (20UL) /*!< GPIO INT0STAT: GPIO20 (Bit 20) */ -#define GPIO_INT0STAT_GPIO20_Msk (0x100000UL) /*!< GPIO INT0STAT: GPIO20 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO19_Pos (19UL) /*!< GPIO INT0STAT: GPIO19 (Bit 19) */ -#define GPIO_INT0STAT_GPIO19_Msk (0x80000UL) /*!< GPIO INT0STAT: GPIO19 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO18_Pos (18UL) /*!< GPIO INT0STAT: GPIO18 (Bit 18) */ -#define GPIO_INT0STAT_GPIO18_Msk (0x40000UL) /*!< GPIO INT0STAT: GPIO18 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO17_Pos (17UL) /*!< GPIO INT0STAT: GPIO17 (Bit 17) */ -#define GPIO_INT0STAT_GPIO17_Msk (0x20000UL) /*!< GPIO INT0STAT: GPIO17 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO16_Pos (16UL) /*!< GPIO INT0STAT: GPIO16 (Bit 16) */ -#define GPIO_INT0STAT_GPIO16_Msk (0x10000UL) /*!< GPIO INT0STAT: GPIO16 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO15_Pos (15UL) /*!< GPIO INT0STAT: GPIO15 (Bit 15) */ -#define GPIO_INT0STAT_GPIO15_Msk (0x8000UL) /*!< GPIO INT0STAT: GPIO15 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO14_Pos (14UL) /*!< GPIO INT0STAT: GPIO14 (Bit 14) */ -#define GPIO_INT0STAT_GPIO14_Msk (0x4000UL) /*!< GPIO INT0STAT: GPIO14 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO13_Pos (13UL) /*!< GPIO INT0STAT: GPIO13 (Bit 13) */ -#define GPIO_INT0STAT_GPIO13_Msk (0x2000UL) /*!< GPIO INT0STAT: GPIO13 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO12_Pos (12UL) /*!< GPIO INT0STAT: GPIO12 (Bit 12) */ -#define GPIO_INT0STAT_GPIO12_Msk (0x1000UL) /*!< GPIO INT0STAT: GPIO12 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO11_Pos (11UL) /*!< GPIO INT0STAT: GPIO11 (Bit 11) */ -#define GPIO_INT0STAT_GPIO11_Msk (0x800UL) /*!< GPIO INT0STAT: GPIO11 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO10_Pos (10UL) /*!< GPIO INT0STAT: GPIO10 (Bit 10) */ -#define GPIO_INT0STAT_GPIO10_Msk (0x400UL) /*!< GPIO INT0STAT: GPIO10 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO9_Pos (9UL) /*!< GPIO INT0STAT: GPIO9 (Bit 9) */ -#define GPIO_INT0STAT_GPIO9_Msk (0x200UL) /*!< GPIO INT0STAT: GPIO9 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO8_Pos (8UL) /*!< GPIO INT0STAT: GPIO8 (Bit 8) */ -#define GPIO_INT0STAT_GPIO8_Msk (0x100UL) /*!< GPIO INT0STAT: GPIO8 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO7_Pos (7UL) /*!< GPIO INT0STAT: GPIO7 (Bit 7) */ -#define GPIO_INT0STAT_GPIO7_Msk (0x80UL) /*!< GPIO INT0STAT: GPIO7 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO6_Pos (6UL) /*!< GPIO INT0STAT: GPIO6 (Bit 6) */ -#define GPIO_INT0STAT_GPIO6_Msk (0x40UL) /*!< GPIO INT0STAT: GPIO6 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO5_Pos (5UL) /*!< GPIO INT0STAT: GPIO5 (Bit 5) */ -#define GPIO_INT0STAT_GPIO5_Msk (0x20UL) /*!< GPIO INT0STAT: GPIO5 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO4_Pos (4UL) /*!< GPIO INT0STAT: GPIO4 (Bit 4) */ -#define GPIO_INT0STAT_GPIO4_Msk (0x10UL) /*!< GPIO INT0STAT: GPIO4 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO3_Pos (3UL) /*!< GPIO INT0STAT: GPIO3 (Bit 3) */ -#define GPIO_INT0STAT_GPIO3_Msk (0x8UL) /*!< GPIO INT0STAT: GPIO3 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO2_Pos (2UL) /*!< GPIO INT0STAT: GPIO2 (Bit 2) */ -#define GPIO_INT0STAT_GPIO2_Msk (0x4UL) /*!< GPIO INT0STAT: GPIO2 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO1_Pos (1UL) /*!< GPIO INT0STAT: GPIO1 (Bit 1) */ -#define GPIO_INT0STAT_GPIO1_Msk (0x2UL) /*!< GPIO INT0STAT: GPIO1 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0STAT_GPIO0_Pos (0UL) /*!< GPIO INT0STAT: GPIO0 (Bit 0) */ -#define GPIO_INT0STAT_GPIO0_Msk (0x1UL) /*!< GPIO INT0STAT: GPIO0 (Bitfield-Mask: 0x01) */ -/* ======================================================== INT0CLR ======================================================== */ -#define GPIO_INT0CLR_GPIO31_Pos (31UL) /*!< GPIO INT0CLR: GPIO31 (Bit 31) */ -#define GPIO_INT0CLR_GPIO31_Msk (0x80000000UL) /*!< GPIO INT0CLR: GPIO31 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO30_Pos (30UL) /*!< GPIO INT0CLR: GPIO30 (Bit 30) */ -#define GPIO_INT0CLR_GPIO30_Msk (0x40000000UL) /*!< GPIO INT0CLR: GPIO30 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO29_Pos (29UL) /*!< GPIO INT0CLR: GPIO29 (Bit 29) */ -#define GPIO_INT0CLR_GPIO29_Msk (0x20000000UL) /*!< GPIO INT0CLR: GPIO29 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO28_Pos (28UL) /*!< GPIO INT0CLR: GPIO28 (Bit 28) */ -#define GPIO_INT0CLR_GPIO28_Msk (0x10000000UL) /*!< GPIO INT0CLR: GPIO28 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO27_Pos (27UL) /*!< GPIO INT0CLR: GPIO27 (Bit 27) */ -#define GPIO_INT0CLR_GPIO27_Msk (0x8000000UL) /*!< GPIO INT0CLR: GPIO27 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO26_Pos (26UL) /*!< GPIO INT0CLR: GPIO26 (Bit 26) */ -#define GPIO_INT0CLR_GPIO26_Msk (0x4000000UL) /*!< GPIO INT0CLR: GPIO26 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO25_Pos (25UL) /*!< GPIO INT0CLR: GPIO25 (Bit 25) */ -#define GPIO_INT0CLR_GPIO25_Msk (0x2000000UL) /*!< GPIO INT0CLR: GPIO25 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO24_Pos (24UL) /*!< GPIO INT0CLR: GPIO24 (Bit 24) */ -#define GPIO_INT0CLR_GPIO24_Msk (0x1000000UL) /*!< GPIO INT0CLR: GPIO24 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO23_Pos (23UL) /*!< GPIO INT0CLR: GPIO23 (Bit 23) */ -#define GPIO_INT0CLR_GPIO23_Msk (0x800000UL) /*!< GPIO INT0CLR: GPIO23 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO22_Pos (22UL) /*!< GPIO INT0CLR: GPIO22 (Bit 22) */ -#define GPIO_INT0CLR_GPIO22_Msk (0x400000UL) /*!< GPIO INT0CLR: GPIO22 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO21_Pos (21UL) /*!< GPIO INT0CLR: GPIO21 (Bit 21) */ -#define GPIO_INT0CLR_GPIO21_Msk (0x200000UL) /*!< GPIO INT0CLR: GPIO21 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO20_Pos (20UL) /*!< GPIO INT0CLR: GPIO20 (Bit 20) */ -#define GPIO_INT0CLR_GPIO20_Msk (0x100000UL) /*!< GPIO INT0CLR: GPIO20 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO19_Pos (19UL) /*!< GPIO INT0CLR: GPIO19 (Bit 19) */ -#define GPIO_INT0CLR_GPIO19_Msk (0x80000UL) /*!< GPIO INT0CLR: GPIO19 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO18_Pos (18UL) /*!< GPIO INT0CLR: GPIO18 (Bit 18) */ -#define GPIO_INT0CLR_GPIO18_Msk (0x40000UL) /*!< GPIO INT0CLR: GPIO18 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO17_Pos (17UL) /*!< GPIO INT0CLR: GPIO17 (Bit 17) */ -#define GPIO_INT0CLR_GPIO17_Msk (0x20000UL) /*!< GPIO INT0CLR: GPIO17 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO16_Pos (16UL) /*!< GPIO INT0CLR: GPIO16 (Bit 16) */ -#define GPIO_INT0CLR_GPIO16_Msk (0x10000UL) /*!< GPIO INT0CLR: GPIO16 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO15_Pos (15UL) /*!< GPIO INT0CLR: GPIO15 (Bit 15) */ -#define GPIO_INT0CLR_GPIO15_Msk (0x8000UL) /*!< GPIO INT0CLR: GPIO15 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO14_Pos (14UL) /*!< GPIO INT0CLR: GPIO14 (Bit 14) */ -#define GPIO_INT0CLR_GPIO14_Msk (0x4000UL) /*!< GPIO INT0CLR: GPIO14 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO13_Pos (13UL) /*!< GPIO INT0CLR: GPIO13 (Bit 13) */ -#define GPIO_INT0CLR_GPIO13_Msk (0x2000UL) /*!< GPIO INT0CLR: GPIO13 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO12_Pos (12UL) /*!< GPIO INT0CLR: GPIO12 (Bit 12) */ -#define GPIO_INT0CLR_GPIO12_Msk (0x1000UL) /*!< GPIO INT0CLR: GPIO12 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO11_Pos (11UL) /*!< GPIO INT0CLR: GPIO11 (Bit 11) */ -#define GPIO_INT0CLR_GPIO11_Msk (0x800UL) /*!< GPIO INT0CLR: GPIO11 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO10_Pos (10UL) /*!< GPIO INT0CLR: GPIO10 (Bit 10) */ -#define GPIO_INT0CLR_GPIO10_Msk (0x400UL) /*!< GPIO INT0CLR: GPIO10 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO9_Pos (9UL) /*!< GPIO INT0CLR: GPIO9 (Bit 9) */ -#define GPIO_INT0CLR_GPIO9_Msk (0x200UL) /*!< GPIO INT0CLR: GPIO9 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO8_Pos (8UL) /*!< GPIO INT0CLR: GPIO8 (Bit 8) */ -#define GPIO_INT0CLR_GPIO8_Msk (0x100UL) /*!< GPIO INT0CLR: GPIO8 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO7_Pos (7UL) /*!< GPIO INT0CLR: GPIO7 (Bit 7) */ -#define GPIO_INT0CLR_GPIO7_Msk (0x80UL) /*!< GPIO INT0CLR: GPIO7 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO6_Pos (6UL) /*!< GPIO INT0CLR: GPIO6 (Bit 6) */ -#define GPIO_INT0CLR_GPIO6_Msk (0x40UL) /*!< GPIO INT0CLR: GPIO6 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO5_Pos (5UL) /*!< GPIO INT0CLR: GPIO5 (Bit 5) */ -#define GPIO_INT0CLR_GPIO5_Msk (0x20UL) /*!< GPIO INT0CLR: GPIO5 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO4_Pos (4UL) /*!< GPIO INT0CLR: GPIO4 (Bit 4) */ -#define GPIO_INT0CLR_GPIO4_Msk (0x10UL) /*!< GPIO INT0CLR: GPIO4 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO3_Pos (3UL) /*!< GPIO INT0CLR: GPIO3 (Bit 3) */ -#define GPIO_INT0CLR_GPIO3_Msk (0x8UL) /*!< GPIO INT0CLR: GPIO3 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO2_Pos (2UL) /*!< GPIO INT0CLR: GPIO2 (Bit 2) */ -#define GPIO_INT0CLR_GPIO2_Msk (0x4UL) /*!< GPIO INT0CLR: GPIO2 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO1_Pos (1UL) /*!< GPIO INT0CLR: GPIO1 (Bit 1) */ -#define GPIO_INT0CLR_GPIO1_Msk (0x2UL) /*!< GPIO INT0CLR: GPIO1 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0CLR_GPIO0_Pos (0UL) /*!< GPIO INT0CLR: GPIO0 (Bit 0) */ -#define GPIO_INT0CLR_GPIO0_Msk (0x1UL) /*!< GPIO INT0CLR: GPIO0 (Bitfield-Mask: 0x01) */ -/* ======================================================== INT0SET ======================================================== */ -#define GPIO_INT0SET_GPIO31_Pos (31UL) /*!< GPIO INT0SET: GPIO31 (Bit 31) */ -#define GPIO_INT0SET_GPIO31_Msk (0x80000000UL) /*!< GPIO INT0SET: GPIO31 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO30_Pos (30UL) /*!< GPIO INT0SET: GPIO30 (Bit 30) */ -#define GPIO_INT0SET_GPIO30_Msk (0x40000000UL) /*!< GPIO INT0SET: GPIO30 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO29_Pos (29UL) /*!< GPIO INT0SET: GPIO29 (Bit 29) */ -#define GPIO_INT0SET_GPIO29_Msk (0x20000000UL) /*!< GPIO INT0SET: GPIO29 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO28_Pos (28UL) /*!< GPIO INT0SET: GPIO28 (Bit 28) */ -#define GPIO_INT0SET_GPIO28_Msk (0x10000000UL) /*!< GPIO INT0SET: GPIO28 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO27_Pos (27UL) /*!< GPIO INT0SET: GPIO27 (Bit 27) */ -#define GPIO_INT0SET_GPIO27_Msk (0x8000000UL) /*!< GPIO INT0SET: GPIO27 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO26_Pos (26UL) /*!< GPIO INT0SET: GPIO26 (Bit 26) */ -#define GPIO_INT0SET_GPIO26_Msk (0x4000000UL) /*!< GPIO INT0SET: GPIO26 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO25_Pos (25UL) /*!< GPIO INT0SET: GPIO25 (Bit 25) */ -#define GPIO_INT0SET_GPIO25_Msk (0x2000000UL) /*!< GPIO INT0SET: GPIO25 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO24_Pos (24UL) /*!< GPIO INT0SET: GPIO24 (Bit 24) */ -#define GPIO_INT0SET_GPIO24_Msk (0x1000000UL) /*!< GPIO INT0SET: GPIO24 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO23_Pos (23UL) /*!< GPIO INT0SET: GPIO23 (Bit 23) */ -#define GPIO_INT0SET_GPIO23_Msk (0x800000UL) /*!< GPIO INT0SET: GPIO23 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO22_Pos (22UL) /*!< GPIO INT0SET: GPIO22 (Bit 22) */ -#define GPIO_INT0SET_GPIO22_Msk (0x400000UL) /*!< GPIO INT0SET: GPIO22 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO21_Pos (21UL) /*!< GPIO INT0SET: GPIO21 (Bit 21) */ -#define GPIO_INT0SET_GPIO21_Msk (0x200000UL) /*!< GPIO INT0SET: GPIO21 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO20_Pos (20UL) /*!< GPIO INT0SET: GPIO20 (Bit 20) */ -#define GPIO_INT0SET_GPIO20_Msk (0x100000UL) /*!< GPIO INT0SET: GPIO20 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO19_Pos (19UL) /*!< GPIO INT0SET: GPIO19 (Bit 19) */ -#define GPIO_INT0SET_GPIO19_Msk (0x80000UL) /*!< GPIO INT0SET: GPIO19 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO18_Pos (18UL) /*!< GPIO INT0SET: GPIO18 (Bit 18) */ -#define GPIO_INT0SET_GPIO18_Msk (0x40000UL) /*!< GPIO INT0SET: GPIO18 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO17_Pos (17UL) /*!< GPIO INT0SET: GPIO17 (Bit 17) */ -#define GPIO_INT0SET_GPIO17_Msk (0x20000UL) /*!< GPIO INT0SET: GPIO17 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO16_Pos (16UL) /*!< GPIO INT0SET: GPIO16 (Bit 16) */ -#define GPIO_INT0SET_GPIO16_Msk (0x10000UL) /*!< GPIO INT0SET: GPIO16 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO15_Pos (15UL) /*!< GPIO INT0SET: GPIO15 (Bit 15) */ -#define GPIO_INT0SET_GPIO15_Msk (0x8000UL) /*!< GPIO INT0SET: GPIO15 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO14_Pos (14UL) /*!< GPIO INT0SET: GPIO14 (Bit 14) */ -#define GPIO_INT0SET_GPIO14_Msk (0x4000UL) /*!< GPIO INT0SET: GPIO14 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO13_Pos (13UL) /*!< GPIO INT0SET: GPIO13 (Bit 13) */ -#define GPIO_INT0SET_GPIO13_Msk (0x2000UL) /*!< GPIO INT0SET: GPIO13 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO12_Pos (12UL) /*!< GPIO INT0SET: GPIO12 (Bit 12) */ -#define GPIO_INT0SET_GPIO12_Msk (0x1000UL) /*!< GPIO INT0SET: GPIO12 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO11_Pos (11UL) /*!< GPIO INT0SET: GPIO11 (Bit 11) */ -#define GPIO_INT0SET_GPIO11_Msk (0x800UL) /*!< GPIO INT0SET: GPIO11 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO10_Pos (10UL) /*!< GPIO INT0SET: GPIO10 (Bit 10) */ -#define GPIO_INT0SET_GPIO10_Msk (0x400UL) /*!< GPIO INT0SET: GPIO10 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO9_Pos (9UL) /*!< GPIO INT0SET: GPIO9 (Bit 9) */ -#define GPIO_INT0SET_GPIO9_Msk (0x200UL) /*!< GPIO INT0SET: GPIO9 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO8_Pos (8UL) /*!< GPIO INT0SET: GPIO8 (Bit 8) */ -#define GPIO_INT0SET_GPIO8_Msk (0x100UL) /*!< GPIO INT0SET: GPIO8 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO7_Pos (7UL) /*!< GPIO INT0SET: GPIO7 (Bit 7) */ -#define GPIO_INT0SET_GPIO7_Msk (0x80UL) /*!< GPIO INT0SET: GPIO7 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO6_Pos (6UL) /*!< GPIO INT0SET: GPIO6 (Bit 6) */ -#define GPIO_INT0SET_GPIO6_Msk (0x40UL) /*!< GPIO INT0SET: GPIO6 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO5_Pos (5UL) /*!< GPIO INT0SET: GPIO5 (Bit 5) */ -#define GPIO_INT0SET_GPIO5_Msk (0x20UL) /*!< GPIO INT0SET: GPIO5 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO4_Pos (4UL) /*!< GPIO INT0SET: GPIO4 (Bit 4) */ -#define GPIO_INT0SET_GPIO4_Msk (0x10UL) /*!< GPIO INT0SET: GPIO4 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO3_Pos (3UL) /*!< GPIO INT0SET: GPIO3 (Bit 3) */ -#define GPIO_INT0SET_GPIO3_Msk (0x8UL) /*!< GPIO INT0SET: GPIO3 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO2_Pos (2UL) /*!< GPIO INT0SET: GPIO2 (Bit 2) */ -#define GPIO_INT0SET_GPIO2_Msk (0x4UL) /*!< GPIO INT0SET: GPIO2 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO1_Pos (1UL) /*!< GPIO INT0SET: GPIO1 (Bit 1) */ -#define GPIO_INT0SET_GPIO1_Msk (0x2UL) /*!< GPIO INT0SET: GPIO1 (Bitfield-Mask: 0x01) */ -#define GPIO_INT0SET_GPIO0_Pos (0UL) /*!< GPIO INT0SET: GPIO0 (Bit 0) */ -#define GPIO_INT0SET_GPIO0_Msk (0x1UL) /*!< GPIO INT0SET: GPIO0 (Bitfield-Mask: 0x01) */ -/* ======================================================== INT1EN ========================================================= */ -#define GPIO_INT1EN_GPIO63_Pos (31UL) /*!< GPIO INT1EN: GPIO63 (Bit 31) */ -#define GPIO_INT1EN_GPIO63_Msk (0x80000000UL) /*!< GPIO INT1EN: GPIO63 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO62_Pos (30UL) /*!< GPIO INT1EN: GPIO62 (Bit 30) */ -#define GPIO_INT1EN_GPIO62_Msk (0x40000000UL) /*!< GPIO INT1EN: GPIO62 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO61_Pos (29UL) /*!< GPIO INT1EN: GPIO61 (Bit 29) */ -#define GPIO_INT1EN_GPIO61_Msk (0x20000000UL) /*!< GPIO INT1EN: GPIO61 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO60_Pos (28UL) /*!< GPIO INT1EN: GPIO60 (Bit 28) */ -#define GPIO_INT1EN_GPIO60_Msk (0x10000000UL) /*!< GPIO INT1EN: GPIO60 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO59_Pos (27UL) /*!< GPIO INT1EN: GPIO59 (Bit 27) */ -#define GPIO_INT1EN_GPIO59_Msk (0x8000000UL) /*!< GPIO INT1EN: GPIO59 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO58_Pos (26UL) /*!< GPIO INT1EN: GPIO58 (Bit 26) */ -#define GPIO_INT1EN_GPIO58_Msk (0x4000000UL) /*!< GPIO INT1EN: GPIO58 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO57_Pos (25UL) /*!< GPIO INT1EN: GPIO57 (Bit 25) */ -#define GPIO_INT1EN_GPIO57_Msk (0x2000000UL) /*!< GPIO INT1EN: GPIO57 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO56_Pos (24UL) /*!< GPIO INT1EN: GPIO56 (Bit 24) */ -#define GPIO_INT1EN_GPIO56_Msk (0x1000000UL) /*!< GPIO INT1EN: GPIO56 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO55_Pos (23UL) /*!< GPIO INT1EN: GPIO55 (Bit 23) */ -#define GPIO_INT1EN_GPIO55_Msk (0x800000UL) /*!< GPIO INT1EN: GPIO55 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO54_Pos (22UL) /*!< GPIO INT1EN: GPIO54 (Bit 22) */ -#define GPIO_INT1EN_GPIO54_Msk (0x400000UL) /*!< GPIO INT1EN: GPIO54 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO53_Pos (21UL) /*!< GPIO INT1EN: GPIO53 (Bit 21) */ -#define GPIO_INT1EN_GPIO53_Msk (0x200000UL) /*!< GPIO INT1EN: GPIO53 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO52_Pos (20UL) /*!< GPIO INT1EN: GPIO52 (Bit 20) */ -#define GPIO_INT1EN_GPIO52_Msk (0x100000UL) /*!< GPIO INT1EN: GPIO52 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO51_Pos (19UL) /*!< GPIO INT1EN: GPIO51 (Bit 19) */ -#define GPIO_INT1EN_GPIO51_Msk (0x80000UL) /*!< GPIO INT1EN: GPIO51 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO50_Pos (18UL) /*!< GPIO INT1EN: GPIO50 (Bit 18) */ -#define GPIO_INT1EN_GPIO50_Msk (0x40000UL) /*!< GPIO INT1EN: GPIO50 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO49_Pos (17UL) /*!< GPIO INT1EN: GPIO49 (Bit 17) */ -#define GPIO_INT1EN_GPIO49_Msk (0x20000UL) /*!< GPIO INT1EN: GPIO49 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO48_Pos (16UL) /*!< GPIO INT1EN: GPIO48 (Bit 16) */ -#define GPIO_INT1EN_GPIO48_Msk (0x10000UL) /*!< GPIO INT1EN: GPIO48 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO47_Pos (15UL) /*!< GPIO INT1EN: GPIO47 (Bit 15) */ -#define GPIO_INT1EN_GPIO47_Msk (0x8000UL) /*!< GPIO INT1EN: GPIO47 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO46_Pos (14UL) /*!< GPIO INT1EN: GPIO46 (Bit 14) */ -#define GPIO_INT1EN_GPIO46_Msk (0x4000UL) /*!< GPIO INT1EN: GPIO46 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO45_Pos (13UL) /*!< GPIO INT1EN: GPIO45 (Bit 13) */ -#define GPIO_INT1EN_GPIO45_Msk (0x2000UL) /*!< GPIO INT1EN: GPIO45 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO44_Pos (12UL) /*!< GPIO INT1EN: GPIO44 (Bit 12) */ -#define GPIO_INT1EN_GPIO44_Msk (0x1000UL) /*!< GPIO INT1EN: GPIO44 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO43_Pos (11UL) /*!< GPIO INT1EN: GPIO43 (Bit 11) */ -#define GPIO_INT1EN_GPIO43_Msk (0x800UL) /*!< GPIO INT1EN: GPIO43 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO42_Pos (10UL) /*!< GPIO INT1EN: GPIO42 (Bit 10) */ -#define GPIO_INT1EN_GPIO42_Msk (0x400UL) /*!< GPIO INT1EN: GPIO42 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO41_Pos (9UL) /*!< GPIO INT1EN: GPIO41 (Bit 9) */ -#define GPIO_INT1EN_GPIO41_Msk (0x200UL) /*!< GPIO INT1EN: GPIO41 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO40_Pos (8UL) /*!< GPIO INT1EN: GPIO40 (Bit 8) */ -#define GPIO_INT1EN_GPIO40_Msk (0x100UL) /*!< GPIO INT1EN: GPIO40 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO39_Pos (7UL) /*!< GPIO INT1EN: GPIO39 (Bit 7) */ -#define GPIO_INT1EN_GPIO39_Msk (0x80UL) /*!< GPIO INT1EN: GPIO39 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO38_Pos (6UL) /*!< GPIO INT1EN: GPIO38 (Bit 6) */ -#define GPIO_INT1EN_GPIO38_Msk (0x40UL) /*!< GPIO INT1EN: GPIO38 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO37_Pos (5UL) /*!< GPIO INT1EN: GPIO37 (Bit 5) */ -#define GPIO_INT1EN_GPIO37_Msk (0x20UL) /*!< GPIO INT1EN: GPIO37 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO36_Pos (4UL) /*!< GPIO INT1EN: GPIO36 (Bit 4) */ -#define GPIO_INT1EN_GPIO36_Msk (0x10UL) /*!< GPIO INT1EN: GPIO36 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO35_Pos (3UL) /*!< GPIO INT1EN: GPIO35 (Bit 3) */ -#define GPIO_INT1EN_GPIO35_Msk (0x8UL) /*!< GPIO INT1EN: GPIO35 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO34_Pos (2UL) /*!< GPIO INT1EN: GPIO34 (Bit 2) */ -#define GPIO_INT1EN_GPIO34_Msk (0x4UL) /*!< GPIO INT1EN: GPIO34 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO33_Pos (1UL) /*!< GPIO INT1EN: GPIO33 (Bit 1) */ -#define GPIO_INT1EN_GPIO33_Msk (0x2UL) /*!< GPIO INT1EN: GPIO33 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1EN_GPIO32_Pos (0UL) /*!< GPIO INT1EN: GPIO32 (Bit 0) */ -#define GPIO_INT1EN_GPIO32_Msk (0x1UL) /*!< GPIO INT1EN: GPIO32 (Bitfield-Mask: 0x01) */ -/* ======================================================= INT1STAT ======================================================== */ -#define GPIO_INT1STAT_GPIO63_Pos (31UL) /*!< GPIO INT1STAT: GPIO63 (Bit 31) */ -#define GPIO_INT1STAT_GPIO63_Msk (0x80000000UL) /*!< GPIO INT1STAT: GPIO63 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO62_Pos (30UL) /*!< GPIO INT1STAT: GPIO62 (Bit 30) */ -#define GPIO_INT1STAT_GPIO62_Msk (0x40000000UL) /*!< GPIO INT1STAT: GPIO62 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO61_Pos (29UL) /*!< GPIO INT1STAT: GPIO61 (Bit 29) */ -#define GPIO_INT1STAT_GPIO61_Msk (0x20000000UL) /*!< GPIO INT1STAT: GPIO61 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO60_Pos (28UL) /*!< GPIO INT1STAT: GPIO60 (Bit 28) */ -#define GPIO_INT1STAT_GPIO60_Msk (0x10000000UL) /*!< GPIO INT1STAT: GPIO60 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO59_Pos (27UL) /*!< GPIO INT1STAT: GPIO59 (Bit 27) */ -#define GPIO_INT1STAT_GPIO59_Msk (0x8000000UL) /*!< GPIO INT1STAT: GPIO59 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO58_Pos (26UL) /*!< GPIO INT1STAT: GPIO58 (Bit 26) */ -#define GPIO_INT1STAT_GPIO58_Msk (0x4000000UL) /*!< GPIO INT1STAT: GPIO58 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO57_Pos (25UL) /*!< GPIO INT1STAT: GPIO57 (Bit 25) */ -#define GPIO_INT1STAT_GPIO57_Msk (0x2000000UL) /*!< GPIO INT1STAT: GPIO57 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO56_Pos (24UL) /*!< GPIO INT1STAT: GPIO56 (Bit 24) */ -#define GPIO_INT1STAT_GPIO56_Msk (0x1000000UL) /*!< GPIO INT1STAT: GPIO56 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO55_Pos (23UL) /*!< GPIO INT1STAT: GPIO55 (Bit 23) */ -#define GPIO_INT1STAT_GPIO55_Msk (0x800000UL) /*!< GPIO INT1STAT: GPIO55 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO54_Pos (22UL) /*!< GPIO INT1STAT: GPIO54 (Bit 22) */ -#define GPIO_INT1STAT_GPIO54_Msk (0x400000UL) /*!< GPIO INT1STAT: GPIO54 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO53_Pos (21UL) /*!< GPIO INT1STAT: GPIO53 (Bit 21) */ -#define GPIO_INT1STAT_GPIO53_Msk (0x200000UL) /*!< GPIO INT1STAT: GPIO53 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO52_Pos (20UL) /*!< GPIO INT1STAT: GPIO52 (Bit 20) */ -#define GPIO_INT1STAT_GPIO52_Msk (0x100000UL) /*!< GPIO INT1STAT: GPIO52 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO51_Pos (19UL) /*!< GPIO INT1STAT: GPIO51 (Bit 19) */ -#define GPIO_INT1STAT_GPIO51_Msk (0x80000UL) /*!< GPIO INT1STAT: GPIO51 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO50_Pos (18UL) /*!< GPIO INT1STAT: GPIO50 (Bit 18) */ -#define GPIO_INT1STAT_GPIO50_Msk (0x40000UL) /*!< GPIO INT1STAT: GPIO50 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO49_Pos (17UL) /*!< GPIO INT1STAT: GPIO49 (Bit 17) */ -#define GPIO_INT1STAT_GPIO49_Msk (0x20000UL) /*!< GPIO INT1STAT: GPIO49 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO48_Pos (16UL) /*!< GPIO INT1STAT: GPIO48 (Bit 16) */ -#define GPIO_INT1STAT_GPIO48_Msk (0x10000UL) /*!< GPIO INT1STAT: GPIO48 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO47_Pos (15UL) /*!< GPIO INT1STAT: GPIO47 (Bit 15) */ -#define GPIO_INT1STAT_GPIO47_Msk (0x8000UL) /*!< GPIO INT1STAT: GPIO47 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO46_Pos (14UL) /*!< GPIO INT1STAT: GPIO46 (Bit 14) */ -#define GPIO_INT1STAT_GPIO46_Msk (0x4000UL) /*!< GPIO INT1STAT: GPIO46 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO45_Pos (13UL) /*!< GPIO INT1STAT: GPIO45 (Bit 13) */ -#define GPIO_INT1STAT_GPIO45_Msk (0x2000UL) /*!< GPIO INT1STAT: GPIO45 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO44_Pos (12UL) /*!< GPIO INT1STAT: GPIO44 (Bit 12) */ -#define GPIO_INT1STAT_GPIO44_Msk (0x1000UL) /*!< GPIO INT1STAT: GPIO44 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO43_Pos (11UL) /*!< GPIO INT1STAT: GPIO43 (Bit 11) */ -#define GPIO_INT1STAT_GPIO43_Msk (0x800UL) /*!< GPIO INT1STAT: GPIO43 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO42_Pos (10UL) /*!< GPIO INT1STAT: GPIO42 (Bit 10) */ -#define GPIO_INT1STAT_GPIO42_Msk (0x400UL) /*!< GPIO INT1STAT: GPIO42 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO41_Pos (9UL) /*!< GPIO INT1STAT: GPIO41 (Bit 9) */ -#define GPIO_INT1STAT_GPIO41_Msk (0x200UL) /*!< GPIO INT1STAT: GPIO41 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO40_Pos (8UL) /*!< GPIO INT1STAT: GPIO40 (Bit 8) */ -#define GPIO_INT1STAT_GPIO40_Msk (0x100UL) /*!< GPIO INT1STAT: GPIO40 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO39_Pos (7UL) /*!< GPIO INT1STAT: GPIO39 (Bit 7) */ -#define GPIO_INT1STAT_GPIO39_Msk (0x80UL) /*!< GPIO INT1STAT: GPIO39 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO38_Pos (6UL) /*!< GPIO INT1STAT: GPIO38 (Bit 6) */ -#define GPIO_INT1STAT_GPIO38_Msk (0x40UL) /*!< GPIO INT1STAT: GPIO38 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO37_Pos (5UL) /*!< GPIO INT1STAT: GPIO37 (Bit 5) */ -#define GPIO_INT1STAT_GPIO37_Msk (0x20UL) /*!< GPIO INT1STAT: GPIO37 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO36_Pos (4UL) /*!< GPIO INT1STAT: GPIO36 (Bit 4) */ -#define GPIO_INT1STAT_GPIO36_Msk (0x10UL) /*!< GPIO INT1STAT: GPIO36 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO35_Pos (3UL) /*!< GPIO INT1STAT: GPIO35 (Bit 3) */ -#define GPIO_INT1STAT_GPIO35_Msk (0x8UL) /*!< GPIO INT1STAT: GPIO35 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO34_Pos (2UL) /*!< GPIO INT1STAT: GPIO34 (Bit 2) */ -#define GPIO_INT1STAT_GPIO34_Msk (0x4UL) /*!< GPIO INT1STAT: GPIO34 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO33_Pos (1UL) /*!< GPIO INT1STAT: GPIO33 (Bit 1) */ -#define GPIO_INT1STAT_GPIO33_Msk (0x2UL) /*!< GPIO INT1STAT: GPIO33 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1STAT_GPIO32_Pos (0UL) /*!< GPIO INT1STAT: GPIO32 (Bit 0) */ -#define GPIO_INT1STAT_GPIO32_Msk (0x1UL) /*!< GPIO INT1STAT: GPIO32 (Bitfield-Mask: 0x01) */ -/* ======================================================== INT1CLR ======================================================== */ -#define GPIO_INT1CLR_GPIO63_Pos (31UL) /*!< GPIO INT1CLR: GPIO63 (Bit 31) */ -#define GPIO_INT1CLR_GPIO63_Msk (0x80000000UL) /*!< GPIO INT1CLR: GPIO63 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO62_Pos (30UL) /*!< GPIO INT1CLR: GPIO62 (Bit 30) */ -#define GPIO_INT1CLR_GPIO62_Msk (0x40000000UL) /*!< GPIO INT1CLR: GPIO62 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO61_Pos (29UL) /*!< GPIO INT1CLR: GPIO61 (Bit 29) */ -#define GPIO_INT1CLR_GPIO61_Msk (0x20000000UL) /*!< GPIO INT1CLR: GPIO61 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO60_Pos (28UL) /*!< GPIO INT1CLR: GPIO60 (Bit 28) */ -#define GPIO_INT1CLR_GPIO60_Msk (0x10000000UL) /*!< GPIO INT1CLR: GPIO60 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO59_Pos (27UL) /*!< GPIO INT1CLR: GPIO59 (Bit 27) */ -#define GPIO_INT1CLR_GPIO59_Msk (0x8000000UL) /*!< GPIO INT1CLR: GPIO59 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO58_Pos (26UL) /*!< GPIO INT1CLR: GPIO58 (Bit 26) */ -#define GPIO_INT1CLR_GPIO58_Msk (0x4000000UL) /*!< GPIO INT1CLR: GPIO58 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO57_Pos (25UL) /*!< GPIO INT1CLR: GPIO57 (Bit 25) */ -#define GPIO_INT1CLR_GPIO57_Msk (0x2000000UL) /*!< GPIO INT1CLR: GPIO57 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO56_Pos (24UL) /*!< GPIO INT1CLR: GPIO56 (Bit 24) */ -#define GPIO_INT1CLR_GPIO56_Msk (0x1000000UL) /*!< GPIO INT1CLR: GPIO56 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO55_Pos (23UL) /*!< GPIO INT1CLR: GPIO55 (Bit 23) */ -#define GPIO_INT1CLR_GPIO55_Msk (0x800000UL) /*!< GPIO INT1CLR: GPIO55 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO54_Pos (22UL) /*!< GPIO INT1CLR: GPIO54 (Bit 22) */ -#define GPIO_INT1CLR_GPIO54_Msk (0x400000UL) /*!< GPIO INT1CLR: GPIO54 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO53_Pos (21UL) /*!< GPIO INT1CLR: GPIO53 (Bit 21) */ -#define GPIO_INT1CLR_GPIO53_Msk (0x200000UL) /*!< GPIO INT1CLR: GPIO53 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO52_Pos (20UL) /*!< GPIO INT1CLR: GPIO52 (Bit 20) */ -#define GPIO_INT1CLR_GPIO52_Msk (0x100000UL) /*!< GPIO INT1CLR: GPIO52 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO51_Pos (19UL) /*!< GPIO INT1CLR: GPIO51 (Bit 19) */ -#define GPIO_INT1CLR_GPIO51_Msk (0x80000UL) /*!< GPIO INT1CLR: GPIO51 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO50_Pos (18UL) /*!< GPIO INT1CLR: GPIO50 (Bit 18) */ -#define GPIO_INT1CLR_GPIO50_Msk (0x40000UL) /*!< GPIO INT1CLR: GPIO50 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO49_Pos (17UL) /*!< GPIO INT1CLR: GPIO49 (Bit 17) */ -#define GPIO_INT1CLR_GPIO49_Msk (0x20000UL) /*!< GPIO INT1CLR: GPIO49 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO48_Pos (16UL) /*!< GPIO INT1CLR: GPIO48 (Bit 16) */ -#define GPIO_INT1CLR_GPIO48_Msk (0x10000UL) /*!< GPIO INT1CLR: GPIO48 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO47_Pos (15UL) /*!< GPIO INT1CLR: GPIO47 (Bit 15) */ -#define GPIO_INT1CLR_GPIO47_Msk (0x8000UL) /*!< GPIO INT1CLR: GPIO47 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO46_Pos (14UL) /*!< GPIO INT1CLR: GPIO46 (Bit 14) */ -#define GPIO_INT1CLR_GPIO46_Msk (0x4000UL) /*!< GPIO INT1CLR: GPIO46 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO45_Pos (13UL) /*!< GPIO INT1CLR: GPIO45 (Bit 13) */ -#define GPIO_INT1CLR_GPIO45_Msk (0x2000UL) /*!< GPIO INT1CLR: GPIO45 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO44_Pos (12UL) /*!< GPIO INT1CLR: GPIO44 (Bit 12) */ -#define GPIO_INT1CLR_GPIO44_Msk (0x1000UL) /*!< GPIO INT1CLR: GPIO44 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO43_Pos (11UL) /*!< GPIO INT1CLR: GPIO43 (Bit 11) */ -#define GPIO_INT1CLR_GPIO43_Msk (0x800UL) /*!< GPIO INT1CLR: GPIO43 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO42_Pos (10UL) /*!< GPIO INT1CLR: GPIO42 (Bit 10) */ -#define GPIO_INT1CLR_GPIO42_Msk (0x400UL) /*!< GPIO INT1CLR: GPIO42 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO41_Pos (9UL) /*!< GPIO INT1CLR: GPIO41 (Bit 9) */ -#define GPIO_INT1CLR_GPIO41_Msk (0x200UL) /*!< GPIO INT1CLR: GPIO41 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO40_Pos (8UL) /*!< GPIO INT1CLR: GPIO40 (Bit 8) */ -#define GPIO_INT1CLR_GPIO40_Msk (0x100UL) /*!< GPIO INT1CLR: GPIO40 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO39_Pos (7UL) /*!< GPIO INT1CLR: GPIO39 (Bit 7) */ -#define GPIO_INT1CLR_GPIO39_Msk (0x80UL) /*!< GPIO INT1CLR: GPIO39 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO38_Pos (6UL) /*!< GPIO INT1CLR: GPIO38 (Bit 6) */ -#define GPIO_INT1CLR_GPIO38_Msk (0x40UL) /*!< GPIO INT1CLR: GPIO38 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO37_Pos (5UL) /*!< GPIO INT1CLR: GPIO37 (Bit 5) */ -#define GPIO_INT1CLR_GPIO37_Msk (0x20UL) /*!< GPIO INT1CLR: GPIO37 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO36_Pos (4UL) /*!< GPIO INT1CLR: GPIO36 (Bit 4) */ -#define GPIO_INT1CLR_GPIO36_Msk (0x10UL) /*!< GPIO INT1CLR: GPIO36 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO35_Pos (3UL) /*!< GPIO INT1CLR: GPIO35 (Bit 3) */ -#define GPIO_INT1CLR_GPIO35_Msk (0x8UL) /*!< GPIO INT1CLR: GPIO35 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO34_Pos (2UL) /*!< GPIO INT1CLR: GPIO34 (Bit 2) */ -#define GPIO_INT1CLR_GPIO34_Msk (0x4UL) /*!< GPIO INT1CLR: GPIO34 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO33_Pos (1UL) /*!< GPIO INT1CLR: GPIO33 (Bit 1) */ -#define GPIO_INT1CLR_GPIO33_Msk (0x2UL) /*!< GPIO INT1CLR: GPIO33 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1CLR_GPIO32_Pos (0UL) /*!< GPIO INT1CLR: GPIO32 (Bit 0) */ -#define GPIO_INT1CLR_GPIO32_Msk (0x1UL) /*!< GPIO INT1CLR: GPIO32 (Bitfield-Mask: 0x01) */ -/* ======================================================== INT1SET ======================================================== */ -#define GPIO_INT1SET_GPIO63_Pos (31UL) /*!< GPIO INT1SET: GPIO63 (Bit 31) */ -#define GPIO_INT1SET_GPIO63_Msk (0x80000000UL) /*!< GPIO INT1SET: GPIO63 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO62_Pos (30UL) /*!< GPIO INT1SET: GPIO62 (Bit 30) */ -#define GPIO_INT1SET_GPIO62_Msk (0x40000000UL) /*!< GPIO INT1SET: GPIO62 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO61_Pos (29UL) /*!< GPIO INT1SET: GPIO61 (Bit 29) */ -#define GPIO_INT1SET_GPIO61_Msk (0x20000000UL) /*!< GPIO INT1SET: GPIO61 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO60_Pos (28UL) /*!< GPIO INT1SET: GPIO60 (Bit 28) */ -#define GPIO_INT1SET_GPIO60_Msk (0x10000000UL) /*!< GPIO INT1SET: GPIO60 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO59_Pos (27UL) /*!< GPIO INT1SET: GPIO59 (Bit 27) */ -#define GPIO_INT1SET_GPIO59_Msk (0x8000000UL) /*!< GPIO INT1SET: GPIO59 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO58_Pos (26UL) /*!< GPIO INT1SET: GPIO58 (Bit 26) */ -#define GPIO_INT1SET_GPIO58_Msk (0x4000000UL) /*!< GPIO INT1SET: GPIO58 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO57_Pos (25UL) /*!< GPIO INT1SET: GPIO57 (Bit 25) */ -#define GPIO_INT1SET_GPIO57_Msk (0x2000000UL) /*!< GPIO INT1SET: GPIO57 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO56_Pos (24UL) /*!< GPIO INT1SET: GPIO56 (Bit 24) */ -#define GPIO_INT1SET_GPIO56_Msk (0x1000000UL) /*!< GPIO INT1SET: GPIO56 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO55_Pos (23UL) /*!< GPIO INT1SET: GPIO55 (Bit 23) */ -#define GPIO_INT1SET_GPIO55_Msk (0x800000UL) /*!< GPIO INT1SET: GPIO55 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO54_Pos (22UL) /*!< GPIO INT1SET: GPIO54 (Bit 22) */ -#define GPIO_INT1SET_GPIO54_Msk (0x400000UL) /*!< GPIO INT1SET: GPIO54 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO53_Pos (21UL) /*!< GPIO INT1SET: GPIO53 (Bit 21) */ -#define GPIO_INT1SET_GPIO53_Msk (0x200000UL) /*!< GPIO INT1SET: GPIO53 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO52_Pos (20UL) /*!< GPIO INT1SET: GPIO52 (Bit 20) */ -#define GPIO_INT1SET_GPIO52_Msk (0x100000UL) /*!< GPIO INT1SET: GPIO52 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO51_Pos (19UL) /*!< GPIO INT1SET: GPIO51 (Bit 19) */ -#define GPIO_INT1SET_GPIO51_Msk (0x80000UL) /*!< GPIO INT1SET: GPIO51 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO50_Pos (18UL) /*!< GPIO INT1SET: GPIO50 (Bit 18) */ -#define GPIO_INT1SET_GPIO50_Msk (0x40000UL) /*!< GPIO INT1SET: GPIO50 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO49_Pos (17UL) /*!< GPIO INT1SET: GPIO49 (Bit 17) */ -#define GPIO_INT1SET_GPIO49_Msk (0x20000UL) /*!< GPIO INT1SET: GPIO49 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO48_Pos (16UL) /*!< GPIO INT1SET: GPIO48 (Bit 16) */ -#define GPIO_INT1SET_GPIO48_Msk (0x10000UL) /*!< GPIO INT1SET: GPIO48 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO47_Pos (15UL) /*!< GPIO INT1SET: GPIO47 (Bit 15) */ -#define GPIO_INT1SET_GPIO47_Msk (0x8000UL) /*!< GPIO INT1SET: GPIO47 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO46_Pos (14UL) /*!< GPIO INT1SET: GPIO46 (Bit 14) */ -#define GPIO_INT1SET_GPIO46_Msk (0x4000UL) /*!< GPIO INT1SET: GPIO46 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO45_Pos (13UL) /*!< GPIO INT1SET: GPIO45 (Bit 13) */ -#define GPIO_INT1SET_GPIO45_Msk (0x2000UL) /*!< GPIO INT1SET: GPIO45 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO44_Pos (12UL) /*!< GPIO INT1SET: GPIO44 (Bit 12) */ -#define GPIO_INT1SET_GPIO44_Msk (0x1000UL) /*!< GPIO INT1SET: GPIO44 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO43_Pos (11UL) /*!< GPIO INT1SET: GPIO43 (Bit 11) */ -#define GPIO_INT1SET_GPIO43_Msk (0x800UL) /*!< GPIO INT1SET: GPIO43 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO42_Pos (10UL) /*!< GPIO INT1SET: GPIO42 (Bit 10) */ -#define GPIO_INT1SET_GPIO42_Msk (0x400UL) /*!< GPIO INT1SET: GPIO42 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO41_Pos (9UL) /*!< GPIO INT1SET: GPIO41 (Bit 9) */ -#define GPIO_INT1SET_GPIO41_Msk (0x200UL) /*!< GPIO INT1SET: GPIO41 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO40_Pos (8UL) /*!< GPIO INT1SET: GPIO40 (Bit 8) */ -#define GPIO_INT1SET_GPIO40_Msk (0x100UL) /*!< GPIO INT1SET: GPIO40 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO39_Pos (7UL) /*!< GPIO INT1SET: GPIO39 (Bit 7) */ -#define GPIO_INT1SET_GPIO39_Msk (0x80UL) /*!< GPIO INT1SET: GPIO39 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO38_Pos (6UL) /*!< GPIO INT1SET: GPIO38 (Bit 6) */ -#define GPIO_INT1SET_GPIO38_Msk (0x40UL) /*!< GPIO INT1SET: GPIO38 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO37_Pos (5UL) /*!< GPIO INT1SET: GPIO37 (Bit 5) */ -#define GPIO_INT1SET_GPIO37_Msk (0x20UL) /*!< GPIO INT1SET: GPIO37 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO36_Pos (4UL) /*!< GPIO INT1SET: GPIO36 (Bit 4) */ -#define GPIO_INT1SET_GPIO36_Msk (0x10UL) /*!< GPIO INT1SET: GPIO36 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO35_Pos (3UL) /*!< GPIO INT1SET: GPIO35 (Bit 3) */ -#define GPIO_INT1SET_GPIO35_Msk (0x8UL) /*!< GPIO INT1SET: GPIO35 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO34_Pos (2UL) /*!< GPIO INT1SET: GPIO34 (Bit 2) */ -#define GPIO_INT1SET_GPIO34_Msk (0x4UL) /*!< GPIO INT1SET: GPIO34 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO33_Pos (1UL) /*!< GPIO INT1SET: GPIO33 (Bit 1) */ -#define GPIO_INT1SET_GPIO33_Msk (0x2UL) /*!< GPIO INT1SET: GPIO33 (Bitfield-Mask: 0x01) */ -#define GPIO_INT1SET_GPIO32_Pos (0UL) /*!< GPIO INT1SET: GPIO32 (Bit 0) */ -#define GPIO_INT1SET_GPIO32_Msk (0x1UL) /*!< GPIO INT1SET: GPIO32 (Bitfield-Mask: 0x01) */ -/* ======================================================== INT2EN ========================================================= */ -#define GPIO_INT2EN_GPIO73_Pos (9UL) /*!< GPIO INT2EN: GPIO73 (Bit 9) */ -#define GPIO_INT2EN_GPIO73_Msk (0x200UL) /*!< GPIO INT2EN: GPIO73 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2EN_GPIO72_Pos (8UL) /*!< GPIO INT2EN: GPIO72 (Bit 8) */ -#define GPIO_INT2EN_GPIO72_Msk (0x100UL) /*!< GPIO INT2EN: GPIO72 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2EN_GPIO71_Pos (7UL) /*!< GPIO INT2EN: GPIO71 (Bit 7) */ -#define GPIO_INT2EN_GPIO71_Msk (0x80UL) /*!< GPIO INT2EN: GPIO71 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2EN_GPIO70_Pos (6UL) /*!< GPIO INT2EN: GPIO70 (Bit 6) */ -#define GPIO_INT2EN_GPIO70_Msk (0x40UL) /*!< GPIO INT2EN: GPIO70 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2EN_GPIO69_Pos (5UL) /*!< GPIO INT2EN: GPIO69 (Bit 5) */ -#define GPIO_INT2EN_GPIO69_Msk (0x20UL) /*!< GPIO INT2EN: GPIO69 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2EN_GPIO68_Pos (4UL) /*!< GPIO INT2EN: GPIO68 (Bit 4) */ -#define GPIO_INT2EN_GPIO68_Msk (0x10UL) /*!< GPIO INT2EN: GPIO68 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2EN_GPIO67_Pos (3UL) /*!< GPIO INT2EN: GPIO67 (Bit 3) */ -#define GPIO_INT2EN_GPIO67_Msk (0x8UL) /*!< GPIO INT2EN: GPIO67 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2EN_GPIO66_Pos (2UL) /*!< GPIO INT2EN: GPIO66 (Bit 2) */ -#define GPIO_INT2EN_GPIO66_Msk (0x4UL) /*!< GPIO INT2EN: GPIO66 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2EN_GPIO65_Pos (1UL) /*!< GPIO INT2EN: GPIO65 (Bit 1) */ -#define GPIO_INT2EN_GPIO65_Msk (0x2UL) /*!< GPIO INT2EN: GPIO65 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2EN_GPIO64_Pos (0UL) /*!< GPIO INT2EN: GPIO64 (Bit 0) */ -#define GPIO_INT2EN_GPIO64_Msk (0x1UL) /*!< GPIO INT2EN: GPIO64 (Bitfield-Mask: 0x01) */ -/* ======================================================= INT2STAT ======================================================== */ -#define GPIO_INT2STAT_GPIO73_Pos (9UL) /*!< GPIO INT2STAT: GPIO73 (Bit 9) */ -#define GPIO_INT2STAT_GPIO73_Msk (0x200UL) /*!< GPIO INT2STAT: GPIO73 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2STAT_GPIO72_Pos (8UL) /*!< GPIO INT2STAT: GPIO72 (Bit 8) */ -#define GPIO_INT2STAT_GPIO72_Msk (0x100UL) /*!< GPIO INT2STAT: GPIO72 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2STAT_GPIO71_Pos (7UL) /*!< GPIO INT2STAT: GPIO71 (Bit 7) */ -#define GPIO_INT2STAT_GPIO71_Msk (0x80UL) /*!< GPIO INT2STAT: GPIO71 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2STAT_GPIO70_Pos (6UL) /*!< GPIO INT2STAT: GPIO70 (Bit 6) */ -#define GPIO_INT2STAT_GPIO70_Msk (0x40UL) /*!< GPIO INT2STAT: GPIO70 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2STAT_GPIO69_Pos (5UL) /*!< GPIO INT2STAT: GPIO69 (Bit 5) */ -#define GPIO_INT2STAT_GPIO69_Msk (0x20UL) /*!< GPIO INT2STAT: GPIO69 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2STAT_GPIO68_Pos (4UL) /*!< GPIO INT2STAT: GPIO68 (Bit 4) */ -#define GPIO_INT2STAT_GPIO68_Msk (0x10UL) /*!< GPIO INT2STAT: GPIO68 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2STAT_GPIO67_Pos (3UL) /*!< GPIO INT2STAT: GPIO67 (Bit 3) */ -#define GPIO_INT2STAT_GPIO67_Msk (0x8UL) /*!< GPIO INT2STAT: GPIO67 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2STAT_GPIO66_Pos (2UL) /*!< GPIO INT2STAT: GPIO66 (Bit 2) */ -#define GPIO_INT2STAT_GPIO66_Msk (0x4UL) /*!< GPIO INT2STAT: GPIO66 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2STAT_GPIO65_Pos (1UL) /*!< GPIO INT2STAT: GPIO65 (Bit 1) */ -#define GPIO_INT2STAT_GPIO65_Msk (0x2UL) /*!< GPIO INT2STAT: GPIO65 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2STAT_GPIO64_Pos (0UL) /*!< GPIO INT2STAT: GPIO64 (Bit 0) */ -#define GPIO_INT2STAT_GPIO64_Msk (0x1UL) /*!< GPIO INT2STAT: GPIO64 (Bitfield-Mask: 0x01) */ -/* ======================================================== INT2CLR ======================================================== */ -#define GPIO_INT2CLR_GPIO73_Pos (9UL) /*!< GPIO INT2CLR: GPIO73 (Bit 9) */ -#define GPIO_INT2CLR_GPIO73_Msk (0x200UL) /*!< GPIO INT2CLR: GPIO73 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2CLR_GPIO72_Pos (8UL) /*!< GPIO INT2CLR: GPIO72 (Bit 8) */ -#define GPIO_INT2CLR_GPIO72_Msk (0x100UL) /*!< GPIO INT2CLR: GPIO72 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2CLR_GPIO71_Pos (7UL) /*!< GPIO INT2CLR: GPIO71 (Bit 7) */ -#define GPIO_INT2CLR_GPIO71_Msk (0x80UL) /*!< GPIO INT2CLR: GPIO71 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2CLR_GPIO70_Pos (6UL) /*!< GPIO INT2CLR: GPIO70 (Bit 6) */ -#define GPIO_INT2CLR_GPIO70_Msk (0x40UL) /*!< GPIO INT2CLR: GPIO70 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2CLR_GPIO69_Pos (5UL) /*!< GPIO INT2CLR: GPIO69 (Bit 5) */ -#define GPIO_INT2CLR_GPIO69_Msk (0x20UL) /*!< GPIO INT2CLR: GPIO69 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2CLR_GPIO68_Pos (4UL) /*!< GPIO INT2CLR: GPIO68 (Bit 4) */ -#define GPIO_INT2CLR_GPIO68_Msk (0x10UL) /*!< GPIO INT2CLR: GPIO68 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2CLR_GPIO67_Pos (3UL) /*!< GPIO INT2CLR: GPIO67 (Bit 3) */ -#define GPIO_INT2CLR_GPIO67_Msk (0x8UL) /*!< GPIO INT2CLR: GPIO67 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2CLR_GPIO66_Pos (2UL) /*!< GPIO INT2CLR: GPIO66 (Bit 2) */ -#define GPIO_INT2CLR_GPIO66_Msk (0x4UL) /*!< GPIO INT2CLR: GPIO66 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2CLR_GPIO65_Pos (1UL) /*!< GPIO INT2CLR: GPIO65 (Bit 1) */ -#define GPIO_INT2CLR_GPIO65_Msk (0x2UL) /*!< GPIO INT2CLR: GPIO65 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2CLR_GPIO64_Pos (0UL) /*!< GPIO INT2CLR: GPIO64 (Bit 0) */ -#define GPIO_INT2CLR_GPIO64_Msk (0x1UL) /*!< GPIO INT2CLR: GPIO64 (Bitfield-Mask: 0x01) */ -/* ======================================================== INT2SET ======================================================== */ -#define GPIO_INT2SET_GPIO73_Pos (9UL) /*!< GPIO INT2SET: GPIO73 (Bit 9) */ -#define GPIO_INT2SET_GPIO73_Msk (0x200UL) /*!< GPIO INT2SET: GPIO73 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2SET_GPIO72_Pos (8UL) /*!< GPIO INT2SET: GPIO72 (Bit 8) */ -#define GPIO_INT2SET_GPIO72_Msk (0x100UL) /*!< GPIO INT2SET: GPIO72 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2SET_GPIO71_Pos (7UL) /*!< GPIO INT2SET: GPIO71 (Bit 7) */ -#define GPIO_INT2SET_GPIO71_Msk (0x80UL) /*!< GPIO INT2SET: GPIO71 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2SET_GPIO70_Pos (6UL) /*!< GPIO INT2SET: GPIO70 (Bit 6) */ -#define GPIO_INT2SET_GPIO70_Msk (0x40UL) /*!< GPIO INT2SET: GPIO70 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2SET_GPIO69_Pos (5UL) /*!< GPIO INT2SET: GPIO69 (Bit 5) */ -#define GPIO_INT2SET_GPIO69_Msk (0x20UL) /*!< GPIO INT2SET: GPIO69 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2SET_GPIO68_Pos (4UL) /*!< GPIO INT2SET: GPIO68 (Bit 4) */ -#define GPIO_INT2SET_GPIO68_Msk (0x10UL) /*!< GPIO INT2SET: GPIO68 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2SET_GPIO67_Pos (3UL) /*!< GPIO INT2SET: GPIO67 (Bit 3) */ -#define GPIO_INT2SET_GPIO67_Msk (0x8UL) /*!< GPIO INT2SET: GPIO67 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2SET_GPIO66_Pos (2UL) /*!< GPIO INT2SET: GPIO66 (Bit 2) */ -#define GPIO_INT2SET_GPIO66_Msk (0x4UL) /*!< GPIO INT2SET: GPIO66 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2SET_GPIO65_Pos (1UL) /*!< GPIO INT2SET: GPIO65 (Bit 1) */ -#define GPIO_INT2SET_GPIO65_Msk (0x2UL) /*!< GPIO INT2SET: GPIO65 (Bitfield-Mask: 0x01) */ -#define GPIO_INT2SET_GPIO64_Pos (0UL) /*!< GPIO INT2SET: GPIO64 (Bit 0) */ -#define GPIO_INT2SET_GPIO64_Msk (0x1UL) /*!< GPIO INT2SET: GPIO64 (Bitfield-Mask: 0x01) */ -/* ======================================================== DBGCTRL ======================================================== */ -#define GPIO_DBGCTRL_GCLK5_Pos (5UL) /*!< GPIO DBGCTRL: GCLK5 (Bit 5) */ -#define GPIO_DBGCTRL_GCLK5_Msk (0x20UL) /*!< GPIO DBGCTRL: GCLK5 (Bitfield-Mask: 0x01) */ -#define GPIO_DBGCTRL_GCLK4_Pos (4UL) /*!< GPIO DBGCTRL: GCLK4 (Bit 4) */ -#define GPIO_DBGCTRL_GCLK4_Msk (0x10UL) /*!< GPIO DBGCTRL: GCLK4 (Bitfield-Mask: 0x01) */ -#define GPIO_DBGCTRL_GCLK3_Pos (3UL) /*!< GPIO DBGCTRL: GCLK3 (Bit 3) */ -#define GPIO_DBGCTRL_GCLK3_Msk (0x8UL) /*!< GPIO DBGCTRL: GCLK3 (Bitfield-Mask: 0x01) */ -#define GPIO_DBGCTRL_GCLK2_Pos (2UL) /*!< GPIO DBGCTRL: GCLK2 (Bit 2) */ -#define GPIO_DBGCTRL_GCLK2_Msk (0x4UL) /*!< GPIO DBGCTRL: GCLK2 (Bitfield-Mask: 0x01) */ -#define GPIO_DBGCTRL_GCLK1_Pos (1UL) /*!< GPIO DBGCTRL: GCLK1 (Bit 1) */ -#define GPIO_DBGCTRL_GCLK1_Msk (0x2UL) /*!< GPIO DBGCTRL: GCLK1 (Bitfield-Mask: 0x01) */ -#define GPIO_DBGCTRL_GCLK0_Pos (0UL) /*!< GPIO DBGCTRL: GCLK0 (Bit 0) */ -#define GPIO_DBGCTRL_GCLK0_Msk (0x1UL) /*!< GPIO DBGCTRL: GCLK0 (Bitfield-Mask: 0x01) */ - - -/* =========================================================================================================================== */ -/* ================ IOM0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= FIFO ========================================================== */ -#define IOM0_FIFO_FIFO_Pos (0UL) /*!< IOM0 FIFO: FIFO (Bit 0) */ -#define IOM0_FIFO_FIFO_Msk (0xffffffffUL) /*!< IOM0 FIFO: FIFO (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== FIFOPTR ======================================================== */ -#define IOM0_FIFOPTR_FIFO1REM_Pos (24UL) /*!< IOM0 FIFOPTR: FIFO1REM (Bit 24) */ -#define IOM0_FIFOPTR_FIFO1REM_Msk (0xff000000UL) /*!< IOM0 FIFOPTR: FIFO1REM (Bitfield-Mask: 0xff) */ -#define IOM0_FIFOPTR_FIFO1SIZ_Pos (16UL) /*!< IOM0 FIFOPTR: FIFO1SIZ (Bit 16) */ -#define IOM0_FIFOPTR_FIFO1SIZ_Msk (0xff0000UL) /*!< IOM0 FIFOPTR: FIFO1SIZ (Bitfield-Mask: 0xff) */ -#define IOM0_FIFOPTR_FIFO0REM_Pos (8UL) /*!< IOM0 FIFOPTR: FIFO0REM (Bit 8) */ -#define IOM0_FIFOPTR_FIFO0REM_Msk (0xff00UL) /*!< IOM0 FIFOPTR: FIFO0REM (Bitfield-Mask: 0xff) */ -#define IOM0_FIFOPTR_FIFO0SIZ_Pos (0UL) /*!< IOM0 FIFOPTR: FIFO0SIZ (Bit 0) */ -#define IOM0_FIFOPTR_FIFO0SIZ_Msk (0xffUL) /*!< IOM0 FIFOPTR: FIFO0SIZ (Bitfield-Mask: 0xff) */ -/* ======================================================== FIFOTHR ======================================================== */ -#define IOM0_FIFOTHR_FIFOWTHR_Pos (8UL) /*!< IOM0 FIFOTHR: FIFOWTHR (Bit 8) */ -#define IOM0_FIFOTHR_FIFOWTHR_Msk (0x3f00UL) /*!< IOM0 FIFOTHR: FIFOWTHR (Bitfield-Mask: 0x3f) */ -#define IOM0_FIFOTHR_FIFORTHR_Pos (0UL) /*!< IOM0 FIFOTHR: FIFORTHR (Bit 0) */ -#define IOM0_FIFOTHR_FIFORTHR_Msk (0x3fUL) /*!< IOM0 FIFOTHR: FIFORTHR (Bitfield-Mask: 0x3f) */ -/* ======================================================== FIFOPOP ======================================================== */ -#define IOM0_FIFOPOP_FIFODOUT_Pos (0UL) /*!< IOM0 FIFOPOP: FIFODOUT (Bit 0) */ -#define IOM0_FIFOPOP_FIFODOUT_Msk (0xffffffffUL) /*!< IOM0 FIFOPOP: FIFODOUT (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= FIFOPUSH ======================================================== */ -#define IOM0_FIFOPUSH_FIFODIN_Pos (0UL) /*!< IOM0 FIFOPUSH: FIFODIN (Bit 0) */ -#define IOM0_FIFOPUSH_FIFODIN_Msk (0xffffffffUL) /*!< IOM0 FIFOPUSH: FIFODIN (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= FIFOCTRL ======================================================== */ -#define IOM0_FIFOCTRL_FIFORSTN_Pos (1UL) /*!< IOM0 FIFOCTRL: FIFORSTN (Bit 1) */ -#define IOM0_FIFOCTRL_FIFORSTN_Msk (0x2UL) /*!< IOM0 FIFOCTRL: FIFORSTN (Bitfield-Mask: 0x01) */ -#define IOM0_FIFOCTRL_POPWR_Pos (0UL) /*!< IOM0 FIFOCTRL: POPWR (Bit 0) */ -#define IOM0_FIFOCTRL_POPWR_Msk (0x1UL) /*!< IOM0 FIFOCTRL: POPWR (Bitfield-Mask: 0x01) */ -/* ======================================================== FIFOLOC ======================================================== */ -#define IOM0_FIFOLOC_FIFORPTR_Pos (8UL) /*!< IOM0 FIFOLOC: FIFORPTR (Bit 8) */ -#define IOM0_FIFOLOC_FIFORPTR_Msk (0xf00UL) /*!< IOM0 FIFOLOC: FIFORPTR (Bitfield-Mask: 0x0f) */ -#define IOM0_FIFOLOC_FIFOWPTR_Pos (0UL) /*!< IOM0 FIFOLOC: FIFOWPTR (Bit 0) */ -#define IOM0_FIFOLOC_FIFOWPTR_Msk (0xfUL) /*!< IOM0 FIFOLOC: FIFOWPTR (Bitfield-Mask: 0x0f) */ -/* ========================================================= INTEN ========================================================= */ -#define IOM0_INTEN_CQERR_Pos (14UL) /*!< IOM0 INTEN: CQERR (Bit 14) */ -#define IOM0_INTEN_CQERR_Msk (0x4000UL) /*!< IOM0 INTEN: CQERR (Bitfield-Mask: 0x01) */ -#define IOM0_INTEN_CQUPD_Pos (13UL) /*!< IOM0 INTEN: CQUPD (Bit 13) */ -#define IOM0_INTEN_CQUPD_Msk (0x2000UL) /*!< IOM0 INTEN: CQUPD (Bitfield-Mask: 0x01) */ -#define IOM0_INTEN_CQPAUSED_Pos (12UL) /*!< IOM0 INTEN: CQPAUSED (Bit 12) */ -#define IOM0_INTEN_CQPAUSED_Msk (0x1000UL) /*!< IOM0 INTEN: CQPAUSED (Bitfield-Mask: 0x01) */ -#define IOM0_INTEN_DERR_Pos (11UL) /*!< IOM0 INTEN: DERR (Bit 11) */ -#define IOM0_INTEN_DERR_Msk (0x800UL) /*!< IOM0 INTEN: DERR (Bitfield-Mask: 0x01) */ -#define IOM0_INTEN_DCMP_Pos (10UL) /*!< IOM0 INTEN: DCMP (Bit 10) */ -#define IOM0_INTEN_DCMP_Msk (0x400UL) /*!< IOM0 INTEN: DCMP (Bitfield-Mask: 0x01) */ -#define IOM0_INTEN_ARB_Pos (9UL) /*!< IOM0 INTEN: ARB (Bit 9) */ -#define IOM0_INTEN_ARB_Msk (0x200UL) /*!< IOM0 INTEN: ARB (Bitfield-Mask: 0x01) */ -#define IOM0_INTEN_STOP_Pos (8UL) /*!< IOM0 INTEN: STOP (Bit 8) */ -#define IOM0_INTEN_STOP_Msk (0x100UL) /*!< IOM0 INTEN: STOP (Bitfield-Mask: 0x01) */ -#define IOM0_INTEN_START_Pos (7UL) /*!< IOM0 INTEN: START (Bit 7) */ -#define IOM0_INTEN_START_Msk (0x80UL) /*!< IOM0 INTEN: START (Bitfield-Mask: 0x01) */ -#define IOM0_INTEN_ICMD_Pos (6UL) /*!< IOM0 INTEN: ICMD (Bit 6) */ -#define IOM0_INTEN_ICMD_Msk (0x40UL) /*!< IOM0 INTEN: ICMD (Bitfield-Mask: 0x01) */ -#define IOM0_INTEN_IACC_Pos (5UL) /*!< IOM0 INTEN: IACC (Bit 5) */ -#define IOM0_INTEN_IACC_Msk (0x20UL) /*!< IOM0 INTEN: IACC (Bitfield-Mask: 0x01) */ -#define IOM0_INTEN_NAK_Pos (4UL) /*!< IOM0 INTEN: NAK (Bit 4) */ -#define IOM0_INTEN_NAK_Msk (0x10UL) /*!< IOM0 INTEN: NAK (Bitfield-Mask: 0x01) */ -#define IOM0_INTEN_FOVFL_Pos (3UL) /*!< IOM0 INTEN: FOVFL (Bit 3) */ -#define IOM0_INTEN_FOVFL_Msk (0x8UL) /*!< IOM0 INTEN: FOVFL (Bitfield-Mask: 0x01) */ -#define IOM0_INTEN_FUNDFL_Pos (2UL) /*!< IOM0 INTEN: FUNDFL (Bit 2) */ -#define IOM0_INTEN_FUNDFL_Msk (0x4UL) /*!< IOM0 INTEN: FUNDFL (Bitfield-Mask: 0x01) */ -#define IOM0_INTEN_THR_Pos (1UL) /*!< IOM0 INTEN: THR (Bit 1) */ -#define IOM0_INTEN_THR_Msk (0x2UL) /*!< IOM0 INTEN: THR (Bitfield-Mask: 0x01) */ -#define IOM0_INTEN_CMDCMP_Pos (0UL) /*!< IOM0 INTEN: CMDCMP (Bit 0) */ -#define IOM0_INTEN_CMDCMP_Msk (0x1UL) /*!< IOM0 INTEN: CMDCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTAT ======================================================== */ -#define IOM0_INTSTAT_CQERR_Pos (14UL) /*!< IOM0 INTSTAT: CQERR (Bit 14) */ -#define IOM0_INTSTAT_CQERR_Msk (0x4000UL) /*!< IOM0 INTSTAT: CQERR (Bitfield-Mask: 0x01) */ -#define IOM0_INTSTAT_CQUPD_Pos (13UL) /*!< IOM0 INTSTAT: CQUPD (Bit 13) */ -#define IOM0_INTSTAT_CQUPD_Msk (0x2000UL) /*!< IOM0 INTSTAT: CQUPD (Bitfield-Mask: 0x01) */ -#define IOM0_INTSTAT_CQPAUSED_Pos (12UL) /*!< IOM0 INTSTAT: CQPAUSED (Bit 12) */ -#define IOM0_INTSTAT_CQPAUSED_Msk (0x1000UL) /*!< IOM0 INTSTAT: CQPAUSED (Bitfield-Mask: 0x01) */ -#define IOM0_INTSTAT_DERR_Pos (11UL) /*!< IOM0 INTSTAT: DERR (Bit 11) */ -#define IOM0_INTSTAT_DERR_Msk (0x800UL) /*!< IOM0 INTSTAT: DERR (Bitfield-Mask: 0x01) */ -#define IOM0_INTSTAT_DCMP_Pos (10UL) /*!< IOM0 INTSTAT: DCMP (Bit 10) */ -#define IOM0_INTSTAT_DCMP_Msk (0x400UL) /*!< IOM0 INTSTAT: DCMP (Bitfield-Mask: 0x01) */ -#define IOM0_INTSTAT_ARB_Pos (9UL) /*!< IOM0 INTSTAT: ARB (Bit 9) */ -#define IOM0_INTSTAT_ARB_Msk (0x200UL) /*!< IOM0 INTSTAT: ARB (Bitfield-Mask: 0x01) */ -#define IOM0_INTSTAT_STOP_Pos (8UL) /*!< IOM0 INTSTAT: STOP (Bit 8) */ -#define IOM0_INTSTAT_STOP_Msk (0x100UL) /*!< IOM0 INTSTAT: STOP (Bitfield-Mask: 0x01) */ -#define IOM0_INTSTAT_START_Pos (7UL) /*!< IOM0 INTSTAT: START (Bit 7) */ -#define IOM0_INTSTAT_START_Msk (0x80UL) /*!< IOM0 INTSTAT: START (Bitfield-Mask: 0x01) */ -#define IOM0_INTSTAT_ICMD_Pos (6UL) /*!< IOM0 INTSTAT: ICMD (Bit 6) */ -#define IOM0_INTSTAT_ICMD_Msk (0x40UL) /*!< IOM0 INTSTAT: ICMD (Bitfield-Mask: 0x01) */ -#define IOM0_INTSTAT_IACC_Pos (5UL) /*!< IOM0 INTSTAT: IACC (Bit 5) */ -#define IOM0_INTSTAT_IACC_Msk (0x20UL) /*!< IOM0 INTSTAT: IACC (Bitfield-Mask: 0x01) */ -#define IOM0_INTSTAT_NAK_Pos (4UL) /*!< IOM0 INTSTAT: NAK (Bit 4) */ -#define IOM0_INTSTAT_NAK_Msk (0x10UL) /*!< IOM0 INTSTAT: NAK (Bitfield-Mask: 0x01) */ -#define IOM0_INTSTAT_FOVFL_Pos (3UL) /*!< IOM0 INTSTAT: FOVFL (Bit 3) */ -#define IOM0_INTSTAT_FOVFL_Msk (0x8UL) /*!< IOM0 INTSTAT: FOVFL (Bitfield-Mask: 0x01) */ -#define IOM0_INTSTAT_FUNDFL_Pos (2UL) /*!< IOM0 INTSTAT: FUNDFL (Bit 2) */ -#define IOM0_INTSTAT_FUNDFL_Msk (0x4UL) /*!< IOM0 INTSTAT: FUNDFL (Bitfield-Mask: 0x01) */ -#define IOM0_INTSTAT_THR_Pos (1UL) /*!< IOM0 INTSTAT: THR (Bit 1) */ -#define IOM0_INTSTAT_THR_Msk (0x2UL) /*!< IOM0 INTSTAT: THR (Bitfield-Mask: 0x01) */ -#define IOM0_INTSTAT_CMDCMP_Pos (0UL) /*!< IOM0 INTSTAT: CMDCMP (Bit 0) */ -#define IOM0_INTSTAT_CMDCMP_Msk (0x1UL) /*!< IOM0 INTSTAT: CMDCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== INTCLR ========================================================= */ -#define IOM0_INTCLR_CQERR_Pos (14UL) /*!< IOM0 INTCLR: CQERR (Bit 14) */ -#define IOM0_INTCLR_CQERR_Msk (0x4000UL) /*!< IOM0 INTCLR: CQERR (Bitfield-Mask: 0x01) */ -#define IOM0_INTCLR_CQUPD_Pos (13UL) /*!< IOM0 INTCLR: CQUPD (Bit 13) */ -#define IOM0_INTCLR_CQUPD_Msk (0x2000UL) /*!< IOM0 INTCLR: CQUPD (Bitfield-Mask: 0x01) */ -#define IOM0_INTCLR_CQPAUSED_Pos (12UL) /*!< IOM0 INTCLR: CQPAUSED (Bit 12) */ -#define IOM0_INTCLR_CQPAUSED_Msk (0x1000UL) /*!< IOM0 INTCLR: CQPAUSED (Bitfield-Mask: 0x01) */ -#define IOM0_INTCLR_DERR_Pos (11UL) /*!< IOM0 INTCLR: DERR (Bit 11) */ -#define IOM0_INTCLR_DERR_Msk (0x800UL) /*!< IOM0 INTCLR: DERR (Bitfield-Mask: 0x01) */ -#define IOM0_INTCLR_DCMP_Pos (10UL) /*!< IOM0 INTCLR: DCMP (Bit 10) */ -#define IOM0_INTCLR_DCMP_Msk (0x400UL) /*!< IOM0 INTCLR: DCMP (Bitfield-Mask: 0x01) */ -#define IOM0_INTCLR_ARB_Pos (9UL) /*!< IOM0 INTCLR: ARB (Bit 9) */ -#define IOM0_INTCLR_ARB_Msk (0x200UL) /*!< IOM0 INTCLR: ARB (Bitfield-Mask: 0x01) */ -#define IOM0_INTCLR_STOP_Pos (8UL) /*!< IOM0 INTCLR: STOP (Bit 8) */ -#define IOM0_INTCLR_STOP_Msk (0x100UL) /*!< IOM0 INTCLR: STOP (Bitfield-Mask: 0x01) */ -#define IOM0_INTCLR_START_Pos (7UL) /*!< IOM0 INTCLR: START (Bit 7) */ -#define IOM0_INTCLR_START_Msk (0x80UL) /*!< IOM0 INTCLR: START (Bitfield-Mask: 0x01) */ -#define IOM0_INTCLR_ICMD_Pos (6UL) /*!< IOM0 INTCLR: ICMD (Bit 6) */ -#define IOM0_INTCLR_ICMD_Msk (0x40UL) /*!< IOM0 INTCLR: ICMD (Bitfield-Mask: 0x01) */ -#define IOM0_INTCLR_IACC_Pos (5UL) /*!< IOM0 INTCLR: IACC (Bit 5) */ -#define IOM0_INTCLR_IACC_Msk (0x20UL) /*!< IOM0 INTCLR: IACC (Bitfield-Mask: 0x01) */ -#define IOM0_INTCLR_NAK_Pos (4UL) /*!< IOM0 INTCLR: NAK (Bit 4) */ -#define IOM0_INTCLR_NAK_Msk (0x10UL) /*!< IOM0 INTCLR: NAK (Bitfield-Mask: 0x01) */ -#define IOM0_INTCLR_FOVFL_Pos (3UL) /*!< IOM0 INTCLR: FOVFL (Bit 3) */ -#define IOM0_INTCLR_FOVFL_Msk (0x8UL) /*!< IOM0 INTCLR: FOVFL (Bitfield-Mask: 0x01) */ -#define IOM0_INTCLR_FUNDFL_Pos (2UL) /*!< IOM0 INTCLR: FUNDFL (Bit 2) */ -#define IOM0_INTCLR_FUNDFL_Msk (0x4UL) /*!< IOM0 INTCLR: FUNDFL (Bitfield-Mask: 0x01) */ -#define IOM0_INTCLR_THR_Pos (1UL) /*!< IOM0 INTCLR: THR (Bit 1) */ -#define IOM0_INTCLR_THR_Msk (0x2UL) /*!< IOM0 INTCLR: THR (Bitfield-Mask: 0x01) */ -#define IOM0_INTCLR_CMDCMP_Pos (0UL) /*!< IOM0 INTCLR: CMDCMP (Bit 0) */ -#define IOM0_INTCLR_CMDCMP_Msk (0x1UL) /*!< IOM0 INTCLR: CMDCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSET ========================================================= */ -#define IOM0_INTSET_CQERR_Pos (14UL) /*!< IOM0 INTSET: CQERR (Bit 14) */ -#define IOM0_INTSET_CQERR_Msk (0x4000UL) /*!< IOM0 INTSET: CQERR (Bitfield-Mask: 0x01) */ -#define IOM0_INTSET_CQUPD_Pos (13UL) /*!< IOM0 INTSET: CQUPD (Bit 13) */ -#define IOM0_INTSET_CQUPD_Msk (0x2000UL) /*!< IOM0 INTSET: CQUPD (Bitfield-Mask: 0x01) */ -#define IOM0_INTSET_CQPAUSED_Pos (12UL) /*!< IOM0 INTSET: CQPAUSED (Bit 12) */ -#define IOM0_INTSET_CQPAUSED_Msk (0x1000UL) /*!< IOM0 INTSET: CQPAUSED (Bitfield-Mask: 0x01) */ -#define IOM0_INTSET_DERR_Pos (11UL) /*!< IOM0 INTSET: DERR (Bit 11) */ -#define IOM0_INTSET_DERR_Msk (0x800UL) /*!< IOM0 INTSET: DERR (Bitfield-Mask: 0x01) */ -#define IOM0_INTSET_DCMP_Pos (10UL) /*!< IOM0 INTSET: DCMP (Bit 10) */ -#define IOM0_INTSET_DCMP_Msk (0x400UL) /*!< IOM0 INTSET: DCMP (Bitfield-Mask: 0x01) */ -#define IOM0_INTSET_ARB_Pos (9UL) /*!< IOM0 INTSET: ARB (Bit 9) */ -#define IOM0_INTSET_ARB_Msk (0x200UL) /*!< IOM0 INTSET: ARB (Bitfield-Mask: 0x01) */ -#define IOM0_INTSET_STOP_Pos (8UL) /*!< IOM0 INTSET: STOP (Bit 8) */ -#define IOM0_INTSET_STOP_Msk (0x100UL) /*!< IOM0 INTSET: STOP (Bitfield-Mask: 0x01) */ -#define IOM0_INTSET_START_Pos (7UL) /*!< IOM0 INTSET: START (Bit 7) */ -#define IOM0_INTSET_START_Msk (0x80UL) /*!< IOM0 INTSET: START (Bitfield-Mask: 0x01) */ -#define IOM0_INTSET_ICMD_Pos (6UL) /*!< IOM0 INTSET: ICMD (Bit 6) */ -#define IOM0_INTSET_ICMD_Msk (0x40UL) /*!< IOM0 INTSET: ICMD (Bitfield-Mask: 0x01) */ -#define IOM0_INTSET_IACC_Pos (5UL) /*!< IOM0 INTSET: IACC (Bit 5) */ -#define IOM0_INTSET_IACC_Msk (0x20UL) /*!< IOM0 INTSET: IACC (Bitfield-Mask: 0x01) */ -#define IOM0_INTSET_NAK_Pos (4UL) /*!< IOM0 INTSET: NAK (Bit 4) */ -#define IOM0_INTSET_NAK_Msk (0x10UL) /*!< IOM0 INTSET: NAK (Bitfield-Mask: 0x01) */ -#define IOM0_INTSET_FOVFL_Pos (3UL) /*!< IOM0 INTSET: FOVFL (Bit 3) */ -#define IOM0_INTSET_FOVFL_Msk (0x8UL) /*!< IOM0 INTSET: FOVFL (Bitfield-Mask: 0x01) */ -#define IOM0_INTSET_FUNDFL_Pos (2UL) /*!< IOM0 INTSET: FUNDFL (Bit 2) */ -#define IOM0_INTSET_FUNDFL_Msk (0x4UL) /*!< IOM0 INTSET: FUNDFL (Bitfield-Mask: 0x01) */ -#define IOM0_INTSET_THR_Pos (1UL) /*!< IOM0 INTSET: THR (Bit 1) */ -#define IOM0_INTSET_THR_Msk (0x2UL) /*!< IOM0 INTSET: THR (Bitfield-Mask: 0x01) */ -#define IOM0_INTSET_CMDCMP_Pos (0UL) /*!< IOM0 INTSET: CMDCMP (Bit 0) */ -#define IOM0_INTSET_CMDCMP_Msk (0x1UL) /*!< IOM0 INTSET: CMDCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== CLKCFG ========================================================= */ -#define IOM0_CLKCFG_TOTPER_Pos (24UL) /*!< IOM0 CLKCFG: TOTPER (Bit 24) */ -#define IOM0_CLKCFG_TOTPER_Msk (0xff000000UL) /*!< IOM0 CLKCFG: TOTPER (Bitfield-Mask: 0xff) */ -#define IOM0_CLKCFG_LOWPER_Pos (16UL) /*!< IOM0 CLKCFG: LOWPER (Bit 16) */ -#define IOM0_CLKCFG_LOWPER_Msk (0xff0000UL) /*!< IOM0 CLKCFG: LOWPER (Bitfield-Mask: 0xff) */ -#define IOM0_CLKCFG_DIVEN_Pos (12UL) /*!< IOM0 CLKCFG: DIVEN (Bit 12) */ -#define IOM0_CLKCFG_DIVEN_Msk (0x1000UL) /*!< IOM0 CLKCFG: DIVEN (Bitfield-Mask: 0x01) */ -#define IOM0_CLKCFG_DIV3_Pos (11UL) /*!< IOM0 CLKCFG: DIV3 (Bit 11) */ -#define IOM0_CLKCFG_DIV3_Msk (0x800UL) /*!< IOM0 CLKCFG: DIV3 (Bitfield-Mask: 0x01) */ -#define IOM0_CLKCFG_FSEL_Pos (8UL) /*!< IOM0 CLKCFG: FSEL (Bit 8) */ -#define IOM0_CLKCFG_FSEL_Msk (0x700UL) /*!< IOM0 CLKCFG: FSEL (Bitfield-Mask: 0x07) */ -#define IOM0_CLKCFG_IOCLKEN_Pos (0UL) /*!< IOM0 CLKCFG: IOCLKEN (Bit 0) */ -#define IOM0_CLKCFG_IOCLKEN_Msk (0x1UL) /*!< IOM0 CLKCFG: IOCLKEN (Bitfield-Mask: 0x01) */ -/* ====================================================== SUBMODCTRL ======================================================= */ -#define IOM0_SUBMODCTRL_SMOD1TYPE_Pos (5UL) /*!< IOM0 SUBMODCTRL: SMOD1TYPE (Bit 5) */ -#define IOM0_SUBMODCTRL_SMOD1TYPE_Msk (0xe0UL) /*!< IOM0 SUBMODCTRL: SMOD1TYPE (Bitfield-Mask: 0x07) */ -#define IOM0_SUBMODCTRL_SMOD1EN_Pos (4UL) /*!< IOM0 SUBMODCTRL: SMOD1EN (Bit 4) */ -#define IOM0_SUBMODCTRL_SMOD1EN_Msk (0x10UL) /*!< IOM0 SUBMODCTRL: SMOD1EN (Bitfield-Mask: 0x01) */ -#define IOM0_SUBMODCTRL_SMOD0TYPE_Pos (1UL) /*!< IOM0 SUBMODCTRL: SMOD0TYPE (Bit 1) */ -#define IOM0_SUBMODCTRL_SMOD0TYPE_Msk (0xeUL) /*!< IOM0 SUBMODCTRL: SMOD0TYPE (Bitfield-Mask: 0x07) */ -#define IOM0_SUBMODCTRL_SMOD0EN_Pos (0UL) /*!< IOM0 SUBMODCTRL: SMOD0EN (Bit 0) */ -#define IOM0_SUBMODCTRL_SMOD0EN_Msk (0x1UL) /*!< IOM0 SUBMODCTRL: SMOD0EN (Bitfield-Mask: 0x01) */ -/* ========================================================== CMD ========================================================== */ -#define IOM0_CMD_OFFSETLO_Pos (24UL) /*!< IOM0 CMD: OFFSETLO (Bit 24) */ -#define IOM0_CMD_OFFSETLO_Msk (0xff000000UL) /*!< IOM0 CMD: OFFSETLO (Bitfield-Mask: 0xff) */ -#define IOM0_CMD_CMDSEL_Pos (20UL) /*!< IOM0 CMD: CMDSEL (Bit 20) */ -#define IOM0_CMD_CMDSEL_Msk (0x300000UL) /*!< IOM0 CMD: CMDSEL (Bitfield-Mask: 0x03) */ -#define IOM0_CMD_TSIZE_Pos (8UL) /*!< IOM0 CMD: TSIZE (Bit 8) */ -#define IOM0_CMD_TSIZE_Msk (0xfff00UL) /*!< IOM0 CMD: TSIZE (Bitfield-Mask: 0xfff) */ -#define IOM0_CMD_CONT_Pos (7UL) /*!< IOM0 CMD: CONT (Bit 7) */ -#define IOM0_CMD_CONT_Msk (0x80UL) /*!< IOM0 CMD: CONT (Bitfield-Mask: 0x01) */ -#define IOM0_CMD_OFFSETCNT_Pos (5UL) /*!< IOM0 CMD: OFFSETCNT (Bit 5) */ -#define IOM0_CMD_OFFSETCNT_Msk (0x60UL) /*!< IOM0 CMD: OFFSETCNT (Bitfield-Mask: 0x03) */ -#define IOM0_CMD_CMD_Pos (0UL) /*!< IOM0 CMD: CMD (Bit 0) */ -#define IOM0_CMD_CMD_Msk (0x1fUL) /*!< IOM0 CMD: CMD (Bitfield-Mask: 0x1f) */ -/* ========================================================== DCX ========================================================== */ -#define IOM0_DCX_DCXEN_Pos (4UL) /*!< IOM0 DCX: DCXEN (Bit 4) */ -#define IOM0_DCX_DCXEN_Msk (0x10UL) /*!< IOM0 DCX: DCXEN (Bitfield-Mask: 0x01) */ -#define IOM0_DCX_CE3OUT_Pos (3UL) /*!< IOM0 DCX: CE3OUT (Bit 3) */ -#define IOM0_DCX_CE3OUT_Msk (0x8UL) /*!< IOM0 DCX: CE3OUT (Bitfield-Mask: 0x01) */ -#define IOM0_DCX_CE2OUT_Pos (2UL) /*!< IOM0 DCX: CE2OUT (Bit 2) */ -#define IOM0_DCX_CE2OUT_Msk (0x4UL) /*!< IOM0 DCX: CE2OUT (Bitfield-Mask: 0x01) */ -#define IOM0_DCX_CE1OUT_Pos (1UL) /*!< IOM0 DCX: CE1OUT (Bit 1) */ -#define IOM0_DCX_CE1OUT_Msk (0x2UL) /*!< IOM0 DCX: CE1OUT (Bitfield-Mask: 0x01) */ -#define IOM0_DCX_CE0OUT_Pos (0UL) /*!< IOM0 DCX: CE0OUT (Bit 0) */ -#define IOM0_DCX_CE0OUT_Msk (0x1UL) /*!< IOM0 DCX: CE0OUT (Bitfield-Mask: 0x01) */ -/* ======================================================= OFFSETHI ======================================================== */ -#define IOM0_OFFSETHI_OFFSETHI_Pos (0UL) /*!< IOM0 OFFSETHI: OFFSETHI (Bit 0) */ -#define IOM0_OFFSETHI_OFFSETHI_Msk (0xffffUL) /*!< IOM0 OFFSETHI: OFFSETHI (Bitfield-Mask: 0xffff) */ -/* ======================================================== CMDSTAT ======================================================== */ -#define IOM0_CMDSTAT_CTSIZE_Pos (8UL) /*!< IOM0 CMDSTAT: CTSIZE (Bit 8) */ -#define IOM0_CMDSTAT_CTSIZE_Msk (0xfff00UL) /*!< IOM0 CMDSTAT: CTSIZE (Bitfield-Mask: 0xfff) */ -#define IOM0_CMDSTAT_CMDSTAT_Pos (5UL) /*!< IOM0 CMDSTAT: CMDSTAT (Bit 5) */ -#define IOM0_CMDSTAT_CMDSTAT_Msk (0xe0UL) /*!< IOM0 CMDSTAT: CMDSTAT (Bitfield-Mask: 0x07) */ -#define IOM0_CMDSTAT_CCMD_Pos (0UL) /*!< IOM0 CMDSTAT: CCMD (Bit 0) */ -#define IOM0_CMDSTAT_CCMD_Msk (0x1fUL) /*!< IOM0 CMDSTAT: CCMD (Bitfield-Mask: 0x1f) */ -/* ======================================================= DMATRIGEN ======================================================= */ -#define IOM0_DMATRIGEN_DTHREN_Pos (1UL) /*!< IOM0 DMATRIGEN: DTHREN (Bit 1) */ -#define IOM0_DMATRIGEN_DTHREN_Msk (0x2UL) /*!< IOM0 DMATRIGEN: DTHREN (Bitfield-Mask: 0x01) */ -#define IOM0_DMATRIGEN_DCMDCMPEN_Pos (0UL) /*!< IOM0 DMATRIGEN: DCMDCMPEN (Bit 0) */ -#define IOM0_DMATRIGEN_DCMDCMPEN_Msk (0x1UL) /*!< IOM0 DMATRIGEN: DCMDCMPEN (Bitfield-Mask: 0x01) */ -/* ====================================================== DMATRIGSTAT ====================================================== */ -#define IOM0_DMATRIGSTAT_DTOTCMP_Pos (2UL) /*!< IOM0 DMATRIGSTAT: DTOTCMP (Bit 2) */ -#define IOM0_DMATRIGSTAT_DTOTCMP_Msk (0x4UL) /*!< IOM0 DMATRIGSTAT: DTOTCMP (Bitfield-Mask: 0x01) */ -#define IOM0_DMATRIGSTAT_DTHR_Pos (1UL) /*!< IOM0 DMATRIGSTAT: DTHR (Bit 1) */ -#define IOM0_DMATRIGSTAT_DTHR_Msk (0x2UL) /*!< IOM0 DMATRIGSTAT: DTHR (Bitfield-Mask: 0x01) */ -#define IOM0_DMATRIGSTAT_DCMDCMP_Pos (0UL) /*!< IOM0 DMATRIGSTAT: DCMDCMP (Bit 0) */ -#define IOM0_DMATRIGSTAT_DCMDCMP_Msk (0x1UL) /*!< IOM0 DMATRIGSTAT: DCMDCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== DMACFG ========================================================= */ -#define IOM0_DMACFG_DPWROFF_Pos (9UL) /*!< IOM0 DMACFG: DPWROFF (Bit 9) */ -#define IOM0_DMACFG_DPWROFF_Msk (0x200UL) /*!< IOM0 DMACFG: DPWROFF (Bitfield-Mask: 0x01) */ -#define IOM0_DMACFG_DMAPRI_Pos (8UL) /*!< IOM0 DMACFG: DMAPRI (Bit 8) */ -#define IOM0_DMACFG_DMAPRI_Msk (0x100UL) /*!< IOM0 DMACFG: DMAPRI (Bitfield-Mask: 0x01) */ -#define IOM0_DMACFG_DMADIR_Pos (1UL) /*!< IOM0 DMACFG: DMADIR (Bit 1) */ -#define IOM0_DMACFG_DMADIR_Msk (0x2UL) /*!< IOM0 DMACFG: DMADIR (Bitfield-Mask: 0x01) */ -#define IOM0_DMACFG_DMAEN_Pos (0UL) /*!< IOM0 DMACFG: DMAEN (Bit 0) */ -#define IOM0_DMACFG_DMAEN_Msk (0x1UL) /*!< IOM0 DMACFG: DMAEN (Bitfield-Mask: 0x01) */ -/* ====================================================== DMATOTCOUNT ====================================================== */ -#define IOM0_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< IOM0 DMATOTCOUNT: TOTCOUNT (Bit 0) */ -#define IOM0_DMATOTCOUNT_TOTCOUNT_Msk (0xfffUL) /*!< IOM0 DMATOTCOUNT: TOTCOUNT (Bitfield-Mask: 0xfff) */ -/* ====================================================== DMATARGADDR ====================================================== */ -#define IOM0_DMATARGADDR_TARGADDR28_Pos (28UL) /*!< IOM0 DMATARGADDR: TARGADDR28 (Bit 28) */ -#define IOM0_DMATARGADDR_TARGADDR28_Msk (0x10000000UL) /*!< IOM0 DMATARGADDR: TARGADDR28 (Bitfield-Mask: 0x01) */ -#define IOM0_DMATARGADDR_TARGADDR_Pos (0UL) /*!< IOM0 DMATARGADDR: TARGADDR (Bit 0) */ -#define IOM0_DMATARGADDR_TARGADDR_Msk (0x1fffffUL) /*!< IOM0 DMATARGADDR: TARGADDR (Bitfield-Mask: 0x1fffff) */ -/* ======================================================== DMASTAT ======================================================== */ -#define IOM0_DMASTAT_DMAERR_Pos (2UL) /*!< IOM0 DMASTAT: DMAERR (Bit 2) */ -#define IOM0_DMASTAT_DMAERR_Msk (0x4UL) /*!< IOM0 DMASTAT: DMAERR (Bitfield-Mask: 0x01) */ -#define IOM0_DMASTAT_DMACPL_Pos (1UL) /*!< IOM0 DMASTAT: DMACPL (Bit 1) */ -#define IOM0_DMASTAT_DMACPL_Msk (0x2UL) /*!< IOM0 DMASTAT: DMACPL (Bitfield-Mask: 0x01) */ -#define IOM0_DMASTAT_DMATIP_Pos (0UL) /*!< IOM0 DMASTAT: DMATIP (Bit 0) */ -#define IOM0_DMASTAT_DMATIP_Msk (0x1UL) /*!< IOM0 DMASTAT: DMATIP (Bitfield-Mask: 0x01) */ -/* ========================================================= CQCFG ========================================================= */ -#define IOM0_CQCFG_MSPIFLGSEL_Pos (2UL) /*!< IOM0 CQCFG: MSPIFLGSEL (Bit 2) */ -#define IOM0_CQCFG_MSPIFLGSEL_Msk (0xcUL) /*!< IOM0 CQCFG: MSPIFLGSEL (Bitfield-Mask: 0x03) */ -#define IOM0_CQCFG_CQPRI_Pos (1UL) /*!< IOM0 CQCFG: CQPRI (Bit 1) */ -#define IOM0_CQCFG_CQPRI_Msk (0x2UL) /*!< IOM0 CQCFG: CQPRI (Bitfield-Mask: 0x01) */ -#define IOM0_CQCFG_CQEN_Pos (0UL) /*!< IOM0 CQCFG: CQEN (Bit 0) */ -#define IOM0_CQCFG_CQEN_Msk (0x1UL) /*!< IOM0 CQCFG: CQEN (Bitfield-Mask: 0x01) */ -/* ======================================================== CQADDR ========================================================= */ -#define IOM0_CQADDR_CQADDR28_Pos (28UL) /*!< IOM0 CQADDR: CQADDR28 (Bit 28) */ -#define IOM0_CQADDR_CQADDR28_Msk (0x10000000UL) /*!< IOM0 CQADDR: CQADDR28 (Bitfield-Mask: 0x01) */ -#define IOM0_CQADDR_CQADDR_Pos (2UL) /*!< IOM0 CQADDR: CQADDR (Bit 2) */ -#define IOM0_CQADDR_CQADDR_Msk (0x1ffffcUL) /*!< IOM0 CQADDR: CQADDR (Bitfield-Mask: 0x7ffff) */ -/* ======================================================== CQSTAT ========================================================= */ -#define IOM0_CQSTAT_CQERR_Pos (2UL) /*!< IOM0 CQSTAT: CQERR (Bit 2) */ -#define IOM0_CQSTAT_CQERR_Msk (0x4UL) /*!< IOM0 CQSTAT: CQERR (Bitfield-Mask: 0x01) */ -#define IOM0_CQSTAT_CQPAUSED_Pos (1UL) /*!< IOM0 CQSTAT: CQPAUSED (Bit 1) */ -#define IOM0_CQSTAT_CQPAUSED_Msk (0x2UL) /*!< IOM0 CQSTAT: CQPAUSED (Bitfield-Mask: 0x01) */ -#define IOM0_CQSTAT_CQTIP_Pos (0UL) /*!< IOM0 CQSTAT: CQTIP (Bit 0) */ -#define IOM0_CQSTAT_CQTIP_Msk (0x1UL) /*!< IOM0 CQSTAT: CQTIP (Bitfield-Mask: 0x01) */ -/* ======================================================== CQFLAGS ======================================================== */ -#define IOM0_CQFLAGS_CQIRQMASK_Pos (16UL) /*!< IOM0 CQFLAGS: CQIRQMASK (Bit 16) */ -#define IOM0_CQFLAGS_CQIRQMASK_Msk (0xffff0000UL) /*!< IOM0 CQFLAGS: CQIRQMASK (Bitfield-Mask: 0xffff) */ -#define IOM0_CQFLAGS_CQFLAGS_Pos (0UL) /*!< IOM0 CQFLAGS: CQFLAGS (Bit 0) */ -#define IOM0_CQFLAGS_CQFLAGS_Msk (0xffffUL) /*!< IOM0 CQFLAGS: CQFLAGS (Bitfield-Mask: 0xffff) */ -/* ====================================================== CQSETCLEAR ======================================================= */ -#define IOM0_CQSETCLEAR_CQFCLR_Pos (16UL) /*!< IOM0 CQSETCLEAR: CQFCLR (Bit 16) */ -#define IOM0_CQSETCLEAR_CQFCLR_Msk (0xff0000UL) /*!< IOM0 CQSETCLEAR: CQFCLR (Bitfield-Mask: 0xff) */ -#define IOM0_CQSETCLEAR_CQFTGL_Pos (8UL) /*!< IOM0 CQSETCLEAR: CQFTGL (Bit 8) */ -#define IOM0_CQSETCLEAR_CQFTGL_Msk (0xff00UL) /*!< IOM0 CQSETCLEAR: CQFTGL (Bitfield-Mask: 0xff) */ -#define IOM0_CQSETCLEAR_CQFSET_Pos (0UL) /*!< IOM0 CQSETCLEAR: CQFSET (Bit 0) */ -#define IOM0_CQSETCLEAR_CQFSET_Msk (0xffUL) /*!< IOM0 CQSETCLEAR: CQFSET (Bitfield-Mask: 0xff) */ -/* ======================================================= CQPAUSEEN ======================================================= */ -#define IOM0_CQPAUSEEN_CQPEN_Pos (0UL) /*!< IOM0 CQPAUSEEN: CQPEN (Bit 0) */ -#define IOM0_CQPAUSEEN_CQPEN_Msk (0xffffUL) /*!< IOM0 CQPAUSEEN: CQPEN (Bitfield-Mask: 0xffff) */ -/* ======================================================= CQCURIDX ======================================================== */ -#define IOM0_CQCURIDX_CQCURIDX_Pos (0UL) /*!< IOM0 CQCURIDX: CQCURIDX (Bit 0) */ -#define IOM0_CQCURIDX_CQCURIDX_Msk (0xffUL) /*!< IOM0 CQCURIDX: CQCURIDX (Bitfield-Mask: 0xff) */ -/* ======================================================= CQENDIDX ======================================================== */ -#define IOM0_CQENDIDX_CQENDIDX_Pos (0UL) /*!< IOM0 CQENDIDX: CQENDIDX (Bit 0) */ -#define IOM0_CQENDIDX_CQENDIDX_Msk (0xffUL) /*!< IOM0 CQENDIDX: CQENDIDX (Bitfield-Mask: 0xff) */ -/* ======================================================== STATUS ========================================================= */ -#define IOM0_STATUS_IDLEST_Pos (2UL) /*!< IOM0 STATUS: IDLEST (Bit 2) */ -#define IOM0_STATUS_IDLEST_Msk (0x4UL) /*!< IOM0 STATUS: IDLEST (Bitfield-Mask: 0x01) */ -#define IOM0_STATUS_CMDACT_Pos (1UL) /*!< IOM0 STATUS: CMDACT (Bit 1) */ -#define IOM0_STATUS_CMDACT_Msk (0x2UL) /*!< IOM0 STATUS: CMDACT (Bitfield-Mask: 0x01) */ -#define IOM0_STATUS_ERR_Pos (0UL) /*!< IOM0 STATUS: ERR (Bit 0) */ -#define IOM0_STATUS_ERR_Msk (0x1UL) /*!< IOM0 STATUS: ERR (Bitfield-Mask: 0x01) */ -/* ======================================================== MSPICFG ======================================================== */ -#define IOM0_MSPICFG_MSPIRST_Pos (30UL) /*!< IOM0 MSPICFG: MSPIRST (Bit 30) */ -#define IOM0_MSPICFG_MSPIRST_Msk (0x40000000UL) /*!< IOM0 MSPICFG: MSPIRST (Bitfield-Mask: 0x01) */ -#define IOM0_MSPICFG_DOUTDLY_Pos (27UL) /*!< IOM0 MSPICFG: DOUTDLY (Bit 27) */ -#define IOM0_MSPICFG_DOUTDLY_Msk (0x38000000UL) /*!< IOM0 MSPICFG: DOUTDLY (Bitfield-Mask: 0x07) */ -#define IOM0_MSPICFG_DINDLY_Pos (24UL) /*!< IOM0 MSPICFG: DINDLY (Bit 24) */ -#define IOM0_MSPICFG_DINDLY_Msk (0x7000000UL) /*!< IOM0 MSPICFG: DINDLY (Bitfield-Mask: 0x07) */ -#define IOM0_MSPICFG_SPILSB_Pos (23UL) /*!< IOM0 MSPICFG: SPILSB (Bit 23) */ -#define IOM0_MSPICFG_SPILSB_Msk (0x800000UL) /*!< IOM0 MSPICFG: SPILSB (Bitfield-Mask: 0x01) */ -#define IOM0_MSPICFG_RDFCPOL_Pos (22UL) /*!< IOM0 MSPICFG: RDFCPOL (Bit 22) */ -#define IOM0_MSPICFG_RDFCPOL_Msk (0x400000UL) /*!< IOM0 MSPICFG: RDFCPOL (Bitfield-Mask: 0x01) */ -#define IOM0_MSPICFG_WTFCPOL_Pos (21UL) /*!< IOM0 MSPICFG: WTFCPOL (Bit 21) */ -#define IOM0_MSPICFG_WTFCPOL_Msk (0x200000UL) /*!< IOM0 MSPICFG: WTFCPOL (Bitfield-Mask: 0x01) */ -#define IOM0_MSPICFG_WTFCIRQ_Pos (20UL) /*!< IOM0 MSPICFG: WTFCIRQ (Bit 20) */ -#define IOM0_MSPICFG_WTFCIRQ_Msk (0x100000UL) /*!< IOM0 MSPICFG: WTFCIRQ (Bitfield-Mask: 0x01) */ -#define IOM0_MSPICFG_MOSIINV_Pos (18UL) /*!< IOM0 MSPICFG: MOSIINV (Bit 18) */ -#define IOM0_MSPICFG_MOSIINV_Msk (0x40000UL) /*!< IOM0 MSPICFG: MOSIINV (Bitfield-Mask: 0x01) */ -#define IOM0_MSPICFG_RDFC_Pos (17UL) /*!< IOM0 MSPICFG: RDFC (Bit 17) */ -#define IOM0_MSPICFG_RDFC_Msk (0x20000UL) /*!< IOM0 MSPICFG: RDFC (Bitfield-Mask: 0x01) */ -#define IOM0_MSPICFG_WTFC_Pos (16UL) /*!< IOM0 MSPICFG: WTFC (Bit 16) */ -#define IOM0_MSPICFG_WTFC_Msk (0x10000UL) /*!< IOM0 MSPICFG: WTFC (Bitfield-Mask: 0x01) */ -#define IOM0_MSPICFG_FULLDUP_Pos (2UL) /*!< IOM0 MSPICFG: FULLDUP (Bit 2) */ -#define IOM0_MSPICFG_FULLDUP_Msk (0x4UL) /*!< IOM0 MSPICFG: FULLDUP (Bitfield-Mask: 0x01) */ -#define IOM0_MSPICFG_SPHA_Pos (1UL) /*!< IOM0 MSPICFG: SPHA (Bit 1) */ -#define IOM0_MSPICFG_SPHA_Msk (0x2UL) /*!< IOM0 MSPICFG: SPHA (Bitfield-Mask: 0x01) */ -#define IOM0_MSPICFG_SPOL_Pos (0UL) /*!< IOM0 MSPICFG: SPOL (Bit 0) */ -#define IOM0_MSPICFG_SPOL_Msk (0x1UL) /*!< IOM0 MSPICFG: SPOL (Bitfield-Mask: 0x01) */ -/* ======================================================== MI2CCFG ======================================================== */ -#define IOM0_MI2CCFG_STRDIS_Pos (24UL) /*!< IOM0 MI2CCFG: STRDIS (Bit 24) */ -#define IOM0_MI2CCFG_STRDIS_Msk (0x1000000UL) /*!< IOM0 MI2CCFG: STRDIS (Bitfield-Mask: 0x01) */ -#define IOM0_MI2CCFG_SMPCNT_Pos (16UL) /*!< IOM0 MI2CCFG: SMPCNT (Bit 16) */ -#define IOM0_MI2CCFG_SMPCNT_Msk (0xff0000UL) /*!< IOM0 MI2CCFG: SMPCNT (Bitfield-Mask: 0xff) */ -#define IOM0_MI2CCFG_SDAENDLY_Pos (12UL) /*!< IOM0 MI2CCFG: SDAENDLY (Bit 12) */ -#define IOM0_MI2CCFG_SDAENDLY_Msk (0xf000UL) /*!< IOM0 MI2CCFG: SDAENDLY (Bitfield-Mask: 0x0f) */ -#define IOM0_MI2CCFG_SCLENDLY_Pos (8UL) /*!< IOM0 MI2CCFG: SCLENDLY (Bit 8) */ -#define IOM0_MI2CCFG_SCLENDLY_Msk (0xf00UL) /*!< IOM0 MI2CCFG: SCLENDLY (Bitfield-Mask: 0x0f) */ -#define IOM0_MI2CCFG_MI2CRST_Pos (6UL) /*!< IOM0 MI2CCFG: MI2CRST (Bit 6) */ -#define IOM0_MI2CCFG_MI2CRST_Msk (0x40UL) /*!< IOM0 MI2CCFG: MI2CRST (Bitfield-Mask: 0x01) */ -#define IOM0_MI2CCFG_SDADLY_Pos (4UL) /*!< IOM0 MI2CCFG: SDADLY (Bit 4) */ -#define IOM0_MI2CCFG_SDADLY_Msk (0x30UL) /*!< IOM0 MI2CCFG: SDADLY (Bitfield-Mask: 0x03) */ -#define IOM0_MI2CCFG_ARBEN_Pos (2UL) /*!< IOM0 MI2CCFG: ARBEN (Bit 2) */ -#define IOM0_MI2CCFG_ARBEN_Msk (0x4UL) /*!< IOM0 MI2CCFG: ARBEN (Bitfield-Mask: 0x01) */ -#define IOM0_MI2CCFG_I2CLSB_Pos (1UL) /*!< IOM0 MI2CCFG: I2CLSB (Bit 1) */ -#define IOM0_MI2CCFG_I2CLSB_Msk (0x2UL) /*!< IOM0 MI2CCFG: I2CLSB (Bitfield-Mask: 0x01) */ -#define IOM0_MI2CCFG_ADDRSZ_Pos (0UL) /*!< IOM0 MI2CCFG: ADDRSZ (Bit 0) */ -#define IOM0_MI2CCFG_ADDRSZ_Msk (0x1UL) /*!< IOM0 MI2CCFG: ADDRSZ (Bitfield-Mask: 0x01) */ -/* ======================================================== DEVCFG ========================================================= */ -#define IOM0_DEVCFG_DEVADDR_Pos (0UL) /*!< IOM0 DEVCFG: DEVADDR (Bit 0) */ -#define IOM0_DEVCFG_DEVADDR_Msk (0x3ffUL) /*!< IOM0 DEVCFG: DEVADDR (Bitfield-Mask: 0x3ff) */ -/* ======================================================== IOMDBG ========================================================= */ -#define IOM0_IOMDBG_DBGDATA_Pos (3UL) /*!< IOM0 IOMDBG: DBGDATA (Bit 3) */ -#define IOM0_IOMDBG_DBGDATA_Msk (0xfffffff8UL) /*!< IOM0 IOMDBG: DBGDATA (Bitfield-Mask: 0x1fffffff) */ -#define IOM0_IOMDBG_APBCLKON_Pos (2UL) /*!< IOM0 IOMDBG: APBCLKON (Bit 2) */ -#define IOM0_IOMDBG_APBCLKON_Msk (0x4UL) /*!< IOM0 IOMDBG: APBCLKON (Bitfield-Mask: 0x01) */ -#define IOM0_IOMDBG_IOCLKON_Pos (1UL) /*!< IOM0 IOMDBG: IOCLKON (Bit 1) */ -#define IOM0_IOMDBG_IOCLKON_Msk (0x2UL) /*!< IOM0 IOMDBG: IOCLKON (Bitfield-Mask: 0x01) */ -#define IOM0_IOMDBG_DBGEN_Pos (0UL) /*!< IOM0 IOMDBG: DBGEN (Bit 0) */ -#define IOM0_IOMDBG_DBGEN_Msk (0x1UL) /*!< IOM0 IOMDBG: DBGEN (Bitfield-Mask: 0x01) */ - - -/* =========================================================================================================================== */ -/* ================ IOSLAVE ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FIFOPTR ======================================================== */ -#define IOSLAVE_FIFOPTR_FIFOSIZ_Pos (8UL) /*!< IOSLAVE FIFOPTR: FIFOSIZ (Bit 8) */ -#define IOSLAVE_FIFOPTR_FIFOSIZ_Msk (0xff00UL) /*!< IOSLAVE FIFOPTR: FIFOSIZ (Bitfield-Mask: 0xff) */ -#define IOSLAVE_FIFOPTR_FIFOPTR_Pos (0UL) /*!< IOSLAVE FIFOPTR: FIFOPTR (Bit 0) */ -#define IOSLAVE_FIFOPTR_FIFOPTR_Msk (0xffUL) /*!< IOSLAVE FIFOPTR: FIFOPTR (Bitfield-Mask: 0xff) */ -/* ======================================================== FIFOCFG ======================================================== */ -#define IOSLAVE_FIFOCFG_ROBASE_Pos (24UL) /*!< IOSLAVE FIFOCFG: ROBASE (Bit 24) */ -#define IOSLAVE_FIFOCFG_ROBASE_Msk (0x3f000000UL) /*!< IOSLAVE FIFOCFG: ROBASE (Bitfield-Mask: 0x3f) */ -#define IOSLAVE_FIFOCFG_FIFOMAX_Pos (8UL) /*!< IOSLAVE FIFOCFG: FIFOMAX (Bit 8) */ -#define IOSLAVE_FIFOCFG_FIFOMAX_Msk (0x3f00UL) /*!< IOSLAVE FIFOCFG: FIFOMAX (Bitfield-Mask: 0x3f) */ -#define IOSLAVE_FIFOCFG_FIFOBASE_Pos (0UL) /*!< IOSLAVE FIFOCFG: FIFOBASE (Bit 0) */ -#define IOSLAVE_FIFOCFG_FIFOBASE_Msk (0x1fUL) /*!< IOSLAVE FIFOCFG: FIFOBASE (Bitfield-Mask: 0x1f) */ -/* ======================================================== FIFOTHR ======================================================== */ -#define IOSLAVE_FIFOTHR_FIFOTHR_Pos (0UL) /*!< IOSLAVE FIFOTHR: FIFOTHR (Bit 0) */ -#define IOSLAVE_FIFOTHR_FIFOTHR_Msk (0xffUL) /*!< IOSLAVE FIFOTHR: FIFOTHR (Bitfield-Mask: 0xff) */ -/* ========================================================= FUPD ========================================================== */ -#define IOSLAVE_FUPD_IOREAD_Pos (1UL) /*!< IOSLAVE FUPD: IOREAD (Bit 1) */ -#define IOSLAVE_FUPD_IOREAD_Msk (0x2UL) /*!< IOSLAVE FUPD: IOREAD (Bitfield-Mask: 0x01) */ -#define IOSLAVE_FUPD_FIFOUPD_Pos (0UL) /*!< IOSLAVE FUPD: FIFOUPD (Bit 0) */ -#define IOSLAVE_FUPD_FIFOUPD_Msk (0x1UL) /*!< IOSLAVE FUPD: FIFOUPD (Bitfield-Mask: 0x01) */ -/* ======================================================== FIFOCTR ======================================================== */ -#define IOSLAVE_FIFOCTR_FIFOCTR_Pos (0UL) /*!< IOSLAVE FIFOCTR: FIFOCTR (Bit 0) */ -#define IOSLAVE_FIFOCTR_FIFOCTR_Msk (0x3ffUL) /*!< IOSLAVE FIFOCTR: FIFOCTR (Bitfield-Mask: 0x3ff) */ -/* ======================================================== FIFOINC ======================================================== */ -#define IOSLAVE_FIFOINC_FIFOINC_Pos (0UL) /*!< IOSLAVE FIFOINC: FIFOINC (Bit 0) */ -#define IOSLAVE_FIFOINC_FIFOINC_Msk (0x3ffUL) /*!< IOSLAVE FIFOINC: FIFOINC (Bitfield-Mask: 0x3ff) */ -/* ========================================================== CFG ========================================================== */ -#define IOSLAVE_CFG_IFCEN_Pos (31UL) /*!< IOSLAVE CFG: IFCEN (Bit 31) */ -#define IOSLAVE_CFG_IFCEN_Msk (0x80000000UL) /*!< IOSLAVE CFG: IFCEN (Bitfield-Mask: 0x01) */ -#define IOSLAVE_CFG_I2CADDR_Pos (8UL) /*!< IOSLAVE CFG: I2CADDR (Bit 8) */ -#define IOSLAVE_CFG_I2CADDR_Msk (0xfff00UL) /*!< IOSLAVE CFG: I2CADDR (Bitfield-Mask: 0xfff) */ -#define IOSLAVE_CFG_STARTRD_Pos (4UL) /*!< IOSLAVE CFG: STARTRD (Bit 4) */ -#define IOSLAVE_CFG_STARTRD_Msk (0x10UL) /*!< IOSLAVE CFG: STARTRD (Bitfield-Mask: 0x01) */ -#define IOSLAVE_CFG_LSB_Pos (2UL) /*!< IOSLAVE CFG: LSB (Bit 2) */ -#define IOSLAVE_CFG_LSB_Msk (0x4UL) /*!< IOSLAVE CFG: LSB (Bitfield-Mask: 0x01) */ -#define IOSLAVE_CFG_SPOL_Pos (1UL) /*!< IOSLAVE CFG: SPOL (Bit 1) */ -#define IOSLAVE_CFG_SPOL_Msk (0x2UL) /*!< IOSLAVE CFG: SPOL (Bitfield-Mask: 0x01) */ -#define IOSLAVE_CFG_IFCSEL_Pos (0UL) /*!< IOSLAVE CFG: IFCSEL (Bit 0) */ -#define IOSLAVE_CFG_IFCSEL_Msk (0x1UL) /*!< IOSLAVE CFG: IFCSEL (Bitfield-Mask: 0x01) */ -/* ========================================================= PRENC ========================================================= */ -#define IOSLAVE_PRENC_PRENC_Pos (0UL) /*!< IOSLAVE PRENC: PRENC (Bit 0) */ -#define IOSLAVE_PRENC_PRENC_Msk (0x1fUL) /*!< IOSLAVE PRENC: PRENC (Bitfield-Mask: 0x1f) */ -/* ======================================================= IOINTCTL ======================================================== */ -#define IOSLAVE_IOINTCTL_IOINTSET_Pos (24UL) /*!< IOSLAVE IOINTCTL: IOINTSET (Bit 24) */ -#define IOSLAVE_IOINTCTL_IOINTSET_Msk (0xff000000UL) /*!< IOSLAVE IOINTCTL: IOINTSET (Bitfield-Mask: 0xff) */ -#define IOSLAVE_IOINTCTL_IOINTCLR_Pos (16UL) /*!< IOSLAVE IOINTCTL: IOINTCLR (Bit 16) */ -#define IOSLAVE_IOINTCTL_IOINTCLR_Msk (0x10000UL) /*!< IOSLAVE IOINTCTL: IOINTCLR (Bitfield-Mask: 0x01) */ -#define IOSLAVE_IOINTCTL_IOINT_Pos (8UL) /*!< IOSLAVE IOINTCTL: IOINT (Bit 8) */ -#define IOSLAVE_IOINTCTL_IOINT_Msk (0xff00UL) /*!< IOSLAVE IOINTCTL: IOINT (Bitfield-Mask: 0xff) */ -#define IOSLAVE_IOINTCTL_IOINTEN_Pos (0UL) /*!< IOSLAVE IOINTCTL: IOINTEN (Bit 0) */ -#define IOSLAVE_IOINTCTL_IOINTEN_Msk (0xffUL) /*!< IOSLAVE IOINTCTL: IOINTEN (Bitfield-Mask: 0xff) */ -/* ======================================================== GENADD ========================================================= */ -#define IOSLAVE_GENADD_GADATA_Pos (0UL) /*!< IOSLAVE GENADD: GADATA (Bit 0) */ -#define IOSLAVE_GENADD_GADATA_Msk (0xffUL) /*!< IOSLAVE GENADD: GADATA (Bitfield-Mask: 0xff) */ -/* ========================================================= INTEN ========================================================= */ -#define IOSLAVE_INTEN_XCMPWR_Pos (9UL) /*!< IOSLAVE INTEN: XCMPWR (Bit 9) */ -#define IOSLAVE_INTEN_XCMPWR_Msk (0x200UL) /*!< IOSLAVE INTEN: XCMPWR (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTEN_XCMPWF_Pos (8UL) /*!< IOSLAVE INTEN: XCMPWF (Bit 8) */ -#define IOSLAVE_INTEN_XCMPWF_Msk (0x100UL) /*!< IOSLAVE INTEN: XCMPWF (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTEN_XCMPRR_Pos (7UL) /*!< IOSLAVE INTEN: XCMPRR (Bit 7) */ -#define IOSLAVE_INTEN_XCMPRR_Msk (0x80UL) /*!< IOSLAVE INTEN: XCMPRR (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTEN_XCMPRF_Pos (6UL) /*!< IOSLAVE INTEN: XCMPRF (Bit 6) */ -#define IOSLAVE_INTEN_XCMPRF_Msk (0x40UL) /*!< IOSLAVE INTEN: XCMPRF (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTEN_IOINTW_Pos (5UL) /*!< IOSLAVE INTEN: IOINTW (Bit 5) */ -#define IOSLAVE_INTEN_IOINTW_Msk (0x20UL) /*!< IOSLAVE INTEN: IOINTW (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTEN_GENAD_Pos (4UL) /*!< IOSLAVE INTEN: GENAD (Bit 4) */ -#define IOSLAVE_INTEN_GENAD_Msk (0x10UL) /*!< IOSLAVE INTEN: GENAD (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTEN_FRDERR_Pos (3UL) /*!< IOSLAVE INTEN: FRDERR (Bit 3) */ -#define IOSLAVE_INTEN_FRDERR_Msk (0x8UL) /*!< IOSLAVE INTEN: FRDERR (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTEN_FUNDFL_Pos (2UL) /*!< IOSLAVE INTEN: FUNDFL (Bit 2) */ -#define IOSLAVE_INTEN_FUNDFL_Msk (0x4UL) /*!< IOSLAVE INTEN: FUNDFL (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTEN_FOVFL_Pos (1UL) /*!< IOSLAVE INTEN: FOVFL (Bit 1) */ -#define IOSLAVE_INTEN_FOVFL_Msk (0x2UL) /*!< IOSLAVE INTEN: FOVFL (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTEN_FSIZE_Pos (0UL) /*!< IOSLAVE INTEN: FSIZE (Bit 0) */ -#define IOSLAVE_INTEN_FSIZE_Msk (0x1UL) /*!< IOSLAVE INTEN: FSIZE (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTAT ======================================================== */ -#define IOSLAVE_INTSTAT_XCMPWR_Pos (9UL) /*!< IOSLAVE INTSTAT: XCMPWR (Bit 9) */ -#define IOSLAVE_INTSTAT_XCMPWR_Msk (0x200UL) /*!< IOSLAVE INTSTAT: XCMPWR (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSTAT_XCMPWF_Pos (8UL) /*!< IOSLAVE INTSTAT: XCMPWF (Bit 8) */ -#define IOSLAVE_INTSTAT_XCMPWF_Msk (0x100UL) /*!< IOSLAVE INTSTAT: XCMPWF (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSTAT_XCMPRR_Pos (7UL) /*!< IOSLAVE INTSTAT: XCMPRR (Bit 7) */ -#define IOSLAVE_INTSTAT_XCMPRR_Msk (0x80UL) /*!< IOSLAVE INTSTAT: XCMPRR (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSTAT_XCMPRF_Pos (6UL) /*!< IOSLAVE INTSTAT: XCMPRF (Bit 6) */ -#define IOSLAVE_INTSTAT_XCMPRF_Msk (0x40UL) /*!< IOSLAVE INTSTAT: XCMPRF (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSTAT_IOINTW_Pos (5UL) /*!< IOSLAVE INTSTAT: IOINTW (Bit 5) */ -#define IOSLAVE_INTSTAT_IOINTW_Msk (0x20UL) /*!< IOSLAVE INTSTAT: IOINTW (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSTAT_GENAD_Pos (4UL) /*!< IOSLAVE INTSTAT: GENAD (Bit 4) */ -#define IOSLAVE_INTSTAT_GENAD_Msk (0x10UL) /*!< IOSLAVE INTSTAT: GENAD (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSTAT_FRDERR_Pos (3UL) /*!< IOSLAVE INTSTAT: FRDERR (Bit 3) */ -#define IOSLAVE_INTSTAT_FRDERR_Msk (0x8UL) /*!< IOSLAVE INTSTAT: FRDERR (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSTAT_FUNDFL_Pos (2UL) /*!< IOSLAVE INTSTAT: FUNDFL (Bit 2) */ -#define IOSLAVE_INTSTAT_FUNDFL_Msk (0x4UL) /*!< IOSLAVE INTSTAT: FUNDFL (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSTAT_FOVFL_Pos (1UL) /*!< IOSLAVE INTSTAT: FOVFL (Bit 1) */ -#define IOSLAVE_INTSTAT_FOVFL_Msk (0x2UL) /*!< IOSLAVE INTSTAT: FOVFL (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSTAT_FSIZE_Pos (0UL) /*!< IOSLAVE INTSTAT: FSIZE (Bit 0) */ -#define IOSLAVE_INTSTAT_FSIZE_Msk (0x1UL) /*!< IOSLAVE INTSTAT: FSIZE (Bitfield-Mask: 0x01) */ -/* ======================================================== INTCLR ========================================================= */ -#define IOSLAVE_INTCLR_XCMPWR_Pos (9UL) /*!< IOSLAVE INTCLR: XCMPWR (Bit 9) */ -#define IOSLAVE_INTCLR_XCMPWR_Msk (0x200UL) /*!< IOSLAVE INTCLR: XCMPWR (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTCLR_XCMPWF_Pos (8UL) /*!< IOSLAVE INTCLR: XCMPWF (Bit 8) */ -#define IOSLAVE_INTCLR_XCMPWF_Msk (0x100UL) /*!< IOSLAVE INTCLR: XCMPWF (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTCLR_XCMPRR_Pos (7UL) /*!< IOSLAVE INTCLR: XCMPRR (Bit 7) */ -#define IOSLAVE_INTCLR_XCMPRR_Msk (0x80UL) /*!< IOSLAVE INTCLR: XCMPRR (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTCLR_XCMPRF_Pos (6UL) /*!< IOSLAVE INTCLR: XCMPRF (Bit 6) */ -#define IOSLAVE_INTCLR_XCMPRF_Msk (0x40UL) /*!< IOSLAVE INTCLR: XCMPRF (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTCLR_IOINTW_Pos (5UL) /*!< IOSLAVE INTCLR: IOINTW (Bit 5) */ -#define IOSLAVE_INTCLR_IOINTW_Msk (0x20UL) /*!< IOSLAVE INTCLR: IOINTW (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTCLR_GENAD_Pos (4UL) /*!< IOSLAVE INTCLR: GENAD (Bit 4) */ -#define IOSLAVE_INTCLR_GENAD_Msk (0x10UL) /*!< IOSLAVE INTCLR: GENAD (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTCLR_FRDERR_Pos (3UL) /*!< IOSLAVE INTCLR: FRDERR (Bit 3) */ -#define IOSLAVE_INTCLR_FRDERR_Msk (0x8UL) /*!< IOSLAVE INTCLR: FRDERR (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTCLR_FUNDFL_Pos (2UL) /*!< IOSLAVE INTCLR: FUNDFL (Bit 2) */ -#define IOSLAVE_INTCLR_FUNDFL_Msk (0x4UL) /*!< IOSLAVE INTCLR: FUNDFL (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTCLR_FOVFL_Pos (1UL) /*!< IOSLAVE INTCLR: FOVFL (Bit 1) */ -#define IOSLAVE_INTCLR_FOVFL_Msk (0x2UL) /*!< IOSLAVE INTCLR: FOVFL (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTCLR_FSIZE_Pos (0UL) /*!< IOSLAVE INTCLR: FSIZE (Bit 0) */ -#define IOSLAVE_INTCLR_FSIZE_Msk (0x1UL) /*!< IOSLAVE INTCLR: FSIZE (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSET ========================================================= */ -#define IOSLAVE_INTSET_XCMPWR_Pos (9UL) /*!< IOSLAVE INTSET: XCMPWR (Bit 9) */ -#define IOSLAVE_INTSET_XCMPWR_Msk (0x200UL) /*!< IOSLAVE INTSET: XCMPWR (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSET_XCMPWF_Pos (8UL) /*!< IOSLAVE INTSET: XCMPWF (Bit 8) */ -#define IOSLAVE_INTSET_XCMPWF_Msk (0x100UL) /*!< IOSLAVE INTSET: XCMPWF (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSET_XCMPRR_Pos (7UL) /*!< IOSLAVE INTSET: XCMPRR (Bit 7) */ -#define IOSLAVE_INTSET_XCMPRR_Msk (0x80UL) /*!< IOSLAVE INTSET: XCMPRR (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSET_XCMPRF_Pos (6UL) /*!< IOSLAVE INTSET: XCMPRF (Bit 6) */ -#define IOSLAVE_INTSET_XCMPRF_Msk (0x40UL) /*!< IOSLAVE INTSET: XCMPRF (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSET_IOINTW_Pos (5UL) /*!< IOSLAVE INTSET: IOINTW (Bit 5) */ -#define IOSLAVE_INTSET_IOINTW_Msk (0x20UL) /*!< IOSLAVE INTSET: IOINTW (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSET_GENAD_Pos (4UL) /*!< IOSLAVE INTSET: GENAD (Bit 4) */ -#define IOSLAVE_INTSET_GENAD_Msk (0x10UL) /*!< IOSLAVE INTSET: GENAD (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSET_FRDERR_Pos (3UL) /*!< IOSLAVE INTSET: FRDERR (Bit 3) */ -#define IOSLAVE_INTSET_FRDERR_Msk (0x8UL) /*!< IOSLAVE INTSET: FRDERR (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSET_FUNDFL_Pos (2UL) /*!< IOSLAVE INTSET: FUNDFL (Bit 2) */ -#define IOSLAVE_INTSET_FUNDFL_Msk (0x4UL) /*!< IOSLAVE INTSET: FUNDFL (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSET_FOVFL_Pos (1UL) /*!< IOSLAVE INTSET: FOVFL (Bit 1) */ -#define IOSLAVE_INTSET_FOVFL_Msk (0x2UL) /*!< IOSLAVE INTSET: FOVFL (Bitfield-Mask: 0x01) */ -#define IOSLAVE_INTSET_FSIZE_Pos (0UL) /*!< IOSLAVE INTSET: FSIZE (Bit 0) */ -#define IOSLAVE_INTSET_FSIZE_Msk (0x1UL) /*!< IOSLAVE INTSET: FSIZE (Bitfield-Mask: 0x01) */ -/* ====================================================== REGACCINTEN ====================================================== */ -#define IOSLAVE_REGACCINTEN_REGACC_Pos (0UL) /*!< IOSLAVE REGACCINTEN: REGACC (Bit 0) */ -#define IOSLAVE_REGACCINTEN_REGACC_Msk (0xffffffffUL) /*!< IOSLAVE REGACCINTEN: REGACC (Bitfield-Mask: 0xffffffff) */ -/* ===================================================== REGACCINTSTAT ===================================================== */ -#define IOSLAVE_REGACCINTSTAT_REGACC_Pos (0UL) /*!< IOSLAVE REGACCINTSTAT: REGACC (Bit 0) */ -#define IOSLAVE_REGACCINTSTAT_REGACC_Msk (0xffffffffUL) /*!< IOSLAVE REGACCINTSTAT: REGACC (Bitfield-Mask: 0xffffffff) */ -/* ===================================================== REGACCINTCLR ====================================================== */ -#define IOSLAVE_REGACCINTCLR_REGACC_Pos (0UL) /*!< IOSLAVE REGACCINTCLR: REGACC (Bit 0) */ -#define IOSLAVE_REGACCINTCLR_REGACC_Msk (0xffffffffUL) /*!< IOSLAVE REGACCINTCLR: REGACC (Bitfield-Mask: 0xffffffff) */ -/* ===================================================== REGACCINTSET ====================================================== */ -#define IOSLAVE_REGACCINTSET_REGACC_Pos (0UL) /*!< IOSLAVE REGACCINTSET: REGACC (Bit 0) */ -#define IOSLAVE_REGACCINTSET_REGACC_Msk (0xffffffffUL) /*!< IOSLAVE REGACCINTSET: REGACC (Bitfield-Mask: 0xffffffff) */ - - -/* =========================================================================================================================== */ -/* ================ MCUCTRL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CHIPPN ========================================================= */ -#define MCUCTRL_CHIPPN_PARTNUM_Pos (0UL) /*!< MCUCTRL CHIPPN: PARTNUM (Bit 0) */ -#define MCUCTRL_CHIPPN_PARTNUM_Msk (0xffffffffUL) /*!< MCUCTRL CHIPPN: PARTNUM (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== CHIPID0 ======================================================== */ -#define MCUCTRL_CHIPID0_CHIPID0_Pos (0UL) /*!< MCUCTRL CHIPID0: CHIPID0 (Bit 0) */ -#define MCUCTRL_CHIPID0_CHIPID0_Msk (0xffffffffUL) /*!< MCUCTRL CHIPID0: CHIPID0 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== CHIPID1 ======================================================== */ -#define MCUCTRL_CHIPID1_CHIPID1_Pos (0UL) /*!< MCUCTRL CHIPID1: CHIPID1 (Bit 0) */ -#define MCUCTRL_CHIPID1_CHIPID1_Msk (0xffffffffUL) /*!< MCUCTRL CHIPID1: CHIPID1 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== CHIPREV ======================================================== */ -#define MCUCTRL_CHIPREV_SIPART_Pos (8UL) /*!< MCUCTRL CHIPREV: SIPART (Bit 8) */ -#define MCUCTRL_CHIPREV_SIPART_Msk (0xfff00UL) /*!< MCUCTRL CHIPREV: SIPART (Bitfield-Mask: 0xfff) */ -#define MCUCTRL_CHIPREV_REVMAJ_Pos (4UL) /*!< MCUCTRL CHIPREV: REVMAJ (Bit 4) */ -#define MCUCTRL_CHIPREV_REVMAJ_Msk (0xf0UL) /*!< MCUCTRL CHIPREV: REVMAJ (Bitfield-Mask: 0x0f) */ -#define MCUCTRL_CHIPREV_REVMIN_Pos (0UL) /*!< MCUCTRL CHIPREV: REVMIN (Bit 0) */ -#define MCUCTRL_CHIPREV_REVMIN_Msk (0xfUL) /*!< MCUCTRL CHIPREV: REVMIN (Bitfield-Mask: 0x0f) */ -/* ======================================================= VENDORID ======================================================== */ -#define MCUCTRL_VENDORID_VENDORID_Pos (0UL) /*!< MCUCTRL VENDORID: VENDORID (Bit 0) */ -#define MCUCTRL_VENDORID_VENDORID_Msk (0xffffffffUL) /*!< MCUCTRL VENDORID: VENDORID (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== SKU ========================================================== */ -#define MCUCTRL_SKU_SECBOOT_Pos (2UL) /*!< MCUCTRL SKU: SECBOOT (Bit 2) */ -#define MCUCTRL_SKU_SECBOOT_Msk (0x4UL) /*!< MCUCTRL SKU: SECBOOT (Bitfield-Mask: 0x01) */ -#define MCUCTRL_SKU_ALLOWBLE_Pos (1UL) /*!< MCUCTRL SKU: ALLOWBLE (Bit 1) */ -#define MCUCTRL_SKU_ALLOWBLE_Msk (0x2UL) /*!< MCUCTRL SKU: ALLOWBLE (Bitfield-Mask: 0x01) */ -#define MCUCTRL_SKU_ALLOWBURST_Pos (0UL) /*!< MCUCTRL SKU: ALLOWBURST (Bit 0) */ -#define MCUCTRL_SKU_ALLOWBURST_Msk (0x1UL) /*!< MCUCTRL SKU: ALLOWBURST (Bitfield-Mask: 0x01) */ -/* ===================================================== FEATUREENABLE ===================================================== */ -#define MCUCTRL_FEATUREENABLE_BURSTAVAIL_Pos (6UL) /*!< MCUCTRL FEATUREENABLE: BURSTAVAIL (Bit 6) */ -#define MCUCTRL_FEATUREENABLE_BURSTAVAIL_Msk (0x40UL) /*!< MCUCTRL FEATUREENABLE: BURSTAVAIL (Bitfield-Mask: 0x01) */ -#define MCUCTRL_FEATUREENABLE_BURSTACK_Pos (5UL) /*!< MCUCTRL FEATUREENABLE: BURSTACK (Bit 5) */ -#define MCUCTRL_FEATUREENABLE_BURSTACK_Msk (0x20UL) /*!< MCUCTRL FEATUREENABLE: BURSTACK (Bitfield-Mask: 0x01) */ -#define MCUCTRL_FEATUREENABLE_BURSTREQ_Pos (4UL) /*!< MCUCTRL FEATUREENABLE: BURSTREQ (Bit 4) */ -#define MCUCTRL_FEATUREENABLE_BURSTREQ_Msk (0x10UL) /*!< MCUCTRL FEATUREENABLE: BURSTREQ (Bitfield-Mask: 0x01) */ -#define MCUCTRL_FEATUREENABLE_BLEAVAIL_Pos (2UL) /*!< MCUCTRL FEATUREENABLE: BLEAVAIL (Bit 2) */ -#define MCUCTRL_FEATUREENABLE_BLEAVAIL_Msk (0x4UL) /*!< MCUCTRL FEATUREENABLE: BLEAVAIL (Bitfield-Mask: 0x01) */ -#define MCUCTRL_FEATUREENABLE_BLEACK_Pos (1UL) /*!< MCUCTRL FEATUREENABLE: BLEACK (Bit 1) */ -#define MCUCTRL_FEATUREENABLE_BLEACK_Msk (0x2UL) /*!< MCUCTRL FEATUREENABLE: BLEACK (Bitfield-Mask: 0x01) */ -#define MCUCTRL_FEATUREENABLE_BLEREQ_Pos (0UL) /*!< MCUCTRL FEATUREENABLE: BLEREQ (Bit 0) */ -#define MCUCTRL_FEATUREENABLE_BLEREQ_Msk (0x1UL) /*!< MCUCTRL FEATUREENABLE: BLEREQ (Bitfield-Mask: 0x01) */ -/* ======================================================= DEBUGGER ======================================================== */ -#define MCUCTRL_DEBUGGER_LOCKOUT_Pos (0UL) /*!< MCUCTRL DEBUGGER: LOCKOUT (Bit 0) */ -#define MCUCTRL_DEBUGGER_LOCKOUT_Msk (0x1UL) /*!< MCUCTRL DEBUGGER: LOCKOUT (Bitfield-Mask: 0x01) */ -/* ================================================= DMASRAMWRITEPROTECT2 ================================================== */ -#define MCUCTRL_DMASRAMWRITEPROTECT2_DMA_WPROT2_Pos (0UL) /*!< MCUCTRL DMASRAMWRITEPROTECT2: DMA_WPROT2 (Bit 0) */ -#define MCUCTRL_DMASRAMWRITEPROTECT2_DMA_WPROT2_Msk (0xffffffffUL) /*!< MCUCTRL DMASRAMWRITEPROTECT2: DMA_WPROT2 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== BODCTRL ======================================================== */ -#define MCUCTRL_BODCTRL_BODHVREFSEL_Pos (5UL) /*!< MCUCTRL BODCTRL: BODHVREFSEL (Bit 5) */ -#define MCUCTRL_BODCTRL_BODHVREFSEL_Msk (0x20UL) /*!< MCUCTRL BODCTRL: BODHVREFSEL (Bitfield-Mask: 0x01) */ -#define MCUCTRL_BODCTRL_BODLVREFSEL_Pos (4UL) /*!< MCUCTRL BODCTRL: BODLVREFSEL (Bit 4) */ -#define MCUCTRL_BODCTRL_BODLVREFSEL_Msk (0x10UL) /*!< MCUCTRL BODCTRL: BODLVREFSEL (Bitfield-Mask: 0x01) */ -#define MCUCTRL_BODCTRL_BODFPWD_Pos (3UL) /*!< MCUCTRL BODCTRL: BODFPWD (Bit 3) */ -#define MCUCTRL_BODCTRL_BODFPWD_Msk (0x8UL) /*!< MCUCTRL BODCTRL: BODFPWD (Bitfield-Mask: 0x01) */ -#define MCUCTRL_BODCTRL_BODCPWD_Pos (2UL) /*!< MCUCTRL BODCTRL: BODCPWD (Bit 2) */ -#define MCUCTRL_BODCTRL_BODCPWD_Msk (0x4UL) /*!< MCUCTRL BODCTRL: BODCPWD (Bitfield-Mask: 0x01) */ -#define MCUCTRL_BODCTRL_BODHPWD_Pos (1UL) /*!< MCUCTRL BODCTRL: BODHPWD (Bit 1) */ -#define MCUCTRL_BODCTRL_BODHPWD_Msk (0x2UL) /*!< MCUCTRL BODCTRL: BODHPWD (Bitfield-Mask: 0x01) */ -#define MCUCTRL_BODCTRL_BODLPWD_Pos (0UL) /*!< MCUCTRL BODCTRL: BODLPWD (Bit 0) */ -#define MCUCTRL_BODCTRL_BODLPWD_Msk (0x1UL) /*!< MCUCTRL BODCTRL: BODLPWD (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCPWRDLY ======================================================= */ -#define MCUCTRL_ADCPWRDLY_ADCPWR1_Pos (8UL) /*!< MCUCTRL ADCPWRDLY: ADCPWR1 (Bit 8) */ -#define MCUCTRL_ADCPWRDLY_ADCPWR1_Msk (0xff00UL) /*!< MCUCTRL ADCPWRDLY: ADCPWR1 (Bitfield-Mask: 0xff) */ -#define MCUCTRL_ADCPWRDLY_ADCPWR0_Pos (0UL) /*!< MCUCTRL ADCPWRDLY: ADCPWR0 (Bit 0) */ -#define MCUCTRL_ADCPWRDLY_ADCPWR0_Msk (0xffUL) /*!< MCUCTRL ADCPWRDLY: ADCPWR0 (Bitfield-Mask: 0xff) */ -/* ======================================================== ADCCAL ========================================================= */ -#define MCUCTRL_ADCCAL_ADCCALIBRATED_Pos (1UL) /*!< MCUCTRL ADCCAL: ADCCALIBRATED (Bit 1) */ -#define MCUCTRL_ADCCAL_ADCCALIBRATED_Msk (0x2UL) /*!< MCUCTRL ADCCAL: ADCCALIBRATED (Bitfield-Mask: 0x01) */ -#define MCUCTRL_ADCCAL_CALONPWRUP_Pos (0UL) /*!< MCUCTRL ADCCAL: CALONPWRUP (Bit 0) */ -#define MCUCTRL_ADCCAL_CALONPWRUP_Msk (0x1UL) /*!< MCUCTRL ADCCAL: CALONPWRUP (Bitfield-Mask: 0x01) */ -/* ====================================================== ADCBATTLOAD ====================================================== */ -#define MCUCTRL_ADCBATTLOAD_BATTLOAD_Pos (0UL) /*!< MCUCTRL ADCBATTLOAD: BATTLOAD (Bit 0) */ -#define MCUCTRL_ADCBATTLOAD_BATTLOAD_Msk (0x1UL) /*!< MCUCTRL ADCBATTLOAD: BATTLOAD (Bitfield-Mask: 0x01) */ -/* ======================================================== ADCTRIM ======================================================== */ -#define MCUCTRL_ADCTRIM_ADCRFBUFIBTRIM_Pos (11UL) /*!< MCUCTRL ADCTRIM: ADCRFBUFIBTRIM (Bit 11) */ -#define MCUCTRL_ADCTRIM_ADCRFBUFIBTRIM_Msk (0x1800UL) /*!< MCUCTRL ADCTRIM: ADCRFBUFIBTRIM (Bitfield-Mask: 0x03) */ -#define MCUCTRL_ADCTRIM_ADCREFBUFTRIM_Pos (6UL) /*!< MCUCTRL ADCTRIM: ADCREFBUFTRIM (Bit 6) */ -#define MCUCTRL_ADCTRIM_ADCREFBUFTRIM_Msk (0x7c0UL) /*!< MCUCTRL ADCTRIM: ADCREFBUFTRIM (Bitfield-Mask: 0x1f) */ -#define MCUCTRL_ADCTRIM_ADCREFKEEPIBTRIM_Pos (0UL) /*!< MCUCTRL ADCTRIM: ADCREFKEEPIBTRIM (Bit 0) */ -#define MCUCTRL_ADCTRIM_ADCREFKEEPIBTRIM_Msk (0x3UL) /*!< MCUCTRL ADCTRIM: ADCREFKEEPIBTRIM (Bitfield-Mask: 0x03) */ -/* ====================================================== ADCREFCOMP ======================================================= */ -#define MCUCTRL_ADCREFCOMP_ADCRFCMPEN_Pos (16UL) /*!< MCUCTRL ADCREFCOMP: ADCRFCMPEN (Bit 16) */ -#define MCUCTRL_ADCREFCOMP_ADCRFCMPEN_Msk (0x10000UL) /*!< MCUCTRL ADCREFCOMP: ADCRFCMPEN (Bitfield-Mask: 0x01) */ -#define MCUCTRL_ADCREFCOMP_ADCREFKEEPTRIM_Pos (8UL) /*!< MCUCTRL ADCREFCOMP: ADCREFKEEPTRIM (Bit 8) */ -#define MCUCTRL_ADCREFCOMP_ADCREFKEEPTRIM_Msk (0x1f00UL) /*!< MCUCTRL ADCREFCOMP: ADCREFKEEPTRIM (Bitfield-Mask: 0x1f) */ -#define MCUCTRL_ADCREFCOMP_ADC_REFCOMP_OUT_Pos (0UL) /*!< MCUCTRL ADCREFCOMP: ADC_REFCOMP_OUT (Bit 0) */ -#define MCUCTRL_ADCREFCOMP_ADC_REFCOMP_OUT_Msk (0x1UL) /*!< MCUCTRL ADCREFCOMP: ADC_REFCOMP_OUT (Bitfield-Mask: 0x01) */ -/* ======================================================= XTALCTRL ======================================================== */ -#define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Pos (8UL) /*!< MCUCTRL XTALCTRL: XTALICOMPTRIM (Bit 8) */ -#define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Msk (0x300UL) /*!< MCUCTRL XTALCTRL: XTALICOMPTRIM (Bitfield-Mask: 0x03) */ -#define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Pos (6UL) /*!< MCUCTRL XTALCTRL: XTALIBUFTRIM (Bit 6) */ -#define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Msk (0xc0UL) /*!< MCUCTRL XTALCTRL: XTALIBUFTRIM (Bitfield-Mask: 0x03) */ -#define MCUCTRL_XTALCTRL_PWDBODXTAL_Pos (5UL) /*!< MCUCTRL XTALCTRL: PWDBODXTAL (Bit 5) */ -#define MCUCTRL_XTALCTRL_PWDBODXTAL_Msk (0x20UL) /*!< MCUCTRL XTALCTRL: PWDBODXTAL (Bitfield-Mask: 0x01) */ -#define MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Pos (4UL) /*!< MCUCTRL XTALCTRL: PDNBCMPRXTAL (Bit 4) */ -#define MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Msk (0x10UL) /*!< MCUCTRL XTALCTRL: PDNBCMPRXTAL (Bitfield-Mask: 0x01) */ -#define MCUCTRL_XTALCTRL_PDNBCOREXTAL_Pos (3UL) /*!< MCUCTRL XTALCTRL: PDNBCOREXTAL (Bit 3) */ -#define MCUCTRL_XTALCTRL_PDNBCOREXTAL_Msk (0x8UL) /*!< MCUCTRL XTALCTRL: PDNBCOREXTAL (Bitfield-Mask: 0x01) */ -#define MCUCTRL_XTALCTRL_BYPCMPRXTAL_Pos (2UL) /*!< MCUCTRL XTALCTRL: BYPCMPRXTAL (Bit 2) */ -#define MCUCTRL_XTALCTRL_BYPCMPRXTAL_Msk (0x4UL) /*!< MCUCTRL XTALCTRL: BYPCMPRXTAL (Bitfield-Mask: 0x01) */ -#define MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Pos (1UL) /*!< MCUCTRL XTALCTRL: FDBKDSBLXTAL (Bit 1) */ -#define MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Msk (0x2UL) /*!< MCUCTRL XTALCTRL: FDBKDSBLXTAL (Bitfield-Mask: 0x01) */ -#define MCUCTRL_XTALCTRL_XTALSWE_Pos (0UL) /*!< MCUCTRL XTALCTRL: XTALSWE (Bit 0) */ -#define MCUCTRL_XTALCTRL_XTALSWE_Msk (0x1UL) /*!< MCUCTRL XTALCTRL: XTALSWE (Bitfield-Mask: 0x01) */ -/* ====================================================== XTALGENCTRL ====================================================== */ -#define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Pos (8UL) /*!< MCUCTRL XTALGENCTRL: XTALKSBIASTRIM (Bit 8) */ -#define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Msk (0x3f00UL) /*!< MCUCTRL XTALGENCTRL: XTALKSBIASTRIM (Bitfield-Mask: 0x3f) */ -#define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Pos (2UL) /*!< MCUCTRL XTALGENCTRL: XTALBIASTRIM (Bit 2) */ -#define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Msk (0xfcUL) /*!< MCUCTRL XTALGENCTRL: XTALBIASTRIM (Bitfield-Mask: 0x3f) */ -#define MCUCTRL_XTALGENCTRL_ACWARMUP_Pos (0UL) /*!< MCUCTRL XTALGENCTRL: ACWARMUP (Bit 0) */ -#define MCUCTRL_XTALGENCTRL_ACWARMUP_Msk (0x3UL) /*!< MCUCTRL XTALGENCTRL: ACWARMUP (Bitfield-Mask: 0x03) */ -/* ======================================================= MISCCTRL ======================================================== */ -#define MCUCTRL_MISCCTRL_BLE_RESETN_Pos (5UL) /*!< MCUCTRL MISCCTRL: BLE_RESETN (Bit 5) */ -#define MCUCTRL_MISCCTRL_BLE_RESETN_Msk (0x20UL) /*!< MCUCTRL MISCCTRL: BLE_RESETN (Bitfield-Mask: 0x01) */ -#define MCUCTRL_MISCCTRL_RESERVED_RW_0_Pos (0UL) /*!< MCUCTRL MISCCTRL: RESERVED_RW_0 (Bit 0) */ -#define MCUCTRL_MISCCTRL_RESERVED_RW_0_Msk (0x1fUL) /*!< MCUCTRL MISCCTRL: RESERVED_RW_0 (Bitfield-Mask: 0x1f) */ -/* ====================================================== BOOTLOADER ======================================================= */ -#define MCUCTRL_BOOTLOADER_SECBOOTONRST_Pos (30UL) /*!< MCUCTRL BOOTLOADER: SECBOOTONRST (Bit 30) */ -#define MCUCTRL_BOOTLOADER_SECBOOTONRST_Msk (0xc0000000UL) /*!< MCUCTRL BOOTLOADER: SECBOOTONRST (Bitfield-Mask: 0x03) */ -#define MCUCTRL_BOOTLOADER_SECBOOT_Pos (28UL) /*!< MCUCTRL BOOTLOADER: SECBOOT (Bit 28) */ -#define MCUCTRL_BOOTLOADER_SECBOOT_Msk (0x30000000UL) /*!< MCUCTRL BOOTLOADER: SECBOOT (Bitfield-Mask: 0x03) */ -#define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Pos (26UL) /*!< MCUCTRL BOOTLOADER: SECBOOTFEATURE (Bit 26) */ -#define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Msk (0xc000000UL) /*!< MCUCTRL BOOTLOADER: SECBOOTFEATURE (Bitfield-Mask: 0x03) */ -#define MCUCTRL_BOOTLOADER_PROTLOCK_Pos (2UL) /*!< MCUCTRL BOOTLOADER: PROTLOCK (Bit 2) */ -#define MCUCTRL_BOOTLOADER_PROTLOCK_Msk (0x4UL) /*!< MCUCTRL BOOTLOADER: PROTLOCK (Bitfield-Mask: 0x01) */ -#define MCUCTRL_BOOTLOADER_SBLOCK_Pos (1UL) /*!< MCUCTRL BOOTLOADER: SBLOCK (Bit 1) */ -#define MCUCTRL_BOOTLOADER_SBLOCK_Msk (0x2UL) /*!< MCUCTRL BOOTLOADER: SBLOCK (Bitfield-Mask: 0x01) */ -#define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Pos (0UL) /*!< MCUCTRL BOOTLOADER: BOOTLOADERLOW (Bit 0) */ -#define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Msk (0x1UL) /*!< MCUCTRL BOOTLOADER: BOOTLOADERLOW (Bitfield-Mask: 0x01) */ -/* ====================================================== SHADOWVALID ====================================================== */ -#define MCUCTRL_SHADOWVALID_INFO0_VALID_Pos (2UL) /*!< MCUCTRL SHADOWVALID: INFO0_VALID (Bit 2) */ -#define MCUCTRL_SHADOWVALID_INFO0_VALID_Msk (0x4UL) /*!< MCUCTRL SHADOWVALID: INFO0_VALID (Bitfield-Mask: 0x01) */ -#define MCUCTRL_SHADOWVALID_BLDSLEEP_Pos (1UL) /*!< MCUCTRL SHADOWVALID: BLDSLEEP (Bit 1) */ -#define MCUCTRL_SHADOWVALID_BLDSLEEP_Msk (0x2UL) /*!< MCUCTRL SHADOWVALID: BLDSLEEP (Bitfield-Mask: 0x01) */ -#define MCUCTRL_SHADOWVALID_VALID_Pos (0UL) /*!< MCUCTRL SHADOWVALID: VALID (Bit 0) */ -#define MCUCTRL_SHADOWVALID_VALID_Msk (0x1UL) /*!< MCUCTRL SHADOWVALID: VALID (Bitfield-Mask: 0x01) */ -/* ======================================================= SCRATCH0 ======================================================== */ -#define MCUCTRL_SCRATCH0_SCRATCH0_Pos (0UL) /*!< MCUCTRL SCRATCH0: SCRATCH0 (Bit 0) */ -#define MCUCTRL_SCRATCH0_SCRATCH0_Msk (0xffffffffUL) /*!< MCUCTRL SCRATCH0: SCRATCH0 (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SCRATCH1 ======================================================== */ -#define MCUCTRL_SCRATCH1_SCRATCH1_Pos (0UL) /*!< MCUCTRL SCRATCH1: SCRATCH1 (Bit 0) */ -#define MCUCTRL_SCRATCH1_SCRATCH1_Msk (0xffffffffUL) /*!< MCUCTRL SCRATCH1: SCRATCH1 (Bitfield-Mask: 0xffffffff) */ -/* ==================================================== ICODEFAULTADDR ===================================================== */ -#define MCUCTRL_ICODEFAULTADDR_ICODEFAULTADDR_Pos (0UL) /*!< MCUCTRL ICODEFAULTADDR: ICODEFAULTADDR (Bit 0) */ -#define MCUCTRL_ICODEFAULTADDR_ICODEFAULTADDR_Msk (0xffffffffUL) /*!< MCUCTRL ICODEFAULTADDR: ICODEFAULTADDR (Bitfield-Mask: 0xffffffff) */ -/* ==================================================== DCODEFAULTADDR ===================================================== */ -#define MCUCTRL_DCODEFAULTADDR_DCODEFAULTADDR_Pos (0UL) /*!< MCUCTRL DCODEFAULTADDR: DCODEFAULTADDR (Bit 0) */ -#define MCUCTRL_DCODEFAULTADDR_DCODEFAULTADDR_Msk (0xffffffffUL) /*!< MCUCTRL DCODEFAULTADDR: DCODEFAULTADDR (Bitfield-Mask: 0xffffffff) */ -/* ===================================================== SYSFAULTADDR ====================================================== */ -#define MCUCTRL_SYSFAULTADDR_SYSFAULTADDR_Pos (0UL) /*!< MCUCTRL SYSFAULTADDR: SYSFAULTADDR (Bit 0) */ -#define MCUCTRL_SYSFAULTADDR_SYSFAULTADDR_Msk (0xffffffffUL) /*!< MCUCTRL SYSFAULTADDR: SYSFAULTADDR (Bitfield-Mask: 0xffffffff) */ -/* ====================================================== FAULTSTATUS ====================================================== */ -#define MCUCTRL_FAULTSTATUS_SYSFAULT_Pos (2UL) /*!< MCUCTRL FAULTSTATUS: SYSFAULT (Bit 2) */ -#define MCUCTRL_FAULTSTATUS_SYSFAULT_Msk (0x4UL) /*!< MCUCTRL FAULTSTATUS: SYSFAULT (Bitfield-Mask: 0x01) */ -#define MCUCTRL_FAULTSTATUS_DCODEFAULT_Pos (1UL) /*!< MCUCTRL FAULTSTATUS: DCODEFAULT (Bit 1) */ -#define MCUCTRL_FAULTSTATUS_DCODEFAULT_Msk (0x2UL) /*!< MCUCTRL FAULTSTATUS: DCODEFAULT (Bitfield-Mask: 0x01) */ -#define MCUCTRL_FAULTSTATUS_ICODEFAULT_Pos (0UL) /*!< MCUCTRL FAULTSTATUS: ICODEFAULT (Bit 0) */ -#define MCUCTRL_FAULTSTATUS_ICODEFAULT_Msk (0x1UL) /*!< MCUCTRL FAULTSTATUS: ICODEFAULT (Bitfield-Mask: 0x01) */ -/* ==================================================== FAULTCAPTUREEN ===================================================== */ -#define MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Pos (0UL) /*!< MCUCTRL FAULTCAPTUREEN: FAULTCAPTUREEN (Bit 0) */ -#define MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Msk (0x1UL) /*!< MCUCTRL FAULTCAPTUREEN: FAULTCAPTUREEN (Bitfield-Mask: 0x01) */ -/* ========================================================= DBGR1 ========================================================= */ -#define MCUCTRL_DBGR1_ONETO8_Pos (0UL) /*!< MCUCTRL DBGR1: ONETO8 (Bit 0) */ -#define MCUCTRL_DBGR1_ONETO8_Msk (0xffffffffUL) /*!< MCUCTRL DBGR1: ONETO8 (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= DBGR2 ========================================================= */ -#define MCUCTRL_DBGR2_COOLCODE_Pos (0UL) /*!< MCUCTRL DBGR2: COOLCODE (Bit 0) */ -#define MCUCTRL_DBGR2_COOLCODE_Msk (0xffffffffUL) /*!< MCUCTRL DBGR2: COOLCODE (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= PMUENABLE ======================================================= */ -#define MCUCTRL_PMUENABLE_ENABLE_Pos (0UL) /*!< MCUCTRL PMUENABLE: ENABLE (Bit 0) */ -#define MCUCTRL_PMUENABLE_ENABLE_Msk (0x1UL) /*!< MCUCTRL PMUENABLE: ENABLE (Bitfield-Mask: 0x01) */ -/* ======================================================= TPIUCTRL ======================================================== */ -#define MCUCTRL_TPIUCTRL_CLKSEL_Pos (8UL) /*!< MCUCTRL TPIUCTRL: CLKSEL (Bit 8) */ -#define MCUCTRL_TPIUCTRL_CLKSEL_Msk (0x700UL) /*!< MCUCTRL TPIUCTRL: CLKSEL (Bitfield-Mask: 0x07) */ -#define MCUCTRL_TPIUCTRL_ENABLE_Pos (0UL) /*!< MCUCTRL TPIUCTRL: ENABLE (Bit 0) */ -#define MCUCTRL_TPIUCTRL_ENABLE_Msk (0x1UL) /*!< MCUCTRL TPIUCTRL: ENABLE (Bitfield-Mask: 0x01) */ -/* ====================================================== OTAPOINTER ======================================================= */ -#define MCUCTRL_OTAPOINTER_OTAPOINTER_Pos (2UL) /*!< MCUCTRL OTAPOINTER: OTAPOINTER (Bit 2) */ -#define MCUCTRL_OTAPOINTER_OTAPOINTER_Msk (0xfffffffcUL) /*!< MCUCTRL OTAPOINTER: OTAPOINTER (Bitfield-Mask: 0x3fffffff) */ -#define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Pos (1UL) /*!< MCUCTRL OTAPOINTER: OTASBLUPDATE (Bit 1) */ -#define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Msk (0x2UL) /*!< MCUCTRL OTAPOINTER: OTASBLUPDATE (Bitfield-Mask: 0x01) */ -#define MCUCTRL_OTAPOINTER_OTAVALID_Pos (0UL) /*!< MCUCTRL OTAPOINTER: OTAVALID (Bit 0) */ -#define MCUCTRL_OTAPOINTER_OTAVALID_Msk (0x1UL) /*!< MCUCTRL OTAPOINTER: OTAVALID (Bitfield-Mask: 0x01) */ -/* ====================================================== APBDMACTRL ======================================================= */ -#define MCUCTRL_APBDMACTRL_HYSTERESIS_Pos (8UL) /*!< MCUCTRL APBDMACTRL: HYSTERESIS (Bit 8) */ -#define MCUCTRL_APBDMACTRL_HYSTERESIS_Msk (0xff00UL) /*!< MCUCTRL APBDMACTRL: HYSTERESIS (Bitfield-Mask: 0xff) */ -#define MCUCTRL_APBDMACTRL_DMAOPT_Pos (2UL) /*!< MCUCTRL APBDMACTRL: DMAOPT (Bit 2) */ -#define MCUCTRL_APBDMACTRL_DMAOPT_Msk (0x4UL) /*!< MCUCTRL APBDMACTRL: DMAOPT (Bitfield-Mask: 0x01) */ -#define MCUCTRL_APBDMACTRL_DECODEABORT_Pos (1UL) /*!< MCUCTRL APBDMACTRL: DECODEABORT (Bit 1) */ -#define MCUCTRL_APBDMACTRL_DECODEABORT_Msk (0x2UL) /*!< MCUCTRL APBDMACTRL: DECODEABORT (Bitfield-Mask: 0x01) */ -#define MCUCTRL_APBDMACTRL_DMA_ENABLE_Pos (0UL) /*!< MCUCTRL APBDMACTRL: DMA_ENABLE (Bit 0) */ -#define MCUCTRL_APBDMACTRL_DMA_ENABLE_Msk (0x1UL) /*!< MCUCTRL APBDMACTRL: DMA_ENABLE (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMMODE ======================================================== */ -#define MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Pos (5UL) /*!< MCUCTRL SRAMMODE: DPREFETCH_CACHE (Bit 5) */ -#define MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk (0x20UL) /*!< MCUCTRL SRAMMODE: DPREFETCH_CACHE (Bitfield-Mask: 0x01) */ -#define MCUCTRL_SRAMMODE_DPREFETCH_Pos (4UL) /*!< MCUCTRL SRAMMODE: DPREFETCH (Bit 4) */ -#define MCUCTRL_SRAMMODE_DPREFETCH_Msk (0x10UL) /*!< MCUCTRL SRAMMODE: DPREFETCH (Bitfield-Mask: 0x01) */ -#define MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Pos (1UL) /*!< MCUCTRL SRAMMODE: IPREFETCH_CACHE (Bit 1) */ -#define MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk (0x2UL) /*!< MCUCTRL SRAMMODE: IPREFETCH_CACHE (Bitfield-Mask: 0x01) */ -#define MCUCTRL_SRAMMODE_IPREFETCH_Pos (0UL) /*!< MCUCTRL SRAMMODE: IPREFETCH (Bit 0) */ -#define MCUCTRL_SRAMMODE_IPREFETCH_Msk (0x1UL) /*!< MCUCTRL SRAMMODE: IPREFETCH (Bitfield-Mask: 0x01) */ -/* ====================================================== KEXTCLKSEL ======================================================= */ -#define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Pos (0UL) /*!< MCUCTRL KEXTCLKSEL: KEXTCLKSEL (Bit 0) */ -#define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Msk (0xffffffffUL) /*!< MCUCTRL KEXTCLKSEL: KEXTCLKSEL (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= SIMOBUCK4 ======================================================= */ -#define MCUCTRL_SIMOBUCK4_SIMOBUCKCLKDIVSEL_Pos (21UL) /*!< MCUCTRL SIMOBUCK4: SIMOBUCKCLKDIVSEL (Bit 21) */ -#define MCUCTRL_SIMOBUCK4_SIMOBUCKCLKDIVSEL_Msk (0x600000UL) /*!< MCUCTRL SIMOBUCK4: SIMOBUCKCLKDIVSEL (Bitfield-Mask: 0x03) */ -/* ======================================================= BLEBUCK2 ======================================================== */ -#define MCUCTRL_BLEBUCK2_BLEBUCKTOND2ATRIM_Pos (12UL) /*!< MCUCTRL BLEBUCK2: BLEBUCKTOND2ATRIM (Bit 12) */ -#define MCUCTRL_BLEBUCK2_BLEBUCKTOND2ATRIM_Msk (0x3f000UL) /*!< MCUCTRL BLEBUCK2: BLEBUCKTOND2ATRIM (Bitfield-Mask: 0x3f) */ -#define MCUCTRL_BLEBUCK2_BLEBUCKTONHITRIM_Pos (6UL) /*!< MCUCTRL BLEBUCK2: BLEBUCKTONHITRIM (Bit 6) */ -#define MCUCTRL_BLEBUCK2_BLEBUCKTONHITRIM_Msk (0xfc0UL) /*!< MCUCTRL BLEBUCK2: BLEBUCKTONHITRIM (Bitfield-Mask: 0x3f) */ -#define MCUCTRL_BLEBUCK2_BLEBUCKTONLOWTRIM_Pos (0UL) /*!< MCUCTRL BLEBUCK2: BLEBUCKTONLOWTRIM (Bit 0) */ -#define MCUCTRL_BLEBUCK2_BLEBUCKTONLOWTRIM_Msk (0x3fUL) /*!< MCUCTRL BLEBUCK2: BLEBUCKTONLOWTRIM (Bitfield-Mask: 0x3f) */ -/* ====================================================== FLASHWPROT0 ====================================================== */ -#define MCUCTRL_FLASHWPROT0_FW0BITS_Pos (0UL) /*!< MCUCTRL FLASHWPROT0: FW0BITS (Bit 0) */ -#define MCUCTRL_FLASHWPROT0_FW0BITS_Msk (0xffffffffUL) /*!< MCUCTRL FLASHWPROT0: FW0BITS (Bitfield-Mask: 0xffffffff) */ -/* ====================================================== FLASHWPROT1 ====================================================== */ -#define MCUCTRL_FLASHWPROT1_FW1BITS_Pos (0UL) /*!< MCUCTRL FLASHWPROT1: FW1BITS (Bit 0) */ -#define MCUCTRL_FLASHWPROT1_FW1BITS_Msk (0xffffffffUL) /*!< MCUCTRL FLASHWPROT1: FW1BITS (Bitfield-Mask: 0xffffffff) */ -/* ====================================================== FLASHWPROT2 ====================================================== */ -#define MCUCTRL_FLASHWPROT2_FW2BITS_Pos (0UL) /*!< MCUCTRL FLASHWPROT2: FW2BITS (Bit 0) */ -#define MCUCTRL_FLASHWPROT2_FW2BITS_Msk (0xffffffffUL) /*!< MCUCTRL FLASHWPROT2: FW2BITS (Bitfield-Mask: 0xffffffff) */ -/* ====================================================== FLASHWPROT3 ====================================================== */ -#define MCUCTRL_FLASHWPROT3_FW3BITS_Pos (0UL) /*!< MCUCTRL FLASHWPROT3: FW3BITS (Bit 0) */ -#define MCUCTRL_FLASHWPROT3_FW3BITS_Msk (0xffffffffUL) /*!< MCUCTRL FLASHWPROT3: FW3BITS (Bitfield-Mask: 0xffffffff) */ -/* ====================================================== FLASHRPROT0 ====================================================== */ -#define MCUCTRL_FLASHRPROT0_FR0BITS_Pos (0UL) /*!< MCUCTRL FLASHRPROT0: FR0BITS (Bit 0) */ -#define MCUCTRL_FLASHRPROT0_FR0BITS_Msk (0xffffffffUL) /*!< MCUCTRL FLASHRPROT0: FR0BITS (Bitfield-Mask: 0xffffffff) */ -/* ====================================================== FLASHRPROT1 ====================================================== */ -#define MCUCTRL_FLASHRPROT1_FR1BITS_Pos (0UL) /*!< MCUCTRL FLASHRPROT1: FR1BITS (Bit 0) */ -#define MCUCTRL_FLASHRPROT1_FR1BITS_Msk (0xffffffffUL) /*!< MCUCTRL FLASHRPROT1: FR1BITS (Bitfield-Mask: 0xffffffff) */ -/* ====================================================== FLASHRPROT2 ====================================================== */ -#define MCUCTRL_FLASHRPROT2_FR2BITS_Pos (0UL) /*!< MCUCTRL FLASHRPROT2: FR2BITS (Bit 0) */ -#define MCUCTRL_FLASHRPROT2_FR2BITS_Msk (0xffffffffUL) /*!< MCUCTRL FLASHRPROT2: FR2BITS (Bitfield-Mask: 0xffffffff) */ -/* ====================================================== FLASHRPROT3 ====================================================== */ -#define MCUCTRL_FLASHRPROT3_FR3BITS_Pos (0UL) /*!< MCUCTRL FLASHRPROT3: FR3BITS (Bit 0) */ -#define MCUCTRL_FLASHRPROT3_FR3BITS_Msk (0xffffffffUL) /*!< MCUCTRL FLASHRPROT3: FR3BITS (Bitfield-Mask: 0xffffffff) */ -/* ================================================= DMASRAMWRITEPROTECT0 ================================================== */ -#define MCUCTRL_DMASRAMWRITEPROTECT0_DMA_WPROT0_Pos (0UL) /*!< MCUCTRL DMASRAMWRITEPROTECT0: DMA_WPROT0 (Bit 0) */ -#define MCUCTRL_DMASRAMWRITEPROTECT0_DMA_WPROT0_Msk (0xffffffffUL) /*!< MCUCTRL DMASRAMWRITEPROTECT0: DMA_WPROT0 (Bitfield-Mask: 0xffffffff) */ -/* ================================================= DMASRAMWRITEPROTECT1 ================================================== */ -#define MCUCTRL_DMASRAMWRITEPROTECT1_DMA_WPROT1_Pos (0UL) /*!< MCUCTRL DMASRAMWRITEPROTECT1: DMA_WPROT1 (Bit 0) */ -#define MCUCTRL_DMASRAMWRITEPROTECT1_DMA_WPROT1_Msk (0xffffffffUL) /*!< MCUCTRL DMASRAMWRITEPROTECT1: DMA_WPROT1 (Bitfield-Mask: 0xffffffff) */ -/* ================================================== DMASRAMREADPROTECT0 ================================================== */ -#define MCUCTRL_DMASRAMREADPROTECT0_DMA_RPROT0_Pos (0UL) /*!< MCUCTRL DMASRAMREADPROTECT0: DMA_RPROT0 (Bit 0) */ -#define MCUCTRL_DMASRAMREADPROTECT0_DMA_RPROT0_Msk (0xffffffffUL) /*!< MCUCTRL DMASRAMREADPROTECT0: DMA_RPROT0 (Bitfield-Mask: 0xffffffff) */ -/* ================================================== DMASRAMREADPROTECT1 ================================================== */ -#define MCUCTRL_DMASRAMREADPROTECT1_DMA_RPROT1_Pos (0UL) /*!< MCUCTRL DMASRAMREADPROTECT1: DMA_RPROT1 (Bit 0) */ -#define MCUCTRL_DMASRAMREADPROTECT1_DMA_RPROT1_Msk (0xffffffffUL) /*!< MCUCTRL DMASRAMREADPROTECT1: DMA_RPROT1 (Bitfield-Mask: 0xffffffff) */ -/* ================================================== DMASRAMREADPROTECT2 ================================================== */ -#define MCUCTRL_DMASRAMREADPROTECT2_DMA_RPROT2_Pos (0UL) /*!< MCUCTRL DMASRAMREADPROTECT2: DMA_RPROT2 (Bit 0) */ -#define MCUCTRL_DMASRAMREADPROTECT2_DMA_RPROT2_Msk (0xffffffffUL) /*!< MCUCTRL DMASRAMREADPROTECT2: DMA_RPROT2 (Bitfield-Mask: 0xffffffff) */ - - -/* =========================================================================================================================== */ -/* ================ MSPI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CTRL ========================================================== */ -#define MSPI0_CTRL_XFERBYTES_Pos (16UL) /*!< MSPI0 CTRL: XFERBYTES (Bit 16) */ -#define MSPI0_CTRL_XFERBYTES_Msk (0xffff0000UL) /*!< MSPI0 CTRL: XFERBYTES (Bitfield-Mask: 0xffff) */ -#define MSPI0_CTRL_ENDCX_Pos (12UL) /*!< MSPI0 CTRL: ENDCX (Bit 12) */ -#define MSPI0_CTRL_ENDCX_Msk (0x1000UL) /*!< MSPI0 CTRL: ENDCX (Bitfield-Mask: 0x01) */ -#define MSPI0_CTRL_PIOSCRAMBLE_Pos (11UL) /*!< MSPI0 CTRL: PIOSCRAMBLE (Bit 11) */ -#define MSPI0_CTRL_PIOSCRAMBLE_Msk (0x800UL) /*!< MSPI0 CTRL: PIOSCRAMBLE (Bitfield-Mask: 0x01) */ -#define MSPI0_CTRL_TXRX_Pos (10UL) /*!< MSPI0 CTRL: TXRX (Bit 10) */ -#define MSPI0_CTRL_TXRX_Msk (0x400UL) /*!< MSPI0 CTRL: TXRX (Bitfield-Mask: 0x01) */ -#define MSPI0_CTRL_SENDI_Pos (9UL) /*!< MSPI0 CTRL: SENDI (Bit 9) */ -#define MSPI0_CTRL_SENDI_Msk (0x200UL) /*!< MSPI0 CTRL: SENDI (Bitfield-Mask: 0x01) */ -#define MSPI0_CTRL_SENDA_Pos (8UL) /*!< MSPI0 CTRL: SENDA (Bit 8) */ -#define MSPI0_CTRL_SENDA_Msk (0x100UL) /*!< MSPI0 CTRL: SENDA (Bitfield-Mask: 0x01) */ -#define MSPI0_CTRL_ENTURN_Pos (7UL) /*!< MSPI0 CTRL: ENTURN (Bit 7) */ -#define MSPI0_CTRL_ENTURN_Msk (0x80UL) /*!< MSPI0 CTRL: ENTURN (Bitfield-Mask: 0x01) */ -#define MSPI0_CTRL_BIGENDIAN_Pos (6UL) /*!< MSPI0 CTRL: BIGENDIAN (Bit 6) */ -#define MSPI0_CTRL_BIGENDIAN_Msk (0x40UL) /*!< MSPI0 CTRL: BIGENDIAN (Bitfield-Mask: 0x01) */ -#define MSPI0_CTRL_CONT_Pos (5UL) /*!< MSPI0 CTRL: CONT (Bit 5) */ -#define MSPI0_CTRL_CONT_Msk (0x20UL) /*!< MSPI0 CTRL: CONT (Bitfield-Mask: 0x01) */ -#define MSPI0_CTRL_ENWLAT_Pos (4UL) /*!< MSPI0 CTRL: ENWLAT (Bit 4) */ -#define MSPI0_CTRL_ENWLAT_Msk (0x10UL) /*!< MSPI0 CTRL: ENWLAT (Bitfield-Mask: 0x01) */ -#define MSPI0_CTRL_QUADCMD_Pos (3UL) /*!< MSPI0 CTRL: QUADCMD (Bit 3) */ -#define MSPI0_CTRL_QUADCMD_Msk (0x8UL) /*!< MSPI0 CTRL: QUADCMD (Bitfield-Mask: 0x01) */ -#define MSPI0_CTRL_BUSY_Pos (2UL) /*!< MSPI0 CTRL: BUSY (Bit 2) */ -#define MSPI0_CTRL_BUSY_Msk (0x4UL) /*!< MSPI0 CTRL: BUSY (Bitfield-Mask: 0x01) */ -#define MSPI0_CTRL_STATUS_Pos (1UL) /*!< MSPI0 CTRL: STATUS (Bit 1) */ -#define MSPI0_CTRL_STATUS_Msk (0x2UL) /*!< MSPI0 CTRL: STATUS (Bitfield-Mask: 0x01) */ -#define MSPI0_CTRL_START_Pos (0UL) /*!< MSPI0 CTRL: START (Bit 0) */ -#define MSPI0_CTRL_START_Msk (0x1UL) /*!< MSPI0 CTRL: START (Bitfield-Mask: 0x01) */ -/* ========================================================== CFG ========================================================== */ -#define MSPI0_CFG_WRITELATENCY_Pos (20UL) /*!< MSPI0 CFG: WRITELATENCY (Bit 20) */ -#define MSPI0_CFG_WRITELATENCY_Msk (0x3f00000UL) /*!< MSPI0 CFG: WRITELATENCY (Bitfield-Mask: 0x3f) */ -#define MSPI0_CFG_CPOL_Pos (17UL) /*!< MSPI0 CFG: CPOL (Bit 17) */ -#define MSPI0_CFG_CPOL_Msk (0x20000UL) /*!< MSPI0 CFG: CPOL (Bitfield-Mask: 0x01) */ -#define MSPI0_CFG_CPHA_Pos (16UL) /*!< MSPI0 CFG: CPHA (Bit 16) */ -#define MSPI0_CFG_CPHA_Msk (0x10000UL) /*!< MSPI0 CFG: CPHA (Bitfield-Mask: 0x01) */ -#define MSPI0_CFG_TURNAROUND_Pos (8UL) /*!< MSPI0 CFG: TURNAROUND (Bit 8) */ -#define MSPI0_CFG_TURNAROUND_Msk (0x3f00UL) /*!< MSPI0 CFG: TURNAROUND (Bitfield-Mask: 0x3f) */ -#define MSPI0_CFG_SEPIO_Pos (7UL) /*!< MSPI0 CFG: SEPIO (Bit 7) */ -#define MSPI0_CFG_SEPIO_Msk (0x80UL) /*!< MSPI0 CFG: SEPIO (Bitfield-Mask: 0x01) */ -#define MSPI0_CFG_ISIZE_Pos (6UL) /*!< MSPI0 CFG: ISIZE (Bit 6) */ -#define MSPI0_CFG_ISIZE_Msk (0x40UL) /*!< MSPI0 CFG: ISIZE (Bitfield-Mask: 0x01) */ -#define MSPI0_CFG_ASIZE_Pos (4UL) /*!< MSPI0 CFG: ASIZE (Bit 4) */ -#define MSPI0_CFG_ASIZE_Msk (0x30UL) /*!< MSPI0 CFG: ASIZE (Bitfield-Mask: 0x03) */ -#define MSPI0_CFG_DEVCFG_Pos (0UL) /*!< MSPI0 CFG: DEVCFG (Bit 0) */ -#define MSPI0_CFG_DEVCFG_Msk (0xfUL) /*!< MSPI0 CFG: DEVCFG (Bitfield-Mask: 0x0f) */ -/* ========================================================= ADDR ========================================================== */ -#define MSPI0_ADDR_ADDR_Pos (0UL) /*!< MSPI0 ADDR: ADDR (Bit 0) */ -#define MSPI0_ADDR_ADDR_Msk (0xffffffffUL) /*!< MSPI0 ADDR: ADDR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= INSTR ========================================================= */ -#define MSPI0_INSTR_INSTR_Pos (0UL) /*!< MSPI0 INSTR: INSTR (Bit 0) */ -#define MSPI0_INSTR_INSTR_Msk (0xffffUL) /*!< MSPI0 INSTR: INSTR (Bitfield-Mask: 0xffff) */ -/* ======================================================== TXFIFO ========================================================= */ -#define MSPI0_TXFIFO_TXFIFO_Pos (0UL) /*!< MSPI0 TXFIFO: TXFIFO (Bit 0) */ -#define MSPI0_TXFIFO_TXFIFO_Msk (0xffffffffUL) /*!< MSPI0 TXFIFO: TXFIFO (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== RXFIFO ========================================================= */ -#define MSPI0_RXFIFO_RXFIFO_Pos (0UL) /*!< MSPI0 RXFIFO: RXFIFO (Bit 0) */ -#define MSPI0_RXFIFO_RXFIFO_Msk (0xffffffffUL) /*!< MSPI0 RXFIFO: RXFIFO (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= TXENTRIES ======================================================= */ -#define MSPI0_TXENTRIES_TXENTRIES_Pos (0UL) /*!< MSPI0 TXENTRIES: TXENTRIES (Bit 0) */ -#define MSPI0_TXENTRIES_TXENTRIES_Msk (0x3fUL) /*!< MSPI0 TXENTRIES: TXENTRIES (Bitfield-Mask: 0x3f) */ -/* ======================================================= RXENTRIES ======================================================= */ -#define MSPI0_RXENTRIES_RXENTRIES_Pos (0UL) /*!< MSPI0 RXENTRIES: RXENTRIES (Bit 0) */ -#define MSPI0_RXENTRIES_RXENTRIES_Msk (0x3fUL) /*!< MSPI0 RXENTRIES: RXENTRIES (Bitfield-Mask: 0x3f) */ -/* ======================================================= THRESHOLD ======================================================= */ -#define MSPI0_THRESHOLD_RXTHRESH_Pos (8UL) /*!< MSPI0 THRESHOLD: RXTHRESH (Bit 8) */ -#define MSPI0_THRESHOLD_RXTHRESH_Msk (0x3f00UL) /*!< MSPI0 THRESHOLD: RXTHRESH (Bitfield-Mask: 0x3f) */ -#define MSPI0_THRESHOLD_TXTHRESH_Pos (0UL) /*!< MSPI0 THRESHOLD: TXTHRESH (Bit 0) */ -#define MSPI0_THRESHOLD_TXTHRESH_Msk (0x3fUL) /*!< MSPI0 THRESHOLD: TXTHRESH (Bitfield-Mask: 0x3f) */ -/* ======================================================== MSPICFG ======================================================== */ -#define MSPI0_MSPICFG_PRSTN_Pos (31UL) /*!< MSPI0 MSPICFG: PRSTN (Bit 31) */ -#define MSPI0_MSPICFG_PRSTN_Msk (0x80000000UL) /*!< MSPI0 MSPICFG: PRSTN (Bitfield-Mask: 0x01) */ -#define MSPI0_MSPICFG_IPRSTN_Pos (30UL) /*!< MSPI0 MSPICFG: IPRSTN (Bit 30) */ -#define MSPI0_MSPICFG_IPRSTN_Msk (0x40000000UL) /*!< MSPI0 MSPICFG: IPRSTN (Bitfield-Mask: 0x01) */ -#define MSPI0_MSPICFG_FIFORESET_Pos (29UL) /*!< MSPI0 MSPICFG: FIFORESET (Bit 29) */ -#define MSPI0_MSPICFG_FIFORESET_Msk (0x20000000UL) /*!< MSPI0 MSPICFG: FIFORESET (Bitfield-Mask: 0x01) */ -#define MSPI0_MSPICFG_CLKDIV_Pos (8UL) /*!< MSPI0 MSPICFG: CLKDIV (Bit 8) */ -#define MSPI0_MSPICFG_CLKDIV_Msk (0x3f00UL) /*!< MSPI0 MSPICFG: CLKDIV (Bitfield-Mask: 0x3f) */ -#define MSPI0_MSPICFG_IOMSEL_Pos (4UL) /*!< MSPI0 MSPICFG: IOMSEL (Bit 4) */ -#define MSPI0_MSPICFG_IOMSEL_Msk (0xf0UL) /*!< MSPI0 MSPICFG: IOMSEL (Bitfield-Mask: 0x0f) */ -#define MSPI0_MSPICFG_TXNEG_Pos (3UL) /*!< MSPI0 MSPICFG: TXNEG (Bit 3) */ -#define MSPI0_MSPICFG_TXNEG_Msk (0x8UL) /*!< MSPI0 MSPICFG: TXNEG (Bitfield-Mask: 0x01) */ -#define MSPI0_MSPICFG_RXNEG_Pos (2UL) /*!< MSPI0 MSPICFG: RXNEG (Bit 2) */ -#define MSPI0_MSPICFG_RXNEG_Msk (0x4UL) /*!< MSPI0 MSPICFG: RXNEG (Bitfield-Mask: 0x01) */ -#define MSPI0_MSPICFG_RXCAP_Pos (1UL) /*!< MSPI0 MSPICFG: RXCAP (Bit 1) */ -#define MSPI0_MSPICFG_RXCAP_Msk (0x2UL) /*!< MSPI0 MSPICFG: RXCAP (Bitfield-Mask: 0x01) */ -#define MSPI0_MSPICFG_APBCLK_Pos (0UL) /*!< MSPI0 MSPICFG: APBCLK (Bit 0) */ -#define MSPI0_MSPICFG_APBCLK_Msk (0x1UL) /*!< MSPI0 MSPICFG: APBCLK (Bitfield-Mask: 0x01) */ -/* ======================================================== MSPIDDR ======================================================== */ -#define MSPI0_MSPIDDR_TXDQSDELAY_Pos (16UL) /*!< MSPI0 MSPIDDR: TXDQSDELAY (Bit 16) */ -#define MSPI0_MSPIDDR_TXDQSDELAY_Msk (0x1f0000UL) /*!< MSPI0 MSPIDDR: TXDQSDELAY (Bitfield-Mask: 0x1f) */ -#define MSPI0_MSPIDDR_RXDQSDELAY_Pos (8UL) /*!< MSPI0 MSPIDDR: RXDQSDELAY (Bit 8) */ -#define MSPI0_MSPIDDR_RXDQSDELAY_Msk (0x1f00UL) /*!< MSPI0 MSPIDDR: RXDQSDELAY (Bitfield-Mask: 0x1f) */ -#define MSPI0_MSPIDDR_ENABLEFINEDELAY_Pos (6UL) /*!< MSPI0 MSPIDDR: ENABLEFINEDELAY (Bit 6) */ -#define MSPI0_MSPIDDR_ENABLEFINEDELAY_Msk (0x40UL) /*!< MSPI0 MSPIDDR: ENABLEFINEDELAY (Bitfield-Mask: 0x01) */ -#define MSPI0_MSPIDDR_OVERRIDEDDRCLKOUTDELAY_Pos (5UL) /*!< MSPI0 MSPIDDR: OVERRIDEDDRCLKOUTDELAY (Bit 5) */ -#define MSPI0_MSPIDDR_OVERRIDEDDRCLKOUTDELAY_Msk (0x20UL) /*!< MSPI0 MSPIDDR: OVERRIDEDDRCLKOUTDELAY (Bitfield-Mask: 0x01) */ -#define MSPI0_MSPIDDR_OVERRIDERXDQSDELAY_Pos (4UL) /*!< MSPI0 MSPIDDR: OVERRIDERXDQSDELAY (Bit 4) */ -#define MSPI0_MSPIDDR_OVERRIDERXDQSDELAY_Msk (0x10UL) /*!< MSPI0 MSPIDDR: OVERRIDERXDQSDELAY (Bitfield-Mask: 0x01) */ -#define MSPI0_MSPIDDR_DQSSYNCNEG_Pos (3UL) /*!< MSPI0 MSPIDDR: DQSSYNCNEG (Bit 3) */ -#define MSPI0_MSPIDDR_DQSSYNCNEG_Msk (0x8UL) /*!< MSPI0 MSPIDDR: DQSSYNCNEG (Bitfield-Mask: 0x01) */ -#define MSPI0_MSPIDDR_ENABLEDQS_Pos (2UL) /*!< MSPI0 MSPIDDR: ENABLEDQS (Bit 2) */ -#define MSPI0_MSPIDDR_ENABLEDQS_Msk (0x4UL) /*!< MSPI0 MSPIDDR: ENABLEDQS (Bitfield-Mask: 0x01) */ -#define MSPI0_MSPIDDR_QUADDDR_Pos (1UL) /*!< MSPI0 MSPIDDR: QUADDDR (Bit 1) */ -#define MSPI0_MSPIDDR_QUADDDR_Msk (0x2UL) /*!< MSPI0 MSPIDDR: QUADDDR (Bitfield-Mask: 0x01) */ -#define MSPI0_MSPIDDR_EMULATEDDR_Pos (0UL) /*!< MSPI0 MSPIDDR: EMULATEDDR (Bit 0) */ -#define MSPI0_MSPIDDR_EMULATEDDR_Msk (0x1UL) /*!< MSPI0 MSPIDDR: EMULATEDDR (Bitfield-Mask: 0x01) */ -/* ======================================================== PADCFG ========================================================= */ -#define MSPI0_PADCFG_REVCS_Pos (21UL) /*!< MSPI0 PADCFG: REVCS (Bit 21) */ -#define MSPI0_PADCFG_REVCS_Msk (0x200000UL) /*!< MSPI0 PADCFG: REVCS (Bitfield-Mask: 0x01) */ -#define MSPI0_PADCFG_IN3_Pos (20UL) /*!< MSPI0 PADCFG: IN3 (Bit 20) */ -#define MSPI0_PADCFG_IN3_Msk (0x100000UL) /*!< MSPI0 PADCFG: IN3 (Bitfield-Mask: 0x01) */ -#define MSPI0_PADCFG_IN2_Pos (19UL) /*!< MSPI0 PADCFG: IN2 (Bit 19) */ -#define MSPI0_PADCFG_IN2_Msk (0x80000UL) /*!< MSPI0 PADCFG: IN2 (Bitfield-Mask: 0x01) */ -#define MSPI0_PADCFG_IN1_Pos (18UL) /*!< MSPI0 PADCFG: IN1 (Bit 18) */ -#define MSPI0_PADCFG_IN1_Msk (0x40000UL) /*!< MSPI0 PADCFG: IN1 (Bitfield-Mask: 0x01) */ -#define MSPI0_PADCFG_IN0_Pos (16UL) /*!< MSPI0 PADCFG: IN0 (Bit 16) */ -#define MSPI0_PADCFG_IN0_Msk (0x30000UL) /*!< MSPI0 PADCFG: IN0 (Bitfield-Mask: 0x03) */ -#define MSPI0_PADCFG_OUT7_Pos (4UL) /*!< MSPI0 PADCFG: OUT7 (Bit 4) */ -#define MSPI0_PADCFG_OUT7_Msk (0x10UL) /*!< MSPI0 PADCFG: OUT7 (Bitfield-Mask: 0x01) */ -#define MSPI0_PADCFG_OUT6_Pos (3UL) /*!< MSPI0 PADCFG: OUT6 (Bit 3) */ -#define MSPI0_PADCFG_OUT6_Msk (0x8UL) /*!< MSPI0 PADCFG: OUT6 (Bitfield-Mask: 0x01) */ -#define MSPI0_PADCFG_OUT5_Pos (2UL) /*!< MSPI0 PADCFG: OUT5 (Bit 2) */ -#define MSPI0_PADCFG_OUT5_Msk (0x4UL) /*!< MSPI0 PADCFG: OUT5 (Bitfield-Mask: 0x01) */ -#define MSPI0_PADCFG_OUT4_Pos (1UL) /*!< MSPI0 PADCFG: OUT4 (Bit 1) */ -#define MSPI0_PADCFG_OUT4_Msk (0x2UL) /*!< MSPI0 PADCFG: OUT4 (Bitfield-Mask: 0x01) */ -#define MSPI0_PADCFG_OUT3_Pos (0UL) /*!< MSPI0 PADCFG: OUT3 (Bit 0) */ -#define MSPI0_PADCFG_OUT3_Msk (0x1UL) /*!< MSPI0 PADCFG: OUT3 (Bitfield-Mask: 0x01) */ -/* ======================================================= PADOUTEN ======================================================== */ -#define MSPI0_PADOUTEN_OUTEN_Pos (0UL) /*!< MSPI0 PADOUTEN: OUTEN (Bit 0) */ -#define MSPI0_PADOUTEN_OUTEN_Msk (0x3ffUL) /*!< MSPI0 PADOUTEN: OUTEN (Bitfield-Mask: 0x3ff) */ -/* ======================================================= PADOVEREN ======================================================= */ -#define MSPI0_PADOVEREN_OVERRIDEEN_Pos (0UL) /*!< MSPI0 PADOVEREN: OVERRIDEEN (Bit 0) */ -#define MSPI0_PADOVEREN_OVERRIDEEN_Msk (0x3ffUL) /*!< MSPI0 PADOVEREN: OVERRIDEEN (Bitfield-Mask: 0x3ff) */ -/* ======================================================== PADOVER ======================================================== */ -#define MSPI0_PADOVER_OVERRIDE_Pos (0UL) /*!< MSPI0 PADOVER: OVERRIDE (Bit 0) */ -#define MSPI0_PADOVER_OVERRIDE_Msk (0x3ffUL) /*!< MSPI0 PADOVER: OVERRIDE (Bitfield-Mask: 0x3ff) */ -/* ========================================================= FLASH ========================================================= */ -#define MSPI0_FLASH_XIPENWLAT_Pos (11UL) /*!< MSPI0 FLASH: XIPENWLAT (Bit 11) */ -#define MSPI0_FLASH_XIPENWLAT_Msk (0x800UL) /*!< MSPI0 FLASH: XIPENWLAT (Bitfield-Mask: 0x01) */ -#define MSPI0_FLASH_XIPMIXED_Pos (8UL) /*!< MSPI0 FLASH: XIPMIXED (Bit 8) */ -#define MSPI0_FLASH_XIPMIXED_Msk (0x700UL) /*!< MSPI0 FLASH: XIPMIXED (Bitfield-Mask: 0x07) */ -#define MSPI0_FLASH_XIPSENDI_Pos (7UL) /*!< MSPI0 FLASH: XIPSENDI (Bit 7) */ -#define MSPI0_FLASH_XIPSENDI_Msk (0x80UL) /*!< MSPI0 FLASH: XIPSENDI (Bitfield-Mask: 0x01) */ -#define MSPI0_FLASH_XIPSENDA_Pos (6UL) /*!< MSPI0 FLASH: XIPSENDA (Bit 6) */ -#define MSPI0_FLASH_XIPSENDA_Msk (0x40UL) /*!< MSPI0 FLASH: XIPSENDA (Bitfield-Mask: 0x01) */ -#define MSPI0_FLASH_XIPENTURN_Pos (5UL) /*!< MSPI0 FLASH: XIPENTURN (Bit 5) */ -#define MSPI0_FLASH_XIPENTURN_Msk (0x20UL) /*!< MSPI0 FLASH: XIPENTURN (Bitfield-Mask: 0x01) */ -#define MSPI0_FLASH_XIPBIGENDIAN_Pos (4UL) /*!< MSPI0 FLASH: XIPBIGENDIAN (Bit 4) */ -#define MSPI0_FLASH_XIPBIGENDIAN_Msk (0x10UL) /*!< MSPI0 FLASH: XIPBIGENDIAN (Bitfield-Mask: 0x01) */ -#define MSPI0_FLASH_XIPACK_Pos (2UL) /*!< MSPI0 FLASH: XIPACK (Bit 2) */ -#define MSPI0_FLASH_XIPACK_Msk (0xcUL) /*!< MSPI0 FLASH: XIPACK (Bitfield-Mask: 0x03) */ -#define MSPI0_FLASH_XIPENDCX_Pos (1UL) /*!< MSPI0 FLASH: XIPENDCX (Bit 1) */ -#define MSPI0_FLASH_XIPENDCX_Msk (0x2UL) /*!< MSPI0 FLASH: XIPENDCX (Bitfield-Mask: 0x01) */ -#define MSPI0_FLASH_XIPEN_Pos (0UL) /*!< MSPI0 FLASH: XIPEN (Bit 0) */ -#define MSPI0_FLASH_XIPEN_Msk (0x1UL) /*!< MSPI0 FLASH: XIPEN (Bitfield-Mask: 0x01) */ -/* ======================================================= XIPINSTR ======================================================== */ -#define MSPI0_XIPINSTR_READINSTR_Pos (16UL) /*!< MSPI0 XIPINSTR: READINSTR (Bit 16) */ -#define MSPI0_XIPINSTR_READINSTR_Msk (0xffff0000UL) /*!< MSPI0 XIPINSTR: READINSTR (Bitfield-Mask: 0xffff) */ -#define MSPI0_XIPINSTR_WRITEINSTR_Pos (0UL) /*!< MSPI0 XIPINSTR: WRITEINSTR (Bit 0) */ -#define MSPI0_XIPINSTR_WRITEINSTR_Msk (0xffffUL) /*!< MSPI0 XIPINSTR: WRITEINSTR (Bitfield-Mask: 0xffff) */ -/* ====================================================== SCRAMBLING ======================================================= */ -#define MSPI0_SCRAMBLING_SCRENABLE_Pos (31UL) /*!< MSPI0 SCRAMBLING: SCRENABLE (Bit 31) */ -#define MSPI0_SCRAMBLING_SCRENABLE_Msk (0x80000000UL) /*!< MSPI0 SCRAMBLING: SCRENABLE (Bitfield-Mask: 0x01) */ -#define MSPI0_SCRAMBLING_SCREND_Pos (16UL) /*!< MSPI0 SCRAMBLING: SCREND (Bit 16) */ -#define MSPI0_SCRAMBLING_SCREND_Msk (0x3ff0000UL) /*!< MSPI0 SCRAMBLING: SCREND (Bitfield-Mask: 0x3ff) */ -#define MSPI0_SCRAMBLING_SCRSTART_Pos (0UL) /*!< MSPI0 SCRAMBLING: SCRSTART (Bit 0) */ -#define MSPI0_SCRAMBLING_SCRSTART_Msk (0x3ffUL) /*!< MSPI0 SCRAMBLING: SCRSTART (Bitfield-Mask: 0x3ff) */ -/* ========================================================= INTEN ========================================================= */ -#define MSPI0_INTEN_SCRERR_Pos (12UL) /*!< MSPI0 INTEN: SCRERR (Bit 12) */ -#define MSPI0_INTEN_SCRERR_Msk (0x1000UL) /*!< MSPI0 INTEN: SCRERR (Bitfield-Mask: 0x01) */ -#define MSPI0_INTEN_CQERR_Pos (11UL) /*!< MSPI0 INTEN: CQERR (Bit 11) */ -#define MSPI0_INTEN_CQERR_Msk (0x800UL) /*!< MSPI0 INTEN: CQERR (Bitfield-Mask: 0x01) */ -#define MSPI0_INTEN_CQPAUSED_Pos (10UL) /*!< MSPI0 INTEN: CQPAUSED (Bit 10) */ -#define MSPI0_INTEN_CQPAUSED_Msk (0x400UL) /*!< MSPI0 INTEN: CQPAUSED (Bitfield-Mask: 0x01) */ -#define MSPI0_INTEN_CQUPD_Pos (9UL) /*!< MSPI0 INTEN: CQUPD (Bit 9) */ -#define MSPI0_INTEN_CQUPD_Msk (0x200UL) /*!< MSPI0 INTEN: CQUPD (Bitfield-Mask: 0x01) */ -#define MSPI0_INTEN_CQCMP_Pos (8UL) /*!< MSPI0 INTEN: CQCMP (Bit 8) */ -#define MSPI0_INTEN_CQCMP_Msk (0x100UL) /*!< MSPI0 INTEN: CQCMP (Bitfield-Mask: 0x01) */ -#define MSPI0_INTEN_DERR_Pos (7UL) /*!< MSPI0 INTEN: DERR (Bit 7) */ -#define MSPI0_INTEN_DERR_Msk (0x80UL) /*!< MSPI0 INTEN: DERR (Bitfield-Mask: 0x01) */ -#define MSPI0_INTEN_DCMP_Pos (6UL) /*!< MSPI0 INTEN: DCMP (Bit 6) */ -#define MSPI0_INTEN_DCMP_Msk (0x40UL) /*!< MSPI0 INTEN: DCMP (Bitfield-Mask: 0x01) */ -#define MSPI0_INTEN_RXF_Pos (5UL) /*!< MSPI0 INTEN: RXF (Bit 5) */ -#define MSPI0_INTEN_RXF_Msk (0x20UL) /*!< MSPI0 INTEN: RXF (Bitfield-Mask: 0x01) */ -#define MSPI0_INTEN_RXO_Pos (4UL) /*!< MSPI0 INTEN: RXO (Bit 4) */ -#define MSPI0_INTEN_RXO_Msk (0x10UL) /*!< MSPI0 INTEN: RXO (Bitfield-Mask: 0x01) */ -#define MSPI0_INTEN_RXU_Pos (3UL) /*!< MSPI0 INTEN: RXU (Bit 3) */ -#define MSPI0_INTEN_RXU_Msk (0x8UL) /*!< MSPI0 INTEN: RXU (Bitfield-Mask: 0x01) */ -#define MSPI0_INTEN_TXO_Pos (2UL) /*!< MSPI0 INTEN: TXO (Bit 2) */ -#define MSPI0_INTEN_TXO_Msk (0x4UL) /*!< MSPI0 INTEN: TXO (Bitfield-Mask: 0x01) */ -#define MSPI0_INTEN_TXE_Pos (1UL) /*!< MSPI0 INTEN: TXE (Bit 1) */ -#define MSPI0_INTEN_TXE_Msk (0x2UL) /*!< MSPI0 INTEN: TXE (Bitfield-Mask: 0x01) */ -#define MSPI0_INTEN_CMDCMP_Pos (0UL) /*!< MSPI0 INTEN: CMDCMP (Bit 0) */ -#define MSPI0_INTEN_CMDCMP_Msk (0x1UL) /*!< MSPI0 INTEN: CMDCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTAT ======================================================== */ -#define MSPI0_INTSTAT_SCRERR_Pos (12UL) /*!< MSPI0 INTSTAT: SCRERR (Bit 12) */ -#define MSPI0_INTSTAT_SCRERR_Msk (0x1000UL) /*!< MSPI0 INTSTAT: SCRERR (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSTAT_CQERR_Pos (11UL) /*!< MSPI0 INTSTAT: CQERR (Bit 11) */ -#define MSPI0_INTSTAT_CQERR_Msk (0x800UL) /*!< MSPI0 INTSTAT: CQERR (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSTAT_CQPAUSED_Pos (10UL) /*!< MSPI0 INTSTAT: CQPAUSED (Bit 10) */ -#define MSPI0_INTSTAT_CQPAUSED_Msk (0x400UL) /*!< MSPI0 INTSTAT: CQPAUSED (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSTAT_CQUPD_Pos (9UL) /*!< MSPI0 INTSTAT: CQUPD (Bit 9) */ -#define MSPI0_INTSTAT_CQUPD_Msk (0x200UL) /*!< MSPI0 INTSTAT: CQUPD (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSTAT_CQCMP_Pos (8UL) /*!< MSPI0 INTSTAT: CQCMP (Bit 8) */ -#define MSPI0_INTSTAT_CQCMP_Msk (0x100UL) /*!< MSPI0 INTSTAT: CQCMP (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSTAT_DERR_Pos (7UL) /*!< MSPI0 INTSTAT: DERR (Bit 7) */ -#define MSPI0_INTSTAT_DERR_Msk (0x80UL) /*!< MSPI0 INTSTAT: DERR (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSTAT_DCMP_Pos (6UL) /*!< MSPI0 INTSTAT: DCMP (Bit 6) */ -#define MSPI0_INTSTAT_DCMP_Msk (0x40UL) /*!< MSPI0 INTSTAT: DCMP (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSTAT_RXF_Pos (5UL) /*!< MSPI0 INTSTAT: RXF (Bit 5) */ -#define MSPI0_INTSTAT_RXF_Msk (0x20UL) /*!< MSPI0 INTSTAT: RXF (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSTAT_RXO_Pos (4UL) /*!< MSPI0 INTSTAT: RXO (Bit 4) */ -#define MSPI0_INTSTAT_RXO_Msk (0x10UL) /*!< MSPI0 INTSTAT: RXO (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSTAT_RXU_Pos (3UL) /*!< MSPI0 INTSTAT: RXU (Bit 3) */ -#define MSPI0_INTSTAT_RXU_Msk (0x8UL) /*!< MSPI0 INTSTAT: RXU (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSTAT_TXO_Pos (2UL) /*!< MSPI0 INTSTAT: TXO (Bit 2) */ -#define MSPI0_INTSTAT_TXO_Msk (0x4UL) /*!< MSPI0 INTSTAT: TXO (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSTAT_TXE_Pos (1UL) /*!< MSPI0 INTSTAT: TXE (Bit 1) */ -#define MSPI0_INTSTAT_TXE_Msk (0x2UL) /*!< MSPI0 INTSTAT: TXE (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSTAT_CMDCMP_Pos (0UL) /*!< MSPI0 INTSTAT: CMDCMP (Bit 0) */ -#define MSPI0_INTSTAT_CMDCMP_Msk (0x1UL) /*!< MSPI0 INTSTAT: CMDCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== INTCLR ========================================================= */ -#define MSPI0_INTCLR_SCRERR_Pos (12UL) /*!< MSPI0 INTCLR: SCRERR (Bit 12) */ -#define MSPI0_INTCLR_SCRERR_Msk (0x1000UL) /*!< MSPI0 INTCLR: SCRERR (Bitfield-Mask: 0x01) */ -#define MSPI0_INTCLR_CQERR_Pos (11UL) /*!< MSPI0 INTCLR: CQERR (Bit 11) */ -#define MSPI0_INTCLR_CQERR_Msk (0x800UL) /*!< MSPI0 INTCLR: CQERR (Bitfield-Mask: 0x01) */ -#define MSPI0_INTCLR_CQPAUSED_Pos (10UL) /*!< MSPI0 INTCLR: CQPAUSED (Bit 10) */ -#define MSPI0_INTCLR_CQPAUSED_Msk (0x400UL) /*!< MSPI0 INTCLR: CQPAUSED (Bitfield-Mask: 0x01) */ -#define MSPI0_INTCLR_CQUPD_Pos (9UL) /*!< MSPI0 INTCLR: CQUPD (Bit 9) */ -#define MSPI0_INTCLR_CQUPD_Msk (0x200UL) /*!< MSPI0 INTCLR: CQUPD (Bitfield-Mask: 0x01) */ -#define MSPI0_INTCLR_CQCMP_Pos (8UL) /*!< MSPI0 INTCLR: CQCMP (Bit 8) */ -#define MSPI0_INTCLR_CQCMP_Msk (0x100UL) /*!< MSPI0 INTCLR: CQCMP (Bitfield-Mask: 0x01) */ -#define MSPI0_INTCLR_DERR_Pos (7UL) /*!< MSPI0 INTCLR: DERR (Bit 7) */ -#define MSPI0_INTCLR_DERR_Msk (0x80UL) /*!< MSPI0 INTCLR: DERR (Bitfield-Mask: 0x01) */ -#define MSPI0_INTCLR_DCMP_Pos (6UL) /*!< MSPI0 INTCLR: DCMP (Bit 6) */ -#define MSPI0_INTCLR_DCMP_Msk (0x40UL) /*!< MSPI0 INTCLR: DCMP (Bitfield-Mask: 0x01) */ -#define MSPI0_INTCLR_RXF_Pos (5UL) /*!< MSPI0 INTCLR: RXF (Bit 5) */ -#define MSPI0_INTCLR_RXF_Msk (0x20UL) /*!< MSPI0 INTCLR: RXF (Bitfield-Mask: 0x01) */ -#define MSPI0_INTCLR_RXO_Pos (4UL) /*!< MSPI0 INTCLR: RXO (Bit 4) */ -#define MSPI0_INTCLR_RXO_Msk (0x10UL) /*!< MSPI0 INTCLR: RXO (Bitfield-Mask: 0x01) */ -#define MSPI0_INTCLR_RXU_Pos (3UL) /*!< MSPI0 INTCLR: RXU (Bit 3) */ -#define MSPI0_INTCLR_RXU_Msk (0x8UL) /*!< MSPI0 INTCLR: RXU (Bitfield-Mask: 0x01) */ -#define MSPI0_INTCLR_TXO_Pos (2UL) /*!< MSPI0 INTCLR: TXO (Bit 2) */ -#define MSPI0_INTCLR_TXO_Msk (0x4UL) /*!< MSPI0 INTCLR: TXO (Bitfield-Mask: 0x01) */ -#define MSPI0_INTCLR_TXE_Pos (1UL) /*!< MSPI0 INTCLR: TXE (Bit 1) */ -#define MSPI0_INTCLR_TXE_Msk (0x2UL) /*!< MSPI0 INTCLR: TXE (Bitfield-Mask: 0x01) */ -#define MSPI0_INTCLR_CMDCMP_Pos (0UL) /*!< MSPI0 INTCLR: CMDCMP (Bit 0) */ -#define MSPI0_INTCLR_CMDCMP_Msk (0x1UL) /*!< MSPI0 INTCLR: CMDCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSET ========================================================= */ -#define MSPI0_INTSET_SCRERR_Pos (12UL) /*!< MSPI0 INTSET: SCRERR (Bit 12) */ -#define MSPI0_INTSET_SCRERR_Msk (0x1000UL) /*!< MSPI0 INTSET: SCRERR (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSET_CQERR_Pos (11UL) /*!< MSPI0 INTSET: CQERR (Bit 11) */ -#define MSPI0_INTSET_CQERR_Msk (0x800UL) /*!< MSPI0 INTSET: CQERR (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSET_CQPAUSED_Pos (10UL) /*!< MSPI0 INTSET: CQPAUSED (Bit 10) */ -#define MSPI0_INTSET_CQPAUSED_Msk (0x400UL) /*!< MSPI0 INTSET: CQPAUSED (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSET_CQUPD_Pos (9UL) /*!< MSPI0 INTSET: CQUPD (Bit 9) */ -#define MSPI0_INTSET_CQUPD_Msk (0x200UL) /*!< MSPI0 INTSET: CQUPD (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSET_CQCMP_Pos (8UL) /*!< MSPI0 INTSET: CQCMP (Bit 8) */ -#define MSPI0_INTSET_CQCMP_Msk (0x100UL) /*!< MSPI0 INTSET: CQCMP (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSET_DERR_Pos (7UL) /*!< MSPI0 INTSET: DERR (Bit 7) */ -#define MSPI0_INTSET_DERR_Msk (0x80UL) /*!< MSPI0 INTSET: DERR (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSET_DCMP_Pos (6UL) /*!< MSPI0 INTSET: DCMP (Bit 6) */ -#define MSPI0_INTSET_DCMP_Msk (0x40UL) /*!< MSPI0 INTSET: DCMP (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSET_RXF_Pos (5UL) /*!< MSPI0 INTSET: RXF (Bit 5) */ -#define MSPI0_INTSET_RXF_Msk (0x20UL) /*!< MSPI0 INTSET: RXF (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSET_RXO_Pos (4UL) /*!< MSPI0 INTSET: RXO (Bit 4) */ -#define MSPI0_INTSET_RXO_Msk (0x10UL) /*!< MSPI0 INTSET: RXO (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSET_RXU_Pos (3UL) /*!< MSPI0 INTSET: RXU (Bit 3) */ -#define MSPI0_INTSET_RXU_Msk (0x8UL) /*!< MSPI0 INTSET: RXU (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSET_TXO_Pos (2UL) /*!< MSPI0 INTSET: TXO (Bit 2) */ -#define MSPI0_INTSET_TXO_Msk (0x4UL) /*!< MSPI0 INTSET: TXO (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSET_TXE_Pos (1UL) /*!< MSPI0 INTSET: TXE (Bit 1) */ -#define MSPI0_INTSET_TXE_Msk (0x2UL) /*!< MSPI0 INTSET: TXE (Bitfield-Mask: 0x01) */ -#define MSPI0_INTSET_CMDCMP_Pos (0UL) /*!< MSPI0 INTSET: CMDCMP (Bit 0) */ -#define MSPI0_INTSET_CMDCMP_Msk (0x1UL) /*!< MSPI0 INTSET: CMDCMP (Bitfield-Mask: 0x01) */ -/* ======================================================== DMACFG ========================================================= */ -#define MSPI0_DMACFG_DMAPWROFF_Pos (18UL) /*!< MSPI0 DMACFG: DMAPWROFF (Bit 18) */ -#define MSPI0_DMACFG_DMAPWROFF_Msk (0x40000UL) /*!< MSPI0 DMACFG: DMAPWROFF (Bitfield-Mask: 0x01) */ -#define MSPI0_DMACFG_DMAPRI_Pos (3UL) /*!< MSPI0 DMACFG: DMAPRI (Bit 3) */ -#define MSPI0_DMACFG_DMAPRI_Msk (0x18UL) /*!< MSPI0 DMACFG: DMAPRI (Bitfield-Mask: 0x03) */ -#define MSPI0_DMACFG_DMADIR_Pos (2UL) /*!< MSPI0 DMACFG: DMADIR (Bit 2) */ -#define MSPI0_DMACFG_DMADIR_Msk (0x4UL) /*!< MSPI0 DMACFG: DMADIR (Bitfield-Mask: 0x01) */ -#define MSPI0_DMACFG_DMAEN_Pos (0UL) /*!< MSPI0 DMACFG: DMAEN (Bit 0) */ -#define MSPI0_DMACFG_DMAEN_Msk (0x3UL) /*!< MSPI0 DMACFG: DMAEN (Bitfield-Mask: 0x03) */ -/* ======================================================== DMASTAT ======================================================== */ -#define MSPI0_DMASTAT_SCRERR_Pos (3UL) /*!< MSPI0 DMASTAT: SCRERR (Bit 3) */ -#define MSPI0_DMASTAT_SCRERR_Msk (0x8UL) /*!< MSPI0 DMASTAT: SCRERR (Bitfield-Mask: 0x01) */ -#define MSPI0_DMASTAT_DMAERR_Pos (2UL) /*!< MSPI0 DMASTAT: DMAERR (Bit 2) */ -#define MSPI0_DMASTAT_DMAERR_Msk (0x4UL) /*!< MSPI0 DMASTAT: DMAERR (Bitfield-Mask: 0x01) */ -#define MSPI0_DMASTAT_DMACPL_Pos (1UL) /*!< MSPI0 DMASTAT: DMACPL (Bit 1) */ -#define MSPI0_DMASTAT_DMACPL_Msk (0x2UL) /*!< MSPI0 DMASTAT: DMACPL (Bitfield-Mask: 0x01) */ -#define MSPI0_DMASTAT_DMATIP_Pos (0UL) /*!< MSPI0 DMASTAT: DMATIP (Bit 0) */ -#define MSPI0_DMASTAT_DMATIP_Msk (0x1UL) /*!< MSPI0 DMASTAT: DMATIP (Bitfield-Mask: 0x01) */ -/* ====================================================== DMATARGADDR ====================================================== */ -#define MSPI0_DMATARGADDR_TARGADDR_Pos (0UL) /*!< MSPI0 DMATARGADDR: TARGADDR (Bit 0) */ -#define MSPI0_DMATARGADDR_TARGADDR_Msk (0xffffffffUL) /*!< MSPI0 DMATARGADDR: TARGADDR (Bitfield-Mask: 0xffffffff) */ -/* ====================================================== DMADEVADDR ======================================================= */ -#define MSPI0_DMADEVADDR_DEVADDR_Pos (0UL) /*!< MSPI0 DMADEVADDR: DEVADDR (Bit 0) */ -#define MSPI0_DMADEVADDR_DEVADDR_Msk (0xffffffffUL) /*!< MSPI0 DMADEVADDR: DEVADDR (Bitfield-Mask: 0xffffffff) */ -/* ====================================================== DMATOTCOUNT ====================================================== */ -#define MSPI0_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< MSPI0 DMATOTCOUNT: TOTCOUNT (Bit 0) */ -#define MSPI0_DMATOTCOUNT_TOTCOUNT_Msk (0xffffffUL) /*!< MSPI0 DMATOTCOUNT: TOTCOUNT (Bitfield-Mask: 0xffffff) */ -/* ======================================================= DMABCOUNT ======================================================= */ -#define MSPI0_DMABCOUNT_BCOUNT_Pos (0UL) /*!< MSPI0 DMABCOUNT: BCOUNT (Bit 0) */ -#define MSPI0_DMABCOUNT_BCOUNT_Msk (0xffUL) /*!< MSPI0 DMABCOUNT: BCOUNT (Bitfield-Mask: 0xff) */ -/* ======================================================= DMATHRESH ======================================================= */ -#define MSPI0_DMATHRESH_DMARXTHRESH_Pos (8UL) /*!< MSPI0 DMATHRESH: DMARXTHRESH (Bit 8) */ -#define MSPI0_DMATHRESH_DMARXTHRESH_Msk (0x1f00UL) /*!< MSPI0 DMATHRESH: DMARXTHRESH (Bitfield-Mask: 0x1f) */ -#define MSPI0_DMATHRESH_DMATXTHRESH_Pos (0UL) /*!< MSPI0 DMATHRESH: DMATXTHRESH (Bit 0) */ -#define MSPI0_DMATHRESH_DMATXTHRESH_Msk (0x1fUL) /*!< MSPI0 DMATHRESH: DMATXTHRESH (Bitfield-Mask: 0x1f) */ -/* ====================================================== DMABOUNDARY ====================================================== */ -#define MSPI0_DMABOUNDARY_DMABOUND_Pos (12UL) /*!< MSPI0 DMABOUNDARY: DMABOUND (Bit 12) */ -#define MSPI0_DMABOUNDARY_DMABOUND_Msk (0xf000UL) /*!< MSPI0 DMABOUNDARY: DMABOUND (Bitfield-Mask: 0x0f) */ -#define MSPI0_DMABOUNDARY_DMATIMELIMIT_Pos (0UL) /*!< MSPI0 DMABOUNDARY: DMATIMELIMIT (Bit 0) */ -#define MSPI0_DMABOUNDARY_DMATIMELIMIT_Msk (0xfffUL) /*!< MSPI0 DMABOUNDARY: DMATIMELIMIT (Bitfield-Mask: 0xfff) */ -/* ========================================================= CQCFG ========================================================= */ -#define MSPI0_CQCFG_CQAUTOCLEARMASK_Pos (3UL) /*!< MSPI0 CQCFG: CQAUTOCLEARMASK (Bit 3) */ -#define MSPI0_CQCFG_CQAUTOCLEARMASK_Msk (0x8UL) /*!< MSPI0 CQCFG: CQAUTOCLEARMASK (Bitfield-Mask: 0x01) */ -#define MSPI0_CQCFG_CQPWROFF_Pos (2UL) /*!< MSPI0 CQCFG: CQPWROFF (Bit 2) */ -#define MSPI0_CQCFG_CQPWROFF_Msk (0x4UL) /*!< MSPI0 CQCFG: CQPWROFF (Bitfield-Mask: 0x01) */ -#define MSPI0_CQCFG_CQPRI_Pos (1UL) /*!< MSPI0 CQCFG: CQPRI (Bit 1) */ -#define MSPI0_CQCFG_CQPRI_Msk (0x2UL) /*!< MSPI0 CQCFG: CQPRI (Bitfield-Mask: 0x01) */ -#define MSPI0_CQCFG_CQEN_Pos (0UL) /*!< MSPI0 CQCFG: CQEN (Bit 0) */ -#define MSPI0_CQCFG_CQEN_Msk (0x1UL) /*!< MSPI0 CQCFG: CQEN (Bitfield-Mask: 0x01) */ -/* ======================================================== CQADDR ========================================================= */ -#define MSPI0_CQADDR_CQADDR_Pos (0UL) /*!< MSPI0 CQADDR: CQADDR (Bit 0) */ -#define MSPI0_CQADDR_CQADDR_Msk (0x1fffffffUL) /*!< MSPI0 CQADDR: CQADDR (Bitfield-Mask: 0x1fffffff) */ -/* ======================================================== CQSTAT ========================================================= */ -#define MSPI0_CQSTAT_CQPAUSED_Pos (3UL) /*!< MSPI0 CQSTAT: CQPAUSED (Bit 3) */ -#define MSPI0_CQSTAT_CQPAUSED_Msk (0x8UL) /*!< MSPI0 CQSTAT: CQPAUSED (Bitfield-Mask: 0x01) */ -#define MSPI0_CQSTAT_CQERR_Pos (2UL) /*!< MSPI0 CQSTAT: CQERR (Bit 2) */ -#define MSPI0_CQSTAT_CQERR_Msk (0x4UL) /*!< MSPI0 CQSTAT: CQERR (Bitfield-Mask: 0x01) */ -#define MSPI0_CQSTAT_CQCPL_Pos (1UL) /*!< MSPI0 CQSTAT: CQCPL (Bit 1) */ -#define MSPI0_CQSTAT_CQCPL_Msk (0x2UL) /*!< MSPI0 CQSTAT: CQCPL (Bitfield-Mask: 0x01) */ -#define MSPI0_CQSTAT_CQTIP_Pos (0UL) /*!< MSPI0 CQSTAT: CQTIP (Bit 0) */ -#define MSPI0_CQSTAT_CQTIP_Msk (0x1UL) /*!< MSPI0 CQSTAT: CQTIP (Bitfield-Mask: 0x01) */ -/* ======================================================== CQFLAGS ======================================================== */ -#define MSPI0_CQFLAGS_CQFLAGS_Pos (0UL) /*!< MSPI0 CQFLAGS: CQFLAGS (Bit 0) */ -#define MSPI0_CQFLAGS_CQFLAGS_Msk (0xffffUL) /*!< MSPI0 CQFLAGS: CQFLAGS (Bitfield-Mask: 0xffff) */ -/* ====================================================== CQSETCLEAR ======================================================= */ -#define MSPI0_CQSETCLEAR_CQFCLR_Pos (16UL) /*!< MSPI0 CQSETCLEAR: CQFCLR (Bit 16) */ -#define MSPI0_CQSETCLEAR_CQFCLR_Msk (0xff0000UL) /*!< MSPI0 CQSETCLEAR: CQFCLR (Bitfield-Mask: 0xff) */ -#define MSPI0_CQSETCLEAR_CQFTOGGLE_Pos (8UL) /*!< MSPI0 CQSETCLEAR: CQFTOGGLE (Bit 8) */ -#define MSPI0_CQSETCLEAR_CQFTOGGLE_Msk (0xff00UL) /*!< MSPI0 CQSETCLEAR: CQFTOGGLE (Bitfield-Mask: 0xff) */ -#define MSPI0_CQSETCLEAR_CQFSET_Pos (0UL) /*!< MSPI0 CQSETCLEAR: CQFSET (Bit 0) */ -#define MSPI0_CQSETCLEAR_CQFSET_Msk (0xffUL) /*!< MSPI0 CQSETCLEAR: CQFSET (Bitfield-Mask: 0xff) */ -/* ======================================================== CQPAUSE ======================================================== */ -#define MSPI0_CQPAUSE_CQMASK_Pos (0UL) /*!< MSPI0 CQPAUSE: CQMASK (Bit 0) */ -#define MSPI0_CQPAUSE_CQMASK_Msk (0xffffUL) /*!< MSPI0 CQPAUSE: CQMASK (Bitfield-Mask: 0xffff) */ -/* ======================================================= CQCURIDX ======================================================== */ -#define MSPI0_CQCURIDX_CQCURIDX_Pos (0UL) /*!< MSPI0 CQCURIDX: CQCURIDX (Bit 0) */ -#define MSPI0_CQCURIDX_CQCURIDX_Msk (0xffUL) /*!< MSPI0 CQCURIDX: CQCURIDX (Bitfield-Mask: 0xff) */ -/* ======================================================= CQENDIDX ======================================================== */ -#define MSPI0_CQENDIDX_CQENDIDX_Pos (0UL) /*!< MSPI0 CQENDIDX: CQENDIDX (Bit 0) */ -#define MSPI0_CQENDIDX_CQENDIDX_Msk (0xffUL) /*!< MSPI0 CQENDIDX: CQENDIDX (Bitfield-Mask: 0xff) */ - - -/* =========================================================================================================================== */ -/* ================ PDM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PCFG ========================================================== */ -#define PDM_PCFG_LRSWAP_Pos (31UL) /*!< PDM PCFG: LRSWAP (Bit 31) */ -#define PDM_PCFG_LRSWAP_Msk (0x80000000UL) /*!< PDM PCFG: LRSWAP (Bitfield-Mask: 0x01) */ -#define PDM_PCFG_PGARIGHT_Pos (26UL) /*!< PDM PCFG: PGARIGHT (Bit 26) */ -#define PDM_PCFG_PGARIGHT_Msk (0x7c000000UL) /*!< PDM PCFG: PGARIGHT (Bitfield-Mask: 0x1f) */ -#define PDM_PCFG_PGALEFT_Pos (21UL) /*!< PDM PCFG: PGALEFT (Bit 21) */ -#define PDM_PCFG_PGALEFT_Msk (0x3e00000UL) /*!< PDM PCFG: PGALEFT (Bitfield-Mask: 0x1f) */ -#define PDM_PCFG_MCLKDIV_Pos (17UL) /*!< PDM PCFG: MCLKDIV (Bit 17) */ -#define PDM_PCFG_MCLKDIV_Msk (0x60000UL) /*!< PDM PCFG: MCLKDIV (Bitfield-Mask: 0x03) */ -#define PDM_PCFG_SINCRATE_Pos (10UL) /*!< PDM PCFG: SINCRATE (Bit 10) */ -#define PDM_PCFG_SINCRATE_Msk (0x1fc00UL) /*!< PDM PCFG: SINCRATE (Bitfield-Mask: 0x7f) */ -#define PDM_PCFG_ADCHPD_Pos (9UL) /*!< PDM PCFG: ADCHPD (Bit 9) */ -#define PDM_PCFG_ADCHPD_Msk (0x200UL) /*!< PDM PCFG: ADCHPD (Bitfield-Mask: 0x01) */ -#define PDM_PCFG_HPCUTOFF_Pos (5UL) /*!< PDM PCFG: HPCUTOFF (Bit 5) */ -#define PDM_PCFG_HPCUTOFF_Msk (0x1e0UL) /*!< PDM PCFG: HPCUTOFF (Bitfield-Mask: 0x0f) */ -#define PDM_PCFG_CYCLES_Pos (2UL) /*!< PDM PCFG: CYCLES (Bit 2) */ -#define PDM_PCFG_CYCLES_Msk (0x1cUL) /*!< PDM PCFG: CYCLES (Bitfield-Mask: 0x07) */ -#define PDM_PCFG_SOFTMUTE_Pos (1UL) /*!< PDM PCFG: SOFTMUTE (Bit 1) */ -#define PDM_PCFG_SOFTMUTE_Msk (0x2UL) /*!< PDM PCFG: SOFTMUTE (Bitfield-Mask: 0x01) */ -#define PDM_PCFG_PDMCOREEN_Pos (0UL) /*!< PDM PCFG: PDMCOREEN (Bit 0) */ -#define PDM_PCFG_PDMCOREEN_Msk (0x1UL) /*!< PDM PCFG: PDMCOREEN (Bitfield-Mask: 0x01) */ -/* ========================================================= VCFG ========================================================== */ -#define PDM_VCFG_IOCLKEN_Pos (31UL) /*!< PDM VCFG: IOCLKEN (Bit 31) */ -#define PDM_VCFG_IOCLKEN_Msk (0x80000000UL) /*!< PDM VCFG: IOCLKEN (Bitfield-Mask: 0x01) */ -#define PDM_VCFG_RSTB_Pos (30UL) /*!< PDM VCFG: RSTB (Bit 30) */ -#define PDM_VCFG_RSTB_Msk (0x40000000UL) /*!< PDM VCFG: RSTB (Bitfield-Mask: 0x01) */ -#define PDM_VCFG_PDMCLKSEL_Pos (27UL) /*!< PDM VCFG: PDMCLKSEL (Bit 27) */ -#define PDM_VCFG_PDMCLKSEL_Msk (0x38000000UL) /*!< PDM VCFG: PDMCLKSEL (Bitfield-Mask: 0x07) */ -#define PDM_VCFG_PDMCLKEN_Pos (26UL) /*!< PDM VCFG: PDMCLKEN (Bit 26) */ -#define PDM_VCFG_PDMCLKEN_Msk (0x4000000UL) /*!< PDM VCFG: PDMCLKEN (Bitfield-Mask: 0x01) */ -#define PDM_VCFG_I2SEN_Pos (20UL) /*!< PDM VCFG: I2SEN (Bit 20) */ -#define PDM_VCFG_I2SEN_Msk (0x100000UL) /*!< PDM VCFG: I2SEN (Bitfield-Mask: 0x01) */ -#define PDM_VCFG_BCLKINV_Pos (19UL) /*!< PDM VCFG: BCLKINV (Bit 19) */ -#define PDM_VCFG_BCLKINV_Msk (0x80000UL) /*!< PDM VCFG: BCLKINV (Bitfield-Mask: 0x01) */ -#define PDM_VCFG_DMICKDEL_Pos (17UL) /*!< PDM VCFG: DMICKDEL (Bit 17) */ -#define PDM_VCFG_DMICKDEL_Msk (0x20000UL) /*!< PDM VCFG: DMICKDEL (Bitfield-Mask: 0x01) */ -#define PDM_VCFG_SELAP_Pos (16UL) /*!< PDM VCFG: SELAP (Bit 16) */ -#define PDM_VCFG_SELAP_Msk (0x10000UL) /*!< PDM VCFG: SELAP (Bitfield-Mask: 0x01) */ -#define PDM_VCFG_PCMPACK_Pos (8UL) /*!< PDM VCFG: PCMPACK (Bit 8) */ -#define PDM_VCFG_PCMPACK_Msk (0x100UL) /*!< PDM VCFG: PCMPACK (Bitfield-Mask: 0x01) */ -#define PDM_VCFG_CHSET_Pos (3UL) /*!< PDM VCFG: CHSET (Bit 3) */ -#define PDM_VCFG_CHSET_Msk (0x18UL) /*!< PDM VCFG: CHSET (Bitfield-Mask: 0x03) */ -/* ======================================================= VOICESTAT ======================================================= */ -#define PDM_VOICESTAT_FIFOCNT_Pos (0UL) /*!< PDM VOICESTAT: FIFOCNT (Bit 0) */ -#define PDM_VOICESTAT_FIFOCNT_Msk (0x3fUL) /*!< PDM VOICESTAT: FIFOCNT (Bitfield-Mask: 0x3f) */ -/* ======================================================= FIFOREAD ======================================================== */ -#define PDM_FIFOREAD_FIFOREAD_Pos (0UL) /*!< PDM FIFOREAD: FIFOREAD (Bit 0) */ -#define PDM_FIFOREAD_FIFOREAD_Msk (0xffffffffUL) /*!< PDM FIFOREAD: FIFOREAD (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= FIFOFLUSH ======================================================= */ -#define PDM_FIFOFLUSH_FIFOFLUSH_Pos (0UL) /*!< PDM FIFOFLUSH: FIFOFLUSH (Bit 0) */ -#define PDM_FIFOFLUSH_FIFOFLUSH_Msk (0x1UL) /*!< PDM FIFOFLUSH: FIFOFLUSH (Bitfield-Mask: 0x01) */ -/* ======================================================== FIFOTHR ======================================================== */ -#define PDM_FIFOTHR_FIFOTHR_Pos (0UL) /*!< PDM FIFOTHR: FIFOTHR (Bit 0) */ -#define PDM_FIFOTHR_FIFOTHR_Msk (0x1fUL) /*!< PDM FIFOTHR: FIFOTHR (Bitfield-Mask: 0x1f) */ -/* ========================================================= INTEN ========================================================= */ -#define PDM_INTEN_DERR_Pos (4UL) /*!< PDM INTEN: DERR (Bit 4) */ -#define PDM_INTEN_DERR_Msk (0x10UL) /*!< PDM INTEN: DERR (Bitfield-Mask: 0x01) */ -#define PDM_INTEN_DCMP_Pos (3UL) /*!< PDM INTEN: DCMP (Bit 3) */ -#define PDM_INTEN_DCMP_Msk (0x8UL) /*!< PDM INTEN: DCMP (Bitfield-Mask: 0x01) */ -#define PDM_INTEN_UNDFL_Pos (2UL) /*!< PDM INTEN: UNDFL (Bit 2) */ -#define PDM_INTEN_UNDFL_Msk (0x4UL) /*!< PDM INTEN: UNDFL (Bitfield-Mask: 0x01) */ -#define PDM_INTEN_OVF_Pos (1UL) /*!< PDM INTEN: OVF (Bit 1) */ -#define PDM_INTEN_OVF_Msk (0x2UL) /*!< PDM INTEN: OVF (Bitfield-Mask: 0x01) */ -#define PDM_INTEN_THR_Pos (0UL) /*!< PDM INTEN: THR (Bit 0) */ -#define PDM_INTEN_THR_Msk (0x1UL) /*!< PDM INTEN: THR (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTAT ======================================================== */ -#define PDM_INTSTAT_DERR_Pos (4UL) /*!< PDM INTSTAT: DERR (Bit 4) */ -#define PDM_INTSTAT_DERR_Msk (0x10UL) /*!< PDM INTSTAT: DERR (Bitfield-Mask: 0x01) */ -#define PDM_INTSTAT_DCMP_Pos (3UL) /*!< PDM INTSTAT: DCMP (Bit 3) */ -#define PDM_INTSTAT_DCMP_Msk (0x8UL) /*!< PDM INTSTAT: DCMP (Bitfield-Mask: 0x01) */ -#define PDM_INTSTAT_UNDFL_Pos (2UL) /*!< PDM INTSTAT: UNDFL (Bit 2) */ -#define PDM_INTSTAT_UNDFL_Msk (0x4UL) /*!< PDM INTSTAT: UNDFL (Bitfield-Mask: 0x01) */ -#define PDM_INTSTAT_OVF_Pos (1UL) /*!< PDM INTSTAT: OVF (Bit 1) */ -#define PDM_INTSTAT_OVF_Msk (0x2UL) /*!< PDM INTSTAT: OVF (Bitfield-Mask: 0x01) */ -#define PDM_INTSTAT_THR_Pos (0UL) /*!< PDM INTSTAT: THR (Bit 0) */ -#define PDM_INTSTAT_THR_Msk (0x1UL) /*!< PDM INTSTAT: THR (Bitfield-Mask: 0x01) */ -/* ======================================================== INTCLR ========================================================= */ -#define PDM_INTCLR_DERR_Pos (4UL) /*!< PDM INTCLR: DERR (Bit 4) */ -#define PDM_INTCLR_DERR_Msk (0x10UL) /*!< PDM INTCLR: DERR (Bitfield-Mask: 0x01) */ -#define PDM_INTCLR_DCMP_Pos (3UL) /*!< PDM INTCLR: DCMP (Bit 3) */ -#define PDM_INTCLR_DCMP_Msk (0x8UL) /*!< PDM INTCLR: DCMP (Bitfield-Mask: 0x01) */ -#define PDM_INTCLR_UNDFL_Pos (2UL) /*!< PDM INTCLR: UNDFL (Bit 2) */ -#define PDM_INTCLR_UNDFL_Msk (0x4UL) /*!< PDM INTCLR: UNDFL (Bitfield-Mask: 0x01) */ -#define PDM_INTCLR_OVF_Pos (1UL) /*!< PDM INTCLR: OVF (Bit 1) */ -#define PDM_INTCLR_OVF_Msk (0x2UL) /*!< PDM INTCLR: OVF (Bitfield-Mask: 0x01) */ -#define PDM_INTCLR_THR_Pos (0UL) /*!< PDM INTCLR: THR (Bit 0) */ -#define PDM_INTCLR_THR_Msk (0x1UL) /*!< PDM INTCLR: THR (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSET ========================================================= */ -#define PDM_INTSET_DERR_Pos (4UL) /*!< PDM INTSET: DERR (Bit 4) */ -#define PDM_INTSET_DERR_Msk (0x10UL) /*!< PDM INTSET: DERR (Bitfield-Mask: 0x01) */ -#define PDM_INTSET_DCMP_Pos (3UL) /*!< PDM INTSET: DCMP (Bit 3) */ -#define PDM_INTSET_DCMP_Msk (0x8UL) /*!< PDM INTSET: DCMP (Bitfield-Mask: 0x01) */ -#define PDM_INTSET_UNDFL_Pos (2UL) /*!< PDM INTSET: UNDFL (Bit 2) */ -#define PDM_INTSET_UNDFL_Msk (0x4UL) /*!< PDM INTSET: UNDFL (Bitfield-Mask: 0x01) */ -#define PDM_INTSET_OVF_Pos (1UL) /*!< PDM INTSET: OVF (Bit 1) */ -#define PDM_INTSET_OVF_Msk (0x2UL) /*!< PDM INTSET: OVF (Bitfield-Mask: 0x01) */ -#define PDM_INTSET_THR_Pos (0UL) /*!< PDM INTSET: THR (Bit 0) */ -#define PDM_INTSET_THR_Msk (0x1UL) /*!< PDM INTSET: THR (Bitfield-Mask: 0x01) */ -/* ======================================================= DMATRIGEN ======================================================= */ -#define PDM_DMATRIGEN_DTHR90_Pos (1UL) /*!< PDM DMATRIGEN: DTHR90 (Bit 1) */ -#define PDM_DMATRIGEN_DTHR90_Msk (0x2UL) /*!< PDM DMATRIGEN: DTHR90 (Bitfield-Mask: 0x01) */ -#define PDM_DMATRIGEN_DTHR_Pos (0UL) /*!< PDM DMATRIGEN: DTHR (Bit 0) */ -#define PDM_DMATRIGEN_DTHR_Msk (0x1UL) /*!< PDM DMATRIGEN: DTHR (Bitfield-Mask: 0x01) */ -/* ====================================================== DMATRIGSTAT ====================================================== */ -#define PDM_DMATRIGSTAT_DTHR90STAT_Pos (1UL) /*!< PDM DMATRIGSTAT: DTHR90STAT (Bit 1) */ -#define PDM_DMATRIGSTAT_DTHR90STAT_Msk (0x2UL) /*!< PDM DMATRIGSTAT: DTHR90STAT (Bitfield-Mask: 0x01) */ -#define PDM_DMATRIGSTAT_DTHRSTAT_Pos (0UL) /*!< PDM DMATRIGSTAT: DTHRSTAT (Bit 0) */ -#define PDM_DMATRIGSTAT_DTHRSTAT_Msk (0x1UL) /*!< PDM DMATRIGSTAT: DTHRSTAT (Bitfield-Mask: 0x01) */ -/* ======================================================== DMACFG ========================================================= */ -#define PDM_DMACFG_DPWROFF_Pos (10UL) /*!< PDM DMACFG: DPWROFF (Bit 10) */ -#define PDM_DMACFG_DPWROFF_Msk (0x400UL) /*!< PDM DMACFG: DPWROFF (Bitfield-Mask: 0x01) */ -#define PDM_DMACFG_DAUTOHIP_Pos (9UL) /*!< PDM DMACFG: DAUTOHIP (Bit 9) */ -#define PDM_DMACFG_DAUTOHIP_Msk (0x200UL) /*!< PDM DMACFG: DAUTOHIP (Bitfield-Mask: 0x01) */ -#define PDM_DMACFG_DMAPRI_Pos (8UL) /*!< PDM DMACFG: DMAPRI (Bit 8) */ -#define PDM_DMACFG_DMAPRI_Msk (0x100UL) /*!< PDM DMACFG: DMAPRI (Bitfield-Mask: 0x01) */ -#define PDM_DMACFG_DMADIR_Pos (2UL) /*!< PDM DMACFG: DMADIR (Bit 2) */ -#define PDM_DMACFG_DMADIR_Msk (0x4UL) /*!< PDM DMACFG: DMADIR (Bitfield-Mask: 0x01) */ -#define PDM_DMACFG_DMAEN_Pos (0UL) /*!< PDM DMACFG: DMAEN (Bit 0) */ -#define PDM_DMACFG_DMAEN_Msk (0x1UL) /*!< PDM DMACFG: DMAEN (Bitfield-Mask: 0x01) */ -/* ====================================================== DMATOTCOUNT ====================================================== */ -#define PDM_DMATOTCOUNT_TOTCOUNT_Pos (0UL) /*!< PDM DMATOTCOUNT: TOTCOUNT (Bit 0) */ -#define PDM_DMATOTCOUNT_TOTCOUNT_Msk (0xfffffUL) /*!< PDM DMATOTCOUNT: TOTCOUNT (Bitfield-Mask: 0xfffff) */ -/* ====================================================== DMATARGADDR ====================================================== */ -#define PDM_DMATARGADDR_UTARGADDR_Pos (21UL) /*!< PDM DMATARGADDR: UTARGADDR (Bit 21) */ -#define PDM_DMATARGADDR_UTARGADDR_Msk (0xffe00000UL) /*!< PDM DMATARGADDR: UTARGADDR (Bitfield-Mask: 0x7ff) */ -#define PDM_DMATARGADDR_LTARGADDR_Pos (0UL) /*!< PDM DMATARGADDR: LTARGADDR (Bit 0) */ -#define PDM_DMATARGADDR_LTARGADDR_Msk (0x1fffffUL) /*!< PDM DMATARGADDR: LTARGADDR (Bitfield-Mask: 0x1fffff) */ -/* ======================================================== DMASTAT ======================================================== */ -#define PDM_DMASTAT_DMAERR_Pos (2UL) /*!< PDM DMASTAT: DMAERR (Bit 2) */ -#define PDM_DMASTAT_DMAERR_Msk (0x4UL) /*!< PDM DMASTAT: DMAERR (Bitfield-Mask: 0x01) */ -#define PDM_DMASTAT_DMACPL_Pos (1UL) /*!< PDM DMASTAT: DMACPL (Bit 1) */ -#define PDM_DMASTAT_DMACPL_Msk (0x2UL) /*!< PDM DMASTAT: DMACPL (Bitfield-Mask: 0x01) */ -#define PDM_DMASTAT_DMATIP_Pos (0UL) /*!< PDM DMASTAT: DMATIP (Bit 0) */ -#define PDM_DMASTAT_DMATIP_Msk (0x1UL) /*!< PDM DMASTAT: DMATIP (Bitfield-Mask: 0x01) */ - - -/* =========================================================================================================================== */ -/* ================ PWRCTRL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================= SUPPLYSRC ======================================================= */ -#define PWRCTRL_SUPPLYSRC_BLEBUCKEN_Pos (0UL) /*!< PWRCTRL SUPPLYSRC: BLEBUCKEN (Bit 0) */ -#define PWRCTRL_SUPPLYSRC_BLEBUCKEN_Msk (0x1UL) /*!< PWRCTRL SUPPLYSRC: BLEBUCKEN (Bitfield-Mask: 0x01) */ -/* ===================================================== SUPPLYSTATUS ====================================================== */ -#define PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Pos (1UL) /*!< PWRCTRL SUPPLYSTATUS: BLEBUCKON (Bit 1) */ -#define PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Msk (0x2UL) /*!< PWRCTRL SUPPLYSTATUS: BLEBUCKON (Bitfield-Mask: 0x01) */ -#define PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Pos (0UL) /*!< PWRCTRL SUPPLYSTATUS: SIMOBUCKON (Bit 0) */ -#define PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Msk (0x1UL) /*!< PWRCTRL SUPPLYSTATUS: SIMOBUCKON (Bitfield-Mask: 0x01) */ -/* ======================================================= DEVPWREN ======================================================== */ -#define PWRCTRL_DEVPWREN_PWRBLEL_Pos (15UL) /*!< PWRCTRL DEVPWREN: PWRBLEL (Bit 15) */ -#define PWRCTRL_DEVPWREN_PWRBLEL_Msk (0x8000UL) /*!< PWRCTRL DEVPWREN: PWRBLEL (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREN_PWRPDM_Pos (14UL) /*!< PWRCTRL DEVPWREN: PWRPDM (Bit 14) */ -#define PWRCTRL_DEVPWREN_PWRPDM_Msk (0x4000UL) /*!< PWRCTRL DEVPWREN: PWRPDM (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREN_PWRMSPI2_Pos (13UL) /*!< PWRCTRL DEVPWREN: PWRMSPI2 (Bit 13) */ -#define PWRCTRL_DEVPWREN_PWRMSPI2_Msk (0x2000UL) /*!< PWRCTRL DEVPWREN: PWRMSPI2 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREN_PWRMSPI1_Pos (12UL) /*!< PWRCTRL DEVPWREN: PWRMSPI1 (Bit 12) */ -#define PWRCTRL_DEVPWREN_PWRMSPI1_Msk (0x1000UL) /*!< PWRCTRL DEVPWREN: PWRMSPI1 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREN_PWRMSPI0_Pos (11UL) /*!< PWRCTRL DEVPWREN: PWRMSPI0 (Bit 11) */ -#define PWRCTRL_DEVPWREN_PWRMSPI0_Msk (0x800UL) /*!< PWRCTRL DEVPWREN: PWRMSPI0 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREN_PWRSCARD_Pos (10UL) /*!< PWRCTRL DEVPWREN: PWRSCARD (Bit 10) */ -#define PWRCTRL_DEVPWREN_PWRSCARD_Msk (0x400UL) /*!< PWRCTRL DEVPWREN: PWRSCARD (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREN_PWRADC_Pos (9UL) /*!< PWRCTRL DEVPWREN: PWRADC (Bit 9) */ -#define PWRCTRL_DEVPWREN_PWRADC_Msk (0x200UL) /*!< PWRCTRL DEVPWREN: PWRADC (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREN_PWRUART1_Pos (8UL) /*!< PWRCTRL DEVPWREN: PWRUART1 (Bit 8) */ -#define PWRCTRL_DEVPWREN_PWRUART1_Msk (0x100UL) /*!< PWRCTRL DEVPWREN: PWRUART1 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREN_PWRUART0_Pos (7UL) /*!< PWRCTRL DEVPWREN: PWRUART0 (Bit 7) */ -#define PWRCTRL_DEVPWREN_PWRUART0_Msk (0x80UL) /*!< PWRCTRL DEVPWREN: PWRUART0 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREN_PWRIOM5_Pos (6UL) /*!< PWRCTRL DEVPWREN: PWRIOM5 (Bit 6) */ -#define PWRCTRL_DEVPWREN_PWRIOM5_Msk (0x40UL) /*!< PWRCTRL DEVPWREN: PWRIOM5 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREN_PWRIOM4_Pos (5UL) /*!< PWRCTRL DEVPWREN: PWRIOM4 (Bit 5) */ -#define PWRCTRL_DEVPWREN_PWRIOM4_Msk (0x20UL) /*!< PWRCTRL DEVPWREN: PWRIOM4 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREN_PWRIOM3_Pos (4UL) /*!< PWRCTRL DEVPWREN: PWRIOM3 (Bit 4) */ -#define PWRCTRL_DEVPWREN_PWRIOM3_Msk (0x10UL) /*!< PWRCTRL DEVPWREN: PWRIOM3 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREN_PWRIOM2_Pos (3UL) /*!< PWRCTRL DEVPWREN: PWRIOM2 (Bit 3) */ -#define PWRCTRL_DEVPWREN_PWRIOM2_Msk (0x8UL) /*!< PWRCTRL DEVPWREN: PWRIOM2 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREN_PWRIOM1_Pos (2UL) /*!< PWRCTRL DEVPWREN: PWRIOM1 (Bit 2) */ -#define PWRCTRL_DEVPWREN_PWRIOM1_Msk (0x4UL) /*!< PWRCTRL DEVPWREN: PWRIOM1 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREN_PWRIOM0_Pos (1UL) /*!< PWRCTRL DEVPWREN: PWRIOM0 (Bit 1) */ -#define PWRCTRL_DEVPWREN_PWRIOM0_Msk (0x2UL) /*!< PWRCTRL DEVPWREN: PWRIOM0 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREN_PWRIOS_Pos (0UL) /*!< PWRCTRL DEVPWREN: PWRIOS (Bit 0) */ -#define PWRCTRL_DEVPWREN_PWRIOS_Msk (0x1UL) /*!< PWRCTRL DEVPWREN: PWRIOS (Bitfield-Mask: 0x01) */ -/* ===================================================== MEMPWDINSLEEP ===================================================== */ -#define PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Pos (31UL) /*!< PWRCTRL MEMPWDINSLEEP: CACHEPWDSLP (Bit 31) */ -#define PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Msk (0x80000000UL) /*!< PWRCTRL MEMPWDINSLEEP: CACHEPWDSLP (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Pos (14UL) /*!< PWRCTRL MEMPWDINSLEEP: FLASH1PWDSLP (Bit 14) */ -#define PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Msk (0x4000UL) /*!< PWRCTRL MEMPWDINSLEEP: FLASH1PWDSLP (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Pos (13UL) /*!< PWRCTRL MEMPWDINSLEEP: FLASH0PWDSLP (Bit 13) */ -#define PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk (0x2000UL) /*!< PWRCTRL MEMPWDINSLEEP: FLASH0PWDSLP (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Pos (3UL) /*!< PWRCTRL MEMPWDINSLEEP: SRAMPWDSLP (Bit 3) */ -#define PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Msk (0x1ff8UL) /*!< PWRCTRL MEMPWDINSLEEP: SRAMPWDSLP (Bitfield-Mask: 0x3ff) */ -#define PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Pos (0UL) /*!< PWRCTRL MEMPWDINSLEEP: DTCMPWDSLP (Bit 0) */ -#define PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Msk (0x7UL) /*!< PWRCTRL MEMPWDINSLEEP: DTCMPWDSLP (Bitfield-Mask: 0x07) */ -/* ======================================================= MEMPWREN ======================================================== */ -#define PWRCTRL_MEMPWREN_CACHEB2_Pos (31UL) /*!< PWRCTRL MEMPWREN: CACHEB2 (Bit 31) */ -#define PWRCTRL_MEMPWREN_CACHEB2_Msk (0x80000000UL) /*!< PWRCTRL MEMPWREN: CACHEB2 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWREN_CACHEB0_Pos (30UL) /*!< PWRCTRL MEMPWREN: CACHEB0 (Bit 30) */ -#define PWRCTRL_MEMPWREN_CACHEB0_Msk (0x40000000UL) /*!< PWRCTRL MEMPWREN: CACHEB0 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWREN_FLASH1_Pos (14UL) /*!< PWRCTRL MEMPWREN: FLASH1 (Bit 14) */ -#define PWRCTRL_MEMPWREN_FLASH1_Msk (0x4000UL) /*!< PWRCTRL MEMPWREN: FLASH1 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWREN_FLASH0_Pos (13UL) /*!< PWRCTRL MEMPWREN: FLASH0 (Bit 13) */ -#define PWRCTRL_MEMPWREN_FLASH0_Msk (0x2000UL) /*!< PWRCTRL MEMPWREN: FLASH0 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWREN_SRAM_Pos (3UL) /*!< PWRCTRL MEMPWREN: SRAM (Bit 3) */ -#define PWRCTRL_MEMPWREN_SRAM_Msk (0x1ff8UL) /*!< PWRCTRL MEMPWREN: SRAM (Bitfield-Mask: 0x3ff) */ -#define PWRCTRL_MEMPWREN_DTCM_Pos (0UL) /*!< PWRCTRL MEMPWREN: DTCM (Bit 0) */ -#define PWRCTRL_MEMPWREN_DTCM_Msk (0x7UL) /*!< PWRCTRL MEMPWREN: DTCM (Bitfield-Mask: 0x07) */ -/* ===================================================== MEMPWRSTATUS ====================================================== */ -#define PWRCTRL_MEMPWRSTATUS_CACHEB2_Pos (16UL) /*!< PWRCTRL MEMPWRSTATUS: CACHEB2 (Bit 16) */ -#define PWRCTRL_MEMPWRSTATUS_CACHEB2_Msk (0x10000UL) /*!< PWRCTRL MEMPWRSTATUS: CACHEB2 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_CACHEB0_Pos (15UL) /*!< PWRCTRL MEMPWRSTATUS: CACHEB0 (Bit 15) */ -#define PWRCTRL_MEMPWRSTATUS_CACHEB0_Msk (0x8000UL) /*!< PWRCTRL MEMPWRSTATUS: CACHEB0 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_FLASH1_Pos (14UL) /*!< PWRCTRL MEMPWRSTATUS: FLASH1 (Bit 14) */ -#define PWRCTRL_MEMPWRSTATUS_FLASH1_Msk (0x4000UL) /*!< PWRCTRL MEMPWRSTATUS: FLASH1 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_FLASH0_Pos (13UL) /*!< PWRCTRL MEMPWRSTATUS: FLASH0 (Bit 13) */ -#define PWRCTRL_MEMPWRSTATUS_FLASH0_Msk (0x2000UL) /*!< PWRCTRL MEMPWRSTATUS: FLASH0 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM9_Pos (12UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM9 (Bit 12) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM9_Msk (0x1000UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM9 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM8_Pos (11UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM8 (Bit 11) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM8_Msk (0x800UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM8 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM7_Pos (10UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM7 (Bit 10) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM7_Msk (0x400UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM7 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM6_Pos (9UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM6 (Bit 9) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM6_Msk (0x200UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM6 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM5_Pos (8UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM5 (Bit 8) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM5_Msk (0x100UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM5 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM4_Pos (7UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM4 (Bit 7) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM4_Msk (0x80UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM4 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM3_Pos (6UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM3 (Bit 6) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM3_Msk (0x40UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM3 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM2_Pos (5UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM2 (Bit 5) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM2_Msk (0x20UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM2 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM1_Pos (4UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM1 (Bit 4) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM1_Msk (0x10UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM1 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM0_Pos (3UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM0 (Bit 3) */ -#define PWRCTRL_MEMPWRSTATUS_SRAM0_Msk (0x8UL) /*!< PWRCTRL MEMPWRSTATUS: SRAM0 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_DTCM1_Pos (2UL) /*!< PWRCTRL MEMPWRSTATUS: DTCM1 (Bit 2) */ -#define PWRCTRL_MEMPWRSTATUS_DTCM1_Msk (0x4UL) /*!< PWRCTRL MEMPWRSTATUS: DTCM1 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_DTCM01_Pos (1UL) /*!< PWRCTRL MEMPWRSTATUS: DTCM01 (Bit 1) */ -#define PWRCTRL_MEMPWRSTATUS_DTCM01_Msk (0x2UL) /*!< PWRCTRL MEMPWRSTATUS: DTCM01 (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWRSTATUS_DTCM00_Pos (0UL) /*!< PWRCTRL MEMPWRSTATUS: DTCM00 (Bit 0) */ -#define PWRCTRL_MEMPWRSTATUS_DTCM00_Msk (0x1UL) /*!< PWRCTRL MEMPWRSTATUS: DTCM00 (Bitfield-Mask: 0x01) */ -/* ===================================================== DEVPWRSTATUS ====================================================== */ -#define PWRCTRL_DEVPWRSTATUS_BLEH_Pos (9UL) /*!< PWRCTRL DEVPWRSTATUS: BLEH (Bit 9) */ -#define PWRCTRL_DEVPWRSTATUS_BLEH_Msk (0x200UL) /*!< PWRCTRL DEVPWRSTATUS: BLEH (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWRSTATUS_BLEL_Pos (8UL) /*!< PWRCTRL DEVPWRSTATUS: BLEL (Bit 8) */ -#define PWRCTRL_DEVPWRSTATUS_BLEL_Msk (0x100UL) /*!< PWRCTRL DEVPWRSTATUS: BLEL (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWRSTATUS_PWRPDM_Pos (7UL) /*!< PWRCTRL DEVPWRSTATUS: PWRPDM (Bit 7) */ -#define PWRCTRL_DEVPWRSTATUS_PWRPDM_Msk (0x80UL) /*!< PWRCTRL DEVPWRSTATUS: PWRPDM (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWRSTATUS_PWRMSPI_Pos (6UL) /*!< PWRCTRL DEVPWRSTATUS: PWRMSPI (Bit 6) */ -#define PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk (0x40UL) /*!< PWRCTRL DEVPWRSTATUS: PWRMSPI (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWRSTATUS_PWRADC_Pos (5UL) /*!< PWRCTRL DEVPWRSTATUS: PWRADC (Bit 5) */ -#define PWRCTRL_DEVPWRSTATUS_PWRADC_Msk (0x20UL) /*!< PWRCTRL DEVPWRSTATUS: PWRADC (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWRSTATUS_HCPC_Pos (4UL) /*!< PWRCTRL DEVPWRSTATUS: HCPC (Bit 4) */ -#define PWRCTRL_DEVPWRSTATUS_HCPC_Msk (0x10UL) /*!< PWRCTRL DEVPWRSTATUS: HCPC (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWRSTATUS_HCPB_Pos (3UL) /*!< PWRCTRL DEVPWRSTATUS: HCPB (Bit 3) */ -#define PWRCTRL_DEVPWRSTATUS_HCPB_Msk (0x8UL) /*!< PWRCTRL DEVPWRSTATUS: HCPB (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWRSTATUS_HCPA_Pos (2UL) /*!< PWRCTRL DEVPWRSTATUS: HCPA (Bit 2) */ -#define PWRCTRL_DEVPWRSTATUS_HCPA_Msk (0x4UL) /*!< PWRCTRL DEVPWRSTATUS: HCPA (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWRSTATUS_MCUH_Pos (1UL) /*!< PWRCTRL DEVPWRSTATUS: MCUH (Bit 1) */ -#define PWRCTRL_DEVPWRSTATUS_MCUH_Msk (0x2UL) /*!< PWRCTRL DEVPWRSTATUS: MCUH (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWRSTATUS_MCUL_Pos (0UL) /*!< PWRCTRL DEVPWRSTATUS: MCUL (Bit 0) */ -#define PWRCTRL_DEVPWRSTATUS_MCUL_Msk (0x1UL) /*!< PWRCTRL DEVPWRSTATUS: MCUL (Bitfield-Mask: 0x01) */ -/* ======================================================= SRAMCTRL ======================================================== */ -#define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Pos (8UL) /*!< PWRCTRL SRAMCTRL: SRAMLIGHTSLEEP (Bit 8) */ -#define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Msk (0xfff00UL) /*!< PWRCTRL SRAMCTRL: SRAMLIGHTSLEEP (Bitfield-Mask: 0xfff) */ -#define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Pos (2UL) /*!< PWRCTRL SRAMCTRL: SRAMMASTERCLKGATE (Bit 2) */ -#define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Msk (0x4UL) /*!< PWRCTRL SRAMCTRL: SRAMMASTERCLKGATE (Bitfield-Mask: 0x01) */ -#define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Pos (1UL) /*!< PWRCTRL SRAMCTRL: SRAMCLKGATE (Bit 1) */ -#define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Msk (0x2UL) /*!< PWRCTRL SRAMCTRL: SRAMCLKGATE (Bitfield-Mask: 0x01) */ -/* ======================================================= ADCSTATUS ======================================================= */ -#define PWRCTRL_ADCSTATUS_REFBUFPWD_Pos (5UL) /*!< PWRCTRL ADCSTATUS: REFBUFPWD (Bit 5) */ -#define PWRCTRL_ADCSTATUS_REFBUFPWD_Msk (0x20UL) /*!< PWRCTRL ADCSTATUS: REFBUFPWD (Bitfield-Mask: 0x01) */ -#define PWRCTRL_ADCSTATUS_REFKEEPPWD_Pos (4UL) /*!< PWRCTRL ADCSTATUS: REFKEEPPWD (Bit 4) */ -#define PWRCTRL_ADCSTATUS_REFKEEPPWD_Msk (0x10UL) /*!< PWRCTRL ADCSTATUS: REFKEEPPWD (Bitfield-Mask: 0x01) */ -#define PWRCTRL_ADCSTATUS_VBATPWD_Pos (3UL) /*!< PWRCTRL ADCSTATUS: VBATPWD (Bit 3) */ -#define PWRCTRL_ADCSTATUS_VBATPWD_Msk (0x8UL) /*!< PWRCTRL ADCSTATUS: VBATPWD (Bitfield-Mask: 0x01) */ -#define PWRCTRL_ADCSTATUS_VPTATPWD_Pos (2UL) /*!< PWRCTRL ADCSTATUS: VPTATPWD (Bit 2) */ -#define PWRCTRL_ADCSTATUS_VPTATPWD_Msk (0x4UL) /*!< PWRCTRL ADCSTATUS: VPTATPWD (Bitfield-Mask: 0x01) */ -#define PWRCTRL_ADCSTATUS_BGTPWD_Pos (1UL) /*!< PWRCTRL ADCSTATUS: BGTPWD (Bit 1) */ -#define PWRCTRL_ADCSTATUS_BGTPWD_Msk (0x2UL) /*!< PWRCTRL ADCSTATUS: BGTPWD (Bitfield-Mask: 0x01) */ -#define PWRCTRL_ADCSTATUS_ADCPWD_Pos (0UL) /*!< PWRCTRL ADCSTATUS: ADCPWD (Bit 0) */ -#define PWRCTRL_ADCSTATUS_ADCPWD_Msk (0x1UL) /*!< PWRCTRL ADCSTATUS: ADCPWD (Bitfield-Mask: 0x01) */ -/* ========================================================= MISC ========================================================== */ -#define PWRCTRL_MISC_MEMVRLPBLE_Pos (6UL) /*!< PWRCTRL MISC: MEMVRLPBLE (Bit 6) */ -#define PWRCTRL_MISC_MEMVRLPBLE_Msk (0x40UL) /*!< PWRCTRL MISC: MEMVRLPBLE (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MISC_FORCEMEMVRLPTIMERS_Pos (3UL) /*!< PWRCTRL MISC: FORCEMEMVRLPTIMERS (Bit 3) */ -#define PWRCTRL_MISC_FORCEMEMVRLPTIMERS_Msk (0x8UL) /*!< PWRCTRL MISC: FORCEMEMVRLPTIMERS (Bitfield-Mask: 0x01) */ -/* ===================================================== DEVPWREVENTEN ===================================================== */ -#define PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Pos (31UL) /*!< PWRCTRL DEVPWREVENTEN: BURSTEVEN (Bit 31) */ -#define PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Msk (0x80000000UL) /*!< PWRCTRL DEVPWREVENTEN: BURSTEVEN (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Pos (30UL) /*!< PWRCTRL DEVPWREVENTEN: BURSTFEATUREEVEN (Bit 30) */ -#define PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Msk (0x40000000UL) /*!< PWRCTRL DEVPWREVENTEN: BURSTFEATUREEVEN (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Pos (29UL) /*!< PWRCTRL DEVPWREVENTEN: BLEFEATUREEVEN (Bit 29) */ -#define PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Msk (0x20000000UL) /*!< PWRCTRL DEVPWREVENTEN: BLEFEATUREEVEN (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREVENTEN_BLELEVEN_Pos (8UL) /*!< PWRCTRL DEVPWREVENTEN: BLELEVEN (Bit 8) */ -#define PWRCTRL_DEVPWREVENTEN_BLELEVEN_Msk (0x100UL) /*!< PWRCTRL DEVPWREVENTEN: BLELEVEN (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREVENTEN_PDMEVEN_Pos (7UL) /*!< PWRCTRL DEVPWREVENTEN: PDMEVEN (Bit 7) */ -#define PWRCTRL_DEVPWREVENTEN_PDMEVEN_Msk (0x80UL) /*!< PWRCTRL DEVPWREVENTEN: PDMEVEN (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Pos (6UL) /*!< PWRCTRL DEVPWREVENTEN: MSPIEVEN (Bit 6) */ -#define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Msk (0x40UL) /*!< PWRCTRL DEVPWREVENTEN: MSPIEVEN (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Pos (5UL) /*!< PWRCTRL DEVPWREVENTEN: ADCEVEN (Bit 5) */ -#define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Msk (0x20UL) /*!< PWRCTRL DEVPWREVENTEN: ADCEVEN (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Pos (4UL) /*!< PWRCTRL DEVPWREVENTEN: HCPCEVEN (Bit 4) */ -#define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Msk (0x10UL) /*!< PWRCTRL DEVPWREVENTEN: HCPCEVEN (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Pos (3UL) /*!< PWRCTRL DEVPWREVENTEN: HCPBEVEN (Bit 3) */ -#define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Msk (0x8UL) /*!< PWRCTRL DEVPWREVENTEN: HCPBEVEN (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Pos (2UL) /*!< PWRCTRL DEVPWREVENTEN: HCPAEVEN (Bit 2) */ -#define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Msk (0x4UL) /*!< PWRCTRL DEVPWREVENTEN: HCPAEVEN (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Pos (1UL) /*!< PWRCTRL DEVPWREVENTEN: MCUHEVEN (Bit 1) */ -#define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Msk (0x2UL) /*!< PWRCTRL DEVPWREVENTEN: MCUHEVEN (Bitfield-Mask: 0x01) */ -#define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Pos (0UL) /*!< PWRCTRL DEVPWREVENTEN: MCULEVEN (Bit 0) */ -#define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Msk (0x1UL) /*!< PWRCTRL DEVPWREVENTEN: MCULEVEN (Bitfield-Mask: 0x01) */ -/* ===================================================== MEMPWREVENTEN ===================================================== */ -#define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Pos (31UL) /*!< PWRCTRL MEMPWREVENTEN: CACHEB2EN (Bit 31) */ -#define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Msk (0x80000000UL) /*!< PWRCTRL MEMPWREVENTEN: CACHEB2EN (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Pos (30UL) /*!< PWRCTRL MEMPWREVENTEN: CACHEB0EN (Bit 30) */ -#define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Msk (0x40000000UL) /*!< PWRCTRL MEMPWREVENTEN: CACHEB0EN (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWREVENTEN_FLASH1EN_Pos (14UL) /*!< PWRCTRL MEMPWREVENTEN: FLASH1EN (Bit 14) */ -#define PWRCTRL_MEMPWREVENTEN_FLASH1EN_Msk (0x4000UL) /*!< PWRCTRL MEMPWREVENTEN: FLASH1EN (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWREVENTEN_FLASH0EN_Pos (13UL) /*!< PWRCTRL MEMPWREVENTEN: FLASH0EN (Bit 13) */ -#define PWRCTRL_MEMPWREVENTEN_FLASH0EN_Msk (0x2000UL) /*!< PWRCTRL MEMPWREVENTEN: FLASH0EN (Bitfield-Mask: 0x01) */ -#define PWRCTRL_MEMPWREVENTEN_SRAMEN_Pos (3UL) /*!< PWRCTRL MEMPWREVENTEN: SRAMEN (Bit 3) */ -#define PWRCTRL_MEMPWREVENTEN_SRAMEN_Msk (0x1ff8UL) /*!< PWRCTRL MEMPWREVENTEN: SRAMEN (Bitfield-Mask: 0x3ff) */ -#define PWRCTRL_MEMPWREVENTEN_DTCMEN_Pos (0UL) /*!< PWRCTRL MEMPWREVENTEN: DTCMEN (Bit 0) */ -#define PWRCTRL_MEMPWREVENTEN_DTCMEN_Msk (0x7UL) /*!< PWRCTRL MEMPWREVENTEN: DTCMEN (Bitfield-Mask: 0x07) */ - - -/* =========================================================================================================================== */ -/* ================ RSTGEN ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CFG ========================================================== */ -#define RSTGEN_CFG_WDREN_Pos (1UL) /*!< RSTGEN CFG: WDREN (Bit 1) */ -#define RSTGEN_CFG_WDREN_Msk (0x2UL) /*!< RSTGEN CFG: WDREN (Bitfield-Mask: 0x01) */ -#define RSTGEN_CFG_BODHREN_Pos (0UL) /*!< RSTGEN CFG: BODHREN (Bit 0) */ -#define RSTGEN_CFG_BODHREN_Msk (0x1UL) /*!< RSTGEN CFG: BODHREN (Bitfield-Mask: 0x01) */ -/* ========================================================= SWPOI ========================================================= */ -#define RSTGEN_SWPOI_SWPOIKEY_Pos (0UL) /*!< RSTGEN SWPOI: SWPOIKEY (Bit 0) */ -#define RSTGEN_SWPOI_SWPOIKEY_Msk (0xffUL) /*!< RSTGEN SWPOI: SWPOIKEY (Bitfield-Mask: 0xff) */ -/* ========================================================= SWPOR ========================================================= */ -#define RSTGEN_SWPOR_SWPORKEY_Pos (0UL) /*!< RSTGEN SWPOR: SWPORKEY (Bit 0) */ -#define RSTGEN_SWPOR_SWPORKEY_Msk (0xffUL) /*!< RSTGEN SWPOR: SWPORKEY (Bitfield-Mask: 0xff) */ -/* ======================================================== TPIURST ======================================================== */ -#define RSTGEN_TPIURST_TPIURST_Pos (0UL) /*!< RSTGEN TPIURST: TPIURST (Bit 0) */ -#define RSTGEN_TPIURST_TPIURST_Msk (0x1UL) /*!< RSTGEN TPIURST: TPIURST (Bitfield-Mask: 0x01) */ -/* ========================================================= INTEN ========================================================= */ -#define RSTGEN_INTEN_BODH_Pos (0UL) /*!< RSTGEN INTEN: BODH (Bit 0) */ -#define RSTGEN_INTEN_BODH_Msk (0x1UL) /*!< RSTGEN INTEN: BODH (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTAT ======================================================== */ -#define RSTGEN_INTSTAT_BODH_Pos (0UL) /*!< RSTGEN INTSTAT: BODH (Bit 0) */ -#define RSTGEN_INTSTAT_BODH_Msk (0x1UL) /*!< RSTGEN INTSTAT: BODH (Bitfield-Mask: 0x01) */ -/* ======================================================== INTCLR ========================================================= */ -#define RSTGEN_INTCLR_BODH_Pos (0UL) /*!< RSTGEN INTCLR: BODH (Bit 0) */ -#define RSTGEN_INTCLR_BODH_Msk (0x1UL) /*!< RSTGEN INTCLR: BODH (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSET ========================================================= */ -#define RSTGEN_INTSET_BODH_Pos (0UL) /*!< RSTGEN INTSET: BODH (Bit 0) */ -#define RSTGEN_INTSET_BODH_Msk (0x1UL) /*!< RSTGEN INTSET: BODH (Bitfield-Mask: 0x01) */ -/* ========================================================= STAT ========================================================== */ -#define RSTGEN_STAT_SBOOT_Pos (31UL) /*!< RSTGEN STAT: SBOOT (Bit 31) */ -#define RSTGEN_STAT_SBOOT_Msk (0x80000000UL) /*!< RSTGEN STAT: SBOOT (Bitfield-Mask: 0x01) */ -#define RSTGEN_STAT_FBOOT_Pos (30UL) /*!< RSTGEN STAT: FBOOT (Bit 30) */ -#define RSTGEN_STAT_FBOOT_Msk (0x40000000UL) /*!< RSTGEN STAT: FBOOT (Bitfield-Mask: 0x01) */ -#define RSTGEN_STAT_BOBSTAT_Pos (10UL) /*!< RSTGEN STAT: BOBSTAT (Bit 10) */ -#define RSTGEN_STAT_BOBSTAT_Msk (0x400UL) /*!< RSTGEN STAT: BOBSTAT (Bitfield-Mask: 0x01) */ -#define RSTGEN_STAT_BOFSTAT_Pos (9UL) /*!< RSTGEN STAT: BOFSTAT (Bit 9) */ -#define RSTGEN_STAT_BOFSTAT_Msk (0x200UL) /*!< RSTGEN STAT: BOFSTAT (Bitfield-Mask: 0x01) */ -#define RSTGEN_STAT_BOCSTAT_Pos (8UL) /*!< RSTGEN STAT: BOCSTAT (Bit 8) */ -#define RSTGEN_STAT_BOCSTAT_Msk (0x100UL) /*!< RSTGEN STAT: BOCSTAT (Bitfield-Mask: 0x01) */ -#define RSTGEN_STAT_BOUSTAT_Pos (7UL) /*!< RSTGEN STAT: BOUSTAT (Bit 7) */ -#define RSTGEN_STAT_BOUSTAT_Msk (0x80UL) /*!< RSTGEN STAT: BOUSTAT (Bitfield-Mask: 0x01) */ -#define RSTGEN_STAT_WDRSTAT_Pos (6UL) /*!< RSTGEN STAT: WDRSTAT (Bit 6) */ -#define RSTGEN_STAT_WDRSTAT_Msk (0x40UL) /*!< RSTGEN STAT: WDRSTAT (Bitfield-Mask: 0x01) */ -#define RSTGEN_STAT_DBGRSTAT_Pos (5UL) /*!< RSTGEN STAT: DBGRSTAT (Bit 5) */ -#define RSTGEN_STAT_DBGRSTAT_Msk (0x20UL) /*!< RSTGEN STAT: DBGRSTAT (Bitfield-Mask: 0x01) */ -#define RSTGEN_STAT_POIRSTAT_Pos (4UL) /*!< RSTGEN STAT: POIRSTAT (Bit 4) */ -#define RSTGEN_STAT_POIRSTAT_Msk (0x10UL) /*!< RSTGEN STAT: POIRSTAT (Bitfield-Mask: 0x01) */ -#define RSTGEN_STAT_SWRSTAT_Pos (3UL) /*!< RSTGEN STAT: SWRSTAT (Bit 3) */ -#define RSTGEN_STAT_SWRSTAT_Msk (0x8UL) /*!< RSTGEN STAT: SWRSTAT (Bitfield-Mask: 0x01) */ -#define RSTGEN_STAT_BORSTAT_Pos (2UL) /*!< RSTGEN STAT: BORSTAT (Bit 2) */ -#define RSTGEN_STAT_BORSTAT_Msk (0x4UL) /*!< RSTGEN STAT: BORSTAT (Bitfield-Mask: 0x01) */ -#define RSTGEN_STAT_PORSTAT_Pos (1UL) /*!< RSTGEN STAT: PORSTAT (Bit 1) */ -#define RSTGEN_STAT_PORSTAT_Msk (0x2UL) /*!< RSTGEN STAT: PORSTAT (Bitfield-Mask: 0x01) */ -#define RSTGEN_STAT_EXRSTAT_Pos (0UL) /*!< RSTGEN STAT: EXRSTAT (Bit 0) */ -#define RSTGEN_STAT_EXRSTAT_Msk (0x1UL) /*!< RSTGEN STAT: EXRSTAT (Bitfield-Mask: 0x01) */ - - -/* =========================================================================================================================== */ -/* ================ RTC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CTRLOW ========================================================= */ -#define RTC_CTRLOW_CTRHR_Pos (24UL) /*!< RTC CTRLOW: CTRHR (Bit 24) */ -#define RTC_CTRLOW_CTRHR_Msk (0x3f000000UL) /*!< RTC CTRLOW: CTRHR (Bitfield-Mask: 0x3f) */ -#define RTC_CTRLOW_CTRMIN_Pos (16UL) /*!< RTC CTRLOW: CTRMIN (Bit 16) */ -#define RTC_CTRLOW_CTRMIN_Msk (0x7f0000UL) /*!< RTC CTRLOW: CTRMIN (Bitfield-Mask: 0x7f) */ -#define RTC_CTRLOW_CTRSEC_Pos (8UL) /*!< RTC CTRLOW: CTRSEC (Bit 8) */ -#define RTC_CTRLOW_CTRSEC_Msk (0x7f00UL) /*!< RTC CTRLOW: CTRSEC (Bitfield-Mask: 0x7f) */ -#define RTC_CTRLOW_CTR100_Pos (0UL) /*!< RTC CTRLOW: CTR100 (Bit 0) */ -#define RTC_CTRLOW_CTR100_Msk (0xffUL) /*!< RTC CTRLOW: CTR100 (Bitfield-Mask: 0xff) */ -/* ========================================================= CTRUP ========================================================= */ -#define RTC_CTRUP_CTERR_Pos (31UL) /*!< RTC CTRUP: CTERR (Bit 31) */ -#define RTC_CTRUP_CTERR_Msk (0x80000000UL) /*!< RTC CTRUP: CTERR (Bitfield-Mask: 0x01) */ -#define RTC_CTRUP_CEB_Pos (28UL) /*!< RTC CTRUP: CEB (Bit 28) */ -#define RTC_CTRUP_CEB_Msk (0x10000000UL) /*!< RTC CTRUP: CEB (Bitfield-Mask: 0x01) */ -#define RTC_CTRUP_CB_Pos (27UL) /*!< RTC CTRUP: CB (Bit 27) */ -#define RTC_CTRUP_CB_Msk (0x8000000UL) /*!< RTC CTRUP: CB (Bitfield-Mask: 0x01) */ -#define RTC_CTRUP_CTRWKDY_Pos (24UL) /*!< RTC CTRUP: CTRWKDY (Bit 24) */ -#define RTC_CTRUP_CTRWKDY_Msk (0x7000000UL) /*!< RTC CTRUP: CTRWKDY (Bitfield-Mask: 0x07) */ -#define RTC_CTRUP_CTRYR_Pos (16UL) /*!< RTC CTRUP: CTRYR (Bit 16) */ -#define RTC_CTRUP_CTRYR_Msk (0xff0000UL) /*!< RTC CTRUP: CTRYR (Bitfield-Mask: 0xff) */ -#define RTC_CTRUP_CTRMO_Pos (8UL) /*!< RTC CTRUP: CTRMO (Bit 8) */ -#define RTC_CTRUP_CTRMO_Msk (0x1f00UL) /*!< RTC CTRUP: CTRMO (Bitfield-Mask: 0x1f) */ -#define RTC_CTRUP_CTRDATE_Pos (0UL) /*!< RTC CTRUP: CTRDATE (Bit 0) */ -#define RTC_CTRUP_CTRDATE_Msk (0x3fUL) /*!< RTC CTRUP: CTRDATE (Bitfield-Mask: 0x3f) */ -/* ======================================================== ALMLOW ========================================================= */ -#define RTC_ALMLOW_ALMHR_Pos (24UL) /*!< RTC ALMLOW: ALMHR (Bit 24) */ -#define RTC_ALMLOW_ALMHR_Msk (0x3f000000UL) /*!< RTC ALMLOW: ALMHR (Bitfield-Mask: 0x3f) */ -#define RTC_ALMLOW_ALMMIN_Pos (16UL) /*!< RTC ALMLOW: ALMMIN (Bit 16) */ -#define RTC_ALMLOW_ALMMIN_Msk (0x7f0000UL) /*!< RTC ALMLOW: ALMMIN (Bitfield-Mask: 0x7f) */ -#define RTC_ALMLOW_ALMSEC_Pos (8UL) /*!< RTC ALMLOW: ALMSEC (Bit 8) */ -#define RTC_ALMLOW_ALMSEC_Msk (0x7f00UL) /*!< RTC ALMLOW: ALMSEC (Bitfield-Mask: 0x7f) */ -#define RTC_ALMLOW_ALM100_Pos (0UL) /*!< RTC ALMLOW: ALM100 (Bit 0) */ -#define RTC_ALMLOW_ALM100_Msk (0xffUL) /*!< RTC ALMLOW: ALM100 (Bitfield-Mask: 0xff) */ -/* ========================================================= ALMUP ========================================================= */ -#define RTC_ALMUP_ALMWKDY_Pos (16UL) /*!< RTC ALMUP: ALMWKDY (Bit 16) */ -#define RTC_ALMUP_ALMWKDY_Msk (0x70000UL) /*!< RTC ALMUP: ALMWKDY (Bitfield-Mask: 0x07) */ -#define RTC_ALMUP_ALMMO_Pos (8UL) /*!< RTC ALMUP: ALMMO (Bit 8) */ -#define RTC_ALMUP_ALMMO_Msk (0x1f00UL) /*!< RTC ALMUP: ALMMO (Bitfield-Mask: 0x1f) */ -#define RTC_ALMUP_ALMDATE_Pos (0UL) /*!< RTC ALMUP: ALMDATE (Bit 0) */ -#define RTC_ALMUP_ALMDATE_Msk (0x3fUL) /*!< RTC ALMUP: ALMDATE (Bitfield-Mask: 0x3f) */ -/* ======================================================== RTCCTL ========================================================= */ -#define RTC_RTCCTL_HR1224_Pos (5UL) /*!< RTC RTCCTL: HR1224 (Bit 5) */ -#define RTC_RTCCTL_HR1224_Msk (0x20UL) /*!< RTC RTCCTL: HR1224 (Bitfield-Mask: 0x01) */ -#define RTC_RTCCTL_RSTOP_Pos (4UL) /*!< RTC RTCCTL: RSTOP (Bit 4) */ -#define RTC_RTCCTL_RSTOP_Msk (0x10UL) /*!< RTC RTCCTL: RSTOP (Bitfield-Mask: 0x01) */ -#define RTC_RTCCTL_RPT_Pos (1UL) /*!< RTC RTCCTL: RPT (Bit 1) */ -#define RTC_RTCCTL_RPT_Msk (0xeUL) /*!< RTC RTCCTL: RPT (Bitfield-Mask: 0x07) */ -#define RTC_RTCCTL_WRTC_Pos (0UL) /*!< RTC RTCCTL: WRTC (Bit 0) */ -#define RTC_RTCCTL_WRTC_Msk (0x1UL) /*!< RTC RTCCTL: WRTC (Bitfield-Mask: 0x01) */ -/* ========================================================= INTEN ========================================================= */ -#define RTC_INTEN_ALM_Pos (0UL) /*!< RTC INTEN: ALM (Bit 0) */ -#define RTC_INTEN_ALM_Msk (0x1UL) /*!< RTC INTEN: ALM (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTAT ======================================================== */ -#define RTC_INTSTAT_ALM_Pos (0UL) /*!< RTC INTSTAT: ALM (Bit 0) */ -#define RTC_INTSTAT_ALM_Msk (0x1UL) /*!< RTC INTSTAT: ALM (Bitfield-Mask: 0x01) */ -/* ======================================================== INTCLR ========================================================= */ -#define RTC_INTCLR_ALM_Pos (0UL) /*!< RTC INTCLR: ALM (Bit 0) */ -#define RTC_INTCLR_ALM_Msk (0x1UL) /*!< RTC INTCLR: ALM (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSET ========================================================= */ -#define RTC_INTSET_ALM_Pos (0UL) /*!< RTC INTSET: ALM (Bit 0) */ -#define RTC_INTSET_ALM_Msk (0x1UL) /*!< RTC INTSET: ALM (Bitfield-Mask: 0x01) */ - - -/* =========================================================================================================================== */ -/* ================ SCARD ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== SR =========================================================== */ -#define SCARD_SR_FHF_Pos (6UL) /*!< SCARD SR: FHF (Bit 6) */ -#define SCARD_SR_FHF_Msk (0x40UL) /*!< SCARD SR: FHF (Bitfield-Mask: 0x01) */ -#define SCARD_SR_FT2REND_Pos (5UL) /*!< SCARD SR: FT2REND (Bit 5) */ -#define SCARD_SR_FT2REND_Msk (0x20UL) /*!< SCARD SR: FT2REND (Bitfield-Mask: 0x01) */ -#define SCARD_SR_PE_Pos (4UL) /*!< SCARD SR: PE (Bit 4) */ -#define SCARD_SR_PE_Msk (0x10UL) /*!< SCARD SR: PE (Bitfield-Mask: 0x01) */ -#define SCARD_SR_OVR_Pos (3UL) /*!< SCARD SR: OVR (Bit 3) */ -#define SCARD_SR_OVR_Msk (0x8UL) /*!< SCARD SR: OVR (Bitfield-Mask: 0x01) */ -#define SCARD_SR_FER_Pos (2UL) /*!< SCARD SR: FER (Bit 2) */ -#define SCARD_SR_FER_Msk (0x4UL) /*!< SCARD SR: FER (Bitfield-Mask: 0x01) */ -#define SCARD_SR_TBERBF_Pos (1UL) /*!< SCARD SR: TBERBF (Bit 1) */ -#define SCARD_SR_TBERBF_Msk (0x2UL) /*!< SCARD SR: TBERBF (Bitfield-Mask: 0x01) */ -#define SCARD_SR_FNE_Pos (0UL) /*!< SCARD SR: FNE (Bit 0) */ -#define SCARD_SR_FNE_Msk (0x1UL) /*!< SCARD SR: FNE (Bitfield-Mask: 0x01) */ -/* ========================================================== IER ========================================================== */ -#define SCARD_IER_FHFEN_Pos (6UL) /*!< SCARD IER: FHFEN (Bit 6) */ -#define SCARD_IER_FHFEN_Msk (0x40UL) /*!< SCARD IER: FHFEN (Bitfield-Mask: 0x01) */ -#define SCARD_IER_FT2RENDEN_Pos (5UL) /*!< SCARD IER: FT2RENDEN (Bit 5) */ -#define SCARD_IER_FT2RENDEN_Msk (0x20UL) /*!< SCARD IER: FT2RENDEN (Bitfield-Mask: 0x01) */ -#define SCARD_IER_PEEN_Pos (4UL) /*!< SCARD IER: PEEN (Bit 4) */ -#define SCARD_IER_PEEN_Msk (0x10UL) /*!< SCARD IER: PEEN (Bitfield-Mask: 0x01) */ -#define SCARD_IER_OVREN_Pos (3UL) /*!< SCARD IER: OVREN (Bit 3) */ -#define SCARD_IER_OVREN_Msk (0x8UL) /*!< SCARD IER: OVREN (Bitfield-Mask: 0x01) */ -#define SCARD_IER_FEREN_Pos (2UL) /*!< SCARD IER: FEREN (Bit 2) */ -#define SCARD_IER_FEREN_Msk (0x4UL) /*!< SCARD IER: FEREN (Bitfield-Mask: 0x01) */ -#define SCARD_IER_TBERBFEN_Pos (1UL) /*!< SCARD IER: TBERBFEN (Bit 1) */ -#define SCARD_IER_TBERBFEN_Msk (0x2UL) /*!< SCARD IER: TBERBFEN (Bitfield-Mask: 0x01) */ -#define SCARD_IER_FNEEN_Pos (0UL) /*!< SCARD IER: FNEEN (Bit 0) */ -#define SCARD_IER_FNEEN_Msk (0x1UL) /*!< SCARD IER: FNEEN (Bitfield-Mask: 0x01) */ -/* ========================================================== TCR ========================================================== */ -#define SCARD_TCR_DMAMD_Pos (7UL) /*!< SCARD TCR: DMAMD (Bit 7) */ -#define SCARD_TCR_DMAMD_Msk (0x80UL) /*!< SCARD TCR: DMAMD (Bitfield-Mask: 0x01) */ -#define SCARD_TCR_FIP_Pos (6UL) /*!< SCARD TCR: FIP (Bit 6) */ -#define SCARD_TCR_FIP_Msk (0x40UL) /*!< SCARD TCR: FIP (Bitfield-Mask: 0x01) */ -#define SCARD_TCR_AUTOCONV_Pos (5UL) /*!< SCARD TCR: AUTOCONV (Bit 5) */ -#define SCARD_TCR_AUTOCONV_Msk (0x20UL) /*!< SCARD TCR: AUTOCONV (Bitfield-Mask: 0x01) */ -#define SCARD_TCR_PROT_Pos (4UL) /*!< SCARD TCR: PROT (Bit 4) */ -#define SCARD_TCR_PROT_Msk (0x10UL) /*!< SCARD TCR: PROT (Bitfield-Mask: 0x01) */ -#define SCARD_TCR_TR_Pos (3UL) /*!< SCARD TCR: TR (Bit 3) */ -#define SCARD_TCR_TR_Msk (0x8UL) /*!< SCARD TCR: TR (Bitfield-Mask: 0x01) */ -#define SCARD_TCR_LCT_Pos (2UL) /*!< SCARD TCR: LCT (Bit 2) */ -#define SCARD_TCR_LCT_Msk (0x4UL) /*!< SCARD TCR: LCT (Bitfield-Mask: 0x01) */ -#define SCARD_TCR_SS_Pos (1UL) /*!< SCARD TCR: SS (Bit 1) */ -#define SCARD_TCR_SS_Msk (0x2UL) /*!< SCARD TCR: SS (Bitfield-Mask: 0x01) */ -#define SCARD_TCR_CONV_Pos (0UL) /*!< SCARD TCR: CONV (Bit 0) */ -#define SCARD_TCR_CONV_Msk (0x1UL) /*!< SCARD TCR: CONV (Bitfield-Mask: 0x01) */ -/* ========================================================== UCR ========================================================== */ -#define SCARD_UCR_RETXEN_Pos (3UL) /*!< SCARD UCR: RETXEN (Bit 3) */ -#define SCARD_UCR_RETXEN_Msk (0x8UL) /*!< SCARD UCR: RETXEN (Bitfield-Mask: 0x01) */ -#define SCARD_UCR_RSTIN_Pos (2UL) /*!< SCARD UCR: RSTIN (Bit 2) */ -#define SCARD_UCR_RSTIN_Msk (0x4UL) /*!< SCARD UCR: RSTIN (Bitfield-Mask: 0x01) */ -#define SCARD_UCR_RIU_Pos (1UL) /*!< SCARD UCR: RIU (Bit 1) */ -#define SCARD_UCR_RIU_Msk (0x2UL) /*!< SCARD UCR: RIU (Bitfield-Mask: 0x01) */ -#define SCARD_UCR_CST_Pos (0UL) /*!< SCARD UCR: CST (Bit 0) */ -#define SCARD_UCR_CST_Msk (0x1UL) /*!< SCARD UCR: CST (Bitfield-Mask: 0x01) */ -/* ========================================================== DR =========================================================== */ -#define SCARD_DR_DR_Pos (0UL) /*!< SCARD DR: DR (Bit 0) */ -#define SCARD_DR_DR_Msk (0xffUL) /*!< SCARD DR: DR (Bitfield-Mask: 0xff) */ -/* ========================================================= BPRL ========================================================== */ -#define SCARD_BPRL_BPRL_Pos (0UL) /*!< SCARD BPRL: BPRL (Bit 0) */ -#define SCARD_BPRL_BPRL_Msk (0xffUL) /*!< SCARD BPRL: BPRL (Bitfield-Mask: 0xff) */ -/* ========================================================= BPRH ========================================================== */ -#define SCARD_BPRH_BPRH_Pos (0UL) /*!< SCARD BPRH: BPRH (Bit 0) */ -#define SCARD_BPRH_BPRH_Msk (0xfUL) /*!< SCARD BPRH: BPRH (Bitfield-Mask: 0x0f) */ -/* ========================================================= UCR1 ========================================================== */ -#define SCARD_UCR1_ENLASTB_Pos (5UL) /*!< SCARD UCR1: ENLASTB (Bit 5) */ -#define SCARD_UCR1_ENLASTB_Msk (0x20UL) /*!< SCARD UCR1: ENLASTB (Bitfield-Mask: 0x01) */ -#define SCARD_UCR1_CLKIOV_Pos (4UL) /*!< SCARD UCR1: CLKIOV (Bit 4) */ -#define SCARD_UCR1_CLKIOV_Msk (0x10UL) /*!< SCARD UCR1: CLKIOV (Bitfield-Mask: 0x01) */ -#define SCARD_UCR1_T1PAREN_Pos (3UL) /*!< SCARD UCR1: T1PAREN (Bit 3) */ -#define SCARD_UCR1_T1PAREN_Msk (0x8UL) /*!< SCARD UCR1: T1PAREN (Bitfield-Mask: 0x01) */ -#define SCARD_UCR1_STSP_Pos (2UL) /*!< SCARD UCR1: STSP (Bit 2) */ -#define SCARD_UCR1_STSP_Msk (0x4UL) /*!< SCARD UCR1: STSP (Bitfield-Mask: 0x01) */ -#define SCARD_UCR1_PR_Pos (0UL) /*!< SCARD UCR1: PR (Bit 0) */ -#define SCARD_UCR1_PR_Msk (0x1UL) /*!< SCARD UCR1: PR (Bitfield-Mask: 0x01) */ -/* ========================================================== SR1 ========================================================== */ -#define SCARD_SR1_IDLE_Pos (3UL) /*!< SCARD SR1: IDLE (Bit 3) */ -#define SCARD_SR1_IDLE_Msk (0x8UL) /*!< SCARD SR1: IDLE (Bitfield-Mask: 0x01) */ -#define SCARD_SR1_SYNCEND_Pos (2UL) /*!< SCARD SR1: SYNCEND (Bit 2) */ -#define SCARD_SR1_SYNCEND_Msk (0x4UL) /*!< SCARD SR1: SYNCEND (Bitfield-Mask: 0x01) */ -#define SCARD_SR1_PRL_Pos (1UL) /*!< SCARD SR1: PRL (Bit 1) */ -#define SCARD_SR1_PRL_Msk (0x2UL) /*!< SCARD SR1: PRL (Bitfield-Mask: 0x01) */ -#define SCARD_SR1_ECNTOVER_Pos (0UL) /*!< SCARD SR1: ECNTOVER (Bit 0) */ -#define SCARD_SR1_ECNTOVER_Msk (0x1UL) /*!< SCARD SR1: ECNTOVER (Bitfield-Mask: 0x01) */ -/* ========================================================= IER1 ========================================================== */ -#define SCARD_IER1_SYNCENDEN_Pos (2UL) /*!< SCARD IER1: SYNCENDEN (Bit 2) */ -#define SCARD_IER1_SYNCENDEN_Msk (0x4UL) /*!< SCARD IER1: SYNCENDEN (Bitfield-Mask: 0x01) */ -#define SCARD_IER1_PRLEN_Pos (1UL) /*!< SCARD IER1: PRLEN (Bit 1) */ -#define SCARD_IER1_PRLEN_Msk (0x2UL) /*!< SCARD IER1: PRLEN (Bitfield-Mask: 0x01) */ -#define SCARD_IER1_ECNTOVEREN_Pos (0UL) /*!< SCARD IER1: ECNTOVEREN (Bit 0) */ -#define SCARD_IER1_ECNTOVEREN_Msk (0x1UL) /*!< SCARD IER1: ECNTOVEREN (Bitfield-Mask: 0x01) */ -/* ========================================================= ECNTL ========================================================= */ -#define SCARD_ECNTL_ECNTL_Pos (0UL) /*!< SCARD ECNTL: ECNTL (Bit 0) */ -#define SCARD_ECNTL_ECNTL_Msk (0xffUL) /*!< SCARD ECNTL: ECNTL (Bitfield-Mask: 0xff) */ -/* ========================================================= ECNTH ========================================================= */ -#define SCARD_ECNTH_ECNTH_Pos (0UL) /*!< SCARD ECNTH: ECNTH (Bit 0) */ -#define SCARD_ECNTH_ECNTH_Msk (0xffUL) /*!< SCARD ECNTH: ECNTH (Bitfield-Mask: 0xff) */ -/* ========================================================== GTR ========================================================== */ -#define SCARD_GTR_GTR_Pos (0UL) /*!< SCARD GTR: GTR (Bit 0) */ -#define SCARD_GTR_GTR_Msk (0xffUL) /*!< SCARD GTR: GTR (Bitfield-Mask: 0xff) */ -/* ======================================================== RETXCNT ======================================================== */ -#define SCARD_RETXCNT_RETXCNT_Pos (0UL) /*!< SCARD RETXCNT: RETXCNT (Bit 0) */ -#define SCARD_RETXCNT_RETXCNT_Msk (0xfUL) /*!< SCARD RETXCNT: RETXCNT (Bitfield-Mask: 0x0f) */ -/* ====================================================== RETXCNTRMI ======================================================= */ -#define SCARD_RETXCNTRMI_RETXCNTRMI_Pos (0UL) /*!< SCARD RETXCNTRMI: RETXCNTRMI (Bit 0) */ -#define SCARD_RETXCNTRMI_RETXCNTRMI_Msk (0xfUL) /*!< SCARD RETXCNTRMI: RETXCNTRMI (Bitfield-Mask: 0x0f) */ -/* ======================================================== CLKCTRL ======================================================== */ -#define SCARD_CLKCTRL_APBCLKEN_Pos (1UL) /*!< SCARD CLKCTRL: APBCLKEN (Bit 1) */ -#define SCARD_CLKCTRL_APBCLKEN_Msk (0x2UL) /*!< SCARD CLKCTRL: APBCLKEN (Bitfield-Mask: 0x01) */ -#define SCARD_CLKCTRL_CLKEN_Pos (0UL) /*!< SCARD CLKCTRL: CLKEN (Bit 0) */ -#define SCARD_CLKCTRL_CLKEN_Msk (0x1UL) /*!< SCARD CLKCTRL: CLKEN (Bitfield-Mask: 0x01) */ - - -/* =========================================================================================================================== */ -/* ================ SECURITY ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CTRL ========================================================== */ -#define SECURITY_CTRL_CRCERROR_Pos (31UL) /*!< SECURITY CTRL: CRCERROR (Bit 31) */ -#define SECURITY_CTRL_CRCERROR_Msk (0x80000000UL) /*!< SECURITY CTRL: CRCERROR (Bitfield-Mask: 0x01) */ -#define SECURITY_CTRL_FUNCTION_Pos (4UL) /*!< SECURITY CTRL: FUNCTION (Bit 4) */ -#define SECURITY_CTRL_FUNCTION_Msk (0xf0UL) /*!< SECURITY CTRL: FUNCTION (Bitfield-Mask: 0x0f) */ -#define SECURITY_CTRL_ENABLE_Pos (0UL) /*!< SECURITY CTRL: ENABLE (Bit 0) */ -#define SECURITY_CTRL_ENABLE_Msk (0x1UL) /*!< SECURITY CTRL: ENABLE (Bitfield-Mask: 0x01) */ -/* ======================================================== SRCADDR ======================================================== */ -#define SECURITY_SRCADDR_ADDR_Pos (0UL) /*!< SECURITY SRCADDR: ADDR (Bit 0) */ -#define SECURITY_SRCADDR_ADDR_Msk (0xffffffffUL) /*!< SECURITY SRCADDR: ADDR (Bitfield-Mask: 0xffffffff) */ -/* ========================================================== LEN ========================================================== */ -#define SECURITY_LEN_LEN_Pos (2UL) /*!< SECURITY LEN: LEN (Bit 2) */ -#define SECURITY_LEN_LEN_Msk (0xfffffcUL) /*!< SECURITY LEN: LEN (Bitfield-Mask: 0x3fffff) */ -/* ======================================================== RESULT ========================================================= */ -#define SECURITY_RESULT_CRC_Pos (0UL) /*!< SECURITY RESULT: CRC (Bit 0) */ -#define SECURITY_RESULT_CRC_Msk (0xffffffffUL) /*!< SECURITY RESULT: CRC (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= LOCKCTRL ======================================================== */ -#define SECURITY_LOCKCTRL_SELECT_Pos (0UL) /*!< SECURITY LOCKCTRL: SELECT (Bit 0) */ -#define SECURITY_LOCKCTRL_SELECT_Msk (0xffUL) /*!< SECURITY LOCKCTRL: SELECT (Bitfield-Mask: 0xff) */ -/* ======================================================= LOCKSTAT ======================================================== */ -#define SECURITY_LOCKSTAT_STATUS_Pos (0UL) /*!< SECURITY LOCKSTAT: STATUS (Bit 0) */ -#define SECURITY_LOCKSTAT_STATUS_Msk (0xffffffffUL) /*!< SECURITY LOCKSTAT: STATUS (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= KEY0 ========================================================== */ -#define SECURITY_KEY0_KEY0_Pos (0UL) /*!< SECURITY KEY0: KEY0 (Bit 0) */ -#define SECURITY_KEY0_KEY0_Msk (0xffffffffUL) /*!< SECURITY KEY0: KEY0 (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= KEY1 ========================================================== */ -#define SECURITY_KEY1_KEY1_Pos (0UL) /*!< SECURITY KEY1: KEY1 (Bit 0) */ -#define SECURITY_KEY1_KEY1_Msk (0xffffffffUL) /*!< SECURITY KEY1: KEY1 (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= KEY2 ========================================================== */ -#define SECURITY_KEY2_KEY2_Pos (0UL) /*!< SECURITY KEY2: KEY2 (Bit 0) */ -#define SECURITY_KEY2_KEY2_Msk (0xffffffffUL) /*!< SECURITY KEY2: KEY2 (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= KEY3 ========================================================== */ -#define SECURITY_KEY3_KEY3_Pos (0UL) /*!< SECURITY KEY3: KEY3 (Bit 0) */ -#define SECURITY_KEY3_KEY3_Msk (0xffffffffUL) /*!< SECURITY KEY3: KEY3 (Bitfield-Mask: 0xffffffff) */ - - -/* =========================================================================================================================== */ -/* ================ UART0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== DR =========================================================== */ -#define UART0_DR_OEDATA_Pos (11UL) /*!< UART0 DR: OEDATA (Bit 11) */ -#define UART0_DR_OEDATA_Msk (0x800UL) /*!< UART0 DR: OEDATA (Bitfield-Mask: 0x01) */ -#define UART0_DR_BEDATA_Pos (10UL) /*!< UART0 DR: BEDATA (Bit 10) */ -#define UART0_DR_BEDATA_Msk (0x400UL) /*!< UART0 DR: BEDATA (Bitfield-Mask: 0x01) */ -#define UART0_DR_PEDATA_Pos (9UL) /*!< UART0 DR: PEDATA (Bit 9) */ -#define UART0_DR_PEDATA_Msk (0x200UL) /*!< UART0 DR: PEDATA (Bitfield-Mask: 0x01) */ -#define UART0_DR_FEDATA_Pos (8UL) /*!< UART0 DR: FEDATA (Bit 8) */ -#define UART0_DR_FEDATA_Msk (0x100UL) /*!< UART0 DR: FEDATA (Bitfield-Mask: 0x01) */ -#define UART0_DR_DATA_Pos (0UL) /*!< UART0 DR: DATA (Bit 0) */ -#define UART0_DR_DATA_Msk (0xffUL) /*!< UART0 DR: DATA (Bitfield-Mask: 0xff) */ -/* ========================================================== RSR ========================================================== */ -#define UART0_RSR_OESTAT_Pos (3UL) /*!< UART0 RSR: OESTAT (Bit 3) */ -#define UART0_RSR_OESTAT_Msk (0x8UL) /*!< UART0 RSR: OESTAT (Bitfield-Mask: 0x01) */ -#define UART0_RSR_BESTAT_Pos (2UL) /*!< UART0 RSR: BESTAT (Bit 2) */ -#define UART0_RSR_BESTAT_Msk (0x4UL) /*!< UART0 RSR: BESTAT (Bitfield-Mask: 0x01) */ -#define UART0_RSR_PESTAT_Pos (1UL) /*!< UART0 RSR: PESTAT (Bit 1) */ -#define UART0_RSR_PESTAT_Msk (0x2UL) /*!< UART0 RSR: PESTAT (Bitfield-Mask: 0x01) */ -#define UART0_RSR_FESTAT_Pos (0UL) /*!< UART0 RSR: FESTAT (Bit 0) */ -#define UART0_RSR_FESTAT_Msk (0x1UL) /*!< UART0 RSR: FESTAT (Bitfield-Mask: 0x01) */ -/* ========================================================== FR =========================================================== */ -#define UART0_FR_TXBUSY_Pos (8UL) /*!< UART0 FR: TXBUSY (Bit 8) */ -#define UART0_FR_TXBUSY_Msk (0x100UL) /*!< UART0 FR: TXBUSY (Bitfield-Mask: 0x01) */ -#define UART0_FR_TXFE_Pos (7UL) /*!< UART0 FR: TXFE (Bit 7) */ -#define UART0_FR_TXFE_Msk (0x80UL) /*!< UART0 FR: TXFE (Bitfield-Mask: 0x01) */ -#define UART0_FR_RXFF_Pos (6UL) /*!< UART0 FR: RXFF (Bit 6) */ -#define UART0_FR_RXFF_Msk (0x40UL) /*!< UART0 FR: RXFF (Bitfield-Mask: 0x01) */ -#define UART0_FR_TXFF_Pos (5UL) /*!< UART0 FR: TXFF (Bit 5) */ -#define UART0_FR_TXFF_Msk (0x20UL) /*!< UART0 FR: TXFF (Bitfield-Mask: 0x01) */ -#define UART0_FR_RXFE_Pos (4UL) /*!< UART0 FR: RXFE (Bit 4) */ -#define UART0_FR_RXFE_Msk (0x10UL) /*!< UART0 FR: RXFE (Bitfield-Mask: 0x01) */ -#define UART0_FR_BUSY_Pos (3UL) /*!< UART0 FR: BUSY (Bit 3) */ -#define UART0_FR_BUSY_Msk (0x8UL) /*!< UART0 FR: BUSY (Bitfield-Mask: 0x01) */ -#define UART0_FR_DCD_Pos (2UL) /*!< UART0 FR: DCD (Bit 2) */ -#define UART0_FR_DCD_Msk (0x4UL) /*!< UART0 FR: DCD (Bitfield-Mask: 0x01) */ -#define UART0_FR_DSR_Pos (1UL) /*!< UART0 FR: DSR (Bit 1) */ -#define UART0_FR_DSR_Msk (0x2UL) /*!< UART0 FR: DSR (Bitfield-Mask: 0x01) */ -#define UART0_FR_CTS_Pos (0UL) /*!< UART0 FR: CTS (Bit 0) */ -#define UART0_FR_CTS_Msk (0x1UL) /*!< UART0 FR: CTS (Bitfield-Mask: 0x01) */ -/* ========================================================= ILPR ========================================================== */ -#define UART0_ILPR_ILPDVSR_Pos (0UL) /*!< UART0 ILPR: ILPDVSR (Bit 0) */ -#define UART0_ILPR_ILPDVSR_Msk (0xffUL) /*!< UART0 ILPR: ILPDVSR (Bitfield-Mask: 0xff) */ -/* ========================================================= IBRD ========================================================== */ -#define UART0_IBRD_DIVINT_Pos (0UL) /*!< UART0 IBRD: DIVINT (Bit 0) */ -#define UART0_IBRD_DIVINT_Msk (0xffffUL) /*!< UART0 IBRD: DIVINT (Bitfield-Mask: 0xffff) */ -/* ========================================================= FBRD ========================================================== */ -#define UART0_FBRD_DIVFRAC_Pos (0UL) /*!< UART0 FBRD: DIVFRAC (Bit 0) */ -#define UART0_FBRD_DIVFRAC_Msk (0x3fUL) /*!< UART0 FBRD: DIVFRAC (Bitfield-Mask: 0x3f) */ -/* ========================================================= LCRH ========================================================== */ -#define UART0_LCRH_SPS_Pos (7UL) /*!< UART0 LCRH: SPS (Bit 7) */ -#define UART0_LCRH_SPS_Msk (0x80UL) /*!< UART0 LCRH: SPS (Bitfield-Mask: 0x01) */ -#define UART0_LCRH_WLEN_Pos (5UL) /*!< UART0 LCRH: WLEN (Bit 5) */ -#define UART0_LCRH_WLEN_Msk (0x60UL) /*!< UART0 LCRH: WLEN (Bitfield-Mask: 0x03) */ -#define UART0_LCRH_FEN_Pos (4UL) /*!< UART0 LCRH: FEN (Bit 4) */ -#define UART0_LCRH_FEN_Msk (0x10UL) /*!< UART0 LCRH: FEN (Bitfield-Mask: 0x01) */ -#define UART0_LCRH_STP2_Pos (3UL) /*!< UART0 LCRH: STP2 (Bit 3) */ -#define UART0_LCRH_STP2_Msk (0x8UL) /*!< UART0 LCRH: STP2 (Bitfield-Mask: 0x01) */ -#define UART0_LCRH_EPS_Pos (2UL) /*!< UART0 LCRH: EPS (Bit 2) */ -#define UART0_LCRH_EPS_Msk (0x4UL) /*!< UART0 LCRH: EPS (Bitfield-Mask: 0x01) */ -#define UART0_LCRH_PEN_Pos (1UL) /*!< UART0 LCRH: PEN (Bit 1) */ -#define UART0_LCRH_PEN_Msk (0x2UL) /*!< UART0 LCRH: PEN (Bitfield-Mask: 0x01) */ -#define UART0_LCRH_BRK_Pos (0UL) /*!< UART0 LCRH: BRK (Bit 0) */ -#define UART0_LCRH_BRK_Msk (0x1UL) /*!< UART0 LCRH: BRK (Bitfield-Mask: 0x01) */ -/* ========================================================== CR =========================================================== */ -#define UART0_CR_CTSEN_Pos (15UL) /*!< UART0 CR: CTSEN (Bit 15) */ -#define UART0_CR_CTSEN_Msk (0x8000UL) /*!< UART0 CR: CTSEN (Bitfield-Mask: 0x01) */ -#define UART0_CR_RTSEN_Pos (14UL) /*!< UART0 CR: RTSEN (Bit 14) */ -#define UART0_CR_RTSEN_Msk (0x4000UL) /*!< UART0 CR: RTSEN (Bitfield-Mask: 0x01) */ -#define UART0_CR_OUT2_Pos (13UL) /*!< UART0 CR: OUT2 (Bit 13) */ -#define UART0_CR_OUT2_Msk (0x2000UL) /*!< UART0 CR: OUT2 (Bitfield-Mask: 0x01) */ -#define UART0_CR_OUT1_Pos (12UL) /*!< UART0 CR: OUT1 (Bit 12) */ -#define UART0_CR_OUT1_Msk (0x1000UL) /*!< UART0 CR: OUT1 (Bitfield-Mask: 0x01) */ -#define UART0_CR_RTS_Pos (11UL) /*!< UART0 CR: RTS (Bit 11) */ -#define UART0_CR_RTS_Msk (0x800UL) /*!< UART0 CR: RTS (Bitfield-Mask: 0x01) */ -#define UART0_CR_DTR_Pos (10UL) /*!< UART0 CR: DTR (Bit 10) */ -#define UART0_CR_DTR_Msk (0x400UL) /*!< UART0 CR: DTR (Bitfield-Mask: 0x01) */ -#define UART0_CR_RXE_Pos (9UL) /*!< UART0 CR: RXE (Bit 9) */ -#define UART0_CR_RXE_Msk (0x200UL) /*!< UART0 CR: RXE (Bitfield-Mask: 0x01) */ -#define UART0_CR_TXE_Pos (8UL) /*!< UART0 CR: TXE (Bit 8) */ -#define UART0_CR_TXE_Msk (0x100UL) /*!< UART0 CR: TXE (Bitfield-Mask: 0x01) */ -#define UART0_CR_LBE_Pos (7UL) /*!< UART0 CR: LBE (Bit 7) */ -#define UART0_CR_LBE_Msk (0x80UL) /*!< UART0 CR: LBE (Bitfield-Mask: 0x01) */ -#define UART0_CR_CLKSEL_Pos (4UL) /*!< UART0 CR: CLKSEL (Bit 4) */ -#define UART0_CR_CLKSEL_Msk (0x70UL) /*!< UART0 CR: CLKSEL (Bitfield-Mask: 0x07) */ -#define UART0_CR_CLKEN_Pos (3UL) /*!< UART0 CR: CLKEN (Bit 3) */ -#define UART0_CR_CLKEN_Msk (0x8UL) /*!< UART0 CR: CLKEN (Bitfield-Mask: 0x01) */ -#define UART0_CR_SIRLP_Pos (2UL) /*!< UART0 CR: SIRLP (Bit 2) */ -#define UART0_CR_SIRLP_Msk (0x4UL) /*!< UART0 CR: SIRLP (Bitfield-Mask: 0x01) */ -#define UART0_CR_SIREN_Pos (1UL) /*!< UART0 CR: SIREN (Bit 1) */ -#define UART0_CR_SIREN_Msk (0x2UL) /*!< UART0 CR: SIREN (Bitfield-Mask: 0x01) */ -#define UART0_CR_UARTEN_Pos (0UL) /*!< UART0 CR: UARTEN (Bit 0) */ -#define UART0_CR_UARTEN_Msk (0x1UL) /*!< UART0 CR: UARTEN (Bitfield-Mask: 0x01) */ -/* ========================================================= IFLS ========================================================== */ -#define UART0_IFLS_RXIFLSEL_Pos (3UL) /*!< UART0 IFLS: RXIFLSEL (Bit 3) */ -#define UART0_IFLS_RXIFLSEL_Msk (0x38UL) /*!< UART0 IFLS: RXIFLSEL (Bitfield-Mask: 0x07) */ -#define UART0_IFLS_TXIFLSEL_Pos (0UL) /*!< UART0 IFLS: TXIFLSEL (Bit 0) */ -#define UART0_IFLS_TXIFLSEL_Msk (0x7UL) /*!< UART0 IFLS: TXIFLSEL (Bitfield-Mask: 0x07) */ -/* ========================================================== IER ========================================================== */ -#define UART0_IER_OEIM_Pos (10UL) /*!< UART0 IER: OEIM (Bit 10) */ -#define UART0_IER_OEIM_Msk (0x400UL) /*!< UART0 IER: OEIM (Bitfield-Mask: 0x01) */ -#define UART0_IER_BEIM_Pos (9UL) /*!< UART0 IER: BEIM (Bit 9) */ -#define UART0_IER_BEIM_Msk (0x200UL) /*!< UART0 IER: BEIM (Bitfield-Mask: 0x01) */ -#define UART0_IER_PEIM_Pos (8UL) /*!< UART0 IER: PEIM (Bit 8) */ -#define UART0_IER_PEIM_Msk (0x100UL) /*!< UART0 IER: PEIM (Bitfield-Mask: 0x01) */ -#define UART0_IER_FEIM_Pos (7UL) /*!< UART0 IER: FEIM (Bit 7) */ -#define UART0_IER_FEIM_Msk (0x80UL) /*!< UART0 IER: FEIM (Bitfield-Mask: 0x01) */ -#define UART0_IER_RTIM_Pos (6UL) /*!< UART0 IER: RTIM (Bit 6) */ -#define UART0_IER_RTIM_Msk (0x40UL) /*!< UART0 IER: RTIM (Bitfield-Mask: 0x01) */ -#define UART0_IER_TXIM_Pos (5UL) /*!< UART0 IER: TXIM (Bit 5) */ -#define UART0_IER_TXIM_Msk (0x20UL) /*!< UART0 IER: TXIM (Bitfield-Mask: 0x01) */ -#define UART0_IER_RXIM_Pos (4UL) /*!< UART0 IER: RXIM (Bit 4) */ -#define UART0_IER_RXIM_Msk (0x10UL) /*!< UART0 IER: RXIM (Bitfield-Mask: 0x01) */ -#define UART0_IER_DSRMIM_Pos (3UL) /*!< UART0 IER: DSRMIM (Bit 3) */ -#define UART0_IER_DSRMIM_Msk (0x8UL) /*!< UART0 IER: DSRMIM (Bitfield-Mask: 0x01) */ -#define UART0_IER_DCDMIM_Pos (2UL) /*!< UART0 IER: DCDMIM (Bit 2) */ -#define UART0_IER_DCDMIM_Msk (0x4UL) /*!< UART0 IER: DCDMIM (Bitfield-Mask: 0x01) */ -#define UART0_IER_CTSMIM_Pos (1UL) /*!< UART0 IER: CTSMIM (Bit 1) */ -#define UART0_IER_CTSMIM_Msk (0x2UL) /*!< UART0 IER: CTSMIM (Bitfield-Mask: 0x01) */ -#define UART0_IER_TXCMPMIM_Pos (0UL) /*!< UART0 IER: TXCMPMIM (Bit 0) */ -#define UART0_IER_TXCMPMIM_Msk (0x1UL) /*!< UART0 IER: TXCMPMIM (Bitfield-Mask: 0x01) */ -/* ========================================================== IES ========================================================== */ -#define UART0_IES_OERIS_Pos (10UL) /*!< UART0 IES: OERIS (Bit 10) */ -#define UART0_IES_OERIS_Msk (0x400UL) /*!< UART0 IES: OERIS (Bitfield-Mask: 0x01) */ -#define UART0_IES_BERIS_Pos (9UL) /*!< UART0 IES: BERIS (Bit 9) */ -#define UART0_IES_BERIS_Msk (0x200UL) /*!< UART0 IES: BERIS (Bitfield-Mask: 0x01) */ -#define UART0_IES_PERIS_Pos (8UL) /*!< UART0 IES: PERIS (Bit 8) */ -#define UART0_IES_PERIS_Msk (0x100UL) /*!< UART0 IES: PERIS (Bitfield-Mask: 0x01) */ -#define UART0_IES_FERIS_Pos (7UL) /*!< UART0 IES: FERIS (Bit 7) */ -#define UART0_IES_FERIS_Msk (0x80UL) /*!< UART0 IES: FERIS (Bitfield-Mask: 0x01) */ -#define UART0_IES_RTRIS_Pos (6UL) /*!< UART0 IES: RTRIS (Bit 6) */ -#define UART0_IES_RTRIS_Msk (0x40UL) /*!< UART0 IES: RTRIS (Bitfield-Mask: 0x01) */ -#define UART0_IES_TXRIS_Pos (5UL) /*!< UART0 IES: TXRIS (Bit 5) */ -#define UART0_IES_TXRIS_Msk (0x20UL) /*!< UART0 IES: TXRIS (Bitfield-Mask: 0x01) */ -#define UART0_IES_RXRIS_Pos (4UL) /*!< UART0 IES: RXRIS (Bit 4) */ -#define UART0_IES_RXRIS_Msk (0x10UL) /*!< UART0 IES: RXRIS (Bitfield-Mask: 0x01) */ -#define UART0_IES_DSRMRIS_Pos (3UL) /*!< UART0 IES: DSRMRIS (Bit 3) */ -#define UART0_IES_DSRMRIS_Msk (0x8UL) /*!< UART0 IES: DSRMRIS (Bitfield-Mask: 0x01) */ -#define UART0_IES_DCDMRIS_Pos (2UL) /*!< UART0 IES: DCDMRIS (Bit 2) */ -#define UART0_IES_DCDMRIS_Msk (0x4UL) /*!< UART0 IES: DCDMRIS (Bitfield-Mask: 0x01) */ -#define UART0_IES_CTSMRIS_Pos (1UL) /*!< UART0 IES: CTSMRIS (Bit 1) */ -#define UART0_IES_CTSMRIS_Msk (0x2UL) /*!< UART0 IES: CTSMRIS (Bitfield-Mask: 0x01) */ -#define UART0_IES_TXCMPMRIS_Pos (0UL) /*!< UART0 IES: TXCMPMRIS (Bit 0) */ -#define UART0_IES_TXCMPMRIS_Msk (0x1UL) /*!< UART0 IES: TXCMPMRIS (Bitfield-Mask: 0x01) */ -/* ========================================================== MIS ========================================================== */ -#define UART0_MIS_OEMIS_Pos (10UL) /*!< UART0 MIS: OEMIS (Bit 10) */ -#define UART0_MIS_OEMIS_Msk (0x400UL) /*!< UART0 MIS: OEMIS (Bitfield-Mask: 0x01) */ -#define UART0_MIS_BEMIS_Pos (9UL) /*!< UART0 MIS: BEMIS (Bit 9) */ -#define UART0_MIS_BEMIS_Msk (0x200UL) /*!< UART0 MIS: BEMIS (Bitfield-Mask: 0x01) */ -#define UART0_MIS_PEMIS_Pos (8UL) /*!< UART0 MIS: PEMIS (Bit 8) */ -#define UART0_MIS_PEMIS_Msk (0x100UL) /*!< UART0 MIS: PEMIS (Bitfield-Mask: 0x01) */ -#define UART0_MIS_FEMIS_Pos (7UL) /*!< UART0 MIS: FEMIS (Bit 7) */ -#define UART0_MIS_FEMIS_Msk (0x80UL) /*!< UART0 MIS: FEMIS (Bitfield-Mask: 0x01) */ -#define UART0_MIS_RTMIS_Pos (6UL) /*!< UART0 MIS: RTMIS (Bit 6) */ -#define UART0_MIS_RTMIS_Msk (0x40UL) /*!< UART0 MIS: RTMIS (Bitfield-Mask: 0x01) */ -#define UART0_MIS_TXMIS_Pos (5UL) /*!< UART0 MIS: TXMIS (Bit 5) */ -#define UART0_MIS_TXMIS_Msk (0x20UL) /*!< UART0 MIS: TXMIS (Bitfield-Mask: 0x01) */ -#define UART0_MIS_RXMIS_Pos (4UL) /*!< UART0 MIS: RXMIS (Bit 4) */ -#define UART0_MIS_RXMIS_Msk (0x10UL) /*!< UART0 MIS: RXMIS (Bitfield-Mask: 0x01) */ -#define UART0_MIS_DSRMMIS_Pos (3UL) /*!< UART0 MIS: DSRMMIS (Bit 3) */ -#define UART0_MIS_DSRMMIS_Msk (0x8UL) /*!< UART0 MIS: DSRMMIS (Bitfield-Mask: 0x01) */ -#define UART0_MIS_DCDMMIS_Pos (2UL) /*!< UART0 MIS: DCDMMIS (Bit 2) */ -#define UART0_MIS_DCDMMIS_Msk (0x4UL) /*!< UART0 MIS: DCDMMIS (Bitfield-Mask: 0x01) */ -#define UART0_MIS_CTSMMIS_Pos (1UL) /*!< UART0 MIS: CTSMMIS (Bit 1) */ -#define UART0_MIS_CTSMMIS_Msk (0x2UL) /*!< UART0 MIS: CTSMMIS (Bitfield-Mask: 0x01) */ -#define UART0_MIS_TXCMPMMIS_Pos (0UL) /*!< UART0 MIS: TXCMPMMIS (Bit 0) */ -#define UART0_MIS_TXCMPMMIS_Msk (0x1UL) /*!< UART0 MIS: TXCMPMMIS (Bitfield-Mask: 0x01) */ -/* ========================================================== IEC ========================================================== */ -#define UART0_IEC_OEIC_Pos (10UL) /*!< UART0 IEC: OEIC (Bit 10) */ -#define UART0_IEC_OEIC_Msk (0x400UL) /*!< UART0 IEC: OEIC (Bitfield-Mask: 0x01) */ -#define UART0_IEC_BEIC_Pos (9UL) /*!< UART0 IEC: BEIC (Bit 9) */ -#define UART0_IEC_BEIC_Msk (0x200UL) /*!< UART0 IEC: BEIC (Bitfield-Mask: 0x01) */ -#define UART0_IEC_PEIC_Pos (8UL) /*!< UART0 IEC: PEIC (Bit 8) */ -#define UART0_IEC_PEIC_Msk (0x100UL) /*!< UART0 IEC: PEIC (Bitfield-Mask: 0x01) */ -#define UART0_IEC_FEIC_Pos (7UL) /*!< UART0 IEC: FEIC (Bit 7) */ -#define UART0_IEC_FEIC_Msk (0x80UL) /*!< UART0 IEC: FEIC (Bitfield-Mask: 0x01) */ -#define UART0_IEC_RTIC_Pos (6UL) /*!< UART0 IEC: RTIC (Bit 6) */ -#define UART0_IEC_RTIC_Msk (0x40UL) /*!< UART0 IEC: RTIC (Bitfield-Mask: 0x01) */ -#define UART0_IEC_TXIC_Pos (5UL) /*!< UART0 IEC: TXIC (Bit 5) */ -#define UART0_IEC_TXIC_Msk (0x20UL) /*!< UART0 IEC: TXIC (Bitfield-Mask: 0x01) */ -#define UART0_IEC_RXIC_Pos (4UL) /*!< UART0 IEC: RXIC (Bit 4) */ -#define UART0_IEC_RXIC_Msk (0x10UL) /*!< UART0 IEC: RXIC (Bitfield-Mask: 0x01) */ -#define UART0_IEC_DSRMIC_Pos (3UL) /*!< UART0 IEC: DSRMIC (Bit 3) */ -#define UART0_IEC_DSRMIC_Msk (0x8UL) /*!< UART0 IEC: DSRMIC (Bitfield-Mask: 0x01) */ -#define UART0_IEC_DCDMIC_Pos (2UL) /*!< UART0 IEC: DCDMIC (Bit 2) */ -#define UART0_IEC_DCDMIC_Msk (0x4UL) /*!< UART0 IEC: DCDMIC (Bitfield-Mask: 0x01) */ -#define UART0_IEC_CTSMIC_Pos (1UL) /*!< UART0 IEC: CTSMIC (Bit 1) */ -#define UART0_IEC_CTSMIC_Msk (0x2UL) /*!< UART0 IEC: CTSMIC (Bitfield-Mask: 0x01) */ -#define UART0_IEC_TXCMPMIC_Pos (0UL) /*!< UART0 IEC: TXCMPMIC (Bit 0) */ -#define UART0_IEC_TXCMPMIC_Msk (0x1UL) /*!< UART0 IEC: TXCMPMIC (Bitfield-Mask: 0x01) */ - - -/* =========================================================================================================================== */ -/* ================ VCOMP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CFG ========================================================== */ -#define VCOMP_CFG_LVLSEL_Pos (16UL) /*!< VCOMP CFG: LVLSEL (Bit 16) */ -#define VCOMP_CFG_LVLSEL_Msk (0xf0000UL) /*!< VCOMP CFG: LVLSEL (Bitfield-Mask: 0x0f) */ -#define VCOMP_CFG_NSEL_Pos (8UL) /*!< VCOMP CFG: NSEL (Bit 8) */ -#define VCOMP_CFG_NSEL_Msk (0x300UL) /*!< VCOMP CFG: NSEL (Bitfield-Mask: 0x03) */ -#define VCOMP_CFG_PSEL_Pos (0UL) /*!< VCOMP CFG: PSEL (Bit 0) */ -#define VCOMP_CFG_PSEL_Msk (0x3UL) /*!< VCOMP CFG: PSEL (Bitfield-Mask: 0x03) */ -/* ========================================================= STAT ========================================================== */ -#define VCOMP_STAT_PWDSTAT_Pos (1UL) /*!< VCOMP STAT: PWDSTAT (Bit 1) */ -#define VCOMP_STAT_PWDSTAT_Msk (0x2UL) /*!< VCOMP STAT: PWDSTAT (Bitfield-Mask: 0x01) */ -#define VCOMP_STAT_CMPOUT_Pos (0UL) /*!< VCOMP STAT: CMPOUT (Bit 0) */ -#define VCOMP_STAT_CMPOUT_Msk (0x1UL) /*!< VCOMP STAT: CMPOUT (Bitfield-Mask: 0x01) */ -/* ======================================================== PWDKEY ========================================================= */ -#define VCOMP_PWDKEY_PWDKEY_Pos (0UL) /*!< VCOMP PWDKEY: PWDKEY (Bit 0) */ -#define VCOMP_PWDKEY_PWDKEY_Msk (0xffffffffUL) /*!< VCOMP PWDKEY: PWDKEY (Bitfield-Mask: 0xffffffff) */ -/* ========================================================= INTEN ========================================================= */ -#define VCOMP_INTEN_OUTHI_Pos (1UL) /*!< VCOMP INTEN: OUTHI (Bit 1) */ -#define VCOMP_INTEN_OUTHI_Msk (0x2UL) /*!< VCOMP INTEN: OUTHI (Bitfield-Mask: 0x01) */ -#define VCOMP_INTEN_OUTLOW_Pos (0UL) /*!< VCOMP INTEN: OUTLOW (Bit 0) */ -#define VCOMP_INTEN_OUTLOW_Msk (0x1UL) /*!< VCOMP INTEN: OUTLOW (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTAT ======================================================== */ -#define VCOMP_INTSTAT_OUTHI_Pos (1UL) /*!< VCOMP INTSTAT: OUTHI (Bit 1) */ -#define VCOMP_INTSTAT_OUTHI_Msk (0x2UL) /*!< VCOMP INTSTAT: OUTHI (Bitfield-Mask: 0x01) */ -#define VCOMP_INTSTAT_OUTLOW_Pos (0UL) /*!< VCOMP INTSTAT: OUTLOW (Bit 0) */ -#define VCOMP_INTSTAT_OUTLOW_Msk (0x1UL) /*!< VCOMP INTSTAT: OUTLOW (Bitfield-Mask: 0x01) */ -/* ======================================================== INTCLR ========================================================= */ -#define VCOMP_INTCLR_OUTHI_Pos (1UL) /*!< VCOMP INTCLR: OUTHI (Bit 1) */ -#define VCOMP_INTCLR_OUTHI_Msk (0x2UL) /*!< VCOMP INTCLR: OUTHI (Bitfield-Mask: 0x01) */ -#define VCOMP_INTCLR_OUTLOW_Pos (0UL) /*!< VCOMP INTCLR: OUTLOW (Bit 0) */ -#define VCOMP_INTCLR_OUTLOW_Msk (0x1UL) /*!< VCOMP INTCLR: OUTLOW (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSET ========================================================= */ -#define VCOMP_INTSET_OUTHI_Pos (1UL) /*!< VCOMP INTSET: OUTHI (Bit 1) */ -#define VCOMP_INTSET_OUTHI_Msk (0x2UL) /*!< VCOMP INTSET: OUTHI (Bitfield-Mask: 0x01) */ -#define VCOMP_INTSET_OUTLOW_Pos (0UL) /*!< VCOMP INTSET: OUTLOW (Bit 0) */ -#define VCOMP_INTSET_OUTLOW_Msk (0x1UL) /*!< VCOMP INTSET: OUTLOW (Bitfield-Mask: 0x01) */ - - -/* =========================================================================================================================== */ -/* ================ WDT ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CFG ========================================================== */ -#define WDT_CFG_CLKSEL_Pos (24UL) /*!< WDT CFG: CLKSEL (Bit 24) */ -#define WDT_CFG_CLKSEL_Msk (0x7000000UL) /*!< WDT CFG: CLKSEL (Bitfield-Mask: 0x07) */ -#define WDT_CFG_INTVAL_Pos (16UL) /*!< WDT CFG: INTVAL (Bit 16) */ -#define WDT_CFG_INTVAL_Msk (0xff0000UL) /*!< WDT CFG: INTVAL (Bitfield-Mask: 0xff) */ -#define WDT_CFG_RESVAL_Pos (8UL) /*!< WDT CFG: RESVAL (Bit 8) */ -#define WDT_CFG_RESVAL_Msk (0xff00UL) /*!< WDT CFG: RESVAL (Bitfield-Mask: 0xff) */ -#define WDT_CFG_RESEN_Pos (2UL) /*!< WDT CFG: RESEN (Bit 2) */ -#define WDT_CFG_RESEN_Msk (0x4UL) /*!< WDT CFG: RESEN (Bitfield-Mask: 0x01) */ -#define WDT_CFG_INTEN_Pos (1UL) /*!< WDT CFG: INTEN (Bit 1) */ -#define WDT_CFG_INTEN_Msk (0x2UL) /*!< WDT CFG: INTEN (Bitfield-Mask: 0x01) */ -#define WDT_CFG_WDTEN_Pos (0UL) /*!< WDT CFG: WDTEN (Bit 0) */ -#define WDT_CFG_WDTEN_Msk (0x1UL) /*!< WDT CFG: WDTEN (Bitfield-Mask: 0x01) */ -/* ========================================================= RSTRT ========================================================= */ -#define WDT_RSTRT_RSTRT_Pos (0UL) /*!< WDT RSTRT: RSTRT (Bit 0) */ -#define WDT_RSTRT_RSTRT_Msk (0xffUL) /*!< WDT RSTRT: RSTRT (Bitfield-Mask: 0xff) */ -/* ========================================================= LOCK ========================================================== */ -#define WDT_LOCK_LOCK_Pos (0UL) /*!< WDT LOCK: LOCK (Bit 0) */ -#define WDT_LOCK_LOCK_Msk (0xffUL) /*!< WDT LOCK: LOCK (Bitfield-Mask: 0xff) */ -/* ========================================================= COUNT ========================================================= */ -#define WDT_COUNT_COUNT_Pos (0UL) /*!< WDT COUNT: COUNT (Bit 0) */ -#define WDT_COUNT_COUNT_Msk (0xffUL) /*!< WDT COUNT: COUNT (Bitfield-Mask: 0xff) */ -/* ========================================================= INTEN ========================================================= */ -#define WDT_INTEN_WDTINT_Pos (0UL) /*!< WDT INTEN: WDTINT (Bit 0) */ -#define WDT_INTEN_WDTINT_Msk (0x1UL) /*!< WDT INTEN: WDTINT (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSTAT ======================================================== */ -#define WDT_INTSTAT_WDTINT_Pos (0UL) /*!< WDT INTSTAT: WDTINT (Bit 0) */ -#define WDT_INTSTAT_WDTINT_Msk (0x1UL) /*!< WDT INTSTAT: WDTINT (Bitfield-Mask: 0x01) */ -/* ======================================================== INTCLR ========================================================= */ -#define WDT_INTCLR_WDTINT_Pos (0UL) /*!< WDT INTCLR: WDTINT (Bit 0) */ -#define WDT_INTCLR_WDTINT_Msk (0x1UL) /*!< WDT INTCLR: WDTINT (Bitfield-Mask: 0x01) */ -/* ======================================================== INTSET ========================================================= */ -#define WDT_INTSET_WDTINT_Pos (0UL) /*!< WDT INTSET: WDTINT (Bit 0) */ -#define WDT_INTSET_WDTINT_Msk (0x1UL) /*!< WDT INTSET: WDTINT (Bitfield-Mask: 0x01) */ - -/** @} */ /* End of group PosMask_peripherals */ - - -/* =========================================================================================================================== */ -/* ================ Enumerated Values Peripheral Section ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup EnumValue_peripherals - * @{ - */ - - - -/* =========================================================================================================================== */ -/* ================ ADC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CFG ========================================================== */ -/* ================================================ ADC CFG CLKSEL [24..25] ================================================ */ -typedef enum { /*!< ADC_CFG_CLKSEL */ - ADC_CFG_CLKSEL_OFF = 0, /*!< OFF : Off mode. The HFRC or HFRC_DIV2 clock must be selected - for the ADC to function. The ADC controller - automatically shuts off the clock in it's - low power modes. When setting ADCEN to '0', - the CLKSEL should remain set to one of the - two clock selects for proper power down - sequencing. */ - ADC_CFG_CLKSEL_HFRC = 1, /*!< HFRC : HFRC Core Clock divided by (CORESEL+1) */ - ADC_CFG_CLKSEL_HFRC_DIV2 = 2, /*!< HFRC_DIV2 : HFRC Core Clock / 2 further divided by (CORESEL+1) */ -} ADC_CFG_CLKSEL_Enum; - -/* =============================================== ADC CFG TRIGPOL [19..19] ================================================ */ -typedef enum { /*!< ADC_CFG_TRIGPOL */ - ADC_CFG_TRIGPOL_RISING_EDGE = 0, /*!< RISING_EDGE : Trigger on rising edge. */ - ADC_CFG_TRIGPOL_FALLING_EDGE = 1, /*!< FALLING_EDGE : Trigger on falling edge. */ -} ADC_CFG_TRIGPOL_Enum; - -/* =============================================== ADC CFG TRIGSEL [16..18] ================================================ */ -typedef enum { /*!< ADC_CFG_TRIGSEL */ - ADC_CFG_TRIGSEL_EXT0 = 0, /*!< EXT0 : Off chip External Trigger0 (ADC_ET0) */ - ADC_CFG_TRIGSEL_EXT1 = 1, /*!< EXT1 : Off chip External Trigger1 (ADC_ET1) */ - ADC_CFG_TRIGSEL_EXT2 = 2, /*!< EXT2 : Off chip External Trigger2 (ADC_ET2) */ - ADC_CFG_TRIGSEL_EXT3 = 3, /*!< EXT3 : Off chip External Trigger3 (ADC_ET3) */ - ADC_CFG_TRIGSEL_VCOMP = 4, /*!< VCOMP : Voltage Comparator Output */ - ADC_CFG_TRIGSEL_SWT = 7, /*!< SWT : Software Trigger */ -} ADC_CFG_TRIGSEL_Enum; - -/* ============================================== ADC CFG DFIFORDEN [12..12] =============================================== */ -typedef enum { /*!< ADC_CFG_DFIFORDEN */ - ADC_CFG_DFIFORDEN_DIS = 0, /*!< DIS : Destructive Reads are prevented. Reads to the FIFOPR register - will not POP an entry off the FIFO. */ - ADC_CFG_DFIFORDEN_EN = 1, /*!< EN : Reads to the FIFOPR registger will automatically pop an - entry off the FIFO. */ -} ADC_CFG_DFIFORDEN_Enum; - -/* ================================================= ADC CFG REFSEL [8..9] ================================================= */ -typedef enum { /*!< ADC_CFG_REFSEL */ - ADC_CFG_REFSEL_INT2P0 = 0, /*!< INT2P0 : Internal 2.0V Bandgap Reference Voltage */ - ADC_CFG_REFSEL_INT1P5 = 1, /*!< INT1P5 : Internal 1.5V Bandgap Reference Voltage */ - ADC_CFG_REFSEL_EXT2P0 = 2, /*!< EXT2P0 : Off Chip 2.0V Reference */ - ADC_CFG_REFSEL_EXT1P5 = 3, /*!< EXT1P5 : Off Chip 1.5V Reference */ -} ADC_CFG_REFSEL_Enum; - -/* ================================================= ADC CFG CKMODE [4..4] ================================================= */ -typedef enum { /*!< ADC_CFG_CKMODE */ - ADC_CFG_CKMODE_LPCKMODE = 0, /*!< LPCKMODE : Disable the clock between scans for LPMODE0. Set - LPCKMODE to 0x1 while configuring the ADC. */ - ADC_CFG_CKMODE_LLCKMODE = 1, /*!< LLCKMODE : Low Latency Clock Mode. When set, HFRC and the adc_clk - will remain on while in functioning in LPMODE0. */ -} ADC_CFG_CKMODE_Enum; - -/* ================================================= ADC CFG LPMODE [3..3] ================================================= */ -typedef enum { /*!< ADC_CFG_LPMODE */ - ADC_CFG_LPMODE_MODE0 = 0, /*!< MODE0 : Low Power Mode 0. Leaves the ADC fully powered between - scans with minimum latency between a trigger event and - sample data collection. */ - ADC_CFG_LPMODE_MODE1 = 1, /*!< MODE1 : Low Power Mode 1. Powers down all circuity and clocks - associated with the ADC until the next trigger event. Between - scans, the reference buffer requires up to 50us of delay - from a scan trigger event before the conversion will commence - while operating in this mode. */ -} ADC_CFG_LPMODE_Enum; - -/* ================================================= ADC CFG RPTEN [2..2] ================================================== */ -typedef enum { /*!< ADC_CFG_RPTEN */ - ADC_CFG_RPTEN_SINGLE_SCAN = 0, /*!< SINGLE_SCAN : In Single Scan Mode, the ADC will complete a single - scan upon each trigger event. */ - ADC_CFG_RPTEN_REPEATING_SCAN = 1, /*!< REPEATING_SCAN : In Repeating Scan Mode, the ADC will complete - it's first scan upon the initial trigger event and all - subsequent scans will occur at regular intervals defined - by the configuration programmed for the CTTMRA3 internal - timer until the timer is disabled or the ADC is disabled. - When disabling the ADC (setting ADCEN to '0'), the RPTEN - bit should be cleared. */ -} ADC_CFG_RPTEN_Enum; - -/* ================================================= ADC CFG ADCEN [0..0] ================================================== */ -typedef enum { /*!< ADC_CFG_ADCEN */ - ADC_CFG_ADCEN_DIS = 0, /*!< DIS : Disable the ADC module. */ - ADC_CFG_ADCEN_EN = 1, /*!< EN : Enable the ADC module. */ -} ADC_CFG_ADCEN_Enum; - -/* ========================================================= STAT ========================================================== */ -/* ================================================ ADC STAT PWDSTAT [0..0] ================================================ */ -typedef enum { /*!< ADC_STAT_PWDSTAT */ - ADC_STAT_PWDSTAT_ON = 0, /*!< ON : Powered on. */ - ADC_STAT_PWDSTAT_POWERED_DOWN = 1, /*!< POWERED_DOWN : ADC Low Power Mode 1. */ -} ADC_STAT_PWDSTAT_Enum; - -/* ========================================================== SWT ========================================================== */ -/* ================================================== ADC SWT SWT [0..7] =================================================== */ -typedef enum { /*!< ADC_SWT_SWT */ - ADC_SWT_SWT_GEN_SW_TRIGGER = 55, /*!< GEN_SW_TRIGGER : Writing this value generates a software trigger. */ -} ADC_SWT_SWT_Enum; - -/* ======================================================== SL0CFG ========================================================= */ -/* ============================================== ADC SL0CFG ADSEL0 [24..26] =============================================== */ -typedef enum { /*!< ADC_SL0CFG_ADSEL0 */ - ADC_SL0CFG_ADSEL0_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide - module for this slot. */ - ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide - module for this slot. */ - ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide - module for this slot. */ - ADC_SL0CFG_ADSEL0_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide - module for this slot. */ - ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate - divide module for this slot. */ - ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate - divide module for this slot. */ - ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate - divide module for this slot. */ - ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate - divide module for this slot. */ -} ADC_SL0CFG_ADSEL0_Enum; - -/* ============================================== ADC SL0CFG PRMODE0 [16..17] ============================================== */ -typedef enum { /*!< ADC_SL0CFG_PRMODE0 */ - ADC_SL0CFG_PRMODE0_P14B = 0, /*!< P14B : 14-bit precision mode */ - ADC_SL0CFG_PRMODE0_P12B = 1, /*!< P12B : 12-bit precision mode */ - ADC_SL0CFG_PRMODE0_P10B = 2, /*!< P10B : 10-bit precision mode */ - ADC_SL0CFG_PRMODE0_P8B = 3, /*!< P8B : 8-bit precision mode */ -} ADC_SL0CFG_PRMODE0_Enum; - -/* =============================================== ADC SL0CFG CHSEL0 [8..11] =============================================== */ -typedef enum { /*!< ADC_SL0CFG_CHSEL0 */ - ADC_SL0CFG_CHSEL0_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ - ADC_SL0CFG_CHSEL0_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ - ADC_SL0CFG_CHSEL0_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ - ADC_SL0CFG_CHSEL0_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ - ADC_SL0CFG_CHSEL0_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ - ADC_SL0CFG_CHSEL0_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ - ADC_SL0CFG_CHSEL0_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ - ADC_SL0CFG_CHSEL0_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ - ADC_SL0CFG_CHSEL0_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ - ADC_SL0CFG_CHSEL0_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ - ADC_SL0CFG_CHSEL0_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and - pad13(P). */ - ADC_SL0CFG_CHSEL0_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and - pad14(P). */ - ADC_SL0CFG_CHSEL0_TEMP = 12, /*!< TEMP : internal temperature sensor. */ - ADC_SL0CFG_CHSEL0_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ - ADC_SL0CFG_CHSEL0_VSS = 14, /*!< VSS : Input VSS */ -} ADC_SL0CFG_CHSEL0_Enum; - -/* ================================================ ADC SL0CFG WCEN0 [1..1] ================================================ */ -typedef enum { /*!< ADC_SL0CFG_WCEN0 */ - ADC_SL0CFG_WCEN0_WCEN = 1, /*!< WCEN : Enable the window compare for slot 0. */ -} ADC_SL0CFG_WCEN0_Enum; - -/* ================================================ ADC SL0CFG SLEN0 [0..0] ================================================ */ -typedef enum { /*!< ADC_SL0CFG_SLEN0 */ - ADC_SL0CFG_SLEN0_SLEN = 1, /*!< SLEN : Enable slot 0 for ADC conversions. */ -} ADC_SL0CFG_SLEN0_Enum; - -/* ======================================================== SL1CFG ========================================================= */ -/* ============================================== ADC SL1CFG ADSEL1 [24..26] =============================================== */ -typedef enum { /*!< ADC_SL1CFG_ADSEL1 */ - ADC_SL1CFG_ADSEL1_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide - module for this slot. */ - ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide - module for this slot. */ - ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide - module for this slot. */ - ADC_SL1CFG_ADSEL1_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide - module for this slot. */ - ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate - divide module for this slot. */ - ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate - divide module for this slot. */ - ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate - divide module for this slot. */ - ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate - divide module for this slot. */ -} ADC_SL1CFG_ADSEL1_Enum; - -/* ============================================== ADC SL1CFG PRMODE1 [16..17] ============================================== */ -typedef enum { /*!< ADC_SL1CFG_PRMODE1 */ - ADC_SL1CFG_PRMODE1_P14B = 0, /*!< P14B : 14-bit precision mode */ - ADC_SL1CFG_PRMODE1_P12B = 1, /*!< P12B : 12-bit precision mode */ - ADC_SL1CFG_PRMODE1_P10B = 2, /*!< P10B : 10-bit precision mode */ - ADC_SL1CFG_PRMODE1_P8B = 3, /*!< P8B : 8-bit precision mode */ -} ADC_SL1CFG_PRMODE1_Enum; - -/* =============================================== ADC SL1CFG CHSEL1 [8..11] =============================================== */ -typedef enum { /*!< ADC_SL1CFG_CHSEL1 */ - ADC_SL1CFG_CHSEL1_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ - ADC_SL1CFG_CHSEL1_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ - ADC_SL1CFG_CHSEL1_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ - ADC_SL1CFG_CHSEL1_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ - ADC_SL1CFG_CHSEL1_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ - ADC_SL1CFG_CHSEL1_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ - ADC_SL1CFG_CHSEL1_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ - ADC_SL1CFG_CHSEL1_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ - ADC_SL1CFG_CHSEL1_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ - ADC_SL1CFG_CHSEL1_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ - ADC_SL1CFG_CHSEL1_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and - pad13(P). */ - ADC_SL1CFG_CHSEL1_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and - pad14(P). */ - ADC_SL1CFG_CHSEL1_TEMP = 12, /*!< TEMP : internal temperature sensor. */ - ADC_SL1CFG_CHSEL1_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ - ADC_SL1CFG_CHSEL1_VSS = 14, /*!< VSS : Input VSS */ -} ADC_SL1CFG_CHSEL1_Enum; - -/* ================================================ ADC SL1CFG WCEN1 [1..1] ================================================ */ -typedef enum { /*!< ADC_SL1CFG_WCEN1 */ - ADC_SL1CFG_WCEN1_WCEN = 1, /*!< WCEN : Enable the window compare for slot 1. */ -} ADC_SL1CFG_WCEN1_Enum; - -/* ================================================ ADC SL1CFG SLEN1 [0..0] ================================================ */ -typedef enum { /*!< ADC_SL1CFG_SLEN1 */ - ADC_SL1CFG_SLEN1_SLEN = 1, /*!< SLEN : Enable slot 1 for ADC conversions. */ -} ADC_SL1CFG_SLEN1_Enum; - -/* ======================================================== SL2CFG ========================================================= */ -/* ============================================== ADC SL2CFG ADSEL2 [24..26] =============================================== */ -typedef enum { /*!< ADC_SL2CFG_ADSEL2 */ - ADC_SL2CFG_ADSEL2_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide - module for this slot. */ - ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide - module for this slot. */ - ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide - module for this slot. */ - ADC_SL2CFG_ADSEL2_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide - module for this slot. */ - ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate - divide module for this slot. */ - ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate - divide module for this slot. */ - ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate - divide module for this slot. */ - ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate - divide module for this slot. */ -} ADC_SL2CFG_ADSEL2_Enum; - -/* ============================================== ADC SL2CFG PRMODE2 [16..17] ============================================== */ -typedef enum { /*!< ADC_SL2CFG_PRMODE2 */ - ADC_SL2CFG_PRMODE2_P14B = 0, /*!< P14B : 14-bit precision mode */ - ADC_SL2CFG_PRMODE2_P12B = 1, /*!< P12B : 12-bit precision mode */ - ADC_SL2CFG_PRMODE2_P10B = 2, /*!< P10B : 10-bit precision mode */ - ADC_SL2CFG_PRMODE2_P8B = 3, /*!< P8B : 8-bit precision mode */ -} ADC_SL2CFG_PRMODE2_Enum; - -/* =============================================== ADC SL2CFG CHSEL2 [8..11] =============================================== */ -typedef enum { /*!< ADC_SL2CFG_CHSEL2 */ - ADC_SL2CFG_CHSEL2_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ - ADC_SL2CFG_CHSEL2_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ - ADC_SL2CFG_CHSEL2_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ - ADC_SL2CFG_CHSEL2_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ - ADC_SL2CFG_CHSEL2_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ - ADC_SL2CFG_CHSEL2_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ - ADC_SL2CFG_CHSEL2_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ - ADC_SL2CFG_CHSEL2_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ - ADC_SL2CFG_CHSEL2_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ - ADC_SL2CFG_CHSEL2_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ - ADC_SL2CFG_CHSEL2_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and - pad13(P). */ - ADC_SL2CFG_CHSEL2_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and - pad14(P). */ - ADC_SL2CFG_CHSEL2_TEMP = 12, /*!< TEMP : internal temperature sensor. */ - ADC_SL2CFG_CHSEL2_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ - ADC_SL2CFG_CHSEL2_VSS = 14, /*!< VSS : Input VSS */ -} ADC_SL2CFG_CHSEL2_Enum; - -/* ================================================ ADC SL2CFG WCEN2 [1..1] ================================================ */ -typedef enum { /*!< ADC_SL2CFG_WCEN2 */ - ADC_SL2CFG_WCEN2_WCEN = 1, /*!< WCEN : Enable the window compare for slot 2. */ -} ADC_SL2CFG_WCEN2_Enum; - -/* ================================================ ADC SL2CFG SLEN2 [0..0] ================================================ */ -typedef enum { /*!< ADC_SL2CFG_SLEN2 */ - ADC_SL2CFG_SLEN2_SLEN = 1, /*!< SLEN : Enable slot 2 for ADC conversions. */ -} ADC_SL2CFG_SLEN2_Enum; - -/* ======================================================== SL3CFG ========================================================= */ -/* ============================================== ADC SL3CFG ADSEL3 [24..26] =============================================== */ -typedef enum { /*!< ADC_SL3CFG_ADSEL3 */ - ADC_SL3CFG_ADSEL3_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide - module for this slot. */ - ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide - module for this slot. */ - ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide - module for this slot. */ - ADC_SL3CFG_ADSEL3_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide - module for this slot. */ - ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate - divide module for this slot. */ - ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate - divide module for this slot. */ - ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate - divide module for this slot. */ - ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate - divide module for this slot. */ -} ADC_SL3CFG_ADSEL3_Enum; - -/* ============================================== ADC SL3CFG PRMODE3 [16..17] ============================================== */ -typedef enum { /*!< ADC_SL3CFG_PRMODE3 */ - ADC_SL3CFG_PRMODE3_P14B = 0, /*!< P14B : 14-bit precision mode */ - ADC_SL3CFG_PRMODE3_P12B = 1, /*!< P12B : 12-bit precision mode */ - ADC_SL3CFG_PRMODE3_P10B = 2, /*!< P10B : 10-bit precision mode */ - ADC_SL3CFG_PRMODE3_P8B = 3, /*!< P8B : 8-bit precision mode */ -} ADC_SL3CFG_PRMODE3_Enum; - -/* =============================================== ADC SL3CFG CHSEL3 [8..11] =============================================== */ -typedef enum { /*!< ADC_SL3CFG_CHSEL3 */ - ADC_SL3CFG_CHSEL3_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ - ADC_SL3CFG_CHSEL3_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ - ADC_SL3CFG_CHSEL3_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ - ADC_SL3CFG_CHSEL3_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ - ADC_SL3CFG_CHSEL3_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ - ADC_SL3CFG_CHSEL3_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ - ADC_SL3CFG_CHSEL3_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ - ADC_SL3CFG_CHSEL3_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ - ADC_SL3CFG_CHSEL3_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ - ADC_SL3CFG_CHSEL3_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ - ADC_SL3CFG_CHSEL3_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and - pad13(P). */ - ADC_SL3CFG_CHSEL3_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and - pad14(P). */ - ADC_SL3CFG_CHSEL3_TEMP = 12, /*!< TEMP : internal temperature sensor. */ - ADC_SL3CFG_CHSEL3_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ - ADC_SL3CFG_CHSEL3_VSS = 14, /*!< VSS : Input VSS */ -} ADC_SL3CFG_CHSEL3_Enum; - -/* ================================================ ADC SL3CFG WCEN3 [1..1] ================================================ */ -typedef enum { /*!< ADC_SL3CFG_WCEN3 */ - ADC_SL3CFG_WCEN3_WCEN = 1, /*!< WCEN : Enable the window compare for slot 3. */ -} ADC_SL3CFG_WCEN3_Enum; - -/* ================================================ ADC SL3CFG SLEN3 [0..0] ================================================ */ -typedef enum { /*!< ADC_SL3CFG_SLEN3 */ - ADC_SL3CFG_SLEN3_SLEN = 1, /*!< SLEN : Enable slot 3 for ADC conversions. */ -} ADC_SL3CFG_SLEN3_Enum; - -/* ======================================================== SL4CFG ========================================================= */ -/* ============================================== ADC SL4CFG ADSEL4 [24..26] =============================================== */ -typedef enum { /*!< ADC_SL4CFG_ADSEL4 */ - ADC_SL4CFG_ADSEL4_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide - module for this slot. */ - ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide - module for this slot. */ - ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide - module for this slot. */ - ADC_SL4CFG_ADSEL4_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide - module for this slot. */ - ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate - divide module for this slot. */ - ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate - divide module for this slot. */ - ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate - divide module for this slot. */ - ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate - divide module for this slot. */ -} ADC_SL4CFG_ADSEL4_Enum; - -/* ============================================== ADC SL4CFG PRMODE4 [16..17] ============================================== */ -typedef enum { /*!< ADC_SL4CFG_PRMODE4 */ - ADC_SL4CFG_PRMODE4_P14B = 0, /*!< P14B : 14-bit precision mode */ - ADC_SL4CFG_PRMODE4_P12B = 1, /*!< P12B : 12-bit precision mode */ - ADC_SL4CFG_PRMODE4_P10B = 2, /*!< P10B : 10-bit precision mode */ - ADC_SL4CFG_PRMODE4_P8B = 3, /*!< P8B : 8-bit precision mode */ -} ADC_SL4CFG_PRMODE4_Enum; - -/* =============================================== ADC SL4CFG CHSEL4 [8..11] =============================================== */ -typedef enum { /*!< ADC_SL4CFG_CHSEL4 */ - ADC_SL4CFG_CHSEL4_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ - ADC_SL4CFG_CHSEL4_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ - ADC_SL4CFG_CHSEL4_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ - ADC_SL4CFG_CHSEL4_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ - ADC_SL4CFG_CHSEL4_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ - ADC_SL4CFG_CHSEL4_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ - ADC_SL4CFG_CHSEL4_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ - ADC_SL4CFG_CHSEL4_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ - ADC_SL4CFG_CHSEL4_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ - ADC_SL4CFG_CHSEL4_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ - ADC_SL4CFG_CHSEL4_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and - pad13(P). */ - ADC_SL4CFG_CHSEL4_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and - pad14(P). */ - ADC_SL4CFG_CHSEL4_TEMP = 12, /*!< TEMP : internal temperature sensor. */ - ADC_SL4CFG_CHSEL4_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ - ADC_SL4CFG_CHSEL4_VSS = 14, /*!< VSS : Input VSS */ -} ADC_SL4CFG_CHSEL4_Enum; - -/* ================================================ ADC SL4CFG WCEN4 [1..1] ================================================ */ -typedef enum { /*!< ADC_SL4CFG_WCEN4 */ - ADC_SL4CFG_WCEN4_WCEN = 1, /*!< WCEN : Enable the window compare for slot 4. */ -} ADC_SL4CFG_WCEN4_Enum; - -/* ================================================ ADC SL4CFG SLEN4 [0..0] ================================================ */ -typedef enum { /*!< ADC_SL4CFG_SLEN4 */ - ADC_SL4CFG_SLEN4_SLEN = 1, /*!< SLEN : Enable slot 4 for ADC conversions. */ -} ADC_SL4CFG_SLEN4_Enum; - -/* ======================================================== SL5CFG ========================================================= */ -/* ============================================== ADC SL5CFG ADSEL5 [24..26] =============================================== */ -typedef enum { /*!< ADC_SL5CFG_ADSEL5 */ - ADC_SL5CFG_ADSEL5_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide - module for this slot. */ - ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide - module for this slot. */ - ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide - module for this slot. */ - ADC_SL5CFG_ADSEL5_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide - module for this slot. */ - ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate - divide module for this slot. */ - ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate - divide module for this slot. */ - ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate - divide module for this slot. */ - ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate - divide module for this slot. */ -} ADC_SL5CFG_ADSEL5_Enum; - -/* ============================================== ADC SL5CFG PRMODE5 [16..17] ============================================== */ -typedef enum { /*!< ADC_SL5CFG_PRMODE5 */ - ADC_SL5CFG_PRMODE5_P14B = 0, /*!< P14B : 14-bit precision mode */ - ADC_SL5CFG_PRMODE5_P12B = 1, /*!< P12B : 12-bit precision mode */ - ADC_SL5CFG_PRMODE5_P10B = 2, /*!< P10B : 10-bit precision mode */ - ADC_SL5CFG_PRMODE5_P8B = 3, /*!< P8B : 8-bit precision mode */ -} ADC_SL5CFG_PRMODE5_Enum; - -/* =============================================== ADC SL5CFG CHSEL5 [8..11] =============================================== */ -typedef enum { /*!< ADC_SL5CFG_CHSEL5 */ - ADC_SL5CFG_CHSEL5_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ - ADC_SL5CFG_CHSEL5_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ - ADC_SL5CFG_CHSEL5_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ - ADC_SL5CFG_CHSEL5_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ - ADC_SL5CFG_CHSEL5_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ - ADC_SL5CFG_CHSEL5_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ - ADC_SL5CFG_CHSEL5_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ - ADC_SL5CFG_CHSEL5_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ - ADC_SL5CFG_CHSEL5_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ - ADC_SL5CFG_CHSEL5_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ - ADC_SL5CFG_CHSEL5_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and - pad13(P). */ - ADC_SL5CFG_CHSEL5_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and - pad14(P). */ - ADC_SL5CFG_CHSEL5_TEMP = 12, /*!< TEMP : internal temperature sensor. */ - ADC_SL5CFG_CHSEL5_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ - ADC_SL5CFG_CHSEL5_VSS = 14, /*!< VSS : Input VSS */ -} ADC_SL5CFG_CHSEL5_Enum; - -/* ================================================ ADC SL5CFG WCEN5 [1..1] ================================================ */ -typedef enum { /*!< ADC_SL5CFG_WCEN5 */ - ADC_SL5CFG_WCEN5_WCEN = 1, /*!< WCEN : Enable the window compare for slot 5. */ -} ADC_SL5CFG_WCEN5_Enum; - -/* ================================================ ADC SL5CFG SLEN5 [0..0] ================================================ */ -typedef enum { /*!< ADC_SL5CFG_SLEN5 */ - ADC_SL5CFG_SLEN5_SLEN = 1, /*!< SLEN : Enable slot 5 for ADC conversions. */ -} ADC_SL5CFG_SLEN5_Enum; - -/* ======================================================== SL6CFG ========================================================= */ -/* ============================================== ADC SL6CFG ADSEL6 [24..26] =============================================== */ -typedef enum { /*!< ADC_SL6CFG_ADSEL6 */ - ADC_SL6CFG_ADSEL6_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide - module for this slot. */ - ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide - module for this slot. */ - ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide - module for this slot. */ - ADC_SL6CFG_ADSEL6_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide - module for this slot. */ - ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate - divide module for this slot. */ - ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate - divide module for this slot. */ - ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate - divide module for this slot. */ - ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate - divide module for this slot. */ -} ADC_SL6CFG_ADSEL6_Enum; - -/* ============================================== ADC SL6CFG PRMODE6 [16..17] ============================================== */ -typedef enum { /*!< ADC_SL6CFG_PRMODE6 */ - ADC_SL6CFG_PRMODE6_P14B = 0, /*!< P14B : 14-bit precision mode */ - ADC_SL6CFG_PRMODE6_P12B = 1, /*!< P12B : 12-bit precision mode */ - ADC_SL6CFG_PRMODE6_P10B = 2, /*!< P10B : 10-bit precision mode */ - ADC_SL6CFG_PRMODE6_P8B = 3, /*!< P8B : 8-bit precision mode */ -} ADC_SL6CFG_PRMODE6_Enum; - -/* =============================================== ADC SL6CFG CHSEL6 [8..11] =============================================== */ -typedef enum { /*!< ADC_SL6CFG_CHSEL6 */ - ADC_SL6CFG_CHSEL6_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ - ADC_SL6CFG_CHSEL6_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ - ADC_SL6CFG_CHSEL6_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ - ADC_SL6CFG_CHSEL6_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ - ADC_SL6CFG_CHSEL6_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ - ADC_SL6CFG_CHSEL6_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ - ADC_SL6CFG_CHSEL6_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ - ADC_SL6CFG_CHSEL6_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ - ADC_SL6CFG_CHSEL6_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ - ADC_SL6CFG_CHSEL6_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ - ADC_SL6CFG_CHSEL6_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and - pad13(P). */ - ADC_SL6CFG_CHSEL6_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and - pad14(P). */ - ADC_SL6CFG_CHSEL6_TEMP = 12, /*!< TEMP : internal temperature sensor. */ - ADC_SL6CFG_CHSEL6_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ - ADC_SL6CFG_CHSEL6_VSS = 14, /*!< VSS : Input VSS */ -} ADC_SL6CFG_CHSEL6_Enum; - -/* ================================================ ADC SL6CFG WCEN6 [1..1] ================================================ */ -typedef enum { /*!< ADC_SL6CFG_WCEN6 */ - ADC_SL6CFG_WCEN6_WCEN = 1, /*!< WCEN : Enable the window compare for slot 6. */ -} ADC_SL6CFG_WCEN6_Enum; - -/* ================================================ ADC SL6CFG SLEN6 [0..0] ================================================ */ -typedef enum { /*!< ADC_SL6CFG_SLEN6 */ - ADC_SL6CFG_SLEN6_SLEN = 1, /*!< SLEN : Enable slot 6 for ADC conversions. */ -} ADC_SL6CFG_SLEN6_Enum; - -/* ======================================================== SL7CFG ========================================================= */ -/* ============================================== ADC SL7CFG ADSEL7 [24..26] =============================================== */ -typedef enum { /*!< ADC_SL7CFG_ADSEL7 */ - ADC_SL7CFG_ADSEL7_AVG_1_MSRMT = 0, /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide - module for this slot. */ - ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS = 1, /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide - module for this slot. */ - ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS = 2, /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide - module for this slot. */ - ADC_SL7CFG_ADSEL7_AVG_8_MSRMT = 3, /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide - module for this slot. */ - ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS = 4, /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate - divide module for this slot. */ - ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS = 5, /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate - divide module for this slot. */ - ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS = 6, /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate - divide module for this slot. */ - ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS = 7, /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate - divide module for this slot. */ -} ADC_SL7CFG_ADSEL7_Enum; - -/* ============================================== ADC SL7CFG PRMODE7 [16..17] ============================================== */ -typedef enum { /*!< ADC_SL7CFG_PRMODE7 */ - ADC_SL7CFG_PRMODE7_P14B = 0, /*!< P14B : 14-bit precision mode */ - ADC_SL7CFG_PRMODE7_P12B = 1, /*!< P12B : 12-bit precision mode */ - ADC_SL7CFG_PRMODE7_P10B = 2, /*!< P10B : 10-bit precision mode */ - ADC_SL7CFG_PRMODE7_P8B = 3, /*!< P8B : 8-bit precision mode */ -} ADC_SL7CFG_PRMODE7_Enum; - -/* =============================================== ADC SL7CFG CHSEL7 [8..11] =============================================== */ -typedef enum { /*!< ADC_SL7CFG_CHSEL7 */ - ADC_SL7CFG_CHSEL7_SE0 = 0, /*!< SE0 : single ended external GPIO connection to pad16. */ - ADC_SL7CFG_CHSEL7_SE1 = 1, /*!< SE1 : single ended external GPIO connection to pad29. */ - ADC_SL7CFG_CHSEL7_SE2 = 2, /*!< SE2 : single ended external GPIO connection to pad11. */ - ADC_SL7CFG_CHSEL7_SE3 = 3, /*!< SE3 : single ended external GPIO connection to pad31. */ - ADC_SL7CFG_CHSEL7_SE4 = 4, /*!< SE4 : single ended external GPIO connection to pad32. */ - ADC_SL7CFG_CHSEL7_SE5 = 5, /*!< SE5 : single ended external GPIO connection to pad33. */ - ADC_SL7CFG_CHSEL7_SE6 = 6, /*!< SE6 : single ended external GPIO connection to pad34. */ - ADC_SL7CFG_CHSEL7_SE7 = 7, /*!< SE7 : single ended external GPIO connection to pad35. */ - ADC_SL7CFG_CHSEL7_SE8 = 8, /*!< SE8 : single ended external GPIO connection to pad13. */ - ADC_SL7CFG_CHSEL7_SE9 = 9, /*!< SE9 : single ended external GPIO connection to pad12. */ - ADC_SL7CFG_CHSEL7_DF0 = 10, /*!< DF0 : differential external GPIO connections to pad12(N) and - pad13(P). */ - ADC_SL7CFG_CHSEL7_DF1 = 11, /*!< DF1 : differential external GPIO connections to pad15(N) and - pad14(P). */ - ADC_SL7CFG_CHSEL7_TEMP = 12, /*!< TEMP : internal temperature sensor. */ - ADC_SL7CFG_CHSEL7_BATT = 13, /*!< BATT : internal voltage divide-by-3 connection. */ - ADC_SL7CFG_CHSEL7_VSS = 14, /*!< VSS : Input VSS */ -} ADC_SL7CFG_CHSEL7_Enum; - -/* ================================================ ADC SL7CFG WCEN7 [1..1] ================================================ */ -typedef enum { /*!< ADC_SL7CFG_WCEN7 */ - ADC_SL7CFG_WCEN7_WCEN = 1, /*!< WCEN : Enable the window compare for slot 7. */ -} ADC_SL7CFG_WCEN7_Enum; - -/* ================================================ ADC SL7CFG SLEN7 [0..0] ================================================ */ -typedef enum { /*!< ADC_SL7CFG_SLEN7 */ - ADC_SL7CFG_SLEN7_SLEN = 1, /*!< SLEN : Enable slot 7 for ADC conversions. */ -} ADC_SL7CFG_SLEN7_Enum; - -/* ========================================================= WULIM ========================================================= */ -/* ========================================================= WLLIM ========================================================= */ -/* ======================================================== SCWLIM ========================================================= */ -/* ========================================================= FIFO ========================================================== */ -/* ======================================================== FIFOPR ========================================================= */ -/* ========================================================= INTEN ========================================================= */ -/* ================================================= ADC INTEN DERR [7..7] ================================================= */ -typedef enum { /*!< ADC_INTEN_DERR */ - ADC_INTEN_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */ -} ADC_INTEN_DERR_Enum; - -/* ================================================= ADC INTEN DCMP [6..6] ================================================= */ -typedef enum { /*!< ADC_INTEN_DCMP */ - ADC_INTEN_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */ -} ADC_INTEN_DCMP_Enum; - -/* ================================================ ADC INTEN WCINC [5..5] ================================================= */ -typedef enum { /*!< ADC_INTEN_WCINC */ - ADC_INTEN_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ -} ADC_INTEN_WCINC_Enum; - -/* ================================================ ADC INTEN WCEXC [4..4] ================================================= */ -typedef enum { /*!< ADC_INTEN_WCEXC */ - ADC_INTEN_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ -} ADC_INTEN_WCEXC_Enum; - -/* =============================================== ADC INTEN FIFOOVR2 [3..3] =============================================== */ -typedef enum { /*!< ADC_INTEN_FIFOOVR2 */ - ADC_INTEN_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ -} ADC_INTEN_FIFOOVR2_Enum; - -/* =============================================== ADC INTEN FIFOOVR1 [2..2] =============================================== */ -typedef enum { /*!< ADC_INTEN_FIFOOVR1 */ - ADC_INTEN_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ -} ADC_INTEN_FIFOOVR1_Enum; - -/* ================================================ ADC INTEN SCNCMP [1..1] ================================================ */ -typedef enum { /*!< ADC_INTEN_SCNCMP */ - ADC_INTEN_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ -} ADC_INTEN_SCNCMP_Enum; - -/* ================================================ ADC INTEN CNVCMP [0..0] ================================================ */ -typedef enum { /*!< ADC_INTEN_CNVCMP */ - ADC_INTEN_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ -} ADC_INTEN_CNVCMP_Enum; - -/* ======================================================== INTSTAT ======================================================== */ -/* ================================================ ADC INTSTAT DERR [7..7] ================================================ */ -typedef enum { /*!< ADC_INTSTAT_DERR */ - ADC_INTSTAT_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */ -} ADC_INTSTAT_DERR_Enum; - -/* ================================================ ADC INTSTAT DCMP [6..6] ================================================ */ -typedef enum { /*!< ADC_INTSTAT_DCMP */ - ADC_INTSTAT_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */ -} ADC_INTSTAT_DCMP_Enum; - -/* =============================================== ADC INTSTAT WCINC [5..5] ================================================ */ -typedef enum { /*!< ADC_INTSTAT_WCINC */ - ADC_INTSTAT_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ -} ADC_INTSTAT_WCINC_Enum; - -/* =============================================== ADC INTSTAT WCEXC [4..4] ================================================ */ -typedef enum { /*!< ADC_INTSTAT_WCEXC */ - ADC_INTSTAT_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ -} ADC_INTSTAT_WCEXC_Enum; - -/* ============================================== ADC INTSTAT FIFOOVR2 [3..3] ============================================== */ -typedef enum { /*!< ADC_INTSTAT_FIFOOVR2 */ - ADC_INTSTAT_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ -} ADC_INTSTAT_FIFOOVR2_Enum; - -/* ============================================== ADC INTSTAT FIFOOVR1 [2..2] ============================================== */ -typedef enum { /*!< ADC_INTSTAT_FIFOOVR1 */ - ADC_INTSTAT_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ -} ADC_INTSTAT_FIFOOVR1_Enum; - -/* =============================================== ADC INTSTAT SCNCMP [1..1] =============================================== */ -typedef enum { /*!< ADC_INTSTAT_SCNCMP */ - ADC_INTSTAT_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ -} ADC_INTSTAT_SCNCMP_Enum; - -/* =============================================== ADC INTSTAT CNVCMP [0..0] =============================================== */ -typedef enum { /*!< ADC_INTSTAT_CNVCMP */ - ADC_INTSTAT_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ -} ADC_INTSTAT_CNVCMP_Enum; - -/* ======================================================== INTCLR ========================================================= */ -/* ================================================ ADC INTCLR DERR [7..7] ================================================= */ -typedef enum { /*!< ADC_INTCLR_DERR */ - ADC_INTCLR_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */ -} ADC_INTCLR_DERR_Enum; - -/* ================================================ ADC INTCLR DCMP [6..6] ================================================= */ -typedef enum { /*!< ADC_INTCLR_DCMP */ - ADC_INTCLR_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */ -} ADC_INTCLR_DCMP_Enum; - -/* ================================================ ADC INTCLR WCINC [5..5] ================================================ */ -typedef enum { /*!< ADC_INTCLR_WCINC */ - ADC_INTCLR_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ -} ADC_INTCLR_WCINC_Enum; - -/* ================================================ ADC INTCLR WCEXC [4..4] ================================================ */ -typedef enum { /*!< ADC_INTCLR_WCEXC */ - ADC_INTCLR_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ -} ADC_INTCLR_WCEXC_Enum; - -/* ============================================== ADC INTCLR FIFOOVR2 [3..3] =============================================== */ -typedef enum { /*!< ADC_INTCLR_FIFOOVR2 */ - ADC_INTCLR_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ -} ADC_INTCLR_FIFOOVR2_Enum; - -/* ============================================== ADC INTCLR FIFOOVR1 [2..2] =============================================== */ -typedef enum { /*!< ADC_INTCLR_FIFOOVR1 */ - ADC_INTCLR_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ -} ADC_INTCLR_FIFOOVR1_Enum; - -/* =============================================== ADC INTCLR SCNCMP [1..1] ================================================ */ -typedef enum { /*!< ADC_INTCLR_SCNCMP */ - ADC_INTCLR_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ -} ADC_INTCLR_SCNCMP_Enum; - -/* =============================================== ADC INTCLR CNVCMP [0..0] ================================================ */ -typedef enum { /*!< ADC_INTCLR_CNVCMP */ - ADC_INTCLR_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ -} ADC_INTCLR_CNVCMP_Enum; - -/* ======================================================== INTSET ========================================================= */ -/* ================================================ ADC INTSET DERR [7..7] ================================================= */ -typedef enum { /*!< ADC_INTSET_DERR */ - ADC_INTSET_DERR_DMAERROR = 1, /*!< DMAERROR : DMA Error Condition Occurred */ -} ADC_INTSET_DERR_Enum; - -/* ================================================ ADC INTSET DCMP [6..6] ================================================= */ -typedef enum { /*!< ADC_INTSET_DCMP */ - ADC_INTSET_DCMP_DMACOMPLETE = 1, /*!< DMACOMPLETE : DMA Completed a transfer */ -} ADC_INTSET_DCMP_Enum; - -/* ================================================ ADC INTSET WCINC [5..5] ================================================ */ -typedef enum { /*!< ADC_INTSET_WCINC */ - ADC_INTSET_WCINC_WCINCINT = 1, /*!< WCINCINT : Window comparitor voltage incursion interrupt. */ -} ADC_INTSET_WCINC_Enum; - -/* ================================================ ADC INTSET WCEXC [4..4] ================================================ */ -typedef enum { /*!< ADC_INTSET_WCEXC */ - ADC_INTSET_WCEXC_WCEXCINT = 1, /*!< WCEXCINT : Window comparitor voltage excursion interrupt. */ -} ADC_INTSET_WCEXC_Enum; - -/* ============================================== ADC INTSET FIFOOVR2 [3..3] =============================================== */ -typedef enum { /*!< ADC_INTSET_FIFOOVR2 */ - ADC_INTSET_FIFOOVR2_FIFOFULLINT = 1, /*!< FIFOFULLINT : FIFO 100 percent full interrupt. */ -} ADC_INTSET_FIFOOVR2_Enum; - -/* ============================================== ADC INTSET FIFOOVR1 [2..2] =============================================== */ -typedef enum { /*!< ADC_INTSET_FIFOOVR1 */ - ADC_INTSET_FIFOOVR1_FIFO75INT = 1, /*!< FIFO75INT : FIFO 75 percent full interrupt. */ -} ADC_INTSET_FIFOOVR1_Enum; - -/* =============================================== ADC INTSET SCNCMP [1..1] ================================================ */ -typedef enum { /*!< ADC_INTSET_SCNCMP */ - ADC_INTSET_SCNCMP_SCNCMPINT = 1, /*!< SCNCMPINT : ADC scan complete interrupt. */ -} ADC_INTSET_SCNCMP_Enum; - -/* =============================================== ADC INTSET CNVCMP [0..0] ================================================ */ -typedef enum { /*!< ADC_INTSET_CNVCMP */ - ADC_INTSET_CNVCMP_CNVCMPINT = 1, /*!< CNVCMPINT : ADC conversion complete interrupt. */ -} ADC_INTSET_CNVCMP_Enum; - -/* ======================================================= DMATRIGEN ======================================================= */ -/* ====================================================== DMATRIGSTAT ====================================================== */ -/* ======================================================== DMACFG ========================================================= */ -/* ============================================== ADC DMACFG DMAMSK [17..17] =============================================== */ -typedef enum { /*!< ADC_DMACFG_DMAMSK */ - ADC_DMACFG_DMAMSK_DIS = 0, /*!< DIS : FIFO Contents are copied directly to memory without modification. */ - ADC_DMACFG_DMAMSK_EN = 1, /*!< EN : Only the FIFODATA contents are copied to memory on DMA - transfers. The SLOTNUM and FIFOCNT contents are cleared - to zero. */ -} ADC_DMACFG_DMAMSK_Enum; - -/* ============================================ ADC DMACFG DMAHONSTAT [16..16] ============================================= */ -typedef enum { /*!< ADC_DMACFG_DMAHONSTAT */ - ADC_DMACFG_DMAHONSTAT_DIS = 0, /*!< DIS : ADC conversions will continue regardless of DMA status - register */ - ADC_DMACFG_DMAHONSTAT_EN = 1, /*!< EN : ADC conversions will not progress if DMAERR or DMACPL bits - in DMA status register are set. */ -} ADC_DMACFG_DMAHONSTAT_Enum; - -/* ============================================== ADC DMACFG DMADYNPRI [9..9] ============================================== */ -typedef enum { /*!< ADC_DMACFG_DMADYNPRI */ - ADC_DMACFG_DMADYNPRI_DIS = 0, /*!< DIS : Disable dynamic priority (use DMAPRI setting only) */ - ADC_DMACFG_DMADYNPRI_EN = 1, /*!< EN : Enable dynamic priority */ -} ADC_DMACFG_DMADYNPRI_Enum; - -/* =============================================== ADC DMACFG DMAPRI [8..8] ================================================ */ -typedef enum { /*!< ADC_DMACFG_DMAPRI */ - ADC_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ - ADC_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ -} ADC_DMACFG_DMAPRI_Enum; - -/* =============================================== ADC DMACFG DMADIR [2..2] ================================================ */ -typedef enum { /*!< ADC_DMACFG_DMADIR */ - ADC_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction */ - ADC_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction */ -} ADC_DMACFG_DMADIR_Enum; - -/* ================================================ ADC DMACFG DMAEN [0..0] ================================================ */ -typedef enum { /*!< ADC_DMACFG_DMAEN */ - ADC_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */ - ADC_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */ -} ADC_DMACFG_DMAEN_Enum; - -/* ====================================================== DMATOTCOUNT ====================================================== */ -/* ====================================================== DMATARGADDR ====================================================== */ -/* ======================================================== DMASTAT ======================================================== */ - - -/* =========================================================================================================================== */ -/* ================ APBDMA ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== BBVALUE ======================================================== */ -/* ====================================================== BBSETCLEAR ======================================================= */ -/* ======================================================== BBINPUT ======================================================== */ -/* ======================================================= DEBUGDATA ======================================================= */ -/* ========================================================= DEBUG ========================================================= */ -/* ============================================== APBDMA DEBUG DEBUGEN [0..3] ============================================== */ -typedef enum { /*!< APBDMA_DEBUG_DEBUGEN */ - APBDMA_DEBUG_DEBUGEN_OFF = 0, /*!< OFF : Debug Disabled */ - APBDMA_DEBUG_DEBUGEN_ARB = 1, /*!< ARB : Debug Arb values */ -} APBDMA_DEBUG_DEBUGEN_Enum; - - - -/* =========================================================================================================================== */ -/* ================ BLEIF ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= FIFO ========================================================== */ -/* ======================================================== FIFOPTR ======================================================== */ -/* ======================================================== FIFOTHR ======================================================== */ -/* ======================================================== FIFOPOP ======================================================== */ -/* ======================================================= FIFOPUSH ======================================================== */ -/* ======================================================= FIFOCTRL ======================================================== */ -/* ======================================================== FIFOLOC ======================================================== */ -/* ======================================================== CLKCFG ========================================================= */ -/* =============================================== BLEIF CLKCFG FSEL [8..10] =============================================== */ -typedef enum { /*!< BLEIF_CLKCFG_FSEL */ - BLEIF_CLKCFG_FSEL_MIN_PWR = 0, /*!< MIN_PWR : Selects the minimum power clock. This setting should - be used whenever the IOM is not active. */ - BLEIF_CLKCFG_FSEL_HFRC = 1, /*!< HFRC : Selects the HFRC as the input clock. */ - BLEIF_CLKCFG_FSEL_HFRC_DIV2 = 2, /*!< HFRC_DIV2 : Selects the HFRC / 2 as the input clock. */ - BLEIF_CLKCFG_FSEL_HFRC_DIV4 = 3, /*!< HFRC_DIV4 : Selects the HFRC / 4 as the input clock. */ - BLEIF_CLKCFG_FSEL_HFRC_DIV8 = 4, /*!< HFRC_DIV8 : Selects the HFRC / 8 as the input clock. */ - BLEIF_CLKCFG_FSEL_HFRC_DIV16 = 5, /*!< HFRC_DIV16 : Selects the HFRC / 16 as the input clock. */ - BLEIF_CLKCFG_FSEL_HFRC_DIV32 = 6, /*!< HFRC_DIV32 : Selects the HFRC / 32 as the input clock. */ - BLEIF_CLKCFG_FSEL_HFRC_DIV64 = 7, /*!< HFRC_DIV64 : Selects the HFRC / 64 as the input clock. */ -} BLEIF_CLKCFG_FSEL_Enum; - -/* ========================================================== CMD ========================================================== */ -/* ================================================= BLEIF CMD CMD [0..4] ================================================== */ -typedef enum { /*!< BLEIF_CMD_CMD */ - BLEIF_CMD_CMD_WRITE = 1, /*!< WRITE : Write command using count of offset bytes specified - in the OFFSETCNT field */ - BLEIF_CMD_CMD_READ = 2, /*!< READ : Read command using count of offset bytes specified in - the OFFSETCNT field */ -} BLEIF_CMD_CMD_Enum; - -/* ======================================================== CMDRPT ========================================================= */ -/* ======================================================= OFFSETHI ======================================================== */ -/* ======================================================== CMDSTAT ======================================================== */ -/* ============================================= BLEIF CMDSTAT CMDSTAT [5..7] ============================================== */ -typedef enum { /*!< BLEIF_CMDSTAT_CMDSTAT */ - BLEIF_CMDSTAT_CMDSTAT_ERR = 1, /*!< ERR : Error encountered with command */ - BLEIF_CMDSTAT_CMDSTAT_ACTIVE = 2, /*!< ACTIVE : Actively processing command */ - BLEIF_CMDSTAT_CMDSTAT_IDLE = 4, /*!< IDLE : Idle state, no active command, no error */ - BLEIF_CMDSTAT_CMDSTAT_WAIT = 6, /*!< WAIT : Command in progress, but waiting on data from host */ -} BLEIF_CMDSTAT_CMDSTAT_Enum; - -/* ========================================================= INTEN ========================================================= */ -/* ======================================================== INTSTAT ======================================================== */ -/* ======================================================== INTCLR ========================================================= */ -/* ======================================================== INTSET ========================================================= */ -/* ======================================================= DMATRIGEN ======================================================= */ -/* ====================================================== DMATRIGSTAT ====================================================== */ -/* ======================================================== DMACFG ========================================================= */ -/* ============================================== BLEIF DMACFG DMAPRI [8..8] =============================================== */ -typedef enum { /*!< BLEIF_DMACFG_DMAPRI */ - BLEIF_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ - BLEIF_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ -} BLEIF_DMACFG_DMAPRI_Enum; - -/* ============================================== BLEIF DMACFG DMADIR [1..1] =============================================== */ -typedef enum { /*!< BLEIF_DMACFG_DMADIR */ - BLEIF_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction. To be set when - doing IOM read operations, ie reading data from external - devices. */ - BLEIF_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction. To be set when doing - IOM write operations, ie writing data to external devices. */ -} BLEIF_DMACFG_DMADIR_Enum; - -/* =============================================== BLEIF DMACFG DMAEN [0..0] =============================================== */ -typedef enum { /*!< BLEIF_DMACFG_DMAEN */ - BLEIF_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */ - BLEIF_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */ -} BLEIF_DMACFG_DMAEN_Enum; - -/* ====================================================== DMATOTCOUNT ====================================================== */ -/* ====================================================== DMATARGADDR ====================================================== */ -/* ======================================================== DMASTAT ======================================================== */ -/* ========================================================= CQCFG ========================================================= */ -/* =============================================== BLEIF CQCFG CQPRI [1..1] ================================================ */ -typedef enum { /*!< BLEIF_CQCFG_CQPRI */ - BLEIF_CQCFG_CQPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ - BLEIF_CQCFG_CQPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ -} BLEIF_CQCFG_CQPRI_Enum; - -/* ================================================ BLEIF CQCFG CQEN [0..0] ================================================ */ -typedef enum { /*!< BLEIF_CQCFG_CQEN */ - BLEIF_CQCFG_CQEN_DIS = 0, /*!< DIS : Disable CQ Function */ - BLEIF_CQCFG_CQEN_EN = 1, /*!< EN : Enable CQ Function */ -} BLEIF_CQCFG_CQEN_Enum; - -/* ======================================================== CQADDR ========================================================= */ -/* ======================================================== CQSTAT ========================================================= */ -/* ======================================================== CQFLAGS ======================================================== */ -/* ====================================================== CQSETCLEAR ======================================================= */ -/* ======================================================= CQPAUSEEN ======================================================= */ -/* ============================================= BLEIF CQPAUSEEN CQPEN [0..15] ============================================= */ -typedef enum { /*!< BLEIF_CQPAUSEEN_CQPEN */ - BLEIF_CQPAUSEEN_CQPEN_CNTEQ = 32768, /*!< CNTEQ : Pauses command queue processing when HWCNT matches SWCNT */ - BLEIF_CQPAUSEEN_CQPEN_BLEXOREN = 16384, /*!< BLEXOREN : Pause command queue when input BLE bit XORed with - SWFLAG4 is '1' */ - BLEIF_CQPAUSEEN_CQPEN_IOMXOREN = 8192, /*!< IOMXOREN : Pause command queue when input IOM bit XORed with - SWFLAG3 is '1' */ - BLEIF_CQPAUSEEN_CQPEN_GPIOXOREN = 4096, /*!< GPIOXOREN : Pause command queue when input GPIO irq_bit XORed - with SWFLAG2 is '1' */ - BLEIF_CQPAUSEEN_CQPEN_MSPI1XNOREN = 2048, /*!< MSPI1XNOREN : Pause command queue when input MSPI1 bit XNORed - with SWFLAG1 is '1' */ - BLEIF_CQPAUSEEN_CQPEN_MSPI0XNOREN = 1024, /*!< MSPI0XNOREN : Pause command queue when input MSPI0 bit XNORed - with SWFLAG0 is '1' */ - BLEIF_CQPAUSEEN_CQPEN_MSPI1XOREN = 512, /*!< MSPI1XOREN : Pause command queue when input MSPI1 bit XORed - with SWFLAG1 is '1' */ - BLEIF_CQPAUSEEN_CQPEN_MSPI0XOREN = 256, /*!< MSPI0XOREN : Pause command queue when input MSPI0 bit XORed - with SWFLAG0 is '1' */ - BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN7 = 128, /*!< SWFLAGEN7 : Pause the command queue when software flag bit 7 - is '1'. */ - BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN6 = 64, /*!< SWFLAGEN6 : Pause the command queue when software flag bit 7 - is '1' */ - BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN5 = 32, /*!< SWFLAGEN5 : Pause the command queue when software flag bit 7 - is '1' */ - BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN4 = 16, /*!< SWFLAGEN4 : Pause the command queue when software flag bit 7 - is '1' */ - BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN3 = 8, /*!< SWFLAGEN3 : Pause the command queue when software flag bit 7 - is '1' */ - BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN2 = 4, /*!< SWFLAGEN2 : Pause the command queue when software flag bit 7 - is '1' */ - BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN1 = 2, /*!< SWFLAGEN1 : Pause the command queue when software flag bit 7 - is '1' */ - BLEIF_CQPAUSEEN_CQPEN_SWFLGEN0 = 1, /*!< SWFLGEN0 : Pause the command queue when software flag bit 7 - is '1' */ -} BLEIF_CQPAUSEEN_CQPEN_Enum; - -/* ======================================================= CQCURIDX ======================================================== */ -/* ======================================================= CQENDIDX ======================================================== */ -/* ======================================================== STATUS ========================================================= */ -/* ============================================== BLEIF STATUS IDLEST [2..2] =============================================== */ -typedef enum { /*!< BLEIF_STATUS_IDLEST */ - BLEIF_STATUS_IDLEST_IDLE = 1, /*!< IDLE : The I/O state machine is in the idle state. */ -} BLEIF_STATUS_IDLEST_Enum; - -/* ============================================== BLEIF STATUS CMDACT [1..1] =============================================== */ -typedef enum { /*!< BLEIF_STATUS_CMDACT */ - BLEIF_STATUS_CMDACT_ACTIVE = 1, /*!< ACTIVE : An I/O command is active. Indicates the active module - has an active command and is processing this. De-asserted - when the command is completed. */ -} BLEIF_STATUS_CMDACT_Enum; - -/* ================================================ BLEIF STATUS ERR [0..0] ================================================ */ -typedef enum { /*!< BLEIF_STATUS_ERR */ - BLEIF_STATUS_ERR_ERROR = 1, /*!< ERROR : Bit has been deprecated and will always return 0. */ -} BLEIF_STATUS_ERR_Enum; - -/* ======================================================== MSPICFG ======================================================== */ -/* ============================================= BLEIF MSPICFG SPILSB [23..23] ============================================= */ -typedef enum { /*!< BLEIF_MSPICFG_SPILSB */ - BLEIF_MSPICFG_SPILSB_MSB = 0, /*!< MSB : Send and receive MSB bit first */ - BLEIF_MSPICFG_SPILSB_LSB = 1, /*!< LSB : Send and receive LSB bit first */ -} BLEIF_MSPICFG_SPILSB_Enum; - -/* ============================================ BLEIF MSPICFG RDFCPOL [22..22] ============================================= */ -typedef enum { /*!< BLEIF_MSPICFG_RDFCPOL */ - BLEIF_MSPICFG_RDFCPOL_NORMAL = 0, /*!< NORMAL : SPI_STATUS signal from BLE Core high(1) creates flow - control and new read spi transactions will not be started - until the signal goes low.(default) */ - BLEIF_MSPICFG_RDFCPOL_INVERTED = 1, /*!< INVERTED : SPI_STATUS signal from BLE Core low(0) creates flow - control and new read spi transactions will not be started - until the signal goes high. */ -} BLEIF_MSPICFG_RDFCPOL_Enum; - -/* ============================================ BLEIF MSPICFG WTFCPOL [21..21] ============================================= */ -typedef enum { /*!< BLEIF_MSPICFG_WTFCPOL */ - BLEIF_MSPICFG_WTFCPOL_NORMAL = 0, /*!< NORMAL : SPI_STATUS signal from BLE Core high(1) creates flow - control and new write spi transactions will not be started - until the signal goes low.(default) */ - BLEIF_MSPICFG_WTFCPOL_INVERTED = 1, /*!< INVERTED : SPI_STATUS signal from BLE Core high(1) creates low(0) - control and new write spi transactions will not be started - until the signal goes high. */ -} BLEIF_MSPICFG_WTFCPOL_Enum; - -/* ============================================== BLEIF MSPICFG RDFC [17..17] ============================================== */ -typedef enum { /*!< BLEIF_MSPICFG_RDFC */ - BLEIF_MSPICFG_RDFC_DIS = 0, /*!< DIS : Read mode flow control disabled. */ - BLEIF_MSPICFG_RDFC_EN = 1, /*!< EN : Read mode flow control enabled. */ -} BLEIF_MSPICFG_RDFC_Enum; - -/* ============================================== BLEIF MSPICFG WTFC [16..16] ============================================== */ -typedef enum { /*!< BLEIF_MSPICFG_WTFC */ - BLEIF_MSPICFG_WTFC_DIS = 0, /*!< DIS : Write mode flow control disabled. */ - BLEIF_MSPICFG_WTFC_EN = 1, /*!< EN : Write mode flow control enabled. */ -} BLEIF_MSPICFG_WTFC_Enum; - -/* =============================================== BLEIF MSPICFG SPHA [1..1] =============================================== */ -typedef enum { /*!< BLEIF_MSPICFG_SPHA */ - BLEIF_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0, /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge, - rising or falling dependant on the value of SPOL */ - BLEIF_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1, /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock - edge, rising of falling dependant on the value of SPOL */ -} BLEIF_MSPICFG_SPHA_Enum; - -/* =============================================== BLEIF MSPICFG SPOL [0..0] =============================================== */ -typedef enum { /*!< BLEIF_MSPICFG_SPOL */ - BLEIF_MSPICFG_SPOL_CLK_BASE_0 = 0, /*!< CLK_BASE_0 : The initial value of the clock is 0. */ - BLEIF_MSPICFG_SPOL_CLK_BASE_1 = 1, /*!< CLK_BASE_1 : The initial value of the clock is 1. */ -} BLEIF_MSPICFG_SPOL_Enum; - -/* ======================================================== BLECFG ========================================================= */ -/* ============================================ BLEIF BLECFG SPIISOCTL [14..15] ============================================ */ -typedef enum { /*!< BLEIF_BLECFG_SPIISOCTL */ - BLEIF_BLECFG_SPIISOCTL_ON = 3, /*!< ON : SPI signals from BLE Core to/from MCU Core are isolated. */ - BLEIF_BLECFG_SPIISOCTL_OFF = 2, /*!< OFF : SPI signals from BLE Core to/from MCU Core are not isolated. */ - BLEIF_BLECFG_SPIISOCTL_AUTO = 0, /*!< AUTO : SPI signals from BLE Core to/from MCU Core are automatically - isolated by the logic */ -} BLEIF_BLECFG_SPIISOCTL_Enum; - -/* ============================================ BLEIF BLECFG PWRISOCTL [12..13] ============================================ */ -typedef enum { /*!< BLEIF_BLECFG_PWRISOCTL */ - BLEIF_BLECFG_PWRISOCTL_ON = 3, /*!< ON : BLEH power signal isolation to on (isolated). */ - BLEIF_BLECFG_PWRISOCTL_OFF = 2, /*!< OFF : BLEH power signal isolation to off (not isolated). */ - BLEIF_BLECFG_PWRISOCTL_AUTO = 0, /*!< AUTO : BLEH Power signal isolation is controlled automatically - through the interface logic */ -} BLEIF_BLECFG_PWRISOCTL_Enum; - -/* ============================================ BLEIF BLECFG BLEHREQCTL [6..7] ============================================= */ -typedef enum { /*!< BLEIF_BLECFG_BLEHREQCTL */ - BLEIF_BLECFG_BLEHREQCTL_ON = 3, /*!< ON : BLEH Power-on reg signal is set to on (1). */ - BLEIF_BLECFG_BLEHREQCTL_OFF = 2, /*!< OFF : BLEH Power-on signal is set to off (0). */ - BLEIF_BLECFG_BLEHREQCTL_AUTO = 0, /*!< AUTO : BLEH Power-on signal is controlled by the PWRSM logic - and automatically controlled */ -} BLEIF_BLECFG_BLEHREQCTL_Enum; - -/* ============================================ BLEIF BLECFG DCDCFLGCTL [4..5] ============================================= */ -typedef enum { /*!< BLEIF_BLECFG_DCDCFLGCTL */ - BLEIF_BLECFG_DCDCFLGCTL_ON = 3, /*!< ON : DCDC Flag signal is set to on (1). */ - BLEIF_BLECFG_DCDCFLGCTL_OFF = 2, /*!< OFF : DCDC Flag signal is set to off (0). */ - BLEIF_BLECFG_DCDCFLGCTL_AUTO = 0, /*!< AUTO : DCDC Flag signal is controlled by the PWRSM logic and - automatically controlled */ -} BLEIF_BLECFG_DCDCFLGCTL_Enum; - -/* ============================================= BLEIF BLECFG WAKEUPCTL [2..3] ============================================= */ -typedef enum { /*!< BLEIF_BLECFG_WAKEUPCTL */ - BLEIF_BLECFG_WAKEUPCTL_ON = 3, /*!< ON : Wake signal is set to on (1). */ - BLEIF_BLECFG_WAKEUPCTL_OFF = 2, /*!< OFF : Wake signal is set to off (0). */ - BLEIF_BLECFG_WAKEUPCTL_AUTO = 0, /*!< AUTO : Wake signal is controlled by the PWRSM logic and automatically - controlled */ -} BLEIF_BLECFG_WAKEUPCTL_Enum; - -/* ============================================== BLEIF BLECFG BLERSTN [1..1] ============================================== */ -typedef enum { /*!< BLEIF_BLECFG_BLERSTN */ - BLEIF_BLECFG_BLERSTN_ACTIVE = 1, /*!< ACTIVE : The reset signal is active (0) */ - BLEIF_BLECFG_BLERSTN_INACTIVE = 0, /*!< INACTIVE : The reset signal is inactive (1) */ -} BLEIF_BLECFG_BLERSTN_Enum; - -/* ============================================== BLEIF BLECFG PWRSMEN [0..0] ============================================== */ -typedef enum { /*!< BLEIF_BLECFG_PWRSMEN */ - BLEIF_BLECFG_PWRSMEN_ON = 1, /*!< ON : Internal power state machine is enabled and will sequence - the BLEH power domain as indicated in the design document. - Overrides for the power signals are not enabled. */ - BLEIF_BLECFG_PWRSMEN_OFF = 0, /*!< OFF : Internal power state machine is disabled and will not - sequence the BLEH power domain. The values of the overrides - will be used to drive the output sequencing signals */ -} BLEIF_BLECFG_PWRSMEN_Enum; - -/* ======================================================== PWRCMD ========================================================= */ -/* ======================================================== BSTATUS ======================================================== */ -/* ============================================== BLEIF BSTATUS PWRST [8..10] ============================================== */ -typedef enum { /*!< BLEIF_BSTATUS_PWRST */ - BLEIF_BSTATUS_PWRST_OFF = 0, /*!< OFF : Internal power state machine is disabled and will not - sequence the BLEH power domain. The values of the overrides - will be used to drive the output sequencing signals */ - BLEIF_BSTATUS_PWRST_INIT = 1, /*!< INIT : Initialization state. BLEH not powered */ - BLEIF_BSTATUS_PWRST_PWRON = 2, /*!< PWRON : Waiting for the powerup of the BLEH */ - BLEIF_BSTATUS_PWRST_ACTIVE = 3, /*!< ACTIVE : The BLE Core is powered and active */ - BLEIF_BSTATUS_PWRST_SLEEP = 6, /*!< SLEEP : The BLE Core has entered sleep mode and the power request - is inactive */ - BLEIF_BSTATUS_PWRST_SHUTDOWN = 4, /*!< SHUTDOWN : The BLE Core is in shutdown mode */ -} BLEIF_BSTATUS_PWRST_Enum; - -/* ============================================= BLEIF BSTATUS B2MSTATE [0..2] ============================================= */ -typedef enum { /*!< BLEIF_BSTATUS_B2MSTATE */ - BLEIF_BSTATUS_B2MSTATE_RESET = 0, /*!< RESET : Reset State */ - BLEIF_BSTATUS_B2MSTATE_Sleep = 1, /*!< Sleep : Sleep state. */ - BLEIF_BSTATUS_B2MSTATE_Standby = 2, /*!< Standby : Standby State */ - BLEIF_BSTATUS_B2MSTATE_Idle = 3, /*!< Idle : Idle state */ - BLEIF_BSTATUS_B2MSTATE_Active = 4, /*!< Active : Active state. */ -} BLEIF_BSTATUS_B2MSTATE_Enum; - -/* ======================================================== BLEDBG ========================================================= */ - - -/* =========================================================================================================================== */ -/* ================ CACHECTRL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================= CACHECFG ======================================================== */ -/* =========================================== CACHECTRL CACHECFG CONFIG [4..7] ============================================ */ -typedef enum { /*!< CACHECTRL_CACHECFG_CONFIG */ - CACHECTRL_CACHECFG_CONFIG_W1_128B_512E = 4, /*!< W1_128B_512E : Direct mapped, 128-bit linesize, 512 entries - (4 SRAMs active) */ - CACHECTRL_CACHECFG_CONFIG_W2_128B_512E = 5, /*!< W2_128B_512E : Two-way set associative, 128-bit linesize, 512 - entries (8 SRAMs active) */ - CACHECTRL_CACHECFG_CONFIG_W1_128B_1024E = 8, /*!< W1_128B_1024E : Direct mapped, 128-bit linesize, 1024 entries - (8 SRAMs active) */ -} CACHECTRL_CACHECFG_CONFIG_Enum; - -/* ========================================================= CTRL ========================================================== */ -/* =========================================== CACHECTRL CTRL RESET_STAT [1..1] ============================================ */ -typedef enum { /*!< CACHECTRL_CTRL_RESET_STAT */ - CACHECTRL_CTRL_RESET_STAT_CLEAR = 1, /*!< CLEAR : Clear Cache Stats */ -} CACHECTRL_CTRL_RESET_STAT_Enum; - -/* ======================================================= NCR0START ======================================================= */ -/* ======================================================== NCR0END ======================================================== */ -/* ======================================================= NCR1START ======================================================= */ -/* ======================================================== NCR1END ======================================================== */ -/* ========================================================= DMON0 ========================================================= */ -/* ========================================================= DMON1 ========================================================= */ -/* ========================================================= DMON2 ========================================================= */ -/* ========================================================= DMON3 ========================================================= */ -/* ========================================================= IMON0 ========================================================= */ -/* ========================================================= IMON1 ========================================================= */ -/* ========================================================= IMON2 ========================================================= */ -/* ========================================================= IMON3 ========================================================= */ -/* ======================================================= FLASH0CFG ======================================================= */ -/* ========================================= CACHECTRL FLASH0CFG LPMMODE0 [12..13] ========================================= */ -typedef enum { /*!< CACHECTRL_FLASH0CFG_LPMMODE0 */ - CACHECTRL_FLASH0CFG_LPMMODE0_NEVER = 0, /*!< NEVER : High power mode (LPM not used). */ - CACHECTRL_FLASH0CFG_LPMMODE0_STANDBY = 1, /*!< STANDBY : Fast Standby mode. LPM deasserted for read operations, - but asserted while flash IDLE. */ - CACHECTRL_FLASH0CFG_LPMMODE0_ALWAYS = 2, /*!< ALWAYS : Low Power mode. LPM always asserted for reads. LPM_RD_WAIT - must be programmed to accomodate longer read access times. */ -} CACHECTRL_FLASH0CFG_LPMMODE0_Enum; - -/* ======================================================= FLASH1CFG ======================================================= */ -/* ========================================= CACHECTRL FLASH1CFG LPMMODE1 [12..13] ========================================= */ -typedef enum { /*!< CACHECTRL_FLASH1CFG_LPMMODE1 */ - CACHECTRL_FLASH1CFG_LPMMODE1_NEVER = 0, /*!< NEVER : High power mode (LPM not used). */ - CACHECTRL_FLASH1CFG_LPMMODE1_STANDBY = 1, /*!< STANDBY : Fast Standby mode. LPM deasserted for read operations, - but asserted while flash IDLE. */ - CACHECTRL_FLASH1CFG_LPMMODE1_ALWAYS = 2, /*!< ALWAYS : Low Power mode. LPM always asserted for reads. LPM_RD_WAIT - must be programmed to accomodate longer read access times. */ -} CACHECTRL_FLASH1CFG_LPMMODE1_Enum; - -/* ======================================================= FLASH2CFG ======================================================= */ -/* ========================================= CACHECTRL FLASH2CFG LPMMODE2 [12..13] ========================================= */ -typedef enum { /*!< CACHECTRL_FLASH2CFG_LPMMODE2 */ - CACHECTRL_FLASH2CFG_LPMMODE2_NEVER = 0, /*!< NEVER : High power mode (LPM not used). */ - CACHECTRL_FLASH2CFG_LPMMODE2_STANDBY = 1, /*!< STANDBY : Fast Standby mode. LPM deasserted for read operations, - but asserted while flash IDLE. */ - CACHECTRL_FLASH2CFG_LPMMODE2_ALWAYS = 2, /*!< ALWAYS : Low Power mode. LPM always asserted for reads. LPM_RD_WAIT - must be programmed to accomodate longer read access times. */ -} CACHECTRL_FLASH2CFG_LPMMODE2_Enum; - -/* ======================================================= FLASH3CFG ======================================================= */ -/* ========================================= CACHECTRL FLASH3CFG LPMMODE3 [12..13] ========================================= */ -typedef enum { /*!< CACHECTRL_FLASH3CFG_LPMMODE3 */ - CACHECTRL_FLASH3CFG_LPMMODE3_NEVER = 0, /*!< NEVER : High power mode (LPM not used). */ - CACHECTRL_FLASH3CFG_LPMMODE3_STANDBY = 1, /*!< STANDBY : Fast Standby mode. LPM deasserted for read operations, - but asserted while flash IDLE. */ - CACHECTRL_FLASH3CFG_LPMMODE3_ALWAYS = 2, /*!< ALWAYS : Low Power mode. LPM always asserted for reads. LPM_RD_WAIT - must be programmed to accomodate longer read access times. */ -} CACHECTRL_FLASH3CFG_LPMMODE3_Enum; - - - -/* =========================================================================================================================== */ -/* ================ CLKGEN ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CALXT ========================================================= */ -/* ========================================================= CALRC ========================================================= */ -/* ======================================================== ACALCTR ======================================================== */ -/* ========================================================= OCTRL ========================================================= */ -/* =============================================== CLKGEN OCTRL ACAL [8..10] =============================================== */ -typedef enum { /*!< CLKGEN_OCTRL_ACAL */ - CLKGEN_OCTRL_ACAL_DIS = 0, /*!< DIS : Disable Autocalibration */ - CLKGEN_OCTRL_ACAL_1024SEC = 2, /*!< 1024SEC : Autocalibrate every 1024 seconds. Once autocalibration - is done, an interrupt will be triggered at the end of 1024 - seconds. */ - CLKGEN_OCTRL_ACAL_512SEC = 3, /*!< 512SEC : Autocalibrate every 512 seconds. Once autocalibration - is done, an interrupt will be trigged at the end of 512 - seconds. */ - CLKGEN_OCTRL_ACAL_XTFREQ = 6, /*!< XTFREQ : Frequency measurement using XT. The XT clock is normally - considered much more accurate than the LFRC clock source. */ - CLKGEN_OCTRL_ACAL_EXTFREQ = 7, /*!< EXTFREQ : Frequency measurement using external clock. */ -} CLKGEN_OCTRL_ACAL_Enum; - -/* =============================================== CLKGEN OCTRL OSEL [7..7] ================================================ */ -typedef enum { /*!< CLKGEN_OCTRL_OSEL */ - CLKGEN_OCTRL_OSEL_RTC_XT = 0, /*!< RTC_XT : RTC uses the XT */ - CLKGEN_OCTRL_OSEL_RTC_LFRC = 1, /*!< RTC_LFRC : RTC uses the LFRC */ -} CLKGEN_OCTRL_OSEL_Enum; - -/* ================================================ CLKGEN OCTRL FOS [6..6] ================================================ */ -typedef enum { /*!< CLKGEN_OCTRL_FOS */ - CLKGEN_OCTRL_FOS_DIS = 0, /*!< DIS : Disable the oscillator switch on failure function. */ - CLKGEN_OCTRL_FOS_EN = 1, /*!< EN : Enable the oscillator switch on failure function. */ -} CLKGEN_OCTRL_FOS_Enum; - -/* ============================================== CLKGEN OCTRL STOPRC [1..1] =============================================== */ -typedef enum { /*!< CLKGEN_OCTRL_STOPRC */ - CLKGEN_OCTRL_STOPRC_EN = 0, /*!< EN : Enable the LFRC Oscillator to drive the RTC */ - CLKGEN_OCTRL_STOPRC_STOP = 1, /*!< STOP : Stop the LFRC Oscillator when driving the RTC */ -} CLKGEN_OCTRL_STOPRC_Enum; - -/* ============================================== CLKGEN OCTRL STOPXT [0..0] =============================================== */ -typedef enum { /*!< CLKGEN_OCTRL_STOPXT */ - CLKGEN_OCTRL_STOPXT_EN = 0, /*!< EN : Enable the XT Oscillator to drive the RTC */ - CLKGEN_OCTRL_STOPXT_STOP = 1, /*!< STOP : Stop the XT Oscillator when driving the RTC */ -} CLKGEN_OCTRL_STOPXT_Enum; - -/* ======================================================== CLKOUT ========================================================= */ -/* =============================================== CLKGEN CLKOUT CKEN [7..7] =============================================== */ -typedef enum { /*!< CLKGEN_CLKOUT_CKEN */ - CLKGEN_CLKOUT_CKEN_DIS = 0, /*!< DIS : Disable CLKOUT */ - CLKGEN_CLKOUT_CKEN_EN = 1, /*!< EN : Enable CLKOUT */ -} CLKGEN_CLKOUT_CKEN_Enum; - -/* ============================================== CLKGEN CLKOUT CKSEL [0..5] =============================================== */ -typedef enum { /*!< CLKGEN_CLKOUT_CKSEL */ - CLKGEN_CLKOUT_CKSEL_LFRC = 0, /*!< LFRC : LFRC */ - CLKGEN_CLKOUT_CKSEL_XT_DIV2 = 1, /*!< XT_DIV2 : XT / 2 */ - CLKGEN_CLKOUT_CKSEL_XT_DIV4 = 2, /*!< XT_DIV4 : XT / 4 */ - CLKGEN_CLKOUT_CKSEL_XT_DIV8 = 3, /*!< XT_DIV8 : XT / 8 */ - CLKGEN_CLKOUT_CKSEL_XT_DIV16 = 4, /*!< XT_DIV16 : XT / 16 */ - CLKGEN_CLKOUT_CKSEL_XT_DIV32 = 5, /*!< XT_DIV32 : XT / 32 */ - CLKGEN_CLKOUT_CKSEL_RTC_1Hz = 16, /*!< RTC_1Hz : 1 Hz as selected in RTC */ - CLKGEN_CLKOUT_CKSEL_XT_DIV2M = 22, /*!< XT_DIV2M : XT / 2^21 */ - CLKGEN_CLKOUT_CKSEL_XT = 23, /*!< XT : XT */ - CLKGEN_CLKOUT_CKSEL_CG_100Hz = 24, /*!< CG_100Hz : 100 Hz as selected in CLKGEN */ - CLKGEN_CLKOUT_CKSEL_HFRC = 25, /*!< HFRC : HFRC */ - CLKGEN_CLKOUT_CKSEL_HFRC_DIV4 = 26, /*!< HFRC_DIV4 : HFRC / 4 */ - CLKGEN_CLKOUT_CKSEL_HFRC_DIV8 = 27, /*!< HFRC_DIV8 : HFRC / 8 */ - CLKGEN_CLKOUT_CKSEL_HFRC_DIV16 = 28, /*!< HFRC_DIV16 : HFRC / 16 */ - CLKGEN_CLKOUT_CKSEL_HFRC_DIV64 = 29, /*!< HFRC_DIV64 : HFRC / 64 */ - CLKGEN_CLKOUT_CKSEL_HFRC_DIV128 = 30, /*!< HFRC_DIV128 : HFRC / 128 */ - CLKGEN_CLKOUT_CKSEL_HFRC_DIV256 = 31, /*!< HFRC_DIV256 : HFRC / 256 */ - CLKGEN_CLKOUT_CKSEL_HFRC_DIV512 = 32, /*!< HFRC_DIV512 : HFRC / 512 */ - CLKGEN_CLKOUT_CKSEL_FLASH_CLK = 34, /*!< FLASH_CLK : Flash Clock */ - CLKGEN_CLKOUT_CKSEL_LFRC_DIV2 = 35, /*!< LFRC_DIV2 : LFRC / 2 */ - CLKGEN_CLKOUT_CKSEL_LFRC_DIV32 = 36, /*!< LFRC_DIV32 : LFRC / 32 */ - CLKGEN_CLKOUT_CKSEL_LFRC_DIV512 = 37, /*!< LFRC_DIV512 : LFRC / 512 */ - CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K = 38, /*!< LFRC_DIV32K : LFRC / 32768 */ - CLKGEN_CLKOUT_CKSEL_XT_DIV256 = 39, /*!< XT_DIV256 : XT / 256 */ - CLKGEN_CLKOUT_CKSEL_XT_DIV8K = 40, /*!< XT_DIV8K : XT / 8192 */ - CLKGEN_CLKOUT_CKSEL_XT_DIV64K = 41, /*!< XT_DIV64K : XT / 2^16 */ - CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16 = 42, /*!< ULFRC_DIV16 : Uncal LFRC / 16 */ - CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 = 43, /*!< ULFRC_DIV128 : Uncal LFRC / 128 */ - CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz = 44, /*!< ULFRC_1Hz : Uncal LFRC / 1024 */ - CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K = 45, /*!< ULFRC_DIV4K : Uncal LFRC / 4096 */ - CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M = 46, /*!< ULFRC_DIV1M : Uncal LFRC / 2^20 */ - CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K = 47, /*!< HFRC_DIV64K : HFRC / 2^16 */ - CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M = 48, /*!< HFRC_DIV16M : HFRC / 2^24 */ - CLKGEN_CLKOUT_CKSEL_LFRC_DIV1M = 49, /*!< LFRC_DIV1M : LFRC / 2^20 */ - CLKGEN_CLKOUT_CKSEL_HFRCNE = 50, /*!< HFRCNE : HFRC (not autoenabled) */ - CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8 = 51, /*!< HFRCNE_DIV8 : HFRC / 8 (not autoenabled) */ - CLKGEN_CLKOUT_CKSEL_XTNE = 53, /*!< XTNE : XT (not autoenabled) */ - CLKGEN_CLKOUT_CKSEL_XTNE_DIV16 = 54, /*!< XTNE_DIV16 : XT / 16 (not autoenabled) */ - CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 = 55, /*!< LFRCNE_DIV32 : LFRC / 32 (not autoenabled) */ - CLKGEN_CLKOUT_CKSEL_LFRCNE = 57, /*!< LFRCNE : LFRC (not autoenabled) - Default for undefined values */ -} CLKGEN_CLKOUT_CKSEL_Enum; - -/* ======================================================== CLKKEY ========================================================= */ -/* ============================================= CLKGEN CLKKEY CLKKEY [0..31] ============================================== */ -typedef enum { /*!< CLKGEN_CLKKEY_CLKKEY */ - CLKGEN_CLKKEY_CLKKEY_Key = 71, /*!< Key : Key */ -} CLKGEN_CLKKEY_CLKKEY_Enum; - -/* ========================================================= CCTRL ========================================================= */ -/* ============================================== CLKGEN CCTRL CORESEL [0..0] ============================================== */ -typedef enum { /*!< CLKGEN_CCTRL_CORESEL */ - CLKGEN_CCTRL_CORESEL_HFRC = 0, /*!< HFRC : Core Clock is HFRC */ - CLKGEN_CCTRL_CORESEL_HFRC_DIV2 = 1, /*!< HFRC_DIV2 : Core Clock is HFRC / 2 */ -} CLKGEN_CCTRL_CORESEL_Enum; - -/* ======================================================== STATUS ========================================================= */ -/* ========================================================= HFADJ ========================================================= */ -/* ============================================ CLKGEN HFADJ HFADJGAIN [21..23] ============================================ */ -typedef enum { /*!< CLKGEN_HFADJ_HFADJGAIN */ - CLKGEN_HFADJ_HFADJGAIN_Gain_of_1 = 0, /*!< Gain_of_1 : HF Adjust with Gain of 1 */ - CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_2 = 1, /*!< Gain_of_1_in_2 : HF Adjust with Gain of 0.5 */ - CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_4 = 2, /*!< Gain_of_1_in_4 : HF Adjust with Gain of 0.25 */ - CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_8 = 3, /*!< Gain_of_1_in_8 : HF Adjust with Gain of 0.125 */ - CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_16 = 4, /*!< Gain_of_1_in_16 : HF Adjust with Gain of 0.0625 */ - CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_32 = 5, /*!< Gain_of_1_in_32 : HF Adjust with Gain of 0.03125 */ -} CLKGEN_HFADJ_HFADJGAIN_Enum; - -/* ============================================ CLKGEN HFADJ HFWARMUP [20..20] ============================================= */ -typedef enum { /*!< CLKGEN_HFADJ_HFWARMUP */ - CLKGEN_HFADJ_HFWARMUP_1SEC = 0, /*!< 1SEC : Autoadjust XT warmup period = 1-2 seconds */ - CLKGEN_HFADJ_HFWARMUP_2SEC = 1, /*!< 2SEC : Autoadjust XT warmup period = 2-4 seconds */ -} CLKGEN_HFADJ_HFWARMUP_Enum; - -/* ============================================== CLKGEN HFADJ HFADJCK [1..3] ============================================== */ -typedef enum { /*!< CLKGEN_HFADJ_HFADJCK */ - CLKGEN_HFADJ_HFADJCK_4SEC = 0, /*!< 4SEC : Autoadjust repeat period = 4 seconds */ - CLKGEN_HFADJ_HFADJCK_16SEC = 1, /*!< 16SEC : Autoadjust repeat period = 16 seconds */ - CLKGEN_HFADJ_HFADJCK_32SEC = 2, /*!< 32SEC : Autoadjust repeat period = 32 seconds */ - CLKGEN_HFADJ_HFADJCK_64SEC = 3, /*!< 64SEC : Autoadjust repeat period = 64 seconds */ - CLKGEN_HFADJ_HFADJCK_128SEC = 4, /*!< 128SEC : Autoadjust repeat period = 128 seconds */ - CLKGEN_HFADJ_HFADJCK_256SEC = 5, /*!< 256SEC : Autoadjust repeat period = 256 seconds */ - CLKGEN_HFADJ_HFADJCK_512SEC = 6, /*!< 512SEC : Autoadjust repeat period = 512 seconds */ - CLKGEN_HFADJ_HFADJCK_1024SEC = 7, /*!< 1024SEC : Autoadjust repeat period = 1024 seconds */ -} CLKGEN_HFADJ_HFADJCK_Enum; - -/* ============================================== CLKGEN HFADJ HFADJEN [0..0] ============================================== */ -typedef enum { /*!< CLKGEN_HFADJ_HFADJEN */ - CLKGEN_HFADJ_HFADJEN_DIS = 0, /*!< DIS : Disable the HFRC adjustment */ - CLKGEN_HFADJ_HFADJEN_EN = 1, /*!< EN : Enable the HFRC adjustment */ -} CLKGEN_HFADJ_HFADJEN_Enum; - -/* ====================================================== CLOCKENSTAT ====================================================== */ -/* ======================================== CLKGEN CLOCKENSTAT CLOCKENSTAT [0..31] ========================================= */ -typedef enum { /*!< CLKGEN_CLOCKENSTAT_CLOCKENSTAT */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_ADC_CLKEN = 1, /*!< ADC_CLKEN : Clock enable for the ADC. */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_ACTIVITY_CLKEN = 2,/*!< APBDMA_ACTIVITY_CLKEN : Clock enable for the APBDMA ACTIVITY */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_AOH_CLKEN = 4,/*!< APBDMA_AOH_CLKEN : Clock enable for the APBDMA AOH DOMAIN */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_AOL_CLKEN = 8,/*!< APBDMA_AOL_CLKEN : Clock enable for the APBDMA AOL DOMAIN */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_APB_CLKEN = 16,/*!< APBDMA_APB_CLKEN : Clock enable for the APBDMA_APB */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_BLEL_CLKEN = 32,/*!< APBDMA_BLEL_CLKEN : Clock enable for the APBDMA_BLEL */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPA_CLKEN = 64,/*!< APBDMA_HCPA_CLKEN : Clock enable for the APBDMA_HCPA */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPB_CLKEN = 128,/*!< APBDMA_HCPB_CLKEN : Clock enable for the APBDMA_HCPB */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPC_CLKEN = 256,/*!< APBDMA_HCPC_CLKEN : Clock enable for the APBDMA_HCPC */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_MSPI_CLKEN = 512,/*!< APBDMA_MSPI_CLKEN : Clock enable for the APBDMA_MSPI */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_MSPI1_CLKEN = 1024,/*!< APBDMA_MSPI1_CLKEN : Clock enable for the APBDMA_MSPI1 */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_MSPI2_CLKEN = 2048,/*!< APBDMA_MSPI2_CLKEN : Clock enable for the APBDMA_MSPI2 */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_PDM_CLKEN = 4096,/*!< APBDMA_PDM_CLKEN : Clock enable for the APBDMA_PDM */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_BLEIF_CLK_CLKEN = 8192,/*!< BLEIF_CLK_CLKEN : Clock enable for the BLEIF */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_BLEIF_CLK32K_CLKEN = 16384,/*!< BLEIF_CLK32K_CLKEN : Clock enable for the BLEIF 32khZ CLOCK */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER_CLKEN = 32768,/*!< CTIMER_CLKEN : Clock enable for the CTIMER BLOCK */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER0A_CLKEN = 65536,/*!< CTIMER0A_CLKEN : Clock enable for the CTIMER0A */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER0B_CLKEN = 131072,/*!< CTIMER0B_CLKEN : Clock enable for the CTIMER0B */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER1A_CLKEN = 262144,/*!< CTIMER1A_CLKEN : Clock enable for the CTIMER1A */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER1B_CLKEN = 524288,/*!< CTIMER1B_CLKEN : Clock enable for the CTIMER1B */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER2A_CLKEN = 1048576,/*!< CTIMER2A_CLKEN : Clock enable for the CTIMER2A */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER2B_CLKEN = 2097152,/*!< CTIMER2B_CLKEN : Clock enable for the CTIMER2B */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER3A_CLKEN = 4194304,/*!< CTIMER3A_CLKEN : Clock enable for the CTIMER3A */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER3B_CLKEN = 8388608,/*!< CTIMER3B_CLKEN : Clock enable for the CTIMER3B */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER4A_CLKEN = 16777216,/*!< CTIMER4A_CLKEN : Clock enable for the CTIMER4A */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER4B_CLKEN = 33554432,/*!< CTIMER4B_CLKEN : Clock enable for the CTIMER4B */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER5A_CLKEN = 67108864,/*!< CTIMER5A_CLKEN : Clock enable for the CTIMER5A */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER5B_CLKEN = 134217728,/*!< CTIMER5B_CLKEN : Clock enable for the CTIMER5B */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER6A_CLKEN = 268435456,/*!< CTIMER6A_CLKEN : Clock enable for the CTIMER6A */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER6B_CLKEN = 536870912,/*!< CTIMER6B_CLKEN : Clock enable for the CTIMER6B */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER7A_CLKEN = 1073741824,/*!< CTIMER7A_CLKEN : Clock enable for the CTIMER7A */ - CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER7B_CLKEN = -2147483648,/*!< CTIMER7B_CLKEN : Clock enable for the CTIMER7B */ -} CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Enum; - -/* ===================================================== CLOCKEN2STAT ====================================================== */ -/* ======================================= CLKGEN CLOCKEN2STAT CLOCKEN2STAT [0..31] ======================================== */ -typedef enum { /*!< CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DAP_CLKEN = 1,/*!< DAP_CLKEN : Clock enable for the DAP */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC0_CLKEN = 2,/*!< IOMSTRIFC0_CLKEN : Clock enable for the IO MASTER 0 IFC INTERFACE */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC1_CLKEN = 4,/*!< IOMSTRIFC1_CLKEN : Clock enable for the IO MASTER 1 IFC INTERFACE */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC2_CLKEN = 8,/*!< IOMSTRIFC2_CLKEN : Clock enable for the IO MASTER 2 IFC INTERFACE */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC3_CLKEN = 16,/*!< IOMSTRIFC3_CLKEN : Clock enable for the IO MASTER 3 IFC INTERFACE */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC4_CLKEN = 32,/*!< IOMSTRIFC4_CLKEN : Clock enable for the IO MASTER 4 IFC INTERFACE */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC5_CLKEN = 64,/*!< IOMSTRIFC5_CLKEN : Clock enable for the IO MASTER 5 IFC INTERFACE */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PDM_CLKEN = 128,/*!< PDM_CLKEN : Clock enable for the PDM */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PDMIFC_CLKEN = 256,/*!< PDMIFC_CLKEN : Clock enable for the PDM INTERFACE */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PWRCTRL_CLKEN = 512,/*!< PWRCTRL_CLKEN : Clock enable for the PWRCTRL */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PWRCTRL_COUNT_CLKEN = 1024,/*!< PWRCTRL_COUNT_CLKEN : Clock enable for the PWRCTRL counter */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_RSTGEN_CLKEN = 2048,/*!< RSTGEN_CLKEN : Clock enable for the RSTGEN */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_SCARD_CLKEN = 4096,/*!< SCARD_CLKEN : Clock enable for the SCARD */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_SCARD_ALTAPB_CLKEN = 8192,/*!< SCARD_ALTAPB_CLKEN : Clock enable for the SCARD ALTAPB */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_STIMER_CNT_CLKEN = 16384,/*!< STIMER_CNT_CLKEN : Clock enable for the STIMER_CNT_CLKEN */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_TPIU_CLKEN = 32768,/*!< TPIU_CLKEN : Clock enable for the TPIU_CLKEN */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_UART0HF_CLKEN = 65536,/*!< UART0HF_CLKEN : Clock enable for the UART0 HF */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_UART1HF_CLKEN = 131072,/*!< UART1HF_CLKEN : Clock enable for the UART1 HF */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_WDT_CLKEN = 262144,/*!< WDT_CLKEN : Clock enable for the Watchdog timer */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_XT_32KHZ_EN = 1073741824,/*!< XT_32KHZ_EN : Clock enable for the XT 32KHZ */ - CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_FORCEHFRC = -2147483648,/*!< FORCEHFRC : HFRC is forced on Status. */ -} CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Enum; - -/* ===================================================== CLOCKEN3STAT ====================================================== */ -/* ======================================= CLKGEN CLOCKEN3STAT CLOCKEN3STAT [0..31] ======================================== */ -typedef enum { /*!< CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT */ - CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DAP_enabled = 131072,/*!< DAP_enabled : DAP clock is enabled [17] */ - CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_VCOMP_enabled = 262144,/*!< VCOMP_enabled : VCOMP powerdown indicator [18] */ - CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_XTAL_enabled = 16777216,/*!< XTAL_enabled : XTAL is enabled [24] */ - CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFRC_enabled = 33554432,/*!< HFRC_enabled : HFRC is enabled [25] */ - CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFADJEN = 67108864,/*!< HFADJEN : HFRC Adjust enabled [26] */ - CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFRC_en_out = 134217728,/*!< HFRC_en_out : HFRC Enabled out [27] */ - CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RTC_XT = 268435456,/*!< RTC_XT : RTC use XT [28] */ - CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_clkout_xtal_en = 536870912,/*!< clkout_xtal_en : XTAL clkout enabled [29] */ - CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_clkout_hfrc_en = 1073741824,/*!< clkout_hfrc_en : HFRC clkout enabled [30] */ - CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_flashclk_en = -2147483648,/*!< flashclk_en : Flash clk is enabled [31] */ -} CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Enum; - -/* ======================================================= FREQCTRL ======================================================== */ -/* ============================================ CLKGEN FREQCTRL BURSTREQ [0..0] ============================================ */ -typedef enum { /*!< CLKGEN_FREQCTRL_BURSTREQ */ - CLKGEN_FREQCTRL_BURSTREQ_DIS = 0, /*!< DIS : Frequency for ARM core stays at 48MHz */ - CLKGEN_FREQCTRL_BURSTREQ_EN = 1, /*!< EN : Frequency for ARM core is increased to 96MHz */ -} CLKGEN_FREQCTRL_BURSTREQ_Enum; - -/* ===================================================== BLEBUCKTONADJ ===================================================== */ -/* ===================================== CLKGEN BLEBUCKTONADJ ZEROLENDETECTEN [27..27] ===================================== */ -typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_DIS = 0, /*!< DIS : Disable Zero Length Detect */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_EN = 1, /*!< EN : Enable Zero Length Detect */ -} CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Enum; - -/* ==================================== CLKGEN BLEBUCKTONADJ ZEROLENDETECTTRIM [23..26] ==================================== */ -typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetF = 15,/*!< SetF : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 81us (10 percent margin of error) or more */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetE = 14,/*!< SetE : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 75.6us (10 percent margin of error) or more */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetD = 13,/*!< SetD : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 70.2us (10 percent margin of error) or more */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetC = 12,/*!< SetC : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 64.8us (10 percent margin of error) or more */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetB = 11,/*!< SetB : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 59.4us (10 percent margin of error) or more */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetA = 10,/*!< SetA : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 54.0us (10 percent margin of error) or more */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set9 = 9,/*!< Set9 : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 48.6us (10 percent margin of error) or more */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set8 = 8,/*!< Set8 : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 43.2us (10 percent margin of error) or more */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set7 = 7,/*!< Set7 : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 37.8us (10 percent margin of error) or more */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set6 = 6,/*!< Set6 : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 32.4us (10 percent margin of error) or more */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set5 = 5,/*!< Set5 : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 27.0us (10 percent margin of error) or more */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set4 = 4,/*!< Set4 : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 21.6us (10 percent margin of error) or more */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set3 = 3,/*!< Set3 : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 16.2us (10 percent margin of error) or more */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set2 = 2,/*!< Set2 : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 10.8us (10 percent margin of error) or more */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set1 = 1,/*!< Set1 : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 5.4us (10 percent margin of error) or more */ - CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set0 = 0,/*!< Set0 : Indicator send when the BLE BUCK asserts blebuck_comp1 - for about 2.0us (10 percent margin of error) or more */ -} CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Enum; - -/* ======================================= CLKGEN BLEBUCKTONADJ TONADJUSTEN [22..22] ======================================= */ -typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_TONADJUSTEN */ - CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_DIS = 0, /*!< DIS : Disable Adjust for BLE BUCK TON trim */ - CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_EN = 1, /*!< EN : Enable Adjust for BLE BUCK TON trim */ -} CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Enum; - -/* ===================================== CLKGEN BLEBUCKTONADJ TONADJUSTPERIOD [20..21] ===================================== */ -typedef enum { /*!< CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD */ - CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_3KHz = 3,/*!< HFRC_3KHz : Adjust done for every 1 3KHz period */ - CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_12KHz = 2,/*!< HFRC_12KHz : Adjust done for every 1 12KHz period */ - CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_47KHz = 1,/*!< HFRC_47KHz : Adjust done for every 1 47KHz period */ - CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_94KHz = 0,/*!< HFRC_94KHz : Adjust done for every 1 94KHz period */ -} CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Enum; - -/* ======================================================= INTRPTEN ======================================================== */ -/* ====================================================== INTRPTSTAT ======================================================= */ -/* ======================================================= INTRPTCLR ======================================================= */ -/* ======================================================= INTRPTSET ======================================================= */ - - -/* =========================================================================================================================== */ -/* ================ CTIMER ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= TMR0 ========================================================== */ -/* ======================================================== CMPRA0 ========================================================= */ -/* ======================================================== CMPRB0 ========================================================= */ -/* ========================================================= CTRL0 ========================================================= */ -/* ============================================= CTIMER CTRL0 CTLINK0 [31..31] ============================================= */ -typedef enum { /*!< CTIMER_CTRL0_CTLINK0 */ - CTIMER_CTRL0_CTLINK0_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A0/B0 timers as two independent 16-bit - timers (default). */ - CTIMER_CTRL0_CTLINK0_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A0/B0 timers into a single 32-bit timer. */ -} CTIMER_CTRL0_CTLINK0_Enum; - -/* ============================================ CTIMER CTRL0 TMRB0POL [28..28] ============================================= */ -typedef enum { /*!< CTIMER_CTRL0_TMRB0POL */ - CTIMER_CTRL0_TMRB0POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB0 pin is the same as the - timer output. */ - CTIMER_CTRL0_TMRB0POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB0 pin is the inverse of - the timer output. */ -} CTIMER_CTRL0_TMRB0POL_Enum; - -/* ============================================ CTIMER CTRL0 TMRB0CLR [27..27] ============================================= */ -typedef enum { /*!< CTIMER_CTRL0_TMRB0CLR */ - CTIMER_CTRL0_TMRB0CLR_RUN = 0, /*!< RUN : Allow counter/timer B0 to run */ - CTIMER_CTRL0_TMRB0CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B0 at 0x0000. */ -} CTIMER_CTRL0_TMRB0CLR_Enum; - -/* ============================================ CTIMER CTRL0 TMRB0IE1 [26..26] ============================================= */ -typedef enum { /*!< CTIMER_CTRL0_TMRB0IE1 */ - CTIMER_CTRL0_TMRB0IE1_DIS = 0, /*!< DIS : Disable counter/timer B0 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL0_TMRB0IE1_EN = 1, /*!< EN : Enable counter/timer B0 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL0_TMRB0IE1_Enum; - -/* ============================================ CTIMER CTRL0 TMRB0IE0 [25..25] ============================================= */ -typedef enum { /*!< CTIMER_CTRL0_TMRB0IE0 */ - CTIMER_CTRL0_TMRB0IE0_DIS = 0, /*!< DIS : Disable counter/timer B0 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL0_TMRB0IE0_EN = 1, /*!< EN : Enable counter/timer B0 to generate an interrupt based - on COMPR0 */ -} CTIMER_CTRL0_TMRB0IE0_Enum; - -/* ============================================= CTIMER CTRL0 TMRB0FN [22..24] ============================================= */ -typedef enum { /*!< CTIMER_CTRL0_TMRB0FN */ - CTIMER_CTRL0_TMRB0FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0B0, stop. */ - CTIMER_CTRL0_TMRB0FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0B0, restart. */ - CTIMER_CTRL0_TMRB0FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B0, assert, - count to CMPR1B0, deassert, stop. */ - CTIMER_CTRL0_TMRB0FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B0, assert, count - to CMPR1B0, deassert, restart. */ - CTIMER_CTRL0_TMRB0FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL0_TMRB0FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL0_TMRB0FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL0_TMRB0FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL0_TMRB0FN_Enum; - -/* ============================================ CTIMER CTRL0 TMRB0CLK [17..21] ============================================= */ -typedef enum { /*!< CTIMER_CTRL0_TMRB0CLK */ - CTIMER_CTRL0_TMRB0CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ - CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL0_TMRB0CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL0_TMRB0CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL0_TMRB0CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL0_TMRB0CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL0_TMRB0CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL0_TMRB0CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL0_TMRB0CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL0_TMRB0CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL0_TMRB0CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL0_TMRB0CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL0_TMRB0CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL0_TMRB0CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL0_TMRB0CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL0_TMRB0CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL0_TMRB0CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL0_TMRB0CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL0_TMRB0CLK_CTMRA0 = 20, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ - CTIMER_CTRL0_TMRB0CLK_CTMRB1 = 21, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ - CTIMER_CTRL0_TMRB0CLK_CTMRA1 = 22, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */ - CTIMER_CTRL0_TMRB0CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ - CTIMER_CTRL0_TMRB0CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ - CTIMER_CTRL0_TMRB0CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ - CTIMER_CTRL0_TMRB0CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ - CTIMER_CTRL0_TMRB0CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ - CTIMER_CTRL0_TMRB0CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ - CTIMER_CTRL0_TMRB0CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL0_TMRB0CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL0_TMRB0CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL0_TMRB0CLK_Enum; - -/* ============================================= CTIMER CTRL0 TMRB0EN [16..16] ============================================= */ -typedef enum { /*!< CTIMER_CTRL0_TMRB0EN */ - CTIMER_CTRL0_TMRB0EN_DIS = 0, /*!< DIS : Counter/Timer B0 Disable. */ - CTIMER_CTRL0_TMRB0EN_EN = 1, /*!< EN : Counter/Timer B0 Enable. */ -} CTIMER_CTRL0_TMRB0EN_Enum; - -/* ============================================ CTIMER CTRL0 TMRA0POL [12..12] ============================================= */ -typedef enum { /*!< CTIMER_CTRL0_TMRA0POL */ - CTIMER_CTRL0_TMRA0POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA0 pin is the same as the - timer output. */ - CTIMER_CTRL0_TMRA0POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA0 pin is the inverse of - the timer output. */ -} CTIMER_CTRL0_TMRA0POL_Enum; - -/* ============================================ CTIMER CTRL0 TMRA0CLR [11..11] ============================================= */ -typedef enum { /*!< CTIMER_CTRL0_TMRA0CLR */ - CTIMER_CTRL0_TMRA0CLR_RUN = 0, /*!< RUN : Allow counter/timer A0 to run */ - CTIMER_CTRL0_TMRA0CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A0 at 0x0000. */ -} CTIMER_CTRL0_TMRA0CLR_Enum; - -/* ============================================ CTIMER CTRL0 TMRA0IE1 [10..10] ============================================= */ -typedef enum { /*!< CTIMER_CTRL0_TMRA0IE1 */ - CTIMER_CTRL0_TMRA0IE1_DIS = 0, /*!< DIS : Disable counter/timer A0 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL0_TMRA0IE1_EN = 1, /*!< EN : Enable counter/timer A0 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL0_TMRA0IE1_Enum; - -/* ============================================= CTIMER CTRL0 TMRA0IE0 [9..9] ============================================== */ -typedef enum { /*!< CTIMER_CTRL0_TMRA0IE0 */ - CTIMER_CTRL0_TMRA0IE0_DIS = 0, /*!< DIS : Disable counter/timer A0 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL0_TMRA0IE0_EN = 1, /*!< EN : Enable counter/timer A0 to generate an interrupt based - on COMPR0. */ -} CTIMER_CTRL0_TMRA0IE0_Enum; - -/* ============================================== CTIMER CTRL0 TMRA0FN [6..8] ============================================== */ -typedef enum { /*!< CTIMER_CTRL0_TMRA0FN */ - CTIMER_CTRL0_TMRA0FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0A0, stop. */ - CTIMER_CTRL0_TMRA0FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0A0, restart. */ - CTIMER_CTRL0_TMRA0FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A0, assert, - count to CMPR1A0, deassert, stop. */ - CTIMER_CTRL0_TMRA0FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A0, assert, count - to CMPR1A0, deassert, restart. */ - CTIMER_CTRL0_TMRA0FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL0_TMRA0FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL0_TMRA0FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL0_TMRA0FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL0_TMRA0FN_Enum; - -/* ============================================= CTIMER CTRL0 TMRA0CLK [1..5] ============================================== */ -typedef enum { /*!< CTIMER_CTRL0_TMRA0CLK */ - CTIMER_CTRL0_TMRA0CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ - CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL0_TMRA0CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL0_TMRA0CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL0_TMRA0CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL0_TMRA0CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL0_TMRA0CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL0_TMRA0CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL0_TMRA0CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL0_TMRA0CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL0_TMRA0CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL0_TMRA0CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL0_TMRA0CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL0_TMRA0CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL0_TMRA0CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL0_TMRA0CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL0_TMRA0CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL0_TMRA0CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL0_TMRA0CLK_CTMRB0 = 20, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ - CTIMER_CTRL0_TMRA0CLK_CTMRA1 = 21, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */ - CTIMER_CTRL0_TMRA0CLK_CTMRB1 = 22, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ - CTIMER_CTRL0_TMRA0CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ - CTIMER_CTRL0_TMRA0CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ - CTIMER_CTRL0_TMRA0CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ - CTIMER_CTRL0_TMRA0CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ - CTIMER_CTRL0_TMRA0CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ - CTIMER_CTRL0_TMRA0CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ - CTIMER_CTRL0_TMRA0CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL0_TMRA0CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL0_TMRA0CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL0_TMRA0CLK_Enum; - -/* ============================================== CTIMER CTRL0 TMRA0EN [0..0] ============================================== */ -typedef enum { /*!< CTIMER_CTRL0_TMRA0EN */ - CTIMER_CTRL0_TMRA0EN_DIS = 0, /*!< DIS : Counter/Timer A0 Disable. */ - CTIMER_CTRL0_TMRA0EN_EN = 1, /*!< EN : Counter/Timer A0 Enable. */ -} CTIMER_CTRL0_TMRA0EN_Enum; - -/* ======================================================= CMPRAUXA0 ======================================================= */ -/* ======================================================= CMPRAUXB0 ======================================================= */ -/* ========================================================= AUX0 ========================================================== */ -/* ============================================ CTIMER AUX0 TMRB0EN23 [30..30] ============================================= */ -typedef enum { /*!< CTIMER_AUX0_TMRB0EN23 */ - CTIMER_AUX0_TMRB0EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX0_TMRB0EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX0_TMRB0EN23_Enum; - -/* ============================================ CTIMER AUX0 TMRB0POL23 [29..29] ============================================ */ -typedef enum { /*!< CTIMER_AUX0_TMRB0POL23 */ - CTIMER_AUX0_TMRB0POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ - CTIMER_AUX0_TMRB0POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX0_TMRB0POL23_Enum; - -/* ============================================ CTIMER AUX0 TMRB0TINV [28..28] ============================================= */ -typedef enum { /*!< CTIMER_AUX0_TMRB0TINV */ - CTIMER_AUX0_TMRB0TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX0_TMRB0TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX0_TMRB0TINV_Enum; - -/* =========================================== CTIMER AUX0 TMRB0NOSYNC [27..27] ============================================ */ -typedef enum { /*!< CTIMER_AUX0_TMRB0NOSYNC */ - CTIMER_AUX0_TMRB0NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX0_TMRB0NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX0_TMRB0NOSYNC_Enum; - -/* ============================================ CTIMER AUX0 TMRB0TRIG [23..26] ============================================= */ -typedef enum { /*!< CTIMER_AUX0_TMRB0TRIG */ - CTIMER_AUX0_TMRB0TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX0_TMRB0TRIG_A0OUT = 1, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */ - CTIMER_AUX0_TMRB0TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ - CTIMER_AUX0_TMRB0TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ - CTIMER_AUX0_TMRB0TRIG_B2OUT = 4, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ - CTIMER_AUX0_TMRB0TRIG_B5OUT = 5, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */ - CTIMER_AUX0_TMRB0TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ - CTIMER_AUX0_TMRB0TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ - CTIMER_AUX0_TMRB0TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ - CTIMER_AUX0_TMRB0TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ - CTIMER_AUX0_TMRB0TRIG_B7OUT2 = 10, /*!< B7OUT2 : Trigger source is CTIMERB7 OUT2. */ - CTIMER_AUX0_TMRB0TRIG_A2OUT2 = 11, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ - CTIMER_AUX0_TMRB0TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ - CTIMER_AUX0_TMRB0TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ - CTIMER_AUX0_TMRB0TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */ - CTIMER_AUX0_TMRB0TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ -} CTIMER_AUX0_TMRB0TRIG_Enum; - -/* ============================================ CTIMER AUX0 TMRA0EN23 [14..14] ============================================= */ -typedef enum { /*!< CTIMER_AUX0_TMRA0EN23 */ - CTIMER_AUX0_TMRA0EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX0_TMRA0EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX0_TMRA0EN23_Enum; - -/* ============================================ CTIMER AUX0 TMRA0POL23 [13..13] ============================================ */ -typedef enum { /*!< CTIMER_AUX0_TMRA0POL23 */ - CTIMER_AUX0_TMRA0POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ - CTIMER_AUX0_TMRA0POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX0_TMRA0POL23_Enum; - -/* ============================================ CTIMER AUX0 TMRA0TINV [12..12] ============================================= */ -typedef enum { /*!< CTIMER_AUX0_TMRA0TINV */ - CTIMER_AUX0_TMRA0TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX0_TMRA0TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX0_TMRA0TINV_Enum; - -/* =========================================== CTIMER AUX0 TMRA0NOSYNC [11..11] ============================================ */ -typedef enum { /*!< CTIMER_AUX0_TMRA0NOSYNC */ - CTIMER_AUX0_TMRA0NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX0_TMRA0NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX0_TMRA0NOSYNC_Enum; - -/* ============================================= CTIMER AUX0 TMRA0TRIG [7..10] ============================================= */ -typedef enum { /*!< CTIMER_AUX0_TMRA0TRIG */ - CTIMER_AUX0_TMRA0TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX0_TMRA0TRIG_B0OUT = 1, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */ - CTIMER_AUX0_TMRA0TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ - CTIMER_AUX0_TMRA0TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ - CTIMER_AUX0_TMRA0TRIG_A1OUT = 4, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ - CTIMER_AUX0_TMRA0TRIG_B1OUT = 5, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ - CTIMER_AUX0_TMRA0TRIG_A5OUT = 6, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */ - CTIMER_AUX0_TMRA0TRIG_B5OUT = 7, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */ - CTIMER_AUX0_TMRA0TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ - CTIMER_AUX0_TMRA0TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ - CTIMER_AUX0_TMRA0TRIG_B6OUT2 = 10, /*!< B6OUT2 : Trigger source is CTIMERB6 OUT2. */ - CTIMER_AUX0_TMRA0TRIG_A2OUT2 = 11, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ - CTIMER_AUX0_TMRA0TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ - CTIMER_AUX0_TMRA0TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ - CTIMER_AUX0_TMRA0TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ - CTIMER_AUX0_TMRA0TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ -} CTIMER_AUX0_TMRA0TRIG_Enum; - -/* ========================================================= TMR1 ========================================================== */ -/* ======================================================== CMPRA1 ========================================================= */ -/* ======================================================== CMPRB1 ========================================================= */ -/* ========================================================= CTRL1 ========================================================= */ -/* ============================================= CTIMER CTRL1 CTLINK1 [31..31] ============================================= */ -typedef enum { /*!< CTIMER_CTRL1_CTLINK1 */ - CTIMER_CTRL1_CTLINK1_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A1/B1 timers as two independent 16-bit - timers (default). */ - CTIMER_CTRL1_CTLINK1_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A1/B1 timers into a single 32-bit timer. */ -} CTIMER_CTRL1_CTLINK1_Enum; - -/* ============================================ CTIMER CTRL1 TMRB1POL [28..28] ============================================= */ -typedef enum { /*!< CTIMER_CTRL1_TMRB1POL */ - CTIMER_CTRL1_TMRB1POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB1 pin is the same as the - timer output. */ - CTIMER_CTRL1_TMRB1POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB1 pin is the inverse of - the timer output. */ -} CTIMER_CTRL1_TMRB1POL_Enum; - -/* ============================================ CTIMER CTRL1 TMRB1CLR [27..27] ============================================= */ -typedef enum { /*!< CTIMER_CTRL1_TMRB1CLR */ - CTIMER_CTRL1_TMRB1CLR_RUN = 0, /*!< RUN : Allow counter/timer B1 to run */ - CTIMER_CTRL1_TMRB1CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B1 at 0x0000. */ -} CTIMER_CTRL1_TMRB1CLR_Enum; - -/* ============================================ CTIMER CTRL1 TMRB1IE1 [26..26] ============================================= */ -typedef enum { /*!< CTIMER_CTRL1_TMRB1IE1 */ - CTIMER_CTRL1_TMRB1IE1_DIS = 0, /*!< DIS : Disable counter/timer B1 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL1_TMRB1IE1_EN = 1, /*!< EN : Enable counter/timer B1 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL1_TMRB1IE1_Enum; - -/* ============================================ CTIMER CTRL1 TMRB1IE0 [25..25] ============================================= */ -typedef enum { /*!< CTIMER_CTRL1_TMRB1IE0 */ - CTIMER_CTRL1_TMRB1IE0_DIS = 0, /*!< DIS : Disable counter/timer B1 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL1_TMRB1IE0_EN = 1, /*!< EN : Enable counter/timer B1 to generate an interrupt based - on COMPR0 */ -} CTIMER_CTRL1_TMRB1IE0_Enum; - -/* ============================================= CTIMER CTRL1 TMRB1FN [22..24] ============================================= */ -typedef enum { /*!< CTIMER_CTRL1_TMRB1FN */ - CTIMER_CTRL1_TMRB1FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0B1, stop. */ - CTIMER_CTRL1_TMRB1FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0B1, restart. */ - CTIMER_CTRL1_TMRB1FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B1, assert, - count to CMPR1B1, deassert, stop. */ - CTIMER_CTRL1_TMRB1FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B1, assert, count - to CMPR1B1, deassert, restart. */ - CTIMER_CTRL1_TMRB1FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL1_TMRB1FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL1_TMRB1FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL1_TMRB1FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL1_TMRB1FN_Enum; - -/* ============================================ CTIMER CTRL1 TMRB1CLK [17..21] ============================================= */ -typedef enum { /*!< CTIMER_CTRL1_TMRB1CLK */ - CTIMER_CTRL1_TMRB1CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ - CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL1_TMRB1CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL1_TMRB1CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL1_TMRB1CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL1_TMRB1CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL1_TMRB1CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL1_TMRB1CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL1_TMRB1CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL1_TMRB1CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL1_TMRB1CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL1_TMRB1CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL1_TMRB1CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL1_TMRB1CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL1_TMRB1CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL1_TMRB1CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL1_TMRB1CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL1_TMRB1CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL1_TMRB1CLK_CTMRA1 = 20, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */ - CTIMER_CTRL1_TMRB1CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ - CTIMER_CTRL1_TMRB1CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ - CTIMER_CTRL1_TMRB1CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ - CTIMER_CTRL1_TMRB1CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ - CTIMER_CTRL1_TMRB1CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ - CTIMER_CTRL1_TMRB1CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ - CTIMER_CTRL1_TMRB1CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ - CTIMER_CTRL1_TMRB1CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ - CTIMER_CTRL1_TMRB1CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL1_TMRB1CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL1_TMRB1CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL1_TMRB1CLK_Enum; - -/* ============================================= CTIMER CTRL1 TMRB1EN [16..16] ============================================= */ -typedef enum { /*!< CTIMER_CTRL1_TMRB1EN */ - CTIMER_CTRL1_TMRB1EN_DIS = 0, /*!< DIS : Counter/Timer B1 Disable. */ - CTIMER_CTRL1_TMRB1EN_EN = 1, /*!< EN : Counter/Timer B1 Enable. */ -} CTIMER_CTRL1_TMRB1EN_Enum; - -/* ============================================ CTIMER CTRL1 TMRA1POL [12..12] ============================================= */ -typedef enum { /*!< CTIMER_CTRL1_TMRA1POL */ - CTIMER_CTRL1_TMRA1POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA1 pin is the same as the - timer output. */ - CTIMER_CTRL1_TMRA1POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA1 pin is the inverse of - the timer output. */ -} CTIMER_CTRL1_TMRA1POL_Enum; - -/* ============================================ CTIMER CTRL1 TMRA1CLR [11..11] ============================================= */ -typedef enum { /*!< CTIMER_CTRL1_TMRA1CLR */ - CTIMER_CTRL1_TMRA1CLR_RUN = 0, /*!< RUN : Allow counter/timer A1 to run */ - CTIMER_CTRL1_TMRA1CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A1 at 0x0000. */ -} CTIMER_CTRL1_TMRA1CLR_Enum; - -/* ============================================ CTIMER CTRL1 TMRA1IE1 [10..10] ============================================= */ -typedef enum { /*!< CTIMER_CTRL1_TMRA1IE1 */ - CTIMER_CTRL1_TMRA1IE1_DIS = 0, /*!< DIS : Disable counter/timer A1 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL1_TMRA1IE1_EN = 1, /*!< EN : Enable counter/timer A1 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL1_TMRA1IE1_Enum; - -/* ============================================= CTIMER CTRL1 TMRA1IE0 [9..9] ============================================== */ -typedef enum { /*!< CTIMER_CTRL1_TMRA1IE0 */ - CTIMER_CTRL1_TMRA1IE0_DIS = 0, /*!< DIS : Disable counter/timer A1 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL1_TMRA1IE0_EN = 1, /*!< EN : Enable counter/timer A1 to generate an interrupt based - on COMPR0. */ -} CTIMER_CTRL1_TMRA1IE0_Enum; - -/* ============================================== CTIMER CTRL1 TMRA1FN [6..8] ============================================== */ -typedef enum { /*!< CTIMER_CTRL1_TMRA1FN */ - CTIMER_CTRL1_TMRA1FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0A1, stop. */ - CTIMER_CTRL1_TMRA1FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0A1, restart. */ - CTIMER_CTRL1_TMRA1FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A1, assert, - count to CMPR1A1, deassert, stop. */ - CTIMER_CTRL1_TMRA1FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A1, assert, count - to CMPR1A1, deassert, restart. */ - CTIMER_CTRL1_TMRA1FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL1_TMRA1FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL1_TMRA1FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL1_TMRA1FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL1_TMRA1FN_Enum; - -/* ============================================= CTIMER CTRL1 TMRA1CLK [1..5] ============================================== */ -typedef enum { /*!< CTIMER_CTRL1_TMRA1CLK */ - CTIMER_CTRL1_TMRA1CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ - CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL1_TMRA1CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL1_TMRA1CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL1_TMRA1CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL1_TMRA1CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL1_TMRA1CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL1_TMRA1CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL1_TMRA1CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL1_TMRA1CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL1_TMRA1CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL1_TMRA1CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL1_TMRA1CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL1_TMRA1CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL1_TMRA1CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL1_TMRA1CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL1_TMRA1CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL1_TMRA1CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL1_TMRA1CLK_CTMRB1 = 20, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ - CTIMER_CTRL1_TMRA1CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ - CTIMER_CTRL1_TMRA1CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ - CTIMER_CTRL1_TMRA1CLK_CTMRA2 = 23, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ - CTIMER_CTRL1_TMRA1CLK_CTMRB2 = 24, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ - CTIMER_CTRL1_TMRA1CLK_CTMRB3 = 25, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ - CTIMER_CTRL1_TMRA1CLK_CTMRB4 = 26, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ - CTIMER_CTRL1_TMRA1CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ - CTIMER_CTRL1_TMRA1CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ - CTIMER_CTRL1_TMRA1CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL1_TMRA1CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL1_TMRA1CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL1_TMRA1CLK_Enum; - -/* ============================================== CTIMER CTRL1 TMRA1EN [0..0] ============================================== */ -typedef enum { /*!< CTIMER_CTRL1_TMRA1EN */ - CTIMER_CTRL1_TMRA1EN_DIS = 0, /*!< DIS : Counter/Timer A1 Disable. */ - CTIMER_CTRL1_TMRA1EN_EN = 1, /*!< EN : Counter/Timer A1 Enable. */ -} CTIMER_CTRL1_TMRA1EN_Enum; - -/* ======================================================= CMPRAUXA1 ======================================================= */ -/* ======================================================= CMPRAUXB1 ======================================================= */ -/* ========================================================= AUX1 ========================================================== */ -/* ============================================ CTIMER AUX1 TMRB1EN23 [30..30] ============================================= */ -typedef enum { /*!< CTIMER_AUX1_TMRB1EN23 */ - CTIMER_AUX1_TMRB1EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX1_TMRB1EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX1_TMRB1EN23_Enum; - -/* ============================================ CTIMER AUX1 TMRB1POL23 [29..29] ============================================ */ -typedef enum { /*!< CTIMER_AUX1_TMRB1POL23 */ - CTIMER_AUX1_TMRB1POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ - CTIMER_AUX1_TMRB1POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX1_TMRB1POL23_Enum; - -/* ============================================ CTIMER AUX1 TMRB1TINV [28..28] ============================================= */ -typedef enum { /*!< CTIMER_AUX1_TMRB1TINV */ - CTIMER_AUX1_TMRB1TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX1_TMRB1TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX1_TMRB1TINV_Enum; - -/* =========================================== CTIMER AUX1 TMRB1NOSYNC [27..27] ============================================ */ -typedef enum { /*!< CTIMER_AUX1_TMRB1NOSYNC */ - CTIMER_AUX1_TMRB1NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX1_TMRB1NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX1_TMRB1NOSYNC_Enum; - -/* ============================================ CTIMER AUX1 TMRB1TRIG [23..26] ============================================= */ -typedef enum { /*!< CTIMER_AUX1_TMRB1TRIG */ - CTIMER_AUX1_TMRB1TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX1_TMRB1TRIG_A1OUT = 1, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ - CTIMER_AUX1_TMRB1TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ - CTIMER_AUX1_TMRB1TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ - CTIMER_AUX1_TMRB1TRIG_A6OUT = 4, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */ - CTIMER_AUX1_TMRB1TRIG_B6OUT = 5, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */ - CTIMER_AUX1_TMRB1TRIG_A0OUT = 6, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */ - CTIMER_AUX1_TMRB1TRIG_B0OUT = 7, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */ - CTIMER_AUX1_TMRB1TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ - CTIMER_AUX1_TMRB1TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ - CTIMER_AUX1_TMRB1TRIG_A4OUT2 = 10, /*!< A4OUT2 : Trigger source is CTIMERA4 OUT2. */ - CTIMER_AUX1_TMRB1TRIG_B4OUT2 = 11, /*!< B4OUT2 : Trigger source is CTIMERB4 OUT2. */ - CTIMER_AUX1_TMRB1TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ - CTIMER_AUX1_TMRB1TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ - CTIMER_AUX1_TMRB1TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */ - CTIMER_AUX1_TMRB1TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ -} CTIMER_AUX1_TMRB1TRIG_Enum; - -/* ============================================ CTIMER AUX1 TMRA1EN23 [14..14] ============================================= */ -typedef enum { /*!< CTIMER_AUX1_TMRA1EN23 */ - CTIMER_AUX1_TMRA1EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX1_TMRA1EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX1_TMRA1EN23_Enum; - -/* ============================================ CTIMER AUX1 TMRA1POL23 [13..13] ============================================ */ -typedef enum { /*!< CTIMER_AUX1_TMRA1POL23 */ - CTIMER_AUX1_TMRA1POL23_NORMAL = 0, /*!< NORMAL : Upper output normal polarity */ - CTIMER_AUX1_TMRA1POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX1_TMRA1POL23_Enum; - -/* ============================================ CTIMER AUX1 TMRA1TINV [12..12] ============================================= */ -typedef enum { /*!< CTIMER_AUX1_TMRA1TINV */ - CTIMER_AUX1_TMRA1TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX1_TMRA1TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX1_TMRA1TINV_Enum; - -/* =========================================== CTIMER AUX1 TMRA1NOSYNC [11..11] ============================================ */ -typedef enum { /*!< CTIMER_AUX1_TMRA1NOSYNC */ - CTIMER_AUX1_TMRA1NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX1_TMRA1NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX1_TMRA1NOSYNC_Enum; - -/* ============================================= CTIMER AUX1 TMRA1TRIG [7..10] ============================================= */ -typedef enum { /*!< CTIMER_AUX1_TMRA1TRIG */ - CTIMER_AUX1_TMRA1TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX1_TMRA1TRIG_B1OUT = 1, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ - CTIMER_AUX1_TMRA1TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ - CTIMER_AUX1_TMRA1TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ - CTIMER_AUX1_TMRA1TRIG_A0OUT = 4, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */ - CTIMER_AUX1_TMRA1TRIG_B0OUT = 5, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */ - CTIMER_AUX1_TMRA1TRIG_A5OUT = 6, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */ - CTIMER_AUX1_TMRA1TRIG_B5OUT = 7, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */ - CTIMER_AUX1_TMRA1TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ - CTIMER_AUX1_TMRA1TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ - CTIMER_AUX1_TMRA1TRIG_A4OUT2 = 10, /*!< A4OUT2 : Trigger source is CTIMERA4 OUT2. */ - CTIMER_AUX1_TMRA1TRIG_B4OUT2 = 11, /*!< B4OUT2 : Trigger source is CTIMERB4 OUT2. */ - CTIMER_AUX1_TMRA1TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ - CTIMER_AUX1_TMRA1TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ - CTIMER_AUX1_TMRA1TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */ - CTIMER_AUX1_TMRA1TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ -} CTIMER_AUX1_TMRA1TRIG_Enum; - -/* ========================================================= TMR2 ========================================================== */ -/* ======================================================== CMPRA2 ========================================================= */ -/* ======================================================== CMPRB2 ========================================================= */ -/* ========================================================= CTRL2 ========================================================= */ -/* ============================================= CTIMER CTRL2 CTLINK2 [31..31] ============================================= */ -typedef enum { /*!< CTIMER_CTRL2_CTLINK2 */ - CTIMER_CTRL2_CTLINK2_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A2/B2 timers as two independent 16-bit - timers (default). */ - CTIMER_CTRL2_CTLINK2_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A2/B2 timers into a single 32-bit timer. */ -} CTIMER_CTRL2_CTLINK2_Enum; - -/* ============================================ CTIMER CTRL2 TMRB2POL [28..28] ============================================= */ -typedef enum { /*!< CTIMER_CTRL2_TMRB2POL */ - CTIMER_CTRL2_TMRB2POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB2 pin is the same as the - timer output. */ - CTIMER_CTRL2_TMRB2POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB2 pin is the inverse of - the timer output. */ -} CTIMER_CTRL2_TMRB2POL_Enum; - -/* ============================================ CTIMER CTRL2 TMRB2CLR [27..27] ============================================= */ -typedef enum { /*!< CTIMER_CTRL2_TMRB2CLR */ - CTIMER_CTRL2_TMRB2CLR_RUN = 0, /*!< RUN : Allow counter/timer B2 to run */ - CTIMER_CTRL2_TMRB2CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B2 at 0x0000. */ -} CTIMER_CTRL2_TMRB2CLR_Enum; - -/* ============================================ CTIMER CTRL2 TMRB2IE1 [26..26] ============================================= */ -typedef enum { /*!< CTIMER_CTRL2_TMRB2IE1 */ - CTIMER_CTRL2_TMRB2IE1_DIS = 0, /*!< DIS : Disable counter/timer B2 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL2_TMRB2IE1_EN = 1, /*!< EN : Enable counter/timer B2 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL2_TMRB2IE1_Enum; - -/* ============================================ CTIMER CTRL2 TMRB2IE0 [25..25] ============================================= */ -typedef enum { /*!< CTIMER_CTRL2_TMRB2IE0 */ - CTIMER_CTRL2_TMRB2IE0_DIS = 0, /*!< DIS : Disable counter/timer B2 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL2_TMRB2IE0_EN = 1, /*!< EN : Enable counter/timer B2 to generate an interrupt based - on COMPR0 */ -} CTIMER_CTRL2_TMRB2IE0_Enum; - -/* ============================================= CTIMER CTRL2 TMRB2FN [22..24] ============================================= */ -typedef enum { /*!< CTIMER_CTRL2_TMRB2FN */ - CTIMER_CTRL2_TMRB2FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0B2, stop. */ - CTIMER_CTRL2_TMRB2FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0B2, restart. */ - CTIMER_CTRL2_TMRB2FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B2, assert, - count to CMPR1B2, deassert, stop. */ - CTIMER_CTRL2_TMRB2FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B2, assert, count - to CMPR1B2, deassert, restart. */ - CTIMER_CTRL2_TMRB2FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL2_TMRB2FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL2_TMRB2FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL2_TMRB2FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL2_TMRB2FN_Enum; - -/* ============================================ CTIMER CTRL2 TMRB2CLK [17..21] ============================================= */ -typedef enum { /*!< CTIMER_CTRL2_TMRB2CLK */ - CTIMER_CTRL2_TMRB2CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ - CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL2_TMRB2CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL2_TMRB2CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL2_TMRB2CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL2_TMRB2CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL2_TMRB2CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL2_TMRB2CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL2_TMRB2CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL2_TMRB2CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL2_TMRB2CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL2_TMRB2CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL2_TMRB2CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL2_TMRB2CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL2_TMRB2CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL2_TMRB2CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL2_TMRB2CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL2_TMRB2CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL2_TMRB2CLK_CTMRA2 = 20, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ - CTIMER_CTRL2_TMRB2CLK_CTMRB3 = 21, /*!< CTMRB3 : Clock source is CTIMERA3 OUT. */ - CTIMER_CTRL2_TMRB2CLK_CTMRA3 = 22, /*!< CTMRA3 : Clock source is CTIMERB3 OUT. */ - CTIMER_CTRL2_TMRB2CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */ - CTIMER_CTRL2_TMRB2CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ - CTIMER_CTRL2_TMRB2CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ - CTIMER_CTRL2_TMRB2CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ - CTIMER_CTRL2_TMRB2CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ - CTIMER_CTRL2_TMRB2CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ - CTIMER_CTRL2_TMRB2CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL2_TMRB2CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL2_TMRB2CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL2_TMRB2CLK_Enum; - -/* ============================================= CTIMER CTRL2 TMRB2EN [16..16] ============================================= */ -typedef enum { /*!< CTIMER_CTRL2_TMRB2EN */ - CTIMER_CTRL2_TMRB2EN_DIS = 0, /*!< DIS : Counter/Timer B2 Disable. */ - CTIMER_CTRL2_TMRB2EN_EN = 1, /*!< EN : Counter/Timer B2 Enable. */ -} CTIMER_CTRL2_TMRB2EN_Enum; - -/* ============================================ CTIMER CTRL2 TMRA2POL [12..12] ============================================= */ -typedef enum { /*!< CTIMER_CTRL2_TMRA2POL */ - CTIMER_CTRL2_TMRA2POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA2 pin is the same as the - timer output. */ - CTIMER_CTRL2_TMRA2POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA2 pin is the inverse of - the timer output. */ -} CTIMER_CTRL2_TMRA2POL_Enum; - -/* ============================================ CTIMER CTRL2 TMRA2CLR [11..11] ============================================= */ -typedef enum { /*!< CTIMER_CTRL2_TMRA2CLR */ - CTIMER_CTRL2_TMRA2CLR_RUN = 0, /*!< RUN : Allow counter/timer A2 to run */ - CTIMER_CTRL2_TMRA2CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A2 at 0x0000. */ -} CTIMER_CTRL2_TMRA2CLR_Enum; - -/* ============================================ CTIMER CTRL2 TMRA2IE1 [10..10] ============================================= */ -typedef enum { /*!< CTIMER_CTRL2_TMRA2IE1 */ - CTIMER_CTRL2_TMRA2IE1_DIS = 0, /*!< DIS : Disable counter/timer A2 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL2_TMRA2IE1_EN = 1, /*!< EN : Enable counter/timer A2 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL2_TMRA2IE1_Enum; - -/* ============================================= CTIMER CTRL2 TMRA2IE0 [9..9] ============================================== */ -typedef enum { /*!< CTIMER_CTRL2_TMRA2IE0 */ - CTIMER_CTRL2_TMRA2IE0_DIS = 0, /*!< DIS : Disable counter/timer A2 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL2_TMRA2IE0_EN = 1, /*!< EN : Enable counter/timer A2 to generate an interrupt based - on COMPR0. */ -} CTIMER_CTRL2_TMRA2IE0_Enum; - -/* ============================================== CTIMER CTRL2 TMRA2FN [6..8] ============================================== */ -typedef enum { /*!< CTIMER_CTRL2_TMRA2FN */ - CTIMER_CTRL2_TMRA2FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0A2, stop. */ - CTIMER_CTRL2_TMRA2FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0A2, restart. */ - CTIMER_CTRL2_TMRA2FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A2, assert, - count to CMPR1A2, deassert, stop. */ - CTIMER_CTRL2_TMRA2FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A2, assert, count - to CMPR1A2, deassert, restart. */ - CTIMER_CTRL2_TMRA2FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL2_TMRA2FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL2_TMRA2FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL2_TMRA2FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL2_TMRA2FN_Enum; - -/* ============================================= CTIMER CTRL2 TMRA2CLK [1..5] ============================================== */ -typedef enum { /*!< CTIMER_CTRL2_TMRA2CLK */ - CTIMER_CTRL2_TMRA2CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ - CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL2_TMRA2CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL2_TMRA2CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL2_TMRA2CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL2_TMRA2CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL2_TMRA2CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL2_TMRA2CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL2_TMRA2CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL2_TMRA2CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL2_TMRA2CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL2_TMRA2CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL2_TMRA2CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL2_TMRA2CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL2_TMRA2CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL2_TMRA2CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL2_TMRA2CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL2_TMRA2CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL2_TMRA2CLK_CTMRB2 = 20, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ - CTIMER_CTRL2_TMRA2CLK_CTMRB3 = 21, /*!< CTMRB3 : Clock source is CTIMERA3 OUT. */ - CTIMER_CTRL2_TMRA2CLK_CTMRA3 = 22, /*!< CTMRA3 : Clock source is CTIMERB3 OUT. */ - CTIMER_CTRL2_TMRA2CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */ - CTIMER_CTRL2_TMRA2CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ - CTIMER_CTRL2_TMRA2CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ - CTIMER_CTRL2_TMRA2CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ - CTIMER_CTRL2_TMRA2CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ - CTIMER_CTRL2_TMRA2CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ - CTIMER_CTRL2_TMRA2CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL2_TMRA2CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL2_TMRA2CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL2_TMRA2CLK_Enum; - -/* ============================================== CTIMER CTRL2 TMRA2EN [0..0] ============================================== */ -typedef enum { /*!< CTIMER_CTRL2_TMRA2EN */ - CTIMER_CTRL2_TMRA2EN_DIS = 0, /*!< DIS : Counter/Timer A2 Disable. */ - CTIMER_CTRL2_TMRA2EN_EN = 1, /*!< EN : Counter/Timer A2 Enable. */ -} CTIMER_CTRL2_TMRA2EN_Enum; - -/* ======================================================= CMPRAUXA2 ======================================================= */ -/* ======================================================= CMPRAUXB2 ======================================================= */ -/* ========================================================= AUX2 ========================================================== */ -/* ============================================ CTIMER AUX2 TMRB2EN23 [30..30] ============================================= */ -typedef enum { /*!< CTIMER_AUX2_TMRB2EN23 */ - CTIMER_AUX2_TMRB2EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX2_TMRB2EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX2_TMRB2EN23_Enum; - -/* ============================================ CTIMER AUX2 TMRB2POL23 [29..29] ============================================ */ -typedef enum { /*!< CTIMER_AUX2_TMRB2POL23 */ - CTIMER_AUX2_TMRB2POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ - CTIMER_AUX2_TMRB2POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX2_TMRB2POL23_Enum; - -/* ============================================ CTIMER AUX2 TMRB2TINV [28..28] ============================================= */ -typedef enum { /*!< CTIMER_AUX2_TMRB2TINV */ - CTIMER_AUX2_TMRB2TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX2_TMRB2TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX2_TMRB2TINV_Enum; - -/* =========================================== CTIMER AUX2 TMRB2NOSYNC [27..27] ============================================ */ -typedef enum { /*!< CTIMER_AUX2_TMRB2NOSYNC */ - CTIMER_AUX2_TMRB2NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX2_TMRB2NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX2_TMRB2NOSYNC_Enum; - -/* ============================================ CTIMER AUX2 TMRB2TRIG [23..26] ============================================= */ -typedef enum { /*!< CTIMER_AUX2_TMRB2TRIG */ - CTIMER_AUX2_TMRB2TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX2_TMRB2TRIG_A2OUT = 1, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ - CTIMER_AUX2_TMRB2TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ - CTIMER_AUX2_TMRB2TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ - CTIMER_AUX2_TMRB2TRIG_A1OUT = 4, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ - CTIMER_AUX2_TMRB2TRIG_B1OUT = 5, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ - CTIMER_AUX2_TMRB2TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ - CTIMER_AUX2_TMRB2TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ - CTIMER_AUX2_TMRB2TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ - CTIMER_AUX2_TMRB2TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ - CTIMER_AUX2_TMRB2TRIG_A5OUT2 = 10, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */ - CTIMER_AUX2_TMRB2TRIG_B5OUT2 = 11, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */ - CTIMER_AUX2_TMRB2TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ - CTIMER_AUX2_TMRB2TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ - CTIMER_AUX2_TMRB2TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ - CTIMER_AUX2_TMRB2TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ -} CTIMER_AUX2_TMRB2TRIG_Enum; - -/* ============================================ CTIMER AUX2 TMRA2EN23 [14..14] ============================================= */ -typedef enum { /*!< CTIMER_AUX2_TMRA2EN23 */ - CTIMER_AUX2_TMRA2EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX2_TMRA2EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX2_TMRA2EN23_Enum; - -/* ============================================ CTIMER AUX2 TMRA2POL23 [13..13] ============================================ */ -typedef enum { /*!< CTIMER_AUX2_TMRA2POL23 */ - CTIMER_AUX2_TMRA2POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ - CTIMER_AUX2_TMRA2POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX2_TMRA2POL23_Enum; - -/* ============================================ CTIMER AUX2 TMRA2TINV [12..12] ============================================= */ -typedef enum { /*!< CTIMER_AUX2_TMRA2TINV */ - CTIMER_AUX2_TMRA2TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX2_TMRA2TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX2_TMRA2TINV_Enum; - -/* =========================================== CTIMER AUX2 TMRA2NOSYNC [11..11] ============================================ */ -typedef enum { /*!< CTIMER_AUX2_TMRA2NOSYNC */ - CTIMER_AUX2_TMRA2NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX2_TMRA2NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX2_TMRA2NOSYNC_Enum; - -/* ============================================= CTIMER AUX2 TMRA2TRIG [7..10] ============================================= */ -typedef enum { /*!< CTIMER_AUX2_TMRA2TRIG */ - CTIMER_AUX2_TMRA2TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX2_TMRA2TRIG_B2OUT = 1, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ - CTIMER_AUX2_TMRA2TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ - CTIMER_AUX2_TMRA2TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ - CTIMER_AUX2_TMRA2TRIG_A0OUT = 4, /*!< A0OUT : Trigger source is CTIMERA0 OUT. */ - CTIMER_AUX2_TMRA2TRIG_B0OUT = 5, /*!< B0OUT : Trigger source is CTIMERB0 OUT. */ - CTIMER_AUX2_TMRA2TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ - CTIMER_AUX2_TMRA2TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ - CTIMER_AUX2_TMRA2TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ - CTIMER_AUX2_TMRA2TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ - CTIMER_AUX2_TMRA2TRIG_A5OUT2 = 10, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */ - CTIMER_AUX2_TMRA2TRIG_B5OUT2 = 11, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */ - CTIMER_AUX2_TMRA2TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ - CTIMER_AUX2_TMRA2TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ - CTIMER_AUX2_TMRA2TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ - CTIMER_AUX2_TMRA2TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ -} CTIMER_AUX2_TMRA2TRIG_Enum; - -/* ========================================================= TMR3 ========================================================== */ -/* ======================================================== CMPRA3 ========================================================= */ -/* ======================================================== CMPRB3 ========================================================= */ -/* ========================================================= CTRL3 ========================================================= */ -/* ============================================= CTIMER CTRL3 CTLINK3 [31..31] ============================================= */ -typedef enum { /*!< CTIMER_CTRL3_CTLINK3 */ - CTIMER_CTRL3_CTLINK3_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A3/B3 timers as two independent 16-bit - timers (default). */ - CTIMER_CTRL3_CTLINK3_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A3/B3 timers into a single 32-bit timer. */ -} CTIMER_CTRL3_CTLINK3_Enum; - -/* ============================================ CTIMER CTRL3 TMRB3POL [28..28] ============================================= */ -typedef enum { /*!< CTIMER_CTRL3_TMRB3POL */ - CTIMER_CTRL3_TMRB3POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB3 pin is the same as the - timer output. */ - CTIMER_CTRL3_TMRB3POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB3 pin is the inverse of - the timer output. */ -} CTIMER_CTRL3_TMRB3POL_Enum; - -/* ============================================ CTIMER CTRL3 TMRB3CLR [27..27] ============================================= */ -typedef enum { /*!< CTIMER_CTRL3_TMRB3CLR */ - CTIMER_CTRL3_TMRB3CLR_RUN = 0, /*!< RUN : Allow counter/timer B3 to run */ - CTIMER_CTRL3_TMRB3CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B3 at 0x0000. */ -} CTIMER_CTRL3_TMRB3CLR_Enum; - -/* ============================================ CTIMER CTRL3 TMRB3IE1 [26..26] ============================================= */ -typedef enum { /*!< CTIMER_CTRL3_TMRB3IE1 */ - CTIMER_CTRL3_TMRB3IE1_DIS = 0, /*!< DIS : Disable counter/timer B3 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL3_TMRB3IE1_EN = 1, /*!< EN : Enable counter/timer B3 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL3_TMRB3IE1_Enum; - -/* ============================================ CTIMER CTRL3 TMRB3IE0 [25..25] ============================================= */ -typedef enum { /*!< CTIMER_CTRL3_TMRB3IE0 */ - CTIMER_CTRL3_TMRB3IE0_DIS = 0, /*!< DIS : Disable counter/timer B3 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL3_TMRB3IE0_EN = 1, /*!< EN : Enable counter/timer B3 to generate an interrupt based - on COMPR0 */ -} CTIMER_CTRL3_TMRB3IE0_Enum; - -/* ============================================= CTIMER CTRL3 TMRB3FN [22..24] ============================================= */ -typedef enum { /*!< CTIMER_CTRL3_TMRB3FN */ - CTIMER_CTRL3_TMRB3FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0B3, stop. */ - CTIMER_CTRL3_TMRB3FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0B3, restart. */ - CTIMER_CTRL3_TMRB3FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B3, assert, - count to CMPR1B3, deassert, stop. */ - CTIMER_CTRL3_TMRB3FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B3, assert, count - to CMPR1B3, deassert, restart. */ - CTIMER_CTRL3_TMRB3FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL3_TMRB3FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL3_TMRB3FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL3_TMRB3FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL3_TMRB3FN_Enum; - -/* ============================================ CTIMER CTRL3 TMRB3CLK [17..21] ============================================= */ -typedef enum { /*!< CTIMER_CTRL3_TMRB3CLK */ - CTIMER_CTRL3_TMRB3CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ - CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL3_TMRB3CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL3_TMRB3CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL3_TMRB3CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL3_TMRB3CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL3_TMRB3CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL3_TMRB3CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL3_TMRB3CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL3_TMRB3CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL3_TMRB3CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL3_TMRB3CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL3_TMRB3CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL3_TMRB3CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL3_TMRB3CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL3_TMRB3CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL3_TMRB3CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL3_TMRB3CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL3_TMRB3CLK_CTMRA3 = 20, /*!< CTMRA3 : Clock source is CTIMERA3 OUT. */ - CTIMER_CTRL3_TMRB3CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ - CTIMER_CTRL3_TMRB3CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ - CTIMER_CTRL3_TMRB3CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */ - CTIMER_CTRL3_TMRB3CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ - CTIMER_CTRL3_TMRB3CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ - CTIMER_CTRL3_TMRB3CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ - CTIMER_CTRL3_TMRB3CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ - CTIMER_CTRL3_TMRB3CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ - CTIMER_CTRL3_TMRB3CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL3_TMRB3CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL3_TMRB3CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL3_TMRB3CLK_Enum; - -/* ============================================= CTIMER CTRL3 TMRB3EN [16..16] ============================================= */ -typedef enum { /*!< CTIMER_CTRL3_TMRB3EN */ - CTIMER_CTRL3_TMRB3EN_DIS = 0, /*!< DIS : Counter/Timer B3 Disable. */ - CTIMER_CTRL3_TMRB3EN_EN = 1, /*!< EN : Counter/Timer B3 Enable. */ -} CTIMER_CTRL3_TMRB3EN_Enum; - -/* ============================================ CTIMER CTRL3 TMRA3POL [12..12] ============================================= */ -typedef enum { /*!< CTIMER_CTRL3_TMRA3POL */ - CTIMER_CTRL3_TMRA3POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA3 pin is the same as the - timer output. */ - CTIMER_CTRL3_TMRA3POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA3 pin is the inverse of - the timer output. */ -} CTIMER_CTRL3_TMRA3POL_Enum; - -/* ============================================ CTIMER CTRL3 TMRA3CLR [11..11] ============================================= */ -typedef enum { /*!< CTIMER_CTRL3_TMRA3CLR */ - CTIMER_CTRL3_TMRA3CLR_RUN = 0, /*!< RUN : Allow counter/timer A3 to run */ - CTIMER_CTRL3_TMRA3CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A3 at 0x0000. */ -} CTIMER_CTRL3_TMRA3CLR_Enum; - -/* ============================================ CTIMER CTRL3 TMRA3IE1 [10..10] ============================================= */ -typedef enum { /*!< CTIMER_CTRL3_TMRA3IE1 */ - CTIMER_CTRL3_TMRA3IE1_DIS = 0, /*!< DIS : Disable counter/timer A3 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL3_TMRA3IE1_EN = 1, /*!< EN : Enable counter/timer A3 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL3_TMRA3IE1_Enum; - -/* ============================================= CTIMER CTRL3 TMRA3IE0 [9..9] ============================================== */ -typedef enum { /*!< CTIMER_CTRL3_TMRA3IE0 */ - CTIMER_CTRL3_TMRA3IE0_DIS = 0, /*!< DIS : Disable counter/timer A3 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL3_TMRA3IE0_EN = 1, /*!< EN : Enable counter/timer A3 to generate an interrupt based - on COMPR0. */ -} CTIMER_CTRL3_TMRA3IE0_Enum; - -/* ============================================== CTIMER CTRL3 TMRA3FN [6..8] ============================================== */ -typedef enum { /*!< CTIMER_CTRL3_TMRA3FN */ - CTIMER_CTRL3_TMRA3FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0A3, stop. */ - CTIMER_CTRL3_TMRA3FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0A3, restart. */ - CTIMER_CTRL3_TMRA3FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A3, assert, - count to CMPR1A3, deassert, stop. */ - CTIMER_CTRL3_TMRA3FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A3, assert, count - to CMPR1A3, deassert, restart. */ - CTIMER_CTRL3_TMRA3FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL3_TMRA3FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL3_TMRA3FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL3_TMRA3FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL3_TMRA3FN_Enum; - -/* ============================================= CTIMER CTRL3 TMRA3CLK [1..5] ============================================== */ -typedef enum { /*!< CTIMER_CTRL3_TMRA3CLK */ - CTIMER_CTRL3_TMRA3CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ - CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL3_TMRA3CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL3_TMRA3CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL3_TMRA3CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL3_TMRA3CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL3_TMRA3CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL3_TMRA3CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL3_TMRA3CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL3_TMRA3CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL3_TMRA3CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL3_TMRA3CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL3_TMRA3CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL3_TMRA3CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL3_TMRA3CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL3_TMRA3CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL3_TMRA3CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL3_TMRA3CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL3_TMRA3CLK_CTMRB3 = 20, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ - CTIMER_CTRL3_TMRA3CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ - CTIMER_CTRL3_TMRA3CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ - CTIMER_CTRL3_TMRA3CLK_CTMRA4 = 23, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */ - CTIMER_CTRL3_TMRA3CLK_CTMRB4 = 24, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ - CTIMER_CTRL3_TMRA3CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ - CTIMER_CTRL3_TMRA3CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ - CTIMER_CTRL3_TMRA3CLK_CTMRB5 = 27, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ - CTIMER_CTRL3_TMRA3CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ - CTIMER_CTRL3_TMRA3CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL3_TMRA3CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL3_TMRA3CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL3_TMRA3CLK_Enum; - -/* ============================================== CTIMER CTRL3 TMRA3EN [0..0] ============================================== */ -typedef enum { /*!< CTIMER_CTRL3_TMRA3EN */ - CTIMER_CTRL3_TMRA3EN_DIS = 0, /*!< DIS : Counter/Timer A3 Disable. */ - CTIMER_CTRL3_TMRA3EN_EN = 1, /*!< EN : Counter/Timer A3 Enable. */ -} CTIMER_CTRL3_TMRA3EN_Enum; - -/* ======================================================= CMPRAUXA3 ======================================================= */ -/* ======================================================= CMPRAUXB3 ======================================================= */ -/* ========================================================= AUX3 ========================================================== */ -/* ============================================ CTIMER AUX3 TMRB3EN23 [30..30] ============================================= */ -typedef enum { /*!< CTIMER_AUX3_TMRB3EN23 */ - CTIMER_AUX3_TMRB3EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX3_TMRB3EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX3_TMRB3EN23_Enum; - -/* ============================================ CTIMER AUX3 TMRB3POL23 [29..29] ============================================ */ -typedef enum { /*!< CTIMER_AUX3_TMRB3POL23 */ - CTIMER_AUX3_TMRB3POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ - CTIMER_AUX3_TMRB3POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX3_TMRB3POL23_Enum; - -/* ============================================ CTIMER AUX3 TMRB3TINV [28..28] ============================================= */ -typedef enum { /*!< CTIMER_AUX3_TMRB3TINV */ - CTIMER_AUX3_TMRB3TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX3_TMRB3TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX3_TMRB3TINV_Enum; - -/* =========================================== CTIMER AUX3 TMRB3NOSYNC [27..27] ============================================ */ -typedef enum { /*!< CTIMER_AUX3_TMRB3NOSYNC */ - CTIMER_AUX3_TMRB3NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX3_TMRB3NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX3_TMRB3NOSYNC_Enum; - -/* ============================================ CTIMER AUX3 TMRB3TRIG [23..26] ============================================= */ -typedef enum { /*!< CTIMER_AUX3_TMRB3TRIG */ - CTIMER_AUX3_TMRB3TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX3_TMRB3TRIG_A3OUT = 1, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ - CTIMER_AUX3_TMRB3TRIG_B2OUT = 2, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ - CTIMER_AUX3_TMRB3TRIG_A2OUT = 3, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ - CTIMER_AUX3_TMRB3TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ - CTIMER_AUX3_TMRB3TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ - CTIMER_AUX3_TMRB3TRIG_A6OUT = 6, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */ - CTIMER_AUX3_TMRB3TRIG_B6OUT = 7, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */ - CTIMER_AUX3_TMRB3TRIG_B5OUT2 = 8, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */ - CTIMER_AUX3_TMRB3TRIG_A5OUT2 = 9, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */ - CTIMER_AUX3_TMRB3TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */ - CTIMER_AUX3_TMRB3TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */ - CTIMER_AUX3_TMRB3TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ - CTIMER_AUX3_TMRB3TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ - CTIMER_AUX3_TMRB3TRIG_B2OUT2DUAL = 14, /*!< B2OUT2DUAL : Trigger source is CTIMERB2 OUT2, dual edge. */ - CTIMER_AUX3_TMRB3TRIG_A2OUT2DUAL = 15, /*!< A2OUT2DUAL : Trigger source is CTIMERA2 OUT2, dual edge. */ -} CTIMER_AUX3_TMRB3TRIG_Enum; - -/* ============================================ CTIMER AUX3 TMRA3EN23 [14..14] ============================================= */ -typedef enum { /*!< CTIMER_AUX3_TMRA3EN23 */ - CTIMER_AUX3_TMRA3EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX3_TMRA3EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX3_TMRA3EN23_Enum; - -/* ============================================ CTIMER AUX3 TMRA3POL23 [13..13] ============================================ */ -typedef enum { /*!< CTIMER_AUX3_TMRA3POL23 */ - CTIMER_AUX3_TMRA3POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ - CTIMER_AUX3_TMRA3POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX3_TMRA3POL23_Enum; - -/* ============================================ CTIMER AUX3 TMRA3TINV [12..12] ============================================= */ -typedef enum { /*!< CTIMER_AUX3_TMRA3TINV */ - CTIMER_AUX3_TMRA3TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX3_TMRA3TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX3_TMRA3TINV_Enum; - -/* =========================================== CTIMER AUX3 TMRA3NOSYNC [11..11] ============================================ */ -typedef enum { /*!< CTIMER_AUX3_TMRA3NOSYNC */ - CTIMER_AUX3_TMRA3NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX3_TMRA3NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX3_TMRA3NOSYNC_Enum; - -/* ============================================= CTIMER AUX3 TMRA3TRIG [7..10] ============================================= */ -typedef enum { /*!< CTIMER_AUX3_TMRA3TRIG */ - CTIMER_AUX3_TMRA3TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX3_TMRA3TRIG_B3OUT = 1, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ - CTIMER_AUX3_TMRA3TRIG_B2OUT = 2, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ - CTIMER_AUX3_TMRA3TRIG_A2OUT = 3, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ - CTIMER_AUX3_TMRA3TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ - CTIMER_AUX3_TMRA3TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ - CTIMER_AUX3_TMRA3TRIG_A7OUT = 6, /*!< A7OUT : Trigger source is CTIMERA7 OUT. */ - CTIMER_AUX3_TMRA3TRIG_B7OUT = 7, /*!< B7OUT : Trigger source is CTIMERB7 OUT. */ - CTIMER_AUX3_TMRA3TRIG_B5OUT2 = 8, /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2. */ - CTIMER_AUX3_TMRA3TRIG_A5OUT2 = 9, /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2. */ - CTIMER_AUX3_TMRA3TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */ - CTIMER_AUX3_TMRA3TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */ - CTIMER_AUX3_TMRA3TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ - CTIMER_AUX3_TMRA3TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ - CTIMER_AUX3_TMRA3TRIG_B2OUT2DUAL = 14, /*!< B2OUT2DUAL : Trigger source is CTIMERB2 OUT2, dual edge. */ - CTIMER_AUX3_TMRA3TRIG_A2OUT2DUAL = 15, /*!< A2OUT2DUAL : Trigger source is CTIMERA2 OUT2, dual edge. */ -} CTIMER_AUX3_TMRA3TRIG_Enum; - -/* ========================================================= TMR4 ========================================================== */ -/* ======================================================== CMPRA4 ========================================================= */ -/* ======================================================== CMPRB4 ========================================================= */ -/* ========================================================= CTRL4 ========================================================= */ -/* ============================================= CTIMER CTRL4 CTLINK4 [31..31] ============================================= */ -typedef enum { /*!< CTIMER_CTRL4_CTLINK4 */ - CTIMER_CTRL4_CTLINK4_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A4/B4 timers as two independent 16-bit - timers (default). */ - CTIMER_CTRL4_CTLINK4_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A4/B4 timers into a single 32-bit timer. */ -} CTIMER_CTRL4_CTLINK4_Enum; - -/* ============================================ CTIMER CTRL4 TMRB4POL [28..28] ============================================= */ -typedef enum { /*!< CTIMER_CTRL4_TMRB4POL */ - CTIMER_CTRL4_TMRB4POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB4 pin is the same as the - timer output. */ - CTIMER_CTRL4_TMRB4POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB4 pin is the inverse of - the timer output. */ -} CTIMER_CTRL4_TMRB4POL_Enum; - -/* ============================================ CTIMER CTRL4 TMRB4CLR [27..27] ============================================= */ -typedef enum { /*!< CTIMER_CTRL4_TMRB4CLR */ - CTIMER_CTRL4_TMRB4CLR_RUN = 0, /*!< RUN : Allow counter/timer B4 to run */ - CTIMER_CTRL4_TMRB4CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B4 at 0x0000. */ -} CTIMER_CTRL4_TMRB4CLR_Enum; - -/* ============================================ CTIMER CTRL4 TMRB4IE1 [26..26] ============================================= */ -typedef enum { /*!< CTIMER_CTRL4_TMRB4IE1 */ - CTIMER_CTRL4_TMRB4IE1_DIS = 0, /*!< DIS : Disable counter/timer B4 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL4_TMRB4IE1_EN = 1, /*!< EN : Enable counter/timer B4 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL4_TMRB4IE1_Enum; - -/* ============================================ CTIMER CTRL4 TMRB4IE0 [25..25] ============================================= */ -typedef enum { /*!< CTIMER_CTRL4_TMRB4IE0 */ - CTIMER_CTRL4_TMRB4IE0_DIS = 0, /*!< DIS : Disable counter/timer B4 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL4_TMRB4IE0_EN = 1, /*!< EN : Enable counter/timer B4 to generate an interrupt based - on COMPR0 */ -} CTIMER_CTRL4_TMRB4IE0_Enum; - -/* ============================================= CTIMER CTRL4 TMRB4FN [22..24] ============================================= */ -typedef enum { /*!< CTIMER_CTRL4_TMRB4FN */ - CTIMER_CTRL4_TMRB4FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0B4, stop. */ - CTIMER_CTRL4_TMRB4FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0B4, restart. */ - CTIMER_CTRL4_TMRB4FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B4, assert, - count to CMPR1B4, deassert, stop. */ - CTIMER_CTRL4_TMRB4FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B4, assert, count - to CMPR1B4, deassert, restart. */ - CTIMER_CTRL4_TMRB4FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL4_TMRB4FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL4_TMRB4FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL4_TMRB4FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL4_TMRB4FN_Enum; - -/* ============================================ CTIMER CTRL4 TMRB4CLK [17..21] ============================================= */ -typedef enum { /*!< CTIMER_CTRL4_TMRB4CLK */ - CTIMER_CTRL4_TMRB4CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ - CTIMER_CTRL4_TMRB4CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL4_TMRB4CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL4_TMRB4CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL4_TMRB4CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL4_TMRB4CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL4_TMRB4CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL4_TMRB4CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL4_TMRB4CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL4_TMRB4CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL4_TMRB4CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL4_TMRB4CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL4_TMRB4CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL4_TMRB4CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL4_TMRB4CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL4_TMRB4CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL4_TMRB4CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL4_TMRB4CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL4_TMRB4CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL4_TMRB4CLK_CTMRA4 = 20, /*!< CTMRA4 : Clock source is CTIMERA4 OUT. */ - CTIMER_CTRL4_TMRB4CLK_CTMRA1 = 21, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */ - CTIMER_CTRL4_TMRB4CLK_CTMRB1 = 22, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ - CTIMER_CTRL4_TMRB4CLK_CTMRA5 = 23, /*!< CTMRA5 : Clock source is CTIMERA5 OUT. */ - CTIMER_CTRL4_TMRB4CLK_CTMRB5 = 24, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ - CTIMER_CTRL4_TMRB4CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ - CTIMER_CTRL4_TMRB4CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ - CTIMER_CTRL4_TMRB4CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ - CTIMER_CTRL4_TMRB4CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ - CTIMER_CTRL4_TMRB4CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL4_TMRB4CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL4_TMRB4CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL4_TMRB4CLK_Enum; - -/* ============================================= CTIMER CTRL4 TMRB4EN [16..16] ============================================= */ -typedef enum { /*!< CTIMER_CTRL4_TMRB4EN */ - CTIMER_CTRL4_TMRB4EN_DIS = 0, /*!< DIS : Counter/Timer B4 Disable. */ - CTIMER_CTRL4_TMRB4EN_EN = 1, /*!< EN : Counter/Timer B4 Enable. */ -} CTIMER_CTRL4_TMRB4EN_Enum; - -/* ============================================ CTIMER CTRL4 TMRA4POL [12..12] ============================================= */ -typedef enum { /*!< CTIMER_CTRL4_TMRA4POL */ - CTIMER_CTRL4_TMRA4POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA4 pin is the same as the - timer output. */ - CTIMER_CTRL4_TMRA4POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA4 pin is the inverse of - the timer output. */ -} CTIMER_CTRL4_TMRA4POL_Enum; - -/* ============================================ CTIMER CTRL4 TMRA4CLR [11..11] ============================================= */ -typedef enum { /*!< CTIMER_CTRL4_TMRA4CLR */ - CTIMER_CTRL4_TMRA4CLR_RUN = 0, /*!< RUN : Allow counter/timer A4 to run */ - CTIMER_CTRL4_TMRA4CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A4 at 0x0000. */ -} CTIMER_CTRL4_TMRA4CLR_Enum; - -/* ============================================ CTIMER CTRL4 TMRA4IE1 [10..10] ============================================= */ -typedef enum { /*!< CTIMER_CTRL4_TMRA4IE1 */ - CTIMER_CTRL4_TMRA4IE1_DIS = 0, /*!< DIS : Disable counter/timer A4 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL4_TMRA4IE1_EN = 1, /*!< EN : Enable counter/timer A4 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL4_TMRA4IE1_Enum; - -/* ============================================= CTIMER CTRL4 TMRA4IE0 [9..9] ============================================== */ -typedef enum { /*!< CTIMER_CTRL4_TMRA4IE0 */ - CTIMER_CTRL4_TMRA4IE0_DIS = 0, /*!< DIS : Disable counter/timer A4 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL4_TMRA4IE0_EN = 1, /*!< EN : Enable counter/timer A4 to generate an interrupt based - on COMPR0. */ -} CTIMER_CTRL4_TMRA4IE0_Enum; - -/* ============================================== CTIMER CTRL4 TMRA4FN [6..8] ============================================== */ -typedef enum { /*!< CTIMER_CTRL4_TMRA4FN */ - CTIMER_CTRL4_TMRA4FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0A4, stop. */ - CTIMER_CTRL4_TMRA4FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0A4, restart. */ - CTIMER_CTRL4_TMRA4FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A4, assert, - count to CMPR1A4, deassert, stop. */ - CTIMER_CTRL4_TMRA4FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A4, assert, count - to CMPR1A4, deassert, restart. */ - CTIMER_CTRL4_TMRA4FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL4_TMRA4FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL4_TMRA4FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL4_TMRA4FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL4_TMRA4FN_Enum; - -/* ============================================= CTIMER CTRL4 TMRA4CLK [1..5] ============================================== */ -typedef enum { /*!< CTIMER_CTRL4_TMRA4CLK */ - CTIMER_CTRL4_TMRA4CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ - CTIMER_CTRL4_TMRA4CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL4_TMRA4CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL4_TMRA4CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL4_TMRA4CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL4_TMRA4CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL4_TMRA4CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL4_TMRA4CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL4_TMRA4CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL4_TMRA4CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL4_TMRA4CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL4_TMRA4CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL4_TMRA4CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL4_TMRA4CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL4_TMRA4CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL4_TMRA4CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4. (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL4_TMRA4CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL4_TMRA4CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL4_TMRA4CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL4_TMRA4CLK_CTMRB4 = 20, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ - CTIMER_CTRL4_TMRA4CLK_CTMRA1 = 21, /*!< CTMRA1 : Clock source is CTIMERA1 OUT. */ - CTIMER_CTRL4_TMRA4CLK_CTMRB1 = 22, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ - CTIMER_CTRL4_TMRA4CLK_CTMRA5 = 23, /*!< CTMRA5 : Clock source is CTIMERA5 OUT. */ - CTIMER_CTRL4_TMRA4CLK_CTMRB5 = 24, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ - CTIMER_CTRL4_TMRA4CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ - CTIMER_CTRL4_TMRA4CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ - CTIMER_CTRL4_TMRA4CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ - CTIMER_CTRL4_TMRA4CLK_CTMRB6 = 28, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ - CTIMER_CTRL4_TMRA4CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL4_TMRA4CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL4_TMRA4CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL4_TMRA4CLK_Enum; - -/* ============================================== CTIMER CTRL4 TMRA4EN [0..0] ============================================== */ -typedef enum { /*!< CTIMER_CTRL4_TMRA4EN */ - CTIMER_CTRL4_TMRA4EN_DIS = 0, /*!< DIS : Counter/Timer A4 Disable. */ - CTIMER_CTRL4_TMRA4EN_EN = 1, /*!< EN : Counter/Timer A4 Enable. */ -} CTIMER_CTRL4_TMRA4EN_Enum; - -/* ======================================================= CMPRAUXA4 ======================================================= */ -/* ======================================================= CMPRAUXB4 ======================================================= */ -/* ========================================================= AUX4 ========================================================== */ -/* ============================================ CTIMER AUX4 TMRB4EN23 [30..30] ============================================= */ -typedef enum { /*!< CTIMER_AUX4_TMRB4EN23 */ - CTIMER_AUX4_TMRB4EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX4_TMRB4EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX4_TMRB4EN23_Enum; - -/* ============================================ CTIMER AUX4 TMRB4POL23 [29..29] ============================================ */ -typedef enum { /*!< CTIMER_AUX4_TMRB4POL23 */ - CTIMER_AUX4_TMRB4POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ - CTIMER_AUX4_TMRB4POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX4_TMRB4POL23_Enum; - -/* ============================================ CTIMER AUX4 TMRB4TINV [28..28] ============================================= */ -typedef enum { /*!< CTIMER_AUX4_TMRB4TINV */ - CTIMER_AUX4_TMRB4TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX4_TMRB4TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX4_TMRB4TINV_Enum; - -/* =========================================== CTIMER AUX4 TMRB4NOSYNC [27..27] ============================================ */ -typedef enum { /*!< CTIMER_AUX4_TMRB4NOSYNC */ - CTIMER_AUX4_TMRB4NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX4_TMRB4NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX4_TMRB4NOSYNC_Enum; - -/* ============================================ CTIMER AUX4 TMRB4TRIG [23..26] ============================================= */ -typedef enum { /*!< CTIMER_AUX4_TMRB4TRIG */ - CTIMER_AUX4_TMRB4TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX4_TMRB4TRIG_A4OUT = 1, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ - CTIMER_AUX4_TMRB4TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ - CTIMER_AUX4_TMRB4TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ - CTIMER_AUX4_TMRB4TRIG_A7OUT = 4, /*!< A7OUT : Trigger source is CTIMERA7 OUT. */ - CTIMER_AUX4_TMRB4TRIG_B7OUT = 5, /*!< B7OUT : Trigger source is CTIMERB7 OUT. */ - CTIMER_AUX4_TMRB4TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ - CTIMER_AUX4_TMRB4TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ - CTIMER_AUX4_TMRB4TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ - CTIMER_AUX4_TMRB4TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ - CTIMER_AUX4_TMRB4TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */ - CTIMER_AUX4_TMRB4TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */ - CTIMER_AUX4_TMRB4TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ - CTIMER_AUX4_TMRB4TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ - CTIMER_AUX4_TMRB4TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */ - CTIMER_AUX4_TMRB4TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ -} CTIMER_AUX4_TMRB4TRIG_Enum; - -/* ============================================ CTIMER AUX4 TMRA4EN23 [14..14] ============================================= */ -typedef enum { /*!< CTIMER_AUX4_TMRA4EN23 */ - CTIMER_AUX4_TMRA4EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX4_TMRA4EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX4_TMRA4EN23_Enum; - -/* ============================================ CTIMER AUX4 TMRA4POL23 [13..13] ============================================ */ -typedef enum { /*!< CTIMER_AUX4_TMRA4POL23 */ - CTIMER_AUX4_TMRA4POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ - CTIMER_AUX4_TMRA4POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX4_TMRA4POL23_Enum; - -/* ============================================ CTIMER AUX4 TMRA4TINV [12..12] ============================================= */ -typedef enum { /*!< CTIMER_AUX4_TMRA4TINV */ - CTIMER_AUX4_TMRA4TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX4_TMRA4TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX4_TMRA4TINV_Enum; - -/* =========================================== CTIMER AUX4 TMRA4NOSYNC [11..11] ============================================ */ -typedef enum { /*!< CTIMER_AUX4_TMRA4NOSYNC */ - CTIMER_AUX4_TMRA4NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX4_TMRA4NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX4_TMRA4NOSYNC_Enum; - -/* ============================================= CTIMER AUX4 TMRA4TRIG [7..10] ============================================= */ -typedef enum { /*!< CTIMER_AUX4_TMRA4TRIG */ - CTIMER_AUX4_TMRA4TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX4_TMRA4TRIG_STIMER = 1, /*!< STIMER : Trigger source is STimer Interrupt. Only Active When - CTLINK==1 and TMRB4TRIG!=0. TMRB4TRIG selects an STIMER - interrupt */ - CTIMER_AUX4_TMRA4TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ - CTIMER_AUX4_TMRA4TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ - CTIMER_AUX4_TMRA4TRIG_A6OUT = 4, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */ - CTIMER_AUX4_TMRA4TRIG_B6OUT = 5, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */ - CTIMER_AUX4_TMRA4TRIG_A2OUT = 6, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ - CTIMER_AUX4_TMRA4TRIG_B2OUT = 7, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ - CTIMER_AUX4_TMRA4TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ - CTIMER_AUX4_TMRA4TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ - CTIMER_AUX4_TMRA4TRIG_A1OUT2 = 10, /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2. */ - CTIMER_AUX4_TMRA4TRIG_B1OUT2 = 11, /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2. */ - CTIMER_AUX4_TMRA4TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ - CTIMER_AUX4_TMRA4TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ - CTIMER_AUX4_TMRA4TRIG_B5OUT2DUAL = 14, /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge. */ - CTIMER_AUX4_TMRA4TRIG_A5OUT2DUAL = 15, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ -} CTIMER_AUX4_TMRA4TRIG_Enum; - -/* ========================================================= TMR5 ========================================================== */ -/* ======================================================== CMPRA5 ========================================================= */ -/* ======================================================== CMPRB5 ========================================================= */ -/* ========================================================= CTRL5 ========================================================= */ -/* ============================================= CTIMER CTRL5 CTLINK5 [31..31] ============================================= */ -typedef enum { /*!< CTIMER_CTRL5_CTLINK5 */ - CTIMER_CTRL5_CTLINK5_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A5/B5 timers as two independent 16-bit - timers (default). */ - CTIMER_CTRL5_CTLINK5_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A5/B5 timers into a single 32-bit timer. */ -} CTIMER_CTRL5_CTLINK5_Enum; - -/* ============================================ CTIMER CTRL5 TMRB5POL [28..28] ============================================= */ -typedef enum { /*!< CTIMER_CTRL5_TMRB5POL */ - CTIMER_CTRL5_TMRB5POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB5 pin is the same as the - timer output. */ - CTIMER_CTRL5_TMRB5POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB5 pin is the inverse of - the timer output. */ -} CTIMER_CTRL5_TMRB5POL_Enum; - -/* ============================================ CTIMER CTRL5 TMRB5CLR [27..27] ============================================= */ -typedef enum { /*!< CTIMER_CTRL5_TMRB5CLR */ - CTIMER_CTRL5_TMRB5CLR_RUN = 0, /*!< RUN : Allow counter/timer B5 to run */ - CTIMER_CTRL5_TMRB5CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B5 at 0x0000. */ -} CTIMER_CTRL5_TMRB5CLR_Enum; - -/* ============================================ CTIMER CTRL5 TMRB5IE1 [26..26] ============================================= */ -typedef enum { /*!< CTIMER_CTRL5_TMRB5IE1 */ - CTIMER_CTRL5_TMRB5IE1_DIS = 0, /*!< DIS : Disable counter/timer B5 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL5_TMRB5IE1_EN = 1, /*!< EN : Enable counter/timer B5 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL5_TMRB5IE1_Enum; - -/* ============================================ CTIMER CTRL5 TMRB5IE0 [25..25] ============================================= */ -typedef enum { /*!< CTIMER_CTRL5_TMRB5IE0 */ - CTIMER_CTRL5_TMRB5IE0_DIS = 0, /*!< DIS : Disable counter/timer B5 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL5_TMRB5IE0_EN = 1, /*!< EN : Enable counter/timer B5 to generate an interrupt based - on COMPR0 */ -} CTIMER_CTRL5_TMRB5IE0_Enum; - -/* ============================================= CTIMER CTRL5 TMRB5FN [22..24] ============================================= */ -typedef enum { /*!< CTIMER_CTRL5_TMRB5FN */ - CTIMER_CTRL5_TMRB5FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0B5, stop. */ - CTIMER_CTRL5_TMRB5FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0B5, restart. */ - CTIMER_CTRL5_TMRB5FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B5, assert, - count to CMPR1B5, deassert, stop. */ - CTIMER_CTRL5_TMRB5FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B5, assert, count - to CMPR1B5, deassert, restart. */ - CTIMER_CTRL5_TMRB5FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL5_TMRB5FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL5_TMRB5FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL5_TMRB5FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL5_TMRB5FN_Enum; - -/* ============================================ CTIMER CTRL5 TMRB5CLK [17..21] ============================================= */ -typedef enum { /*!< CTIMER_CTRL5_TMRB5CLK */ - CTIMER_CTRL5_TMRB5CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ - CTIMER_CTRL5_TMRB5CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL5_TMRB5CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL5_TMRB5CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL5_TMRB5CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL5_TMRB5CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL5_TMRB5CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL5_TMRB5CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL5_TMRB5CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL5_TMRB5CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL5_TMRB5CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL5_TMRB5CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL5_TMRB5CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL5_TMRB5CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL5_TMRB5CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL5_TMRB5CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL5_TMRB5CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL5_TMRB5CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL5_TMRB5CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL5_TMRB5CLK_CTMRA5 = 20, /*!< CTMRA5 : Clock source is CTIMERA5 OUT. */ - CTIMER_CTRL5_TMRB5CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ - CTIMER_CTRL5_TMRB5CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ - CTIMER_CTRL5_TMRB5CLK_CTMRA6 = 23, /*!< CTMRA6 : Clock source is CTIMERA6 OUT. */ - CTIMER_CTRL5_TMRB5CLK_CTMRB6 = 24, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ - CTIMER_CTRL5_TMRB5CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ - CTIMER_CTRL5_TMRB5CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ - CTIMER_CTRL5_TMRB5CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ - CTIMER_CTRL5_TMRB5CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ - CTIMER_CTRL5_TMRB5CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL5_TMRB5CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL5_TMRB5CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL5_TMRB5CLK_Enum; - -/* ============================================= CTIMER CTRL5 TMRB5EN [16..16] ============================================= */ -typedef enum { /*!< CTIMER_CTRL5_TMRB5EN */ - CTIMER_CTRL5_TMRB5EN_DIS = 0, /*!< DIS : Counter/Timer B5 Disable. */ - CTIMER_CTRL5_TMRB5EN_EN = 1, /*!< EN : Counter/Timer B5 Enable. */ -} CTIMER_CTRL5_TMRB5EN_Enum; - -/* ============================================ CTIMER CTRL5 TMRA5POL [12..12] ============================================= */ -typedef enum { /*!< CTIMER_CTRL5_TMRA5POL */ - CTIMER_CTRL5_TMRA5POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA5 pin is the same as the - timer output. */ - CTIMER_CTRL5_TMRA5POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA5 pin is the inverse of - the timer output. */ -} CTIMER_CTRL5_TMRA5POL_Enum; - -/* ============================================ CTIMER CTRL5 TMRA5CLR [11..11] ============================================= */ -typedef enum { /*!< CTIMER_CTRL5_TMRA5CLR */ - CTIMER_CTRL5_TMRA5CLR_RUN = 0, /*!< RUN : Allow counter/timer A5 to run */ - CTIMER_CTRL5_TMRA5CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A5 at 0x0000. */ -} CTIMER_CTRL5_TMRA5CLR_Enum; - -/* ============================================ CTIMER CTRL5 TMRA5IE1 [10..10] ============================================= */ -typedef enum { /*!< CTIMER_CTRL5_TMRA5IE1 */ - CTIMER_CTRL5_TMRA5IE1_DIS = 0, /*!< DIS : Disable counter/timer A5 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL5_TMRA5IE1_EN = 1, /*!< EN : Enable counter/timer A5 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL5_TMRA5IE1_Enum; - -/* ============================================= CTIMER CTRL5 TMRA5IE0 [9..9] ============================================== */ -typedef enum { /*!< CTIMER_CTRL5_TMRA5IE0 */ - CTIMER_CTRL5_TMRA5IE0_DIS = 0, /*!< DIS : Disable counter/timer A5 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL5_TMRA5IE0_EN = 1, /*!< EN : Enable counter/timer A5 to generate an interrupt based - on COMPR0. */ -} CTIMER_CTRL5_TMRA5IE0_Enum; - -/* ============================================== CTIMER CTRL5 TMRA5FN [6..8] ============================================== */ -typedef enum { /*!< CTIMER_CTRL5_TMRA5FN */ - CTIMER_CTRL5_TMRA5FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0A5, stop. */ - CTIMER_CTRL5_TMRA5FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0A5, restart. */ - CTIMER_CTRL5_TMRA5FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A5, assert, - count to CMPR1A5, deassert, stop. */ - CTIMER_CTRL5_TMRA5FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A5, assert, count - to CMPR1A5, deassert, restart. */ - CTIMER_CTRL5_TMRA5FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL5_TMRA5FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL5_TMRA5FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL5_TMRA5FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL5_TMRA5FN_Enum; - -/* ============================================= CTIMER CTRL5 TMRA5CLK [1..5] ============================================== */ -typedef enum { /*!< CTIMER_CTRL5_TMRA5CLK */ - CTIMER_CTRL5_TMRA5CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ - CTIMER_CTRL5_TMRA5CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL5_TMRA5CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL5_TMRA5CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL5_TMRA5CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL5_TMRA5CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL5_TMRA5CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL5_TMRA5CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL5_TMRA5CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL5_TMRA5CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL5_TMRA5CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL5_TMRA5CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL5_TMRA5CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL5_TMRA5CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL5_TMRA5CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL5_TMRA5CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL5_TMRA5CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL5_TMRA5CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL5_TMRA5CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL5_TMRA5CLK_CTMRB5 = 20, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ - CTIMER_CTRL5_TMRA5CLK_CTMRA0 = 21, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ - CTIMER_CTRL5_TMRA5CLK_CTMRB0 = 22, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ - CTIMER_CTRL5_TMRA5CLK_CTMRA6 = 23, /*!< CTMRA6 : Clock source is CTIMERA6 OUT. */ - CTIMER_CTRL5_TMRA5CLK_CTMRB6 = 24, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ - CTIMER_CTRL5_TMRA5CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ - CTIMER_CTRL5_TMRA5CLK_CTMRB2 = 26, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ - CTIMER_CTRL5_TMRA5CLK_CTMRB3 = 27, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ - CTIMER_CTRL5_TMRA5CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ - CTIMER_CTRL5_TMRA5CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL5_TMRA5CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL5_TMRA5CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL5_TMRA5CLK_Enum; - -/* ============================================== CTIMER CTRL5 TMRA5EN [0..0] ============================================== */ -typedef enum { /*!< CTIMER_CTRL5_TMRA5EN */ - CTIMER_CTRL5_TMRA5EN_DIS = 0, /*!< DIS : Counter/Timer A5 Disable. */ - CTIMER_CTRL5_TMRA5EN_EN = 1, /*!< EN : Counter/Timer A5 Enable. */ -} CTIMER_CTRL5_TMRA5EN_Enum; - -/* ======================================================= CMPRAUXA5 ======================================================= */ -/* ======================================================= CMPRAUXB5 ======================================================= */ -/* ========================================================= AUX5 ========================================================== */ -/* ============================================ CTIMER AUX5 TMRB5EN23 [30..30] ============================================= */ -typedef enum { /*!< CTIMER_AUX5_TMRB5EN23 */ - CTIMER_AUX5_TMRB5EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX5_TMRB5EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX5_TMRB5EN23_Enum; - -/* ============================================ CTIMER AUX5 TMRB5POL23 [29..29] ============================================ */ -typedef enum { /*!< CTIMER_AUX5_TMRB5POL23 */ - CTIMER_AUX5_TMRB5POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ - CTIMER_AUX5_TMRB5POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX5_TMRB5POL23_Enum; - -/* ============================================ CTIMER AUX5 TMRB5TINV [28..28] ============================================= */ -typedef enum { /*!< CTIMER_AUX5_TMRB5TINV */ - CTIMER_AUX5_TMRB5TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX5_TMRB5TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX5_TMRB5TINV_Enum; - -/* =========================================== CTIMER AUX5 TMRB5NOSYNC [27..27] ============================================ */ -typedef enum { /*!< CTIMER_AUX5_TMRB5NOSYNC */ - CTIMER_AUX5_TMRB5NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX5_TMRB5NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX5_TMRB5NOSYNC_Enum; - -/* ============================================ CTIMER AUX5 TMRB5TRIG [23..26] ============================================= */ -typedef enum { /*!< CTIMER_AUX5_TMRB5TRIG */ - CTIMER_AUX5_TMRB5TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX5_TMRB5TRIG_A5OUT = 1, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */ - CTIMER_AUX5_TMRB5TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ - CTIMER_AUX5_TMRB5TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ - CTIMER_AUX5_TMRB5TRIG_A6OUT = 4, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */ - CTIMER_AUX5_TMRB5TRIG_B6OUT = 5, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */ - CTIMER_AUX5_TMRB5TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ - CTIMER_AUX5_TMRB5TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ - CTIMER_AUX5_TMRB5TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ - CTIMER_AUX5_TMRB5TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ - CTIMER_AUX5_TMRB5TRIG_A0OUT2 = 10, /*!< A0OUT2 : Trigger source is CTIMERA0 OUT2. */ - CTIMER_AUX5_TMRB5TRIG_B0OUT2 = 11, /*!< B0OUT2 : Trigger source is CTIMERB0 OUT2. */ - CTIMER_AUX5_TMRB5TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ - CTIMER_AUX5_TMRB5TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ - CTIMER_AUX5_TMRB5TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ - CTIMER_AUX5_TMRB5TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ -} CTIMER_AUX5_TMRB5TRIG_Enum; - -/* ============================================ CTIMER AUX5 TMRA5EN23 [14..14] ============================================= */ -typedef enum { /*!< CTIMER_AUX5_TMRA5EN23 */ - CTIMER_AUX5_TMRA5EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX5_TMRA5EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX5_TMRA5EN23_Enum; - -/* ============================================ CTIMER AUX5 TMRA5POL23 [13..13] ============================================ */ -typedef enum { /*!< CTIMER_AUX5_TMRA5POL23 */ - CTIMER_AUX5_TMRA5POL23_NORMAL = 0, /*!< NORMAL : Upper output normal polarity */ - CTIMER_AUX5_TMRA5POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX5_TMRA5POL23_Enum; - -/* ============================================ CTIMER AUX5 TMRA5TINV [12..12] ============================================= */ -typedef enum { /*!< CTIMER_AUX5_TMRA5TINV */ - CTIMER_AUX5_TMRA5TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX5_TMRA5TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX5_TMRA5TINV_Enum; - -/* =========================================== CTIMER AUX5 TMRA5NOSYNC [11..11] ============================================ */ -typedef enum { /*!< CTIMER_AUX5_TMRA5NOSYNC */ - CTIMER_AUX5_TMRA5NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX5_TMRA5NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX5_TMRA5NOSYNC_Enum; - -/* ============================================= CTIMER AUX5 TMRA5TRIG [7..10] ============================================= */ -typedef enum { /*!< CTIMER_AUX5_TMRA5TRIG */ - CTIMER_AUX5_TMRA5TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX5_TMRA5TRIG_STIMER = 1, /*!< STIMER : Trigger source is STimer Interrupt. Only Active When - CTLINK==1 and TMRB5TRIG!=0. TMRB5TRIG selects an STIMER - interrupt */ - CTIMER_AUX5_TMRA5TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ - CTIMER_AUX5_TMRA5TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ - CTIMER_AUX5_TMRA5TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ - CTIMER_AUX5_TMRA5TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ - CTIMER_AUX5_TMRA5TRIG_A2OUT = 6, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ - CTIMER_AUX5_TMRA5TRIG_B2OUT = 7, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ - CTIMER_AUX5_TMRA5TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ - CTIMER_AUX5_TMRA5TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ - CTIMER_AUX5_TMRA5TRIG_A0OUT2 = 10, /*!< A0OUT2 : Trigger source is CTIMERA0 OUT2. */ - CTIMER_AUX5_TMRA5TRIG_B0OUT2 = 11, /*!< B0OUT2 : Trigger source is CTIMERB0 OUT2. */ - CTIMER_AUX5_TMRA5TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ - CTIMER_AUX5_TMRA5TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ - CTIMER_AUX5_TMRA5TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ - CTIMER_AUX5_TMRA5TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ -} CTIMER_AUX5_TMRA5TRIG_Enum; - -/* ========================================================= TMR6 ========================================================== */ -/* ======================================================== CMPRA6 ========================================================= */ -/* ======================================================== CMPRB6 ========================================================= */ -/* ========================================================= CTRL6 ========================================================= */ -/* ============================================= CTIMER CTRL6 CTLINK6 [31..31] ============================================= */ -typedef enum { /*!< CTIMER_CTRL6_CTLINK6 */ - CTIMER_CTRL6_CTLINK6_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A6/B6 timers as two independent 16-bit - timers (default). */ - CTIMER_CTRL6_CTLINK6_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A6/B6 timers into a single 32-bit timer. */ -} CTIMER_CTRL6_CTLINK6_Enum; - -/* ============================================ CTIMER CTRL6 TMRB6POL [28..28] ============================================= */ -typedef enum { /*!< CTIMER_CTRL6_TMRB6POL */ - CTIMER_CTRL6_TMRB6POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB6 pin is the same as the - timer output. */ - CTIMER_CTRL6_TMRB6POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB6 pin is the inverse of - the timer output. */ -} CTIMER_CTRL6_TMRB6POL_Enum; - -/* ============================================ CTIMER CTRL6 TMRB6CLR [27..27] ============================================= */ -typedef enum { /*!< CTIMER_CTRL6_TMRB6CLR */ - CTIMER_CTRL6_TMRB6CLR_RUN = 0, /*!< RUN : Allow counter/timer B6 to run */ - CTIMER_CTRL6_TMRB6CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B6 at 0x0000. */ -} CTIMER_CTRL6_TMRB6CLR_Enum; - -/* ============================================ CTIMER CTRL6 TMRB6IE1 [26..26] ============================================= */ -typedef enum { /*!< CTIMER_CTRL6_TMRB6IE1 */ - CTIMER_CTRL6_TMRB6IE1_DIS = 0, /*!< DIS : Disable counter/timer B6 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL6_TMRB6IE1_EN = 1, /*!< EN : Enable counter/timer B6 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL6_TMRB6IE1_Enum; - -/* ============================================ CTIMER CTRL6 TMRB6IE0 [25..25] ============================================= */ -typedef enum { /*!< CTIMER_CTRL6_TMRB6IE0 */ - CTIMER_CTRL6_TMRB6IE0_DIS = 0, /*!< DIS : Disable counter/timer B6 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL6_TMRB6IE0_EN = 1, /*!< EN : Enable counter/timer B6 to generate an interrupt based - on COMPR0 */ -} CTIMER_CTRL6_TMRB6IE0_Enum; - -/* ============================================= CTIMER CTRL6 TMRB6FN [22..24] ============================================= */ -typedef enum { /*!< CTIMER_CTRL6_TMRB6FN */ - CTIMER_CTRL6_TMRB6FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0B6, stop. */ - CTIMER_CTRL6_TMRB6FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0B6, restart. */ - CTIMER_CTRL6_TMRB6FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B6, assert, - count to CMPR1B6, deassert, stop. */ - CTIMER_CTRL6_TMRB6FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B6, assert, count - to CMPR1B6, deassert, restart. */ - CTIMER_CTRL6_TMRB6FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL6_TMRB6FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL6_TMRB6FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL6_TMRB6FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL6_TMRB6FN_Enum; - -/* ============================================ CTIMER CTRL6 TMRB6CLK [17..21] ============================================= */ -typedef enum { /*!< CTIMER_CTRL6_TMRB6CLK */ - CTIMER_CTRL6_TMRB6CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ - CTIMER_CTRL6_TMRB6CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL6_TMRB6CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL6_TMRB6CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL6_TMRB6CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL6_TMRB6CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL6_TMRB6CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL6_TMRB6CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL6_TMRB6CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL6_TMRB6CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL6_TMRB6CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL6_TMRB6CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL6_TMRB6CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL6_TMRB6CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL6_TMRB6CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL6_TMRB6CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL6_TMRB6CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL6_TMRB6CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL6_TMRB6CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL6_TMRB6CLK_CTMRA6 = 20, /*!< CTMRA6 : Clock source is CTIMERA6 OUT. */ - CTIMER_CTRL6_TMRB6CLK_CTMRA3 = 21, /*!< CTMRA3 : Clock source is CTIMERA3 OUT. */ - CTIMER_CTRL6_TMRB6CLK_CTMRB3 = 22, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ - CTIMER_CTRL6_TMRB6CLK_CTMRA7 = 23, /*!< CTMRA7 : Clock source is CTIMERA7 OUT. */ - CTIMER_CTRL6_TMRB6CLK_CTMRB7 = 24, /*!< CTMRB7 : Clock source is CTIMERB7 OUT. */ - CTIMER_CTRL6_TMRB6CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ - CTIMER_CTRL6_TMRB6CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ - CTIMER_CTRL6_TMRB6CLK_CTMRB2 = 27, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ - CTIMER_CTRL6_TMRB6CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ - CTIMER_CTRL6_TMRB6CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL6_TMRB6CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL6_TMRB6CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL6_TMRB6CLK_Enum; - -/* ============================================= CTIMER CTRL6 TMRB6EN [16..16] ============================================= */ -typedef enum { /*!< CTIMER_CTRL6_TMRB6EN */ - CTIMER_CTRL6_TMRB6EN_DIS = 0, /*!< DIS : Counter/Timer B6 Disable. */ - CTIMER_CTRL6_TMRB6EN_EN = 1, /*!< EN : Counter/Timer B6 Enable. */ -} CTIMER_CTRL6_TMRB6EN_Enum; - -/* ============================================ CTIMER CTRL6 TMRA6POL [12..12] ============================================= */ -typedef enum { /*!< CTIMER_CTRL6_TMRA6POL */ - CTIMER_CTRL6_TMRA6POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA6 pin is the same as the - timer output. */ - CTIMER_CTRL6_TMRA6POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA6 pin is the inverse of - the timer output. */ -} CTIMER_CTRL6_TMRA6POL_Enum; - -/* ============================================ CTIMER CTRL6 TMRA6CLR [11..11] ============================================= */ -typedef enum { /*!< CTIMER_CTRL6_TMRA6CLR */ - CTIMER_CTRL6_TMRA6CLR_RUN = 0, /*!< RUN : Allow counter/timer A6 to run */ - CTIMER_CTRL6_TMRA6CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A6 at 0x0000. */ -} CTIMER_CTRL6_TMRA6CLR_Enum; - -/* ============================================ CTIMER CTRL6 TMRA6IE1 [10..10] ============================================= */ -typedef enum { /*!< CTIMER_CTRL6_TMRA6IE1 */ - CTIMER_CTRL6_TMRA6IE1_DIS = 0, /*!< DIS : Disable counter/timer A6 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL6_TMRA6IE1_EN = 1, /*!< EN : Enable counter/timer A6 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL6_TMRA6IE1_Enum; - -/* ============================================= CTIMER CTRL6 TMRA6IE0 [9..9] ============================================== */ -typedef enum { /*!< CTIMER_CTRL6_TMRA6IE0 */ - CTIMER_CTRL6_TMRA6IE0_DIS = 0, /*!< DIS : Disable counter/timer A6 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL6_TMRA6IE0_EN = 1, /*!< EN : Enable counter/timer A6 to generate an interrupt based - on COMPR0. */ -} CTIMER_CTRL6_TMRA6IE0_Enum; - -/* ============================================== CTIMER CTRL6 TMRA6FN [6..8] ============================================== */ -typedef enum { /*!< CTIMER_CTRL6_TMRA6FN */ - CTIMER_CTRL6_TMRA6FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0A6, stop. */ - CTIMER_CTRL6_TMRA6FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0A6, restart. */ - CTIMER_CTRL6_TMRA6FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A6, assert, - count to CMPR1A6, deassert, stop. */ - CTIMER_CTRL6_TMRA6FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A6, assert, count - to CMPR1A6, deassert, restart. */ - CTIMER_CTRL6_TMRA6FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL6_TMRA6FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL6_TMRA6FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL6_TMRA6FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL6_TMRA6FN_Enum; - -/* ============================================= CTIMER CTRL6 TMRA6CLK [1..5] ============================================== */ -typedef enum { /*!< CTIMER_CTRL6_TMRA6CLK */ - CTIMER_CTRL6_TMRA6CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ - CTIMER_CTRL6_TMRA6CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL6_TMRA6CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL6_TMRA6CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL6_TMRA6CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL6_TMRA6CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL6_TMRA6CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL6_TMRA6CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL6_TMRA6CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL6_TMRA6CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL6_TMRA6CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL6_TMRA6CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL6_TMRA6CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL6_TMRA6CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL6_TMRA6CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL6_TMRA6CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL6_TMRA6CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL6_TMRA6CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL6_TMRA6CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL6_TMRA6CLK_CTMRB6 = 20, /*!< CTMRB6 : Clock source is CTIMERB6 OUT. */ - CTIMER_CTRL6_TMRA6CLK_CTMRA3 = 21, /*!< CTMRA3 : Clock source is CTIMERA3 OUT. */ - CTIMER_CTRL6_TMRA6CLK_CTMRB3 = 22, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ - CTIMER_CTRL6_TMRA6CLK_CTMRA7 = 23, /*!< CTMRA7 : Clock source is CTIMERA7 OUT. */ - CTIMER_CTRL6_TMRA6CLK_CTMRB7 = 24, /*!< CTMRB7 : Clock source is CTIMERB7 OUT. */ - CTIMER_CTRL6_TMRA6CLK_CTMRB0 = 25, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ - CTIMER_CTRL6_TMRA6CLK_CTMRB1 = 26, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ - CTIMER_CTRL6_TMRA6CLK_CTMRB2 = 27, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ - CTIMER_CTRL6_TMRA6CLK_CTMRB4 = 28, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ - CTIMER_CTRL6_TMRA6CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL6_TMRA6CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL6_TMRA6CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL6_TMRA6CLK_Enum; - -/* ============================================== CTIMER CTRL6 TMRA6EN [0..0] ============================================== */ -typedef enum { /*!< CTIMER_CTRL6_TMRA6EN */ - CTIMER_CTRL6_TMRA6EN_DIS = 0, /*!< DIS : Counter/Timer A6 Disable. */ - CTIMER_CTRL6_TMRA6EN_EN = 1, /*!< EN : Counter/Timer A6 Enable. */ -} CTIMER_CTRL6_TMRA6EN_Enum; - -/* ======================================================= CMPRAUXA6 ======================================================= */ -/* ======================================================= CMPRAUXB6 ======================================================= */ -/* ========================================================= AUX6 ========================================================== */ -/* ============================================ CTIMER AUX6 TMRB6EN23 [30..30] ============================================= */ -typedef enum { /*!< CTIMER_AUX6_TMRB6EN23 */ - CTIMER_AUX6_TMRB6EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX6_TMRB6EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX6_TMRB6EN23_Enum; - -/* ============================================ CTIMER AUX6 TMRB6POL23 [29..29] ============================================ */ -typedef enum { /*!< CTIMER_AUX6_TMRB6POL23 */ - CTIMER_AUX6_TMRB6POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ - CTIMER_AUX6_TMRB6POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX6_TMRB6POL23_Enum; - -/* ============================================ CTIMER AUX6 TMRB6TINV [28..28] ============================================= */ -typedef enum { /*!< CTIMER_AUX6_TMRB6TINV */ - CTIMER_AUX6_TMRB6TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX6_TMRB6TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX6_TMRB6TINV_Enum; - -/* =========================================== CTIMER AUX6 TMRB6NOSYNC [27..27] ============================================ */ -typedef enum { /*!< CTIMER_AUX6_TMRB6NOSYNC */ - CTIMER_AUX6_TMRB6NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX6_TMRB6NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX6_TMRB6NOSYNC_Enum; - -/* ============================================ CTIMER AUX6 TMRB6TRIG [23..26] ============================================= */ -typedef enum { /*!< CTIMER_AUX6_TMRB6TRIG */ - CTIMER_AUX6_TMRB6TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX6_TMRB6TRIG_A6OUT = 1, /*!< A6OUT : Trigger source is CTIMERA6 OUT. */ - CTIMER_AUX6_TMRB6TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ - CTIMER_AUX6_TMRB6TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ - CTIMER_AUX6_TMRB6TRIG_A4OUT = 4, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ - CTIMER_AUX6_TMRB6TRIG_B4OUT = 5, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ - CTIMER_AUX6_TMRB6TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ - CTIMER_AUX6_TMRB6TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ - CTIMER_AUX6_TMRB6TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ - CTIMER_AUX6_TMRB6TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ - CTIMER_AUX6_TMRB6TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ - CTIMER_AUX6_TMRB6TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2. */ - CTIMER_AUX6_TMRB6TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ - CTIMER_AUX6_TMRB6TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ - CTIMER_AUX6_TMRB6TRIG_B0OUT2DUAL = 14, /*!< B0OUT2DUAL : Trigger source is CTIMERB0 OUT2, dual edge. */ - CTIMER_AUX6_TMRB6TRIG_A0OUT2DUAL = 15, /*!< A0OUT2DUAL : Trigger source is CTIMERA0 OUT2, dual edge. */ -} CTIMER_AUX6_TMRB6TRIG_Enum; - -/* ============================================ CTIMER AUX6 TMRA6EN23 [14..14] ============================================= */ -typedef enum { /*!< CTIMER_AUX6_TMRA6EN23 */ - CTIMER_AUX6_TMRA6EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX6_TMRA6EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX6_TMRA6EN23_Enum; - -/* ============================================ CTIMER AUX6 TMRA6POL23 [13..13] ============================================ */ -typedef enum { /*!< CTIMER_AUX6_TMRA6POL23 */ - CTIMER_AUX6_TMRA6POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ - CTIMER_AUX6_TMRA6POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX6_TMRA6POL23_Enum; - -/* ============================================ CTIMER AUX6 TMRA6TINV [12..12] ============================================= */ -typedef enum { /*!< CTIMER_AUX6_TMRA6TINV */ - CTIMER_AUX6_TMRA6TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX6_TMRA6TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX6_TMRA6TINV_Enum; - -/* =========================================== CTIMER AUX6 TMRA6NOSYNC [11..11] ============================================ */ -typedef enum { /*!< CTIMER_AUX6_TMRA6NOSYNC */ - CTIMER_AUX6_TMRA6NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX6_TMRA6NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX6_TMRA6NOSYNC_Enum; - -/* ============================================= CTIMER AUX6 TMRA6TRIG [7..10] ============================================= */ -typedef enum { /*!< CTIMER_AUX6_TMRA6TRIG */ - CTIMER_AUX6_TMRA6TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX6_TMRA6TRIG_B6OUT = 1, /*!< B6OUT : Trigger source is CTIMERB6 OUT. */ - CTIMER_AUX6_TMRA6TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ - CTIMER_AUX6_TMRA6TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ - CTIMER_AUX6_TMRA6TRIG_A5OUT = 4, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */ - CTIMER_AUX6_TMRA6TRIG_B5OUT = 5, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */ - CTIMER_AUX6_TMRA6TRIG_A1OUT = 6, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ - CTIMER_AUX6_TMRA6TRIG_B1OUT = 7, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ - CTIMER_AUX6_TMRA6TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ - CTIMER_AUX6_TMRA6TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ - CTIMER_AUX6_TMRA6TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ - CTIMER_AUX6_TMRA6TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERBb OUT2. */ - CTIMER_AUX6_TMRA6TRIG_A5OUT2DUAL = 12, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ - CTIMER_AUX6_TMRA6TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ - CTIMER_AUX6_TMRA6TRIG_B0OUT2DUAL = 14, /*!< B0OUT2DUAL : Trigger source is CTIMERB0 OUT2, dual edge. */ - CTIMER_AUX6_TMRA6TRIG_A0OUT2DUAL = 15, /*!< A0OUT2DUAL : Trigger source is CTIMERA0 OUT2, dual edge. */ -} CTIMER_AUX6_TMRA6TRIG_Enum; - -/* ========================================================= TMR7 ========================================================== */ -/* ======================================================== CMPRA7 ========================================================= */ -/* ======================================================== CMPRB7 ========================================================= */ -/* ========================================================= CTRL7 ========================================================= */ -/* ============================================= CTIMER CTRL7 CTLINK7 [31..31] ============================================= */ -typedef enum { /*!< CTIMER_CTRL7_CTLINK7 */ - CTIMER_CTRL7_CTLINK7_TWO_16BIT_TIMERS = 0, /*!< TWO_16BIT_TIMERS : Use A7/B7 timers as two independent 16-bit - timers (default). */ - CTIMER_CTRL7_CTLINK7_32BIT_TIMER = 1, /*!< 32BIT_TIMER : Link A7/B7 timers into a single 32-bit timer. */ -} CTIMER_CTRL7_CTLINK7_Enum; - -/* ============================================ CTIMER CTRL7 TMRB7POL [28..28] ============================================= */ -typedef enum { /*!< CTIMER_CTRL7_TMRB7POL */ - CTIMER_CTRL7_TMRB7POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINB7 pin is the same as the - timer output. */ - CTIMER_CTRL7_TMRB7POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINB7 pin is the inverse of - the timer output. */ -} CTIMER_CTRL7_TMRB7POL_Enum; - -/* ============================================ CTIMER CTRL7 TMRB7CLR [27..27] ============================================= */ -typedef enum { /*!< CTIMER_CTRL7_TMRB7CLR */ - CTIMER_CTRL7_TMRB7CLR_RUN = 0, /*!< RUN : Allow counter/timer B7 to run */ - CTIMER_CTRL7_TMRB7CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer B7 at 0x0000. */ -} CTIMER_CTRL7_TMRB7CLR_Enum; - -/* ============================================ CTIMER CTRL7 TMRB7IE1 [26..26] ============================================= */ -typedef enum { /*!< CTIMER_CTRL7_TMRB7IE1 */ - CTIMER_CTRL7_TMRB7IE1_DIS = 0, /*!< DIS : Disable counter/timer B7 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL7_TMRB7IE1_EN = 1, /*!< EN : Enable counter/timer B7 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL7_TMRB7IE1_Enum; - -/* ============================================ CTIMER CTRL7 TMRB7IE0 [25..25] ============================================= */ -typedef enum { /*!< CTIMER_CTRL7_TMRB7IE0 */ - CTIMER_CTRL7_TMRB7IE0_DIS = 0, /*!< DIS : Disable counter/timer B7 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL7_TMRB7IE0_EN = 1, /*!< EN : Enable counter/timer B7 to generate an interrupt based - on COMPR0 */ -} CTIMER_CTRL7_TMRB7IE0_Enum; - -/* ============================================= CTIMER CTRL7 TMRB7FN [22..24] ============================================= */ -typedef enum { /*!< CTIMER_CTRL7_TMRB7FN */ - CTIMER_CTRL7_TMRB7FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0B7, stop. */ - CTIMER_CTRL7_TMRB7FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0B7, restart. */ - CTIMER_CTRL7_TMRB7FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B7, assert, - count to CMPR1B7, deassert, stop. */ - CTIMER_CTRL7_TMRB7FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0B7, assert, count - to CMPR1B7, deassert, restart. */ - CTIMER_CTRL7_TMRB7FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL7_TMRB7FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL7_TMRB7FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL7_TMRB7FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL7_TMRB7FN_Enum; - -/* ============================================ CTIMER CTRL7 TMRB7CLK [17..21] ============================================= */ -typedef enum { /*!< CTIMER_CTRL7_TMRB7CLK */ - CTIMER_CTRL7_TMRB7CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINB. */ - CTIMER_CTRL7_TMRB7CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL7_TMRB7CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL7_TMRB7CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL7_TMRB7CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL7_TMRB7CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL7_TMRB7CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL7_TMRB7CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL7_TMRB7CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL7_TMRB7CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL7_TMRB7CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL7_TMRB7CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL7_TMRB7CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL7_TMRB7CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL7_TMRB7CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL7_TMRB7CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL7_TMRB7CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL7_TMRB7CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL7_TMRB7CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL7_TMRB7CLK_CTMRA7 = 20, /*!< CTMRA7 : Clock source is CTIMERA7 OUT. */ - CTIMER_CTRL7_TMRB7CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ - CTIMER_CTRL7_TMRB7CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ - CTIMER_CTRL7_TMRB7CLK_CTMRA0 = 23, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ - CTIMER_CTRL7_TMRB7CLK_CTMRB0 = 24, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ - CTIMER_CTRL7_TMRB7CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ - CTIMER_CTRL7_TMRB7CLK_CTMRB3 = 26, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ - CTIMER_CTRL7_TMRB7CLK_CTMRB4 = 27, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ - CTIMER_CTRL7_TMRB7CLK_CTMRB5 = 28, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ - CTIMER_CTRL7_TMRB7CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL7_TMRB7CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL7_TMRB7CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL7_TMRB7CLK_Enum; - -/* ============================================= CTIMER CTRL7 TMRB7EN [16..16] ============================================= */ -typedef enum { /*!< CTIMER_CTRL7_TMRB7EN */ - CTIMER_CTRL7_TMRB7EN_DIS = 0, /*!< DIS : Counter/Timer B7 Disable. */ - CTIMER_CTRL7_TMRB7EN_EN = 1, /*!< EN : Counter/Timer B7 Enable. */ -} CTIMER_CTRL7_TMRB7EN_Enum; - -/* ============================================ CTIMER CTRL7 TMRA7POL [12..12] ============================================= */ -typedef enum { /*!< CTIMER_CTRL7_TMRA7POL */ - CTIMER_CTRL7_TMRA7POL_NORMAL = 0, /*!< NORMAL : The polarity of the TMRPINA7 pin is the same as the - timer output. */ - CTIMER_CTRL7_TMRA7POL_INVERTED = 1, /*!< INVERTED : The polarity of the TMRPINA7 pin is the inverse of - the timer output. */ -} CTIMER_CTRL7_TMRA7POL_Enum; - -/* ============================================ CTIMER CTRL7 TMRA7CLR [11..11] ============================================= */ -typedef enum { /*!< CTIMER_CTRL7_TMRA7CLR */ - CTIMER_CTRL7_TMRA7CLR_RUN = 0, /*!< RUN : Allow counter/timer A7 to run */ - CTIMER_CTRL7_TMRA7CLR_CLEAR = 1, /*!< CLEAR : Holds counter/timer A7 at 0x0000. */ -} CTIMER_CTRL7_TMRA7CLR_Enum; - -/* ============================================ CTIMER CTRL7 TMRA7IE1 [10..10] ============================================= */ -typedef enum { /*!< CTIMER_CTRL7_TMRA7IE1 */ - CTIMER_CTRL7_TMRA7IE1_DIS = 0, /*!< DIS : Disable counter/timer A7 from generating an interrupt - based on COMPR1. */ - CTIMER_CTRL7_TMRA7IE1_EN = 1, /*!< EN : Enable counter/timer A7 to generate an interrupt based - on COMPR1. */ -} CTIMER_CTRL7_TMRA7IE1_Enum; - -/* ============================================= CTIMER CTRL7 TMRA7IE0 [9..9] ============================================== */ -typedef enum { /*!< CTIMER_CTRL7_TMRA7IE0 */ - CTIMER_CTRL7_TMRA7IE0_DIS = 0, /*!< DIS : Disable counter/timer A7 from generating an interrupt - based on COMPR0. */ - CTIMER_CTRL7_TMRA7IE0_EN = 1, /*!< EN : Enable counter/timer A7 to generate an interrupt based - on COMPR0. */ -} CTIMER_CTRL7_TMRA7IE0_Enum; - -/* ============================================== CTIMER CTRL7 TMRA7FN [6..8] ============================================== */ -typedef enum { /*!< CTIMER_CTRL7_TMRA7FN */ - CTIMER_CTRL7_TMRA7FN_SINGLECOUNT = 0, /*!< SINGLECOUNT : Single count (output toggles and sticks). Count - to CMPR0A7, stop. */ - CTIMER_CTRL7_TMRA7FN_REPEATEDCOUNT = 1, /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide - pulses). Count to CMPR0A7, restart. */ - CTIMER_CTRL7_TMRA7FN_PULSE_ONCE = 2, /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A7, assert, - count to CMPR1A7, deassert, stop. */ - CTIMER_CTRL7_TMRA7FN_PULSE_CONT = 3, /*!< PULSE_CONT : Pulse continously. Count to CMPR0A7, assert, count - to CMPR1A7, deassert, restart. */ - CTIMER_CTRL7_TMRA7FN_SINGLEPATTERN = 4, /*!< SINGLEPATTERN : Single pattern. */ - CTIMER_CTRL7_TMRA7FN_REPEATPATTERN = 5, /*!< REPEATPATTERN : Repeated pattern. */ - CTIMER_CTRL7_TMRA7FN_CONTINUOUS = 6, /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously. */ - CTIMER_CTRL7_TMRA7FN_ALTPWN = 7, /*!< ALTPWN : Alternate PWM */ -} CTIMER_CTRL7_TMRA7FN_Enum; - -/* ============================================= CTIMER CTRL7 TMRA7CLK [1..5] ============================================== */ -typedef enum { /*!< CTIMER_CTRL7_TMRA7CLK */ - CTIMER_CTRL7_TMRA7CLK_TMRPIN = 0, /*!< TMRPIN : Clock source is TMRPINA. */ - CTIMER_CTRL7_TMRA7CLK_HFRC_DIV4 = 1, /*!< HFRC_DIV4 : Clock source is the HFRC / 4 */ - CTIMER_CTRL7_TMRA7CLK_HFRC_DIV16 = 2, /*!< HFRC_DIV16 : Clock source is HFRC / 16 */ - CTIMER_CTRL7_TMRA7CLK_HFRC_DIV256 = 3, /*!< HFRC_DIV256 : Clock source is HFRC / 256 */ - CTIMER_CTRL7_TMRA7CLK_HFRC_DIV1024 = 4, /*!< HFRC_DIV1024 : Clock source is HFRC / 1024 */ - CTIMER_CTRL7_TMRA7CLK_HFRC_DIV4K = 5, /*!< HFRC_DIV4K : Clock source is HFRC / 4096 */ - CTIMER_CTRL7_TMRA7CLK_XT = 6, /*!< XT : Clock source is the XT (uncalibrated). */ - CTIMER_CTRL7_TMRA7CLK_XT_DIV2 = 7, /*!< XT_DIV2 : Clock source is XT / 2 */ - CTIMER_CTRL7_TMRA7CLK_XT_DIV16 = 8, /*!< XT_DIV16 : Clock source is XT / 16 */ - CTIMER_CTRL7_TMRA7CLK_XT_DIV128 = 9, /*!< XT_DIV128 : Clock source is XT / 128 */ - CTIMER_CTRL7_TMRA7CLK_LFRC_DIV2 = 10, /*!< LFRC_DIV2 : Clock source is LFRC / 2 */ - CTIMER_CTRL7_TMRA7CLK_LFRC_DIV32 = 11, /*!< LFRC_DIV32 : Clock source is LFRC / 32 */ - CTIMER_CTRL7_TMRA7CLK_LFRC_DIV1K = 12, /*!< LFRC_DIV1K : Clock source is LFRC / 1024 */ - CTIMER_CTRL7_TMRA7CLK_LFRC = 13, /*!< LFRC : Clock source is LFRC */ - CTIMER_CTRL7_TMRA7CLK_RTC_100HZ = 14, /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator. */ - CTIMER_CTRL7_TMRA7CLK_HCLK_DIV4 = 15, /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only - available when MCU is in active mode) */ - CTIMER_CTRL7_TMRA7CLK_XT_DIV4 = 16, /*!< XT_DIV4 : Clock source is XT / 4 */ - CTIMER_CTRL7_TMRA7CLK_XT_DIV8 = 17, /*!< XT_DIV8 : Clock source is XT / 8 */ - CTIMER_CTRL7_TMRA7CLK_XT_DIV32 = 18, /*!< XT_DIV32 : Clock source is XT / 32 */ - CTIMER_CTRL7_TMRA7CLK_CTMRB7 = 20, /*!< CTMRB7 : Clock source is CTIMERB7 OUT. */ - CTIMER_CTRL7_TMRA7CLK_CTMRA2 = 21, /*!< CTMRA2 : Clock source is CTIMERA2 OUT. */ - CTIMER_CTRL7_TMRA7CLK_CTMRB2 = 22, /*!< CTMRB2 : Clock source is CTIMERB2 OUT. */ - CTIMER_CTRL7_TMRA7CLK_CTMRA0 = 23, /*!< CTMRA0 : Clock source is CTIMERA0 OUT. */ - CTIMER_CTRL7_TMRA7CLK_CTMRB0 = 24, /*!< CTMRB0 : Clock source is CTIMERB0 OUT. */ - CTIMER_CTRL7_TMRA7CLK_CTMRB1 = 25, /*!< CTMRB1 : Clock source is CTIMERB1 OUT. */ - CTIMER_CTRL7_TMRA7CLK_CTMRB3 = 26, /*!< CTMRB3 : Clock source is CTIMERB3 OUT. */ - CTIMER_CTRL7_TMRA7CLK_CTMRB4 = 27, /*!< CTMRB4 : Clock source is CTIMERB4 OUT. */ - CTIMER_CTRL7_TMRA7CLK_CTMRB5 = 28, /*!< CTMRB5 : Clock source is CTIMERB5 OUT. */ - CTIMER_CTRL7_TMRA7CLK_BUCKBLE = 29, /*!< BUCKBLE : Clock source is BLE buck converter TON pulses. */ - CTIMER_CTRL7_TMRA7CLK_BUCKB = 30, /*!< BUCKB : Clock source is Memory buck converter TON pulses. */ - CTIMER_CTRL7_TMRA7CLK_BUCKA = 31, /*!< BUCKA : Clock source is CPU buck converter TON pulses. */ -} CTIMER_CTRL7_TMRA7CLK_Enum; - -/* ============================================== CTIMER CTRL7 TMRA7EN [0..0] ============================================== */ -typedef enum { /*!< CTIMER_CTRL7_TMRA7EN */ - CTIMER_CTRL7_TMRA7EN_DIS = 0, /*!< DIS : Counter/Timer A7 Disable. */ - CTIMER_CTRL7_TMRA7EN_EN = 1, /*!< EN : Counter/Timer A7 Enable. */ -} CTIMER_CTRL7_TMRA7EN_Enum; - -/* ======================================================= CMPRAUXA7 ======================================================= */ -/* ======================================================= CMPRAUXB7 ======================================================= */ -/* ========================================================= AUX7 ========================================================== */ -/* ============================================ CTIMER AUX7 TMRB7EN23 [30..30] ============================================= */ -typedef enum { /*!< CTIMER_AUX7_TMRB7EN23 */ - CTIMER_AUX7_TMRB7EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX7_TMRB7EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX7_TMRB7EN23_Enum; - -/* ============================================ CTIMER AUX7 TMRB7POL23 [29..29] ============================================ */ -typedef enum { /*!< CTIMER_AUX7_TMRB7POL23 */ - CTIMER_AUX7_TMRB7POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ - CTIMER_AUX7_TMRB7POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX7_TMRB7POL23_Enum; - -/* ============================================ CTIMER AUX7 TMRB7TINV [28..28] ============================================= */ -typedef enum { /*!< CTIMER_AUX7_TMRB7TINV */ - CTIMER_AUX7_TMRB7TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX7_TMRB7TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX7_TMRB7TINV_Enum; - -/* =========================================== CTIMER AUX7 TMRB7NOSYNC [27..27] ============================================ */ -typedef enum { /*!< CTIMER_AUX7_TMRB7NOSYNC */ - CTIMER_AUX7_TMRB7NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX7_TMRB7NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX7_TMRB7NOSYNC_Enum; - -/* ============================================ CTIMER AUX7 TMRB7TRIG [23..26] ============================================= */ -typedef enum { /*!< CTIMER_AUX7_TMRB7TRIG */ - CTIMER_AUX7_TMRB7TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX7_TMRB7TRIG_A7OUT = 1, /*!< A7OUT : Trigger source is CTIMERA7 OUT. */ - CTIMER_AUX7_TMRB7TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ - CTIMER_AUX7_TMRB7TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ - CTIMER_AUX7_TMRB7TRIG_A5OUT = 4, /*!< A5OUT : Trigger source is CTIMERA5 OUT. */ - CTIMER_AUX7_TMRB7TRIG_B5OUT = 5, /*!< B5OUT : Trigger source is CTIMERB5 OUT. */ - CTIMER_AUX7_TMRB7TRIG_A2OUT = 6, /*!< A2OUT : Trigger source is CTIMERA2 OUT. */ - CTIMER_AUX7_TMRB7TRIG_B2OUT = 7, /*!< B2OUT : Trigger source is CTIMERB2 OUT. */ - CTIMER_AUX7_TMRB7TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ - CTIMER_AUX7_TMRB7TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ - CTIMER_AUX7_TMRB7TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ - CTIMER_AUX7_TMRB7TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2. */ - CTIMER_AUX7_TMRB7TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ - CTIMER_AUX7_TMRB7TRIG_A7OUT2DUAL = 13, /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge. */ - CTIMER_AUX7_TMRB7TRIG_B1OUT2DUAL = 14, /*!< B1OUT2DUAL : Trigger source is CTIMERB1 OUT2, dual edge. */ - CTIMER_AUX7_TMRB7TRIG_A1OUT2DUAL = 15, /*!< A1OUT2DUAL : Trigger source is CTIMERA1 OUT2, dual edge. */ -} CTIMER_AUX7_TMRB7TRIG_Enum; - -/* ============================================ CTIMER AUX7 TMRA7EN23 [14..14] ============================================= */ -typedef enum { /*!< CTIMER_AUX7_TMRA7EN23 */ - CTIMER_AUX7_TMRA7EN23_DIS = 1, /*!< DIS : Disable enhanced functions. */ - CTIMER_AUX7_TMRA7EN23_EN = 0, /*!< EN : Enable enhanced functions. */ -} CTIMER_AUX7_TMRA7EN23_Enum; - -/* ============================================ CTIMER AUX7 TMRA7POL23 [13..13] ============================================ */ -typedef enum { /*!< CTIMER_AUX7_TMRA7POL23 */ - CTIMER_AUX7_TMRA7POL23_NORM = 0, /*!< NORM : Upper output normal polarity */ - CTIMER_AUX7_TMRA7POL23_INV = 1, /*!< INV : Upper output inverted polarity. */ -} CTIMER_AUX7_TMRA7POL23_Enum; - -/* ============================================ CTIMER AUX7 TMRA7TINV [12..12] ============================================= */ -typedef enum { /*!< CTIMER_AUX7_TMRA7TINV */ - CTIMER_AUX7_TMRA7TINV_DIS = 0, /*!< DIS : Disable invert on trigger */ - CTIMER_AUX7_TMRA7TINV_EN = 1, /*!< EN : Enable invert on trigger */ -} CTIMER_AUX7_TMRA7TINV_Enum; - -/* =========================================== CTIMER AUX7 TMRA7NOSYNC [11..11] ============================================ */ -typedef enum { /*!< CTIMER_AUX7_TMRA7NOSYNC */ - CTIMER_AUX7_TMRA7NOSYNC_DIS = 0, /*!< DIS : Synchronization on source clock */ - CTIMER_AUX7_TMRA7NOSYNC_NOSYNC = 1, /*!< NOSYNC : No synchronization on source clock */ -} CTIMER_AUX7_TMRA7NOSYNC_Enum; - -/* ============================================= CTIMER AUX7 TMRA7TRIG [7..10] ============================================= */ -typedef enum { /*!< CTIMER_AUX7_TMRA7TRIG */ - CTIMER_AUX7_TMRA7TRIG_DIS = 0, /*!< DIS : Trigger source is disabled. */ - CTIMER_AUX7_TMRA7TRIG_B7OUT = 1, /*!< B7OUT : Trigger source is CTIMERB7 OUT. */ - CTIMER_AUX7_TMRA7TRIG_B3OUT = 2, /*!< B3OUT : Trigger source is CTIMERB3 OUT. */ - CTIMER_AUX7_TMRA7TRIG_A3OUT = 3, /*!< A3OUT : Trigger source is CTIMERA3 OUT. */ - CTIMER_AUX7_TMRA7TRIG_A1OUT = 4, /*!< A1OUT : Trigger source is CTIMERA1 OUT. */ - CTIMER_AUX7_TMRA7TRIG_B1OUT = 5, /*!< B1OUT : Trigger source is CTIMERB1 OUT. */ - CTIMER_AUX7_TMRA7TRIG_A4OUT = 6, /*!< A4OUT : Trigger source is CTIMERA4 OUT. */ - CTIMER_AUX7_TMRA7TRIG_B4OUT = 7, /*!< B4OUT : Trigger source is CTIMERB4 OUT. */ - CTIMER_AUX7_TMRA7TRIG_B3OUT2 = 8, /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2. */ - CTIMER_AUX7_TMRA7TRIG_A3OUT2 = 9, /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2. */ - CTIMER_AUX7_TMRA7TRIG_A2OUT2 = 10, /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2. */ - CTIMER_AUX7_TMRA7TRIG_B2OUT2 = 11, /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2. */ - CTIMER_AUX7_TMRA7TRIG_A6OUT2DUAL = 12, /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge. */ - CTIMER_AUX7_TMRA7TRIG_A5OUT2DUAL = 13, /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge. */ - CTIMER_AUX7_TMRA7TRIG_B4OUT2DUAL = 14, /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge. */ - CTIMER_AUX7_TMRA7TRIG_A4OUT2DUAL = 15, /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge. */ -} CTIMER_AUX7_TMRA7TRIG_Enum; - -/* ======================================================== GLOBEN ========================================================= */ -/* ============================================== CTIMER GLOBEN ENB7 [15..15] ============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENB7 */ - CTIMER_GLOBEN_ENB7_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENB7_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENB7_Enum; - -/* ============================================== CTIMER GLOBEN ENA7 [14..14] ============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENA7 */ - CTIMER_GLOBEN_ENA7_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENA7_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENA7_Enum; - -/* ============================================== CTIMER GLOBEN ENB6 [13..13] ============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENB6 */ - CTIMER_GLOBEN_ENB6_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENB6_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENB6_Enum; - -/* ============================================== CTIMER GLOBEN ENA6 [12..12] ============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENA6 */ - CTIMER_GLOBEN_ENA6_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENA6_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENA6_Enum; - -/* ============================================== CTIMER GLOBEN ENB5 [11..11] ============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENB5 */ - CTIMER_GLOBEN_ENB5_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENB5_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENB5_Enum; - -/* ============================================== CTIMER GLOBEN ENA5 [10..10] ============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENA5 */ - CTIMER_GLOBEN_ENA5_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENA5_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENA5_Enum; - -/* =============================================== CTIMER GLOBEN ENB4 [9..9] =============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENB4 */ - CTIMER_GLOBEN_ENB4_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENB4_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENB4_Enum; - -/* =============================================== CTIMER GLOBEN ENA4 [8..8] =============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENA4 */ - CTIMER_GLOBEN_ENA4_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENA4_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENA4_Enum; - -/* =============================================== CTIMER GLOBEN ENB3 [7..7] =============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENB3 */ - CTIMER_GLOBEN_ENB3_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENB3_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENB3_Enum; - -/* =============================================== CTIMER GLOBEN ENA3 [6..6] =============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENA3 */ - CTIMER_GLOBEN_ENA3_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENA3_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENA3_Enum; - -/* =============================================== CTIMER GLOBEN ENB2 [5..5] =============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENB2 */ - CTIMER_GLOBEN_ENB2_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENB2_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENB2_Enum; - -/* =============================================== CTIMER GLOBEN ENA2 [4..4] =============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENA2 */ - CTIMER_GLOBEN_ENA2_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENA2_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENA2_Enum; - -/* =============================================== CTIMER GLOBEN ENB1 [3..3] =============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENB1 */ - CTIMER_GLOBEN_ENB1_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENB1_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENB1_Enum; - -/* =============================================== CTIMER GLOBEN ENA1 [2..2] =============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENA1 */ - CTIMER_GLOBEN_ENA1_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENA1_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENA1_Enum; - -/* =============================================== CTIMER GLOBEN ENB0 [1..1] =============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENB0 */ - CTIMER_GLOBEN_ENB0_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENB0_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENB0_Enum; - -/* =============================================== CTIMER GLOBEN ENA0 [0..0] =============================================== */ -typedef enum { /*!< CTIMER_GLOBEN_ENA0 */ - CTIMER_GLOBEN_ENA0_LCO = 1, /*!< LCO : Use local enable. */ - CTIMER_GLOBEN_ENA0_DIS = 0, /*!< DIS : Disable CTIMER. */ -} CTIMER_GLOBEN_ENA0_Enum; - -/* ======================================================== OUTCFG0 ======================================================== */ -/* ============================================= CTIMER OUTCFG0 CFG9 [28..30] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG0_CFG9 */ - CTIMER_OUTCFG0_CFG9_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG0_CFG9_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG0_CFG9_B0OUT = 5, /*!< B0OUT : Output is B0OUT. */ - CTIMER_OUTCFG0_CFG9_A4OUT = 4, /*!< A4OUT : Output is A4OUT. */ - CTIMER_OUTCFG0_CFG9_A2OUT = 3, /*!< A2OUT : Output is A2OUT. */ - CTIMER_OUTCFG0_CFG9_A2OUT2 = 2, /*!< A2OUT2 : Output is A2OUT2 */ - CTIMER_OUTCFG0_CFG9_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG0_CFG9_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG0_CFG9_Enum; - -/* ============================================= CTIMER OUTCFG0 CFG8 [25..27] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG0_CFG8 */ - CTIMER_OUTCFG0_CFG8_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG0_CFG8_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG0_CFG8_B6OUT = 5, /*!< B6OUT : Output is B6OUT. */ - CTIMER_OUTCFG0_CFG8_A4OUT2 = 4, /*!< A4OUT2 : Output is A4OUT2. */ - CTIMER_OUTCFG0_CFG8_A3OUT2 = 3, /*!< A3OUT2 : Output is A3OUT. */ - CTIMER_OUTCFG0_CFG8_A2OUT = 2, /*!< A2OUT : Output is A2OUT */ - CTIMER_OUTCFG0_CFG8_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG0_CFG8_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG0_CFG8_Enum; - -/* ============================================= CTIMER OUTCFG0 CFG7 [22..24] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG0_CFG7 */ - CTIMER_OUTCFG0_CFG7_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG0_CFG7_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG0_CFG7_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */ - CTIMER_OUTCFG0_CFG7_B5OUT = 4, /*!< B5OUT : Output is B5OUT. */ - CTIMER_OUTCFG0_CFG7_B1OUT = 3, /*!< B1OUT : Output is B1OUT. */ - CTIMER_OUTCFG0_CFG7_B1OUT2 = 2, /*!< B1OUT2 : Output is B1OUT2 */ - CTIMER_OUTCFG0_CFG7_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG0_CFG7_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG0_CFG7_Enum; - -/* ============================================= CTIMER OUTCFG0 CFG6 [19..21] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG0_CFG6 */ - CTIMER_OUTCFG0_CFG6_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG0_CFG6_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG0_CFG6_B7OUT = 5, /*!< B7OUT : Output is B7OUT. */ - CTIMER_OUTCFG0_CFG6_B5OUT2 = 4, /*!< B5OUT2 : Output is B5OUT2. */ - CTIMER_OUTCFG0_CFG6_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ - CTIMER_OUTCFG0_CFG6_B1OUT = 2, /*!< B1OUT : Output is B1OUT */ - CTIMER_OUTCFG0_CFG6_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG0_CFG6_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG0_CFG6_Enum; - -/* ============================================= CTIMER OUTCFG0 CFG5 [16..18] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG0_CFG5 */ - CTIMER_OUTCFG0_CFG5_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG0_CFG5_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG0_CFG5_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */ - CTIMER_OUTCFG0_CFG5_B6OUT = 4, /*!< B6OUT : Output is A5OUT. */ - CTIMER_OUTCFG0_CFG5_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ - CTIMER_OUTCFG0_CFG5_A1OUT2 = 2, /*!< A1OUT2 : Output is A1OUT2 */ - CTIMER_OUTCFG0_CFG5_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG0_CFG5_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG0_CFG5_Enum; - -/* ============================================= CTIMER OUTCFG0 CFG4 [12..14] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG0_CFG4 */ - CTIMER_OUTCFG0_CFG4_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG0_CFG4_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG0_CFG4_B5OUT = 5, /*!< B5OUT : Output is B5OUT. */ - CTIMER_OUTCFG0_CFG4_A5OUT2 = 4, /*!< A5OUT2 : Output is A5OUT2. */ - CTIMER_OUTCFG0_CFG4_A2OUT2 = 3, /*!< A2OUT2 : Output is A2OUT2. */ - CTIMER_OUTCFG0_CFG4_A1OUT = 2, /*!< A1OUT : Output is A1OUT */ - CTIMER_OUTCFG0_CFG4_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG0_CFG4_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG0_CFG4_Enum; - -/* ============================================== CTIMER OUTCFG0 CFG3 [9..11] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG0_CFG3 */ - CTIMER_OUTCFG0_CFG3_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG0_CFG3_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG0_CFG3_A6OUT = 5, /*!< A6OUT : Output is A6OUT. */ - CTIMER_OUTCFG0_CFG3_A1OUT = 4, /*!< A1OUT : Output is A1OUT. */ - CTIMER_OUTCFG0_CFG3_B0OUT = 3, /*!< B0OUT : Output is B0OUT. */ - CTIMER_OUTCFG0_CFG3_B0OUT2 = 2, /*!< B0OUT2 : Output is B0OUT2 */ - CTIMER_OUTCFG0_CFG3_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG0_CFG3_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG0_CFG3_Enum; - -/* ============================================== CTIMER OUTCFG0 CFG2 [6..8] =============================================== */ -typedef enum { /*!< CTIMER_OUTCFG0_CFG2 */ - CTIMER_OUTCFG0_CFG2_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG0_CFG2_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG0_CFG2_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */ - CTIMER_OUTCFG0_CFG2_B6OUT2 = 4, /*!< B6OUT2 : Output is B6OUT2. */ - CTIMER_OUTCFG0_CFG2_B1OUT2 = 3, /*!< B1OUT2 : Output is B1OUT2. */ - CTIMER_OUTCFG0_CFG2_B0OUT = 2, /*!< B0OUT : Output is B0OUT */ - CTIMER_OUTCFG0_CFG2_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG0_CFG2_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG0_CFG2_Enum; - -/* ============================================== CTIMER OUTCFG0 CFG1 [3..5] =============================================== */ -typedef enum { /*!< CTIMER_OUTCFG0_CFG1 */ - CTIMER_OUTCFG0_CFG1_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG0_CFG1_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG0_CFG1_B7OUT2 = 5, /*!< B7OUT2 : Output is B7OUT2. */ - CTIMER_OUTCFG0_CFG1_A5OUT = 4, /*!< A5OUT : Output is A5OUT. */ - CTIMER_OUTCFG0_CFG1_A0OUT = 3, /*!< A0OUT : Output is A0OUT. */ - CTIMER_OUTCFG0_CFG1_A0OUT2 = 2, /*!< A0OUT2 : Output is A0OUT2 */ - CTIMER_OUTCFG0_CFG1_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG0_CFG1_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG0_CFG1_Enum; - -/* ============================================== CTIMER OUTCFG0 CFG0 [0..2] =============================================== */ -typedef enum { /*!< CTIMER_OUTCFG0_CFG0 */ - CTIMER_OUTCFG0_CFG0_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG0_CFG0_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG0_CFG0_A6OUT = 5, /*!< A6OUT : Output is A6OUT. */ - CTIMER_OUTCFG0_CFG0_A5OUT2 = 4, /*!< A5OUT2 : Output is A5OUT2. */ - CTIMER_OUTCFG0_CFG0_B2OUT2 = 3, /*!< B2OUT2 : Output is B2OUT2. */ - CTIMER_OUTCFG0_CFG0_A0OUT = 2, /*!< A0OUT : Output is A0OUT */ - CTIMER_OUTCFG0_CFG0_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG0_CFG0_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG0_CFG0_Enum; - -/* ======================================================== OUTCFG1 ======================================================== */ -/* ============================================= CTIMER OUTCFG1 CFG19 [28..30] ============================================= */ -typedef enum { /*!< CTIMER_OUTCFG1_CFG19 */ - CTIMER_OUTCFG1_CFG19_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG1_CFG19_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG1_CFG19_B1OUT2 = 5, /*!< B1OUT2 : Output is B1OUT2. */ - CTIMER_OUTCFG1_CFG19_B4OUT = 4, /*!< B4OUT : Output is B4OUT. */ - CTIMER_OUTCFG1_CFG19_A2OUT = 3, /*!< A2OUT : Output is A2OUT. */ - CTIMER_OUTCFG1_CFG19_B4OUT2 = 2, /*!< B4OUT2 : Output is B4OUT2 */ - CTIMER_OUTCFG1_CFG19_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG1_CFG19_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG1_CFG19_Enum; - -/* ============================================= CTIMER OUTCFG1 CFG18 [25..27] ============================================= */ -typedef enum { /*!< CTIMER_OUTCFG1_CFG18 */ - CTIMER_OUTCFG1_CFG18_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG1_CFG18_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG1_CFG18_A3OUT2 = 5, /*!< A3OUT2 : Output is A3OUT2. */ - CTIMER_OUTCFG1_CFG18_A0OUT = 4, /*!< A0OUT : Output is A0OUT. */ - CTIMER_OUTCFG1_CFG18_B0OUT = 3, /*!< B0OUT : Output is B0OUT. */ - CTIMER_OUTCFG1_CFG18_B4OUT = 2, /*!< B4OUT : Output is B4OUT */ - CTIMER_OUTCFG1_CFG18_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG1_CFG18_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG1_CFG18_Enum; - -/* ============================================= CTIMER OUTCFG1 CFG17 [22..24] ============================================= */ -typedef enum { /*!< CTIMER_OUTCFG1_CFG17 */ - CTIMER_OUTCFG1_CFG17_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG1_CFG17_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG1_CFG17_A1OUT2 = 5, /*!< A1OUT2 : Output is A1OUT2. */ - CTIMER_OUTCFG1_CFG17_A4OUT = 4, /*!< A4OUT : Output is A4OUT. */ - CTIMER_OUTCFG1_CFG17_B7OUT = 3, /*!< B7OUT : Output is B7OUT. */ - CTIMER_OUTCFG1_CFG17_A4OUT2 = 2, /*!< A4OUT2 : Output is A4OUT2 */ - CTIMER_OUTCFG1_CFG17_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG1_CFG17_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG1_CFG17_Enum; - -/* ============================================= CTIMER OUTCFG1 CFG16 [19..21] ============================================= */ -typedef enum { /*!< CTIMER_OUTCFG1_CFG16 */ - CTIMER_OUTCFG1_CFG16_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG1_CFG16_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG1_CFG16_B3OUT2 = 5, /*!< B3OUT2 : Output is B3OUT2. */ - CTIMER_OUTCFG1_CFG16_A0OUT2 = 4, /*!< A0OUT2 : Output is A0OUT2. */ - CTIMER_OUTCFG1_CFG16_A0OUT = 3, /*!< A0OUT : Output is A0OUT. */ - CTIMER_OUTCFG1_CFG16_A4OUT = 2, /*!< A4OUT : Output is A4OUT */ - CTIMER_OUTCFG1_CFG16_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG1_CFG16_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG1_CFG16_Enum; - -/* ============================================= CTIMER OUTCFG1 CFG15 [16..18] ============================================= */ -typedef enum { /*!< CTIMER_OUTCFG1_CFG15 */ - CTIMER_OUTCFG1_CFG15_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG1_CFG15_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG1_CFG15_A4OUT2 = 5, /*!< A4OUT2 : Output is A4OUT2. */ - CTIMER_OUTCFG1_CFG15_A7OUT = 4, /*!< A7OUT : Output is A7OUT. */ - CTIMER_OUTCFG1_CFG15_B3OUT = 3, /*!< B3OUT : Output is B3OUT. */ - CTIMER_OUTCFG1_CFG15_B3OUT2 = 2, /*!< B3OUT2 : Output is B3OUT2 */ - CTIMER_OUTCFG1_CFG15_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG1_CFG15_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG1_CFG15_Enum; - -/* ============================================= CTIMER OUTCFG1 CFG14 [12..14] ============================================= */ -typedef enum { /*!< CTIMER_OUTCFG1_CFG14 */ - CTIMER_OUTCFG1_CFG14_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG1_CFG14_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG1_CFG14_A7OUT = 5, /*!< A7OUT : Output is A7OUT. */ - CTIMER_OUTCFG1_CFG14_B7OUT2 = 4, /*!< B7OUT2 : Output is B7OUT2. */ - CTIMER_OUTCFG1_CFG14_B1OUT = 3, /*!< B1OUT : Output is B1OUT. */ - CTIMER_OUTCFG1_CFG14_B3OUT = 2, /*!< B3OUT : Output is B3OUT */ - CTIMER_OUTCFG1_CFG14_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG1_CFG14_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG1_CFG14_Enum; - -/* ============================================= CTIMER OUTCFG1 CFG13 [9..11] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG1_CFG13 */ - CTIMER_OUTCFG1_CFG13_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG1_CFG13_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG1_CFG13_B4OUT2 = 5, /*!< B4OUT2 : Output is B4OUT2. */ - CTIMER_OUTCFG1_CFG13_A6OUT = 4, /*!< A6OUT : Output is A6OUT. */ - CTIMER_OUTCFG1_CFG13_A3OUT = 3, /*!< A3OUT : Output is A3OUT. */ - CTIMER_OUTCFG1_CFG13_A3OUT2 = 2, /*!< A3OUT2 : Output is A3OUT2 */ - CTIMER_OUTCFG1_CFG13_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG1_CFG13_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG1_CFG13_Enum; - -/* ============================================== CTIMER OUTCFG1 CFG12 [6..8] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG1_CFG12 */ - CTIMER_OUTCFG1_CFG12_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG1_CFG12_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG1_CFG12_B6OUT2 = 5, /*!< B6OUT2 : Output is B6OUT2. */ - CTIMER_OUTCFG1_CFG12_B0OUT2 = 4, /*!< B0OUT2 : Output is B0OUT2. */ - CTIMER_OUTCFG1_CFG12_B1OUT = 3, /*!< B1OUT : Output is B1OUT. */ - CTIMER_OUTCFG1_CFG12_A3OUT = 2, /*!< A3OUT : Output is A3OUT */ - CTIMER_OUTCFG1_CFG12_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG1_CFG12_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG1_CFG12_Enum; - -/* ============================================== CTIMER OUTCFG1 CFG11 [3..5] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG1_CFG11 */ - CTIMER_OUTCFG1_CFG11_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG1_CFG11_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG1_CFG11_B5OUT2 = 5, /*!< B5OUT2 : Output is B5OUT2. */ - CTIMER_OUTCFG1_CFG11_B4OUT = 4, /*!< B4OUT : Output is B4OUT. */ - CTIMER_OUTCFG1_CFG11_B2OUT = 3, /*!< B2OUT : Output is B2OUT. */ - CTIMER_OUTCFG1_CFG11_B2OUT2 = 2, /*!< B2OUT2 : Output is B2OUT2 */ - CTIMER_OUTCFG1_CFG11_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG1_CFG11_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG1_CFG11_Enum; - -/* ============================================== CTIMER OUTCFG1 CFG10 [0..2] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG1_CFG10 */ - CTIMER_OUTCFG1_CFG10_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG1_CFG10_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG1_CFG10_A6OUT = 5, /*!< A6OUT : Output is A6OUT. */ - CTIMER_OUTCFG1_CFG10_B4OUT2 = 4, /*!< B4OUT2 : Output is B4OUT2. */ - CTIMER_OUTCFG1_CFG10_B3OUT2 = 3, /*!< B3OUT2 : Output is B3OUT2. */ - CTIMER_OUTCFG1_CFG10_B2OUT = 2, /*!< B2OUT : Output is B2OUT */ - CTIMER_OUTCFG1_CFG10_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG1_CFG10_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG1_CFG10_Enum; - -/* ======================================================== OUTCFG2 ======================================================== */ -/* ============================================= CTIMER OUTCFG2 CFG29 [28..30] ============================================= */ -typedef enum { /*!< CTIMER_OUTCFG2_CFG29 */ - CTIMER_OUTCFG2_CFG29_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG2_CFG29_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG2_CFG29_A3OUT2 = 5, /*!< A3OUT2 : Output is A3OUT2. */ - CTIMER_OUTCFG2_CFG29_A7OUT = 4, /*!< A7OUT : Output is A7OUT. */ - CTIMER_OUTCFG2_CFG29_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ - CTIMER_OUTCFG2_CFG29_B5OUT2 = 2, /*!< B5OUT2 : Output is B5OUT2 */ - CTIMER_OUTCFG2_CFG29_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG2_CFG29_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG2_CFG29_Enum; - -/* ============================================= CTIMER OUTCFG2 CFG28 [25..27] ============================================= */ -typedef enum { /*!< CTIMER_OUTCFG2_CFG28 */ - CTIMER_OUTCFG2_CFG28_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG2_CFG28_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG2_CFG28_B0OUT2 = 5, /*!< B0OUT2 : Output is B0OUT2. */ - CTIMER_OUTCFG2_CFG28_A5OUT2 = 4, /*!< A5OUT2 : Output is A5OUT2. */ - CTIMER_OUTCFG2_CFG28_A3OUT = 3, /*!< A3OUT : Output is A3OUT. */ - CTIMER_OUTCFG2_CFG28_A7OUT = 2, /*!< A7OUT : Output is A7OUT */ - CTIMER_OUTCFG2_CFG28_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG2_CFG28_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG2_CFG28_Enum; - -/* ============================================= CTIMER OUTCFG2 CFG27 [22..24] ============================================= */ -typedef enum { /*!< CTIMER_OUTCFG2_CFG27 */ - CTIMER_OUTCFG2_CFG27_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG2_CFG27_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG2_CFG27_B2OUT2 = 5, /*!< B2OUT2 : Output is B2OUT2. */ - CTIMER_OUTCFG2_CFG27_B6OUT = 4, /*!< B6OUT : Output is B6OUT. */ - CTIMER_OUTCFG2_CFG27_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ - CTIMER_OUTCFG2_CFG27_B6OUT2 = 2, /*!< B6OUT2 : Output is B6OUT2 */ - CTIMER_OUTCFG2_CFG27_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG2_CFG27_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG2_CFG27_Enum; - -/* ============================================= CTIMER OUTCFG2 CFG26 [19..21] ============================================= */ -typedef enum { /*!< CTIMER_OUTCFG2_CFG26 */ - CTIMER_OUTCFG2_CFG26_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG2_CFG26_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG2_CFG26_A1OUT2 = 5, /*!< A1OUT2 : Output is A1OUT2. */ - CTIMER_OUTCFG2_CFG26_A5OUT = 4, /*!< A5OUT : Output is A5OUT. */ - CTIMER_OUTCFG2_CFG26_B2OUT = 3, /*!< B2OUT : Output is B2OUT. */ - CTIMER_OUTCFG2_CFG26_B6OUT = 2, /*!< B6OUT : Output is B6OUT */ - CTIMER_OUTCFG2_CFG26_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG2_CFG26_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG2_CFG26_Enum; - -/* ============================================= CTIMER OUTCFG2 CFG25 [16..18] ============================================= */ -typedef enum { /*!< CTIMER_OUTCFG2_CFG25 */ - CTIMER_OUTCFG2_CFG25_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG2_CFG25_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG2_CFG25_A2OUT2 = 5, /*!< A2OUT2 : Output is A2OUT2. */ - CTIMER_OUTCFG2_CFG25_A6OUT = 4, /*!< A6OUT : Output is A6OUT. */ - CTIMER_OUTCFG2_CFG25_B2OUT = 3, /*!< B2OUT : Output is B2OUT. */ - CTIMER_OUTCFG2_CFG25_B4OUT2 = 2, /*!< B4OUT2 : Output is B4OUT2 */ - CTIMER_OUTCFG2_CFG25_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG2_CFG25_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG2_CFG25_Enum; - -/* ============================================= CTIMER OUTCFG2 CFG24 [12..14] ============================================= */ -typedef enum { /*!< CTIMER_OUTCFG2_CFG24 */ - CTIMER_OUTCFG2_CFG24_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG2_CFG24_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG2_CFG24_B1OUT2 = 5, /*!< B1OUT2 : Output is B1OUT2. */ - CTIMER_OUTCFG2_CFG24_A1OUT = 4, /*!< A1OUT : Output is A1OUT. */ - CTIMER_OUTCFG2_CFG24_A2OUT = 3, /*!< A2OUT : Output is A2OUT. */ - CTIMER_OUTCFG2_CFG24_A6OUT = 2, /*!< A6OUT : Output is A6OUT */ - CTIMER_OUTCFG2_CFG24_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG2_CFG24_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG2_CFG24_Enum; - -/* ============================================= CTIMER OUTCFG2 CFG23 [9..11] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG2_CFG23 */ - CTIMER_OUTCFG2_CFG23_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG2_CFG23_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG2_CFG23_B0OUT2 = 5, /*!< B0OUT2 : Output is B0OUT2. */ - CTIMER_OUTCFG2_CFG23_A5OUT = 4, /*!< A5OUT : Output is A5OUT. */ - CTIMER_OUTCFG2_CFG23_A7OUT = 3, /*!< A7OUT : Output is A7OUT. */ - CTIMER_OUTCFG2_CFG23_B5OUT2 = 2, /*!< B5OUT2 : Output is B5OUT2 */ - CTIMER_OUTCFG2_CFG23_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG2_CFG23_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG2_CFG23_Enum; - -/* ============================================== CTIMER OUTCFG2 CFG22 [6..8] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG2_CFG22 */ - CTIMER_OUTCFG2_CFG22_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG2_CFG22_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG2_CFG22_A2OUT2 = 5, /*!< A2OUT2 : Output is A2OUT2. */ - CTIMER_OUTCFG2_CFG22_A1OUT = 4, /*!< A1OUT : Output is A1OUT. */ - CTIMER_OUTCFG2_CFG22_A6OUT = 3, /*!< A6OUT : Output is A6OUT. */ - CTIMER_OUTCFG2_CFG22_B5OUT = 2, /*!< B5OUT : Output is B5OUT */ - CTIMER_OUTCFG2_CFG22_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG2_CFG22_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG2_CFG22_Enum; - -/* ============================================== CTIMER OUTCFG2 CFG21 [3..5] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG2_CFG21 */ - CTIMER_OUTCFG2_CFG21_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG2_CFG21_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG2_CFG21_A0OUT2 = 5, /*!< A0OUT2 : Output is A0OUT2. */ - CTIMER_OUTCFG2_CFG21_B5OUT = 4, /*!< B5OUT : Output is B5OUT. */ - CTIMER_OUTCFG2_CFG21_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ - CTIMER_OUTCFG2_CFG21_A5OUT2 = 2, /*!< A5OUT2 : Output is A5OUT2 */ - CTIMER_OUTCFG2_CFG21_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG2_CFG21_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG2_CFG21_Enum; - -/* ============================================== CTIMER OUTCFG2 CFG20 [0..2] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG2_CFG20 */ - CTIMER_OUTCFG2_CFG20_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG2_CFG20_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG2_CFG20_B2OUT2 = 5, /*!< B2OUT2 : Output is B2OUT2. */ - CTIMER_OUTCFG2_CFG20_A1OUT2 = 4, /*!< A1OUT2 : Output is A1OUT2. */ - CTIMER_OUTCFG2_CFG20_A1OUT = 3, /*!< A1OUT : Output is A1OUT. */ - CTIMER_OUTCFG2_CFG20_A5OUT = 2, /*!< A5OUT : Output is A5OUT */ - CTIMER_OUTCFG2_CFG20_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG2_CFG20_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG2_CFG20_Enum; - -/* ======================================================== OUTCFG3 ======================================================== */ -/* ============================================== CTIMER OUTCFG3 CFG31 [3..5] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG3_CFG31 */ - CTIMER_OUTCFG3_CFG31_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG3_CFG31_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG3_CFG31_B3OUT2 = 5, /*!< B3OUT2 : Output is B3OUT2. */ - CTIMER_OUTCFG3_CFG31_B7OUT = 4, /*!< B7OUT : Output is B7OUT. */ - CTIMER_OUTCFG3_CFG31_A6OUT = 3, /*!< A6OUT : Output is A6OUT. */ - CTIMER_OUTCFG3_CFG31_B7OUT2 = 2, /*!< B7OUT2 : Output is B7OUT2 */ - CTIMER_OUTCFG3_CFG31_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG3_CFG31_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG3_CFG31_Enum; - -/* ============================================== CTIMER OUTCFG3 CFG30 [0..2] ============================================== */ -typedef enum { /*!< CTIMER_OUTCFG3_CFG30 */ - CTIMER_OUTCFG3_CFG30_A7OUT2 = 7, /*!< A7OUT2 : Output is A7OUT2. */ - CTIMER_OUTCFG3_CFG30_A6OUT2 = 6, /*!< A6OUT2 : Output is A6OUT2. */ - CTIMER_OUTCFG3_CFG30_A0OUT2 = 5, /*!< A0OUT2 : Output is A0OUT2. */ - CTIMER_OUTCFG3_CFG30_A4OUT2 = 4, /*!< A4OUT2 : Output is A4OUT2. */ - CTIMER_OUTCFG3_CFG30_B3OUT = 3, /*!< B3OUT : Output is B3OUT. */ - CTIMER_OUTCFG3_CFG30_B7OUT = 2, /*!< B7OUT : Output is B7OUT */ - CTIMER_OUTCFG3_CFG30_ONE = 1, /*!< ONE : Force output to 1. */ - CTIMER_OUTCFG3_CFG30_ZERO = 0, /*!< ZERO : Force output to 0 */ -} CTIMER_OUTCFG3_CFG30_Enum; - -/* ========================================================= INCFG ========================================================= */ -/* ============================================== CTIMER INCFG CFGB7 [15..15] ============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGB7 */ - CTIMER_INCFG_CFGB7_CT31 = 1, /*!< CT31 : Input is CT31 */ - CTIMER_INCFG_CFGB7_CT30 = 0, /*!< CT30 : Input is CT30 */ -} CTIMER_INCFG_CFGB7_Enum; - -/* ============================================== CTIMER INCFG CFGA7 [14..14] ============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGA7 */ - CTIMER_INCFG_CFGA7_CT29 = 1, /*!< CT29 : Input is CT29 */ - CTIMER_INCFG_CFGA7_CT28 = 0, /*!< CT28 : Input is CT28 */ -} CTIMER_INCFG_CFGA7_Enum; - -/* ============================================== CTIMER INCFG CFGB6 [13..13] ============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGB6 */ - CTIMER_INCFG_CFGB6_CT27 = 1, /*!< CT27 : Input is CT27 */ - CTIMER_INCFG_CFGB6_CT26 = 0, /*!< CT26 : Input is CT26 */ -} CTIMER_INCFG_CFGB6_Enum; - -/* ============================================== CTIMER INCFG CFGA6 [12..12] ============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGA6 */ - CTIMER_INCFG_CFGA6_CT25 = 1, /*!< CT25 : Input is CT25 */ - CTIMER_INCFG_CFGA6_CT24 = 0, /*!< CT24 : Input is CT24 */ -} CTIMER_INCFG_CFGA6_Enum; - -/* ============================================== CTIMER INCFG CFGB5 [11..11] ============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGB5 */ - CTIMER_INCFG_CFGB5_CT23 = 1, /*!< CT23 : Input is CT23 */ - CTIMER_INCFG_CFGB5_CT22 = 0, /*!< CT22 : Input is CT22 */ -} CTIMER_INCFG_CFGB5_Enum; - -/* ============================================== CTIMER INCFG CFGA5 [10..10] ============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGA5 */ - CTIMER_INCFG_CFGA5_CT21 = 1, /*!< CT21 : Input is CT21 */ - CTIMER_INCFG_CFGA5_CT20 = 0, /*!< CT20 : Input is CT20 */ -} CTIMER_INCFG_CFGA5_Enum; - -/* =============================================== CTIMER INCFG CFGB4 [9..9] =============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGB4 */ - CTIMER_INCFG_CFGB4_CT19 = 1, /*!< CT19 : Input is CT19 */ - CTIMER_INCFG_CFGB4_CT18 = 0, /*!< CT18 : Input is CT18 */ -} CTIMER_INCFG_CFGB4_Enum; - -/* =============================================== CTIMER INCFG CFGA4 [8..8] =============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGA4 */ - CTIMER_INCFG_CFGA4_CT17 = 1, /*!< CT17 : Input is CT17 */ - CTIMER_INCFG_CFGA4_CT16 = 0, /*!< CT16 : Input is CT16 */ -} CTIMER_INCFG_CFGA4_Enum; - -/* =============================================== CTIMER INCFG CFGB3 [7..7] =============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGB3 */ - CTIMER_INCFG_CFGB3_CT15 = 1, /*!< CT15 : Input is CT15 */ - CTIMER_INCFG_CFGB3_CT14 = 0, /*!< CT14 : Input is CT14 */ -} CTIMER_INCFG_CFGB3_Enum; - -/* =============================================== CTIMER INCFG CFGA3 [6..6] =============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGA3 */ - CTIMER_INCFG_CFGA3_CT13 = 1, /*!< CT13 : Input is CT13 */ - CTIMER_INCFG_CFGA3_CT12 = 0, /*!< CT12 : Input is CT12 */ -} CTIMER_INCFG_CFGA3_Enum; - -/* =============================================== CTIMER INCFG CFGB2 [5..5] =============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGB2 */ - CTIMER_INCFG_CFGB2_CT11 = 1, /*!< CT11 : Input is CT11 */ - CTIMER_INCFG_CFGB2_CT10 = 0, /*!< CT10 : Input is CT10 */ -} CTIMER_INCFG_CFGB2_Enum; - -/* =============================================== CTIMER INCFG CFGA2 [4..4] =============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGA2 */ - CTIMER_INCFG_CFGA2_CT9 = 1, /*!< CT9 : Input is CT9 */ - CTIMER_INCFG_CFGA2_CT8 = 0, /*!< CT8 : Input is CT8 */ -} CTIMER_INCFG_CFGA2_Enum; - -/* =============================================== CTIMER INCFG CFGB1 [3..3] =============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGB1 */ - CTIMER_INCFG_CFGB1_CT7 = 1, /*!< CT7 : Input is CT7 */ - CTIMER_INCFG_CFGB1_CT6 = 0, /*!< CT6 : Input is CT6 */ -} CTIMER_INCFG_CFGB1_Enum; - -/* =============================================== CTIMER INCFG CFGA1 [2..2] =============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGA1 */ - CTIMER_INCFG_CFGA1_CT5 = 1, /*!< CT5 : Input is CT5 */ - CTIMER_INCFG_CFGA1_CT4 = 0, /*!< CT4 : Input is CT4 */ -} CTIMER_INCFG_CFGA1_Enum; - -/* =============================================== CTIMER INCFG CFGB0 [1..1] =============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGB0 */ - CTIMER_INCFG_CFGB0_CT3 = 1, /*!< CT3 : Input is CT3 */ - CTIMER_INCFG_CFGB0_CT2 = 0, /*!< CT2 : Input is CT2 */ -} CTIMER_INCFG_CFGB0_Enum; - -/* =============================================== CTIMER INCFG CFGA0 [0..0] =============================================== */ -typedef enum { /*!< CTIMER_INCFG_CFGA0 */ - CTIMER_INCFG_CFGA0_CT1 = 1, /*!< CT1 : Input is CT1 */ - CTIMER_INCFG_CFGA0_CT0 = 0, /*!< CT0 : Input is CT0 */ -} CTIMER_INCFG_CFGA0_Enum; - -/* ========================================================= STCFG ========================================================= */ -/* ============================================= CTIMER STCFG FREEZE [31..31] ============================================== */ -typedef enum { /*!< CTIMER_STCFG_FREEZE */ - CTIMER_STCFG_FREEZE_THAW = 0, /*!< THAW : Let the COUNTER register run on its input clock. */ - CTIMER_STCFG_FREEZE_FREEZE = 1, /*!< FREEZE : Stop the COUNTER register for loading. */ -} CTIMER_STCFG_FREEZE_Enum; - -/* ============================================== CTIMER STCFG CLEAR [30..30] ============================================== */ -typedef enum { /*!< CTIMER_STCFG_CLEAR */ - CTIMER_STCFG_CLEAR_RUN = 0, /*!< RUN : Let the COUNTER register run on its input clock. */ - CTIMER_STCFG_CLEAR_CLEAR = 1, /*!< CLEAR : Stop the COUNTER register for loading. */ -} CTIMER_STCFG_CLEAR_Enum; - -/* ========================================== CTIMER STCFG COMPARE_H_EN [15..15] =========================================== */ -typedef enum { /*!< CTIMER_STCFG_COMPARE_H_EN */ - CTIMER_STCFG_COMPARE_H_EN_DISABLE = 0, /*!< DISABLE : Compare H disabled. */ - CTIMER_STCFG_COMPARE_H_EN_ENABLE = 1, /*!< ENABLE : Compare H enabled. */ -} CTIMER_STCFG_COMPARE_H_EN_Enum; - -/* ========================================== CTIMER STCFG COMPARE_G_EN [14..14] =========================================== */ -typedef enum { /*!< CTIMER_STCFG_COMPARE_G_EN */ - CTIMER_STCFG_COMPARE_G_EN_DISABLE = 0, /*!< DISABLE : Compare G disabled. */ - CTIMER_STCFG_COMPARE_G_EN_ENABLE = 1, /*!< ENABLE : Compare G enabled. */ -} CTIMER_STCFG_COMPARE_G_EN_Enum; - -/* ========================================== CTIMER STCFG COMPARE_F_EN [13..13] =========================================== */ -typedef enum { /*!< CTIMER_STCFG_COMPARE_F_EN */ - CTIMER_STCFG_COMPARE_F_EN_DISABLE = 0, /*!< DISABLE : Compare F disabled. */ - CTIMER_STCFG_COMPARE_F_EN_ENABLE = 1, /*!< ENABLE : Compare F enabled. */ -} CTIMER_STCFG_COMPARE_F_EN_Enum; - -/* ========================================== CTIMER STCFG COMPARE_E_EN [12..12] =========================================== */ -typedef enum { /*!< CTIMER_STCFG_COMPARE_E_EN */ - CTIMER_STCFG_COMPARE_E_EN_DISABLE = 0, /*!< DISABLE : Compare E disabled. */ - CTIMER_STCFG_COMPARE_E_EN_ENABLE = 1, /*!< ENABLE : Compare E enabled. */ -} CTIMER_STCFG_COMPARE_E_EN_Enum; - -/* ========================================== CTIMER STCFG COMPARE_D_EN [11..11] =========================================== */ -typedef enum { /*!< CTIMER_STCFG_COMPARE_D_EN */ - CTIMER_STCFG_COMPARE_D_EN_DISABLE = 0, /*!< DISABLE : Compare D disabled. */ - CTIMER_STCFG_COMPARE_D_EN_ENABLE = 1, /*!< ENABLE : Compare D enabled. */ -} CTIMER_STCFG_COMPARE_D_EN_Enum; - -/* ========================================== CTIMER STCFG COMPARE_C_EN [10..10] =========================================== */ -typedef enum { /*!< CTIMER_STCFG_COMPARE_C_EN */ - CTIMER_STCFG_COMPARE_C_EN_DISABLE = 0, /*!< DISABLE : Compare C disabled. */ - CTIMER_STCFG_COMPARE_C_EN_ENABLE = 1, /*!< ENABLE : Compare C enabled. */ -} CTIMER_STCFG_COMPARE_C_EN_Enum; - -/* =========================================== CTIMER STCFG COMPARE_B_EN [9..9] ============================================ */ -typedef enum { /*!< CTIMER_STCFG_COMPARE_B_EN */ - CTIMER_STCFG_COMPARE_B_EN_DISABLE = 0, /*!< DISABLE : Compare B disabled. */ - CTIMER_STCFG_COMPARE_B_EN_ENABLE = 1, /*!< ENABLE : Compare B enabled. */ -} CTIMER_STCFG_COMPARE_B_EN_Enum; - -/* =========================================== CTIMER STCFG COMPARE_A_EN [8..8] ============================================ */ -typedef enum { /*!< CTIMER_STCFG_COMPARE_A_EN */ - CTIMER_STCFG_COMPARE_A_EN_DISABLE = 0, /*!< DISABLE : Compare A disabled. */ - CTIMER_STCFG_COMPARE_A_EN_ENABLE = 1, /*!< ENABLE : Compare A enabled. */ -} CTIMER_STCFG_COMPARE_A_EN_Enum; - -/* ============================================== CTIMER STCFG CLKSEL [0..3] =============================================== */ -typedef enum { /*!< CTIMER_STCFG_CLKSEL */ - CTIMER_STCFG_CLKSEL_NOCLK = 0, /*!< NOCLK : No clock enabled. */ - CTIMER_STCFG_CLKSEL_HFRC_DIV16 = 1, /*!< HFRC_DIV16 : 3MHz from the HFRC clock divider. */ - CTIMER_STCFG_CLKSEL_HFRC_DIV256 = 2, /*!< HFRC_DIV256 : 187.5KHz from the HFRC clock divider. */ - CTIMER_STCFG_CLKSEL_XTAL_DIV1 = 3, /*!< XTAL_DIV1 : 32768Hz from the crystal oscillator. */ - CTIMER_STCFG_CLKSEL_XTAL_DIV2 = 4, /*!< XTAL_DIV2 : 16384Hz from the crystal oscillator. */ - CTIMER_STCFG_CLKSEL_XTAL_DIV32 = 5, /*!< XTAL_DIV32 : 1024Hz from the crystal oscillator. */ - CTIMER_STCFG_CLKSEL_LFRC_DIV1 = 6, /*!< LFRC_DIV1 : Approximately 1KHz from the LFRC oscillator (uncalibrated). */ - CTIMER_STCFG_CLKSEL_CTIMER0A = 7, /*!< CTIMER0A : Use CTIMER 0 section A as a prescaler for the clock - source. */ - CTIMER_STCFG_CLKSEL_CTIMER0B = 8, /*!< CTIMER0B : Use CTIMER 0 section B (or A and B linked together) - as a prescaler for the clock source. */ -} CTIMER_STCFG_CLKSEL_Enum; - -/* ========================================================= STTMR ========================================================= */ -/* ==================================================== CAPTURECONTROL ===================================================== */ -/* ========================================= CTIMER CAPTURECONTROL CAPTURE3 [3..3] ========================================= */ -typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE3 */ - CTIMER_CAPTURECONTROL_CAPTURE3_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ - CTIMER_CAPTURECONTROL_CAPTURE3_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ -} CTIMER_CAPTURECONTROL_CAPTURE3_Enum; - -/* ========================================= CTIMER CAPTURECONTROL CAPTURE2 [2..2] ========================================= */ -typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE2 */ - CTIMER_CAPTURECONTROL_CAPTURE2_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ - CTIMER_CAPTURECONTROL_CAPTURE2_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ -} CTIMER_CAPTURECONTROL_CAPTURE2_Enum; - -/* ========================================= CTIMER CAPTURECONTROL CAPTURE1 [1..1] ========================================= */ -typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE1 */ - CTIMER_CAPTURECONTROL_CAPTURE1_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ - CTIMER_CAPTURECONTROL_CAPTURE1_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ -} CTIMER_CAPTURECONTROL_CAPTURE1_Enum; - -/* ========================================= CTIMER CAPTURECONTROL CAPTURE0 [0..0] ========================================= */ -typedef enum { /*!< CTIMER_CAPTURECONTROL_CAPTURE0 */ - CTIMER_CAPTURECONTROL_CAPTURE0_DISABLE = 0, /*!< DISABLE : Capture function disabled. */ - CTIMER_CAPTURECONTROL_CAPTURE0_ENABLE = 1, /*!< ENABLE : Capture function enabled. */ -} CTIMER_CAPTURECONTROL_CAPTURE0_Enum; - -/* ======================================================== SCMPR0 ========================================================= */ -/* ======================================================== SCMPR1 ========================================================= */ -/* ======================================================== SCMPR2 ========================================================= */ -/* ======================================================== SCMPR3 ========================================================= */ -/* ======================================================== SCMPR4 ========================================================= */ -/* ======================================================== SCMPR5 ========================================================= */ -/* ======================================================== SCMPR6 ========================================================= */ -/* ======================================================== SCMPR7 ========================================================= */ -/* ======================================================== SCAPT0 ========================================================= */ -/* ======================================================== SCAPT1 ========================================================= */ -/* ======================================================== SCAPT2 ========================================================= */ -/* ======================================================== SCAPT3 ========================================================= */ -/* ========================================================= SNVR0 ========================================================= */ -/* ========================================================= SNVR1 ========================================================= */ -/* ========================================================= SNVR2 ========================================================= */ -/* ========================================================= SNVR3 ========================================================= */ -/* ========================================================= INTEN ========================================================= */ -/* ======================================================== INTSTAT ======================================================== */ -/* ======================================================== INTCLR ========================================================= */ -/* ======================================================== INTSET ========================================================= */ -/* ======================================================= STMINTEN ======================================================== */ -/* =========================================== CTIMER STMINTEN CAPTURED [12..12] =========================================== */ -typedef enum { /*!< CTIMER_STMINTEN_CAPTURED */ - CTIMER_STMINTEN_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ -} CTIMER_STMINTEN_CAPTURED_Enum; - -/* =========================================== CTIMER STMINTEN CAPTUREC [11..11] =========================================== */ -typedef enum { /*!< CTIMER_STMINTEN_CAPTUREC */ - CTIMER_STMINTEN_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ -} CTIMER_STMINTEN_CAPTUREC_Enum; - -/* =========================================== CTIMER STMINTEN CAPTUREB [10..10] =========================================== */ -typedef enum { /*!< CTIMER_STMINTEN_CAPTUREB */ - CTIMER_STMINTEN_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ -} CTIMER_STMINTEN_CAPTUREB_Enum; - -/* ============================================ CTIMER STMINTEN CAPTUREA [9..9] ============================================ */ -typedef enum { /*!< CTIMER_STMINTEN_CAPTUREA */ - CTIMER_STMINTEN_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ -} CTIMER_STMINTEN_CAPTUREA_Enum; - -/* ============================================ CTIMER STMINTEN OVERFLOW [8..8] ============================================ */ -typedef enum { /*!< CTIMER_STMINTEN_OVERFLOW */ - CTIMER_STMINTEN_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ -} CTIMER_STMINTEN_OVERFLOW_Enum; - -/* ============================================ CTIMER STMINTEN COMPAREH [7..7] ============================================ */ -typedef enum { /*!< CTIMER_STMINTEN_COMPAREH */ - CTIMER_STMINTEN_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTEN_COMPAREH_Enum; - -/* ============================================ CTIMER STMINTEN COMPAREG [6..6] ============================================ */ -typedef enum { /*!< CTIMER_STMINTEN_COMPAREG */ - CTIMER_STMINTEN_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTEN_COMPAREG_Enum; - -/* ============================================ CTIMER STMINTEN COMPAREF [5..5] ============================================ */ -typedef enum { /*!< CTIMER_STMINTEN_COMPAREF */ - CTIMER_STMINTEN_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTEN_COMPAREF_Enum; - -/* ============================================ CTIMER STMINTEN COMPAREE [4..4] ============================================ */ -typedef enum { /*!< CTIMER_STMINTEN_COMPAREE */ - CTIMER_STMINTEN_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTEN_COMPAREE_Enum; - -/* ============================================ CTIMER STMINTEN COMPARED [3..3] ============================================ */ -typedef enum { /*!< CTIMER_STMINTEN_COMPARED */ - CTIMER_STMINTEN_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTEN_COMPARED_Enum; - -/* ============================================ CTIMER STMINTEN COMPAREC [2..2] ============================================ */ -typedef enum { /*!< CTIMER_STMINTEN_COMPAREC */ - CTIMER_STMINTEN_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTEN_COMPAREC_Enum; - -/* ============================================ CTIMER STMINTEN COMPAREB [1..1] ============================================ */ -typedef enum { /*!< CTIMER_STMINTEN_COMPAREB */ - CTIMER_STMINTEN_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTEN_COMPAREB_Enum; - -/* ============================================ CTIMER STMINTEN COMPAREA [0..0] ============================================ */ -typedef enum { /*!< CTIMER_STMINTEN_COMPAREA */ - CTIMER_STMINTEN_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTEN_COMPAREA_Enum; - -/* ====================================================== STMINTSTAT ======================================================= */ -/* ========================================== CTIMER STMINTSTAT CAPTURED [12..12] ========================================== */ -typedef enum { /*!< CTIMER_STMINTSTAT_CAPTURED */ - CTIMER_STMINTSTAT_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ -} CTIMER_STMINTSTAT_CAPTURED_Enum; - -/* ========================================== CTIMER STMINTSTAT CAPTUREC [11..11] ========================================== */ -typedef enum { /*!< CTIMER_STMINTSTAT_CAPTUREC */ - CTIMER_STMINTSTAT_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ -} CTIMER_STMINTSTAT_CAPTUREC_Enum; - -/* ========================================== CTIMER STMINTSTAT CAPTUREB [10..10] ========================================== */ -typedef enum { /*!< CTIMER_STMINTSTAT_CAPTUREB */ - CTIMER_STMINTSTAT_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ -} CTIMER_STMINTSTAT_CAPTUREB_Enum; - -/* =========================================== CTIMER STMINTSTAT CAPTUREA [9..9] =========================================== */ -typedef enum { /*!< CTIMER_STMINTSTAT_CAPTUREA */ - CTIMER_STMINTSTAT_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ -} CTIMER_STMINTSTAT_CAPTUREA_Enum; - -/* =========================================== CTIMER STMINTSTAT OVERFLOW [8..8] =========================================== */ -typedef enum { /*!< CTIMER_STMINTSTAT_OVERFLOW */ - CTIMER_STMINTSTAT_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ -} CTIMER_STMINTSTAT_OVERFLOW_Enum; - -/* =========================================== CTIMER STMINTSTAT COMPAREH [7..7] =========================================== */ -typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREH */ - CTIMER_STMINTSTAT_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSTAT_COMPAREH_Enum; - -/* =========================================== CTIMER STMINTSTAT COMPAREG [6..6] =========================================== */ -typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREG */ - CTIMER_STMINTSTAT_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSTAT_COMPAREG_Enum; - -/* =========================================== CTIMER STMINTSTAT COMPAREF [5..5] =========================================== */ -typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREF */ - CTIMER_STMINTSTAT_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSTAT_COMPAREF_Enum; - -/* =========================================== CTIMER STMINTSTAT COMPAREE [4..4] =========================================== */ -typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREE */ - CTIMER_STMINTSTAT_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSTAT_COMPAREE_Enum; - -/* =========================================== CTIMER STMINTSTAT COMPARED [3..3] =========================================== */ -typedef enum { /*!< CTIMER_STMINTSTAT_COMPARED */ - CTIMER_STMINTSTAT_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSTAT_COMPARED_Enum; - -/* =========================================== CTIMER STMINTSTAT COMPAREC [2..2] =========================================== */ -typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREC */ - CTIMER_STMINTSTAT_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSTAT_COMPAREC_Enum; - -/* =========================================== CTIMER STMINTSTAT COMPAREB [1..1] =========================================== */ -typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREB */ - CTIMER_STMINTSTAT_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSTAT_COMPAREB_Enum; - -/* =========================================== CTIMER STMINTSTAT COMPAREA [0..0] =========================================== */ -typedef enum { /*!< CTIMER_STMINTSTAT_COMPAREA */ - CTIMER_STMINTSTAT_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSTAT_COMPAREA_Enum; - -/* ======================================================= STMINTCLR ======================================================= */ -/* ========================================== CTIMER STMINTCLR CAPTURED [12..12] =========================================== */ -typedef enum { /*!< CTIMER_STMINTCLR_CAPTURED */ - CTIMER_STMINTCLR_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ -} CTIMER_STMINTCLR_CAPTURED_Enum; - -/* ========================================== CTIMER STMINTCLR CAPTUREC [11..11] =========================================== */ -typedef enum { /*!< CTIMER_STMINTCLR_CAPTUREC */ - CTIMER_STMINTCLR_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ -} CTIMER_STMINTCLR_CAPTUREC_Enum; - -/* ========================================== CTIMER STMINTCLR CAPTUREB [10..10] =========================================== */ -typedef enum { /*!< CTIMER_STMINTCLR_CAPTUREB */ - CTIMER_STMINTCLR_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ -} CTIMER_STMINTCLR_CAPTUREB_Enum; - -/* =========================================== CTIMER STMINTCLR CAPTUREA [9..9] ============================================ */ -typedef enum { /*!< CTIMER_STMINTCLR_CAPTUREA */ - CTIMER_STMINTCLR_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ -} CTIMER_STMINTCLR_CAPTUREA_Enum; - -/* =========================================== CTIMER STMINTCLR OVERFLOW [8..8] ============================================ */ -typedef enum { /*!< CTIMER_STMINTCLR_OVERFLOW */ - CTIMER_STMINTCLR_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ -} CTIMER_STMINTCLR_OVERFLOW_Enum; - -/* =========================================== CTIMER STMINTCLR COMPAREH [7..7] ============================================ */ -typedef enum { /*!< CTIMER_STMINTCLR_COMPAREH */ - CTIMER_STMINTCLR_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTCLR_COMPAREH_Enum; - -/* =========================================== CTIMER STMINTCLR COMPAREG [6..6] ============================================ */ -typedef enum { /*!< CTIMER_STMINTCLR_COMPAREG */ - CTIMER_STMINTCLR_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTCLR_COMPAREG_Enum; - -/* =========================================== CTIMER STMINTCLR COMPAREF [5..5] ============================================ */ -typedef enum { /*!< CTIMER_STMINTCLR_COMPAREF */ - CTIMER_STMINTCLR_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTCLR_COMPAREF_Enum; - -/* =========================================== CTIMER STMINTCLR COMPAREE [4..4] ============================================ */ -typedef enum { /*!< CTIMER_STMINTCLR_COMPAREE */ - CTIMER_STMINTCLR_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTCLR_COMPAREE_Enum; - -/* =========================================== CTIMER STMINTCLR COMPARED [3..3] ============================================ */ -typedef enum { /*!< CTIMER_STMINTCLR_COMPARED */ - CTIMER_STMINTCLR_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTCLR_COMPARED_Enum; - -/* =========================================== CTIMER STMINTCLR COMPAREC [2..2] ============================================ */ -typedef enum { /*!< CTIMER_STMINTCLR_COMPAREC */ - CTIMER_STMINTCLR_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTCLR_COMPAREC_Enum; - -/* =========================================== CTIMER STMINTCLR COMPAREB [1..1] ============================================ */ -typedef enum { /*!< CTIMER_STMINTCLR_COMPAREB */ - CTIMER_STMINTCLR_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTCLR_COMPAREB_Enum; - -/* =========================================== CTIMER STMINTCLR COMPAREA [0..0] ============================================ */ -typedef enum { /*!< CTIMER_STMINTCLR_COMPAREA */ - CTIMER_STMINTCLR_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTCLR_COMPAREA_Enum; - -/* ======================================================= STMINTSET ======================================================= */ -/* ========================================== CTIMER STMINTSET CAPTURED [12..12] =========================================== */ -typedef enum { /*!< CTIMER_STMINTSET_CAPTURED */ - CTIMER_STMINTSET_CAPTURED_CAPD_INT = 1, /*!< CAPD_INT : Capture D interrupt status bit was set. */ -} CTIMER_STMINTSET_CAPTURED_Enum; - -/* ========================================== CTIMER STMINTSET CAPTUREC [11..11] =========================================== */ -typedef enum { /*!< CTIMER_STMINTSET_CAPTUREC */ - CTIMER_STMINTSET_CAPTUREC_CAPC_INT = 1, /*!< CAPC_INT : CAPTURE C interrupt status bit was set. */ -} CTIMER_STMINTSET_CAPTUREC_Enum; - -/* ========================================== CTIMER STMINTSET CAPTUREB [10..10] =========================================== */ -typedef enum { /*!< CTIMER_STMINTSET_CAPTUREB */ - CTIMER_STMINTSET_CAPTUREB_CAPB_INT = 1, /*!< CAPB_INT : CAPTURE B interrupt status bit was set. */ -} CTIMER_STMINTSET_CAPTUREB_Enum; - -/* =========================================== CTIMER STMINTSET CAPTUREA [9..9] ============================================ */ -typedef enum { /*!< CTIMER_STMINTSET_CAPTUREA */ - CTIMER_STMINTSET_CAPTUREA_CAPA_INT = 1, /*!< CAPA_INT : CAPTURE A interrupt status bit was set. */ -} CTIMER_STMINTSET_CAPTUREA_Enum; - -/* =========================================== CTIMER STMINTSET OVERFLOW [8..8] ============================================ */ -typedef enum { /*!< CTIMER_STMINTSET_OVERFLOW */ - CTIMER_STMINTSET_OVERFLOW_OFLOW_INT = 1, /*!< OFLOW_INT : Overflow interrupt status bit was set. */ -} CTIMER_STMINTSET_OVERFLOW_Enum; - -/* =========================================== CTIMER STMINTSET COMPAREH [7..7] ============================================ */ -typedef enum { /*!< CTIMER_STMINTSET_COMPAREH */ - CTIMER_STMINTSET_COMPAREH_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSET_COMPAREH_Enum; - -/* =========================================== CTIMER STMINTSET COMPAREG [6..6] ============================================ */ -typedef enum { /*!< CTIMER_STMINTSET_COMPAREG */ - CTIMER_STMINTSET_COMPAREG_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSET_COMPAREG_Enum; - -/* =========================================== CTIMER STMINTSET COMPAREF [5..5] ============================================ */ -typedef enum { /*!< CTIMER_STMINTSET_COMPAREF */ - CTIMER_STMINTSET_COMPAREF_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSET_COMPAREF_Enum; - -/* =========================================== CTIMER STMINTSET COMPAREE [4..4] ============================================ */ -typedef enum { /*!< CTIMER_STMINTSET_COMPAREE */ - CTIMER_STMINTSET_COMPAREE_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSET_COMPAREE_Enum; - -/* =========================================== CTIMER STMINTSET COMPARED [3..3] ============================================ */ -typedef enum { /*!< CTIMER_STMINTSET_COMPARED */ - CTIMER_STMINTSET_COMPARED_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSET_COMPARED_Enum; - -/* =========================================== CTIMER STMINTSET COMPAREC [2..2] ============================================ */ -typedef enum { /*!< CTIMER_STMINTSET_COMPAREC */ - CTIMER_STMINTSET_COMPAREC_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSET_COMPAREC_Enum; - -/* =========================================== CTIMER STMINTSET COMPAREB [1..1] ============================================ */ -typedef enum { /*!< CTIMER_STMINTSET_COMPAREB */ - CTIMER_STMINTSET_COMPAREB_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSET_COMPAREB_Enum; - -/* =========================================== CTIMER STMINTSET COMPAREA [0..0] ============================================ */ -typedef enum { /*!< CTIMER_STMINTSET_COMPAREA */ - CTIMER_STMINTSET_COMPAREA_COMPARED = 1, /*!< COMPARED : COUNTER greater than or equal to COMPARE register. */ -} CTIMER_STMINTSET_COMPAREA_Enum; - - - -/* =========================================================================================================================== */ -/* ================ GPIO ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== PADREGA ======================================================== */ -/* ============================================ GPIO PADREGA PAD3PWRUP [30..30] ============================================ */ -typedef enum { /*!< GPIO_PADREGA_PAD3PWRUP */ - GPIO_PADREGA_PAD3PWRUP_DIS = 0, /*!< DIS : Power switch disabled */ - GPIO_PADREGA_PAD3PWRUP_EN = 1, /*!< EN : Power switch enabled (switched to VDD) */ -} GPIO_PADREGA_PAD3PWRUP_Enum; - -/* =========================================== GPIO PADREGA PAD3FNCSEL [27..29] ============================================ */ -typedef enum { /*!< GPIO_PADREGA_PAD3FNCSEL */ - GPIO_PADREGA_PAD3FNCSEL_UA0RTS = 0, /*!< UA0RTS : Configure as the UART0 RTS output */ - GPIO_PADREGA_PAD3FNCSEL_SLnCE = 1, /*!< SLnCE : Configure as the IOSLAVE SPI nCE signal */ - GPIO_PADREGA_PAD3FNCSEL_NCE3 = 2, /*!< NCE3 : IOM/MSPI nCE group 3 */ - GPIO_PADREGA_PAD3FNCSEL_GPIO3 = 3, /*!< GPIO3 : Configure as GPIO3 */ - GPIO_PADREGA_PAD3FNCSEL_MSPI7 = 5, /*!< MSPI7 : MSPI data connection 7 */ - GPIO_PADREGA_PAD3FNCSEL_TRIG1 = 6, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */ - GPIO_PADREGA_PAD3FNCSEL_I2S_WCLK = 7, /*!< I2S_WCLK : Configure as the PDM I2S Word Clock input */ -} GPIO_PADREGA_PAD3FNCSEL_Enum; - -/* ============================================ GPIO PADREGA PAD3STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGA_PAD3STRNG */ - GPIO_PADREGA_PAD3STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGA_PAD3STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGA_PAD3STRNG_Enum; - -/* ============================================ GPIO PADREGA PAD3INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGA_PAD3INPEN */ - GPIO_PADREGA_PAD3INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGA_PAD3INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGA_PAD3INPEN_Enum; - -/* ============================================ GPIO PADREGA PAD3PULL [24..24] ============================================= */ -typedef enum { /*!< GPIO_PADREGA_PAD3PULL */ - GPIO_PADREGA_PAD3PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGA_PAD3PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGA_PAD3PULL_Enum; - -/* =========================================== GPIO PADREGA PAD2FNCSEL [19..21] ============================================ */ -typedef enum { /*!< GPIO_PADREGA_PAD2FNCSEL */ - GPIO_PADREGA_PAD2FNCSEL_UART1RX = 0, /*!< UART1RX : Configure as the UART1 RX input. */ - GPIO_PADREGA_PAD2FNCSEL_SLMISO = 1, /*!< SLMISO : Configure as the IOSLAVE SPI MISO signal. */ - GPIO_PADREGA_PAD2FNCSEL_UART0RX = 2, /*!< UART0RX : Configure as the UART0 RX input. */ - GPIO_PADREGA_PAD2FNCSEL_GPIO2 = 3, /*!< GPIO2 : Configure as GPIO2. */ - GPIO_PADREGA_PAD2FNCSEL_MSPI6 = 5, /*!< MSPI6 : MSPI data connection 6. */ - GPIO_PADREGA_PAD2FNCSEL_NCE2 = 7, /*!< NCE2 : IOM/MSPI nCE group 2 */ -} GPIO_PADREGA_PAD2FNCSEL_Enum; - -/* ============================================ GPIO PADREGA PAD2STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGA_PAD2STRNG */ - GPIO_PADREGA_PAD2STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGA_PAD2STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGA_PAD2STRNG_Enum; - -/* ============================================ GPIO PADREGA PAD2INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGA_PAD2INPEN */ - GPIO_PADREGA_PAD2INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGA_PAD2INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGA_PAD2INPEN_Enum; - -/* ============================================ GPIO PADREGA PAD2PULL [16..16] ============================================= */ -typedef enum { /*!< GPIO_PADREGA_PAD2PULL */ - GPIO_PADREGA_PAD2PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGA_PAD2PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGA_PAD2PULL_Enum; - -/* ============================================ GPIO PADREGA PAD1RSEL [14..15] ============================================= */ -typedef enum { /*!< GPIO_PADREGA_PAD1RSEL */ - GPIO_PADREGA_PAD1RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ - GPIO_PADREGA_PAD1RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ - GPIO_PADREGA_PAD1RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ - GPIO_PADREGA_PAD1RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ -} GPIO_PADREGA_PAD1RSEL_Enum; - -/* =========================================== GPIO PADREGA PAD1FNCSEL [11..13] ============================================ */ -typedef enum { /*!< GPIO_PADREGA_PAD1FNCSEL */ - GPIO_PADREGA_PAD1FNCSEL_SLSDAWIR3 = 0, /*!< SLSDAWIR3 : Configure as the IOSLAVE I2C SDA or SPI WIR3 signal */ - GPIO_PADREGA_PAD1FNCSEL_SLMOSI = 1, /*!< SLMOSI : Configure as the IOSLAVE SPI MOSI signal */ - GPIO_PADREGA_PAD1FNCSEL_UART0TX = 2, /*!< UART0TX : Configure as the UART0 TX output signal */ - GPIO_PADREGA_PAD1FNCSEL_GPIO1 = 3, /*!< GPIO1 : Configure as GPIO1 */ - GPIO_PADREGA_PAD1FNCSEL_MSPI5 = 5, /*!< MSPI5 : MSPI data connection 5 */ - GPIO_PADREGA_PAD1FNCSEL_NCE1 = 7, /*!< NCE1 : IOM/MSPI nCE group 1 */ -} GPIO_PADREGA_PAD1FNCSEL_Enum; - -/* ============================================ GPIO PADREGA PAD1STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGA_PAD1STRNG */ - GPIO_PADREGA_PAD1STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGA_PAD1STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGA_PAD1STRNG_Enum; - -/* ============================================= GPIO PADREGA PAD1INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGA_PAD1INPEN */ - GPIO_PADREGA_PAD1INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGA_PAD1INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGA_PAD1INPEN_Enum; - -/* ============================================= GPIO PADREGA PAD1PULL [8..8] ============================================== */ -typedef enum { /*!< GPIO_PADREGA_PAD1PULL */ - GPIO_PADREGA_PAD1PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGA_PAD1PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGA_PAD1PULL_Enum; - -/* ============================================= GPIO PADREGA PAD0RSEL [6..7] ============================================== */ -typedef enum { /*!< GPIO_PADREGA_PAD0RSEL */ - GPIO_PADREGA_PAD0RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ - GPIO_PADREGA_PAD0RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ - GPIO_PADREGA_PAD0RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ - GPIO_PADREGA_PAD0RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ -} GPIO_PADREGA_PAD0RSEL_Enum; - -/* ============================================ GPIO PADREGA PAD0FNCSEL [3..5] ============================================= */ -typedef enum { /*!< GPIO_PADREGA_PAD0FNCSEL */ - GPIO_PADREGA_PAD0FNCSEL_SLSCL = 0, /*!< SLSCL : Configure as the IOSLAVE I2C SCL signal */ - GPIO_PADREGA_PAD0FNCSEL_SLSCK = 1, /*!< SLSCK : Configure as the IOSLAVE SPI SCK signal */ - GPIO_PADREGA_PAD0FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */ - GPIO_PADREGA_PAD0FNCSEL_GPIO0 = 3, /*!< GPIO0 : Configure as GPIO0 */ - GPIO_PADREGA_PAD0FNCSEL_MSPI4 = 5, /*!< MSPI4 : MSPI data connection 4 */ - GPIO_PADREGA_PAD0FNCSEL_NCE0 = 7, /*!< NCE0 : IOM/MSPI nCE group 0 */ -} GPIO_PADREGA_PAD0FNCSEL_Enum; - -/* ============================================= GPIO PADREGA PAD0STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGA_PAD0STRNG */ - GPIO_PADREGA_PAD0STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGA_PAD0STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGA_PAD0STRNG_Enum; - -/* ============================================= GPIO PADREGA PAD0INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGA_PAD0INPEN */ - GPIO_PADREGA_PAD0INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGA_PAD0INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGA_PAD0INPEN_Enum; - -/* ============================================= GPIO PADREGA PAD0PULL [0..0] ============================================== */ -typedef enum { /*!< GPIO_PADREGA_PAD0PULL */ - GPIO_PADREGA_PAD0PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGA_PAD0PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGA_PAD0PULL_Enum; - -/* ======================================================== PADREGB ======================================================== */ -/* =========================================== GPIO PADREGB PAD7FNCSEL [27..29] ============================================ */ -typedef enum { /*!< GPIO_PADREGB_PAD7FNCSEL */ - GPIO_PADREGB_PAD7FNCSEL_NCE7 = 0, /*!< NCE7 : IOM/MSPI nCE group 7 */ - GPIO_PADREGB_PAD7FNCSEL_M0MOSI = 1, /*!< M0MOSI : Configure as the IOMSTR0 SPI MOSI signal */ - GPIO_PADREGB_PAD7FNCSEL_CLKOUT = 2, /*!< CLKOUT : Configure as the CLKOUT signal */ - GPIO_PADREGB_PAD7FNCSEL_GPIO7 = 3, /*!< GPIO7 : Configure as GPIO7 */ - GPIO_PADREGB_PAD7FNCSEL_TRIG0 = 4, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */ - GPIO_PADREGB_PAD7FNCSEL_UART0TX = 5, /*!< UART0TX : Configure as the UART0 TX output signal */ - GPIO_PADREGB_PAD7FNCSEL_CT19 = 7, /*!< CT19 : CTIMER connection 19 */ -} GPIO_PADREGB_PAD7FNCSEL_Enum; - -/* ============================================ GPIO PADREGB PAD7STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGB_PAD7STRNG */ - GPIO_PADREGB_PAD7STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGB_PAD7STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGB_PAD7STRNG_Enum; - -/* ============================================ GPIO PADREGB PAD7INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGB_PAD7INPEN */ - GPIO_PADREGB_PAD7INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGB_PAD7INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGB_PAD7INPEN_Enum; - -/* ============================================ GPIO PADREGB PAD7PULL [24..24] ============================================= */ -typedef enum { /*!< GPIO_PADREGB_PAD7PULL */ - GPIO_PADREGB_PAD7PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGB_PAD7PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGB_PAD7PULL_Enum; - -/* ============================================ GPIO PADREGB PAD6RSEL [22..23] ============================================= */ -typedef enum { /*!< GPIO_PADREGB_PAD6RSEL */ - GPIO_PADREGB_PAD6RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ - GPIO_PADREGB_PAD6RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ - GPIO_PADREGB_PAD6RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ - GPIO_PADREGB_PAD6RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ -} GPIO_PADREGB_PAD6RSEL_Enum; - -/* =========================================== GPIO PADREGB PAD6FNCSEL [19..21] ============================================ */ -typedef enum { /*!< GPIO_PADREGB_PAD6FNCSEL */ - GPIO_PADREGB_PAD6FNCSEL_M0SDAWIR3 = 0, /*!< M0SDAWIR3 : Configure as the IOMSTR0 I2C SDA or SPI WIR3 signal */ - GPIO_PADREGB_PAD6FNCSEL_M0MISO = 1, /*!< M0MISO : Configure as the IOMSTR0 SPI MISO signal */ - GPIO_PADREGB_PAD6FNCSEL_UA0CTS = 2, /*!< UA0CTS : Configure as the UART0 CTS input signal */ - GPIO_PADREGB_PAD6FNCSEL_GPIO6 = 3, /*!< GPIO6 : Configure as GPIO6 */ - GPIO_PADREGB_PAD6FNCSEL_CT10 = 5, /*!< CT10 : CTIMER connection 10 */ - GPIO_PADREGB_PAD6FNCSEL_I2S_DAT = 7, /*!< I2S_DAT : Configure as the PDM I2S Data output signal */ -} GPIO_PADREGB_PAD6FNCSEL_Enum; - -/* ============================================ GPIO PADREGB PAD6STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGB_PAD6STRNG */ - GPIO_PADREGB_PAD6STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGB_PAD6STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGB_PAD6STRNG_Enum; - -/* ============================================ GPIO PADREGB PAD6INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGB_PAD6INPEN */ - GPIO_PADREGB_PAD6INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGB_PAD6INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGB_PAD6INPEN_Enum; - -/* ============================================ GPIO PADREGB PAD6PULL [16..16] ============================================= */ -typedef enum { /*!< GPIO_PADREGB_PAD6PULL */ - GPIO_PADREGB_PAD6PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGB_PAD6PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGB_PAD6PULL_Enum; - -/* ============================================ GPIO PADREGB PAD5RSEL [14..15] ============================================= */ -typedef enum { /*!< GPIO_PADREGB_PAD5RSEL */ - GPIO_PADREGB_PAD5RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ - GPIO_PADREGB_PAD5RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ - GPIO_PADREGB_PAD5RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ - GPIO_PADREGB_PAD5RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ -} GPIO_PADREGB_PAD5RSEL_Enum; - -/* =========================================== GPIO PADREGB PAD5FNCSEL [11..13] ============================================ */ -typedef enum { /*!< GPIO_PADREGB_PAD5FNCSEL */ - GPIO_PADREGB_PAD5FNCSEL_M0SCL = 0, /*!< M0SCL : Configure as the IOMSTR0 I2C SCL signal */ - GPIO_PADREGB_PAD5FNCSEL_M0SCK = 1, /*!< M0SCK : Configure as the IOMSTR0 SPI SCK signal */ - GPIO_PADREGB_PAD5FNCSEL_UA0RTS = 2, /*!< UA0RTS : Configure as the UART0 RTS signal output */ - GPIO_PADREGB_PAD5FNCSEL_GPIO5 = 3, /*!< GPIO5 : Configure as GPIO5 */ - GPIO_PADREGB_PAD5FNCSEL_EXTHFA = 5, /*!< EXTHFA : Configure as the External HFA input clock */ - GPIO_PADREGB_PAD5FNCSEL_CT8 = 7, /*!< CT8 : CTIMER connection 8 */ -} GPIO_PADREGB_PAD5FNCSEL_Enum; - -/* ============================================ GPIO PADREGB PAD5STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGB_PAD5STRNG */ - GPIO_PADREGB_PAD5STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGB_PAD5STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGB_PAD5STRNG_Enum; - -/* ============================================= GPIO PADREGB PAD5INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGB_PAD5INPEN */ - GPIO_PADREGB_PAD5INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGB_PAD5INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGB_PAD5INPEN_Enum; - -/* ============================================= GPIO PADREGB PAD5PULL [8..8] ============================================== */ -typedef enum { /*!< GPIO_PADREGB_PAD5PULL */ - GPIO_PADREGB_PAD5PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGB_PAD5PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGB_PAD5PULL_Enum; - -/* ============================================ GPIO PADREGB PAD4FNCSEL [3..5] ============================================= */ -typedef enum { /*!< GPIO_PADREGB_PAD4FNCSEL */ - GPIO_PADREGB_PAD4FNCSEL_UA0CTS = 0, /*!< UA0CTS : Configure as the UART0 CTS input signal */ - GPIO_PADREGB_PAD4FNCSEL_SLINT = 1, /*!< SLINT : Configure as the IOSLAVE interrupt out signal */ - GPIO_PADREGB_PAD4FNCSEL_NCE4 = 2, /*!< NCE4 : IOM/SPI nCE group 4 */ - GPIO_PADREGB_PAD4FNCSEL_GPIO4 = 3, /*!< GPIO4 : Configure as GPIO4 */ - GPIO_PADREGB_PAD4FNCSEL_UART0RX = 5, /*!< UART0RX : Configure as the UART0 RX input */ - GPIO_PADREGB_PAD4FNCSEL_CT17 = 6, /*!< CT17 : CTIMER connection 17 */ - GPIO_PADREGB_PAD4FNCSEL_MSPI2 = 7, /*!< MSPI2 : MSPI data connection 2 */ -} GPIO_PADREGB_PAD4FNCSEL_Enum; - -/* ============================================= GPIO PADREGB PAD4STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGB_PAD4STRNG */ - GPIO_PADREGB_PAD4STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGB_PAD4STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGB_PAD4STRNG_Enum; - -/* ============================================= GPIO PADREGB PAD4INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGB_PAD4INPEN */ - GPIO_PADREGB_PAD4INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGB_PAD4INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGB_PAD4INPEN_Enum; - -/* ============================================= GPIO PADREGB PAD4PULL [0..0] ============================================== */ -typedef enum { /*!< GPIO_PADREGB_PAD4PULL */ - GPIO_PADREGB_PAD4PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGB_PAD4PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGB_PAD4PULL_Enum; - -/* ======================================================== PADREGC ======================================================== */ -/* =========================================== GPIO PADREGC PAD11FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGC_PAD11FNCSEL */ - GPIO_PADREGC_PAD11FNCSEL_ADCSE2 = 0, /*!< ADCSE2 : Configure as the analog input for ADC single ended - input 2 */ - GPIO_PADREGC_PAD11FNCSEL_NCE11 = 1, /*!< NCE11 : IOM/MSPI nCE group 11 */ - GPIO_PADREGC_PAD11FNCSEL_CT31 = 2, /*!< CT31 : CTIMER connection 31 */ - GPIO_PADREGC_PAD11FNCSEL_GPIO11 = 3, /*!< GPIO11 : Configure as GPIO11 */ - GPIO_PADREGC_PAD11FNCSEL_SLINT = 4, /*!< SLINT : Configure as the IOSLAVE interrupt out signal */ - GPIO_PADREGC_PAD11FNCSEL_UA1CTS = 5, /*!< UA1CTS : Configure as the UART1 CTS input signal */ - GPIO_PADREGC_PAD11FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the UART0 RX input signal */ - GPIO_PADREGC_PAD11FNCSEL_PDM_DATA = 7, /*!< PDM_DATA : Configure as the PDM Data input signal */ -} GPIO_PADREGC_PAD11FNCSEL_Enum; - -/* =========================================== GPIO PADREGC PAD11STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGC_PAD11STRNG */ - GPIO_PADREGC_PAD11STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGC_PAD11STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGC_PAD11STRNG_Enum; - -/* =========================================== GPIO PADREGC PAD11INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGC_PAD11INPEN */ - GPIO_PADREGC_PAD11INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGC_PAD11INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGC_PAD11INPEN_Enum; - -/* ============================================ GPIO PADREGC PAD11PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGC_PAD11PULL */ - GPIO_PADREGC_PAD11PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGC_PAD11PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGC_PAD11PULL_Enum; - -/* =========================================== GPIO PADREGC PAD10FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGC_PAD10FNCSEL */ - GPIO_PADREGC_PAD10FNCSEL_M1MOSI = 1, /*!< M1MOSI : Configure as the IOMSTR1 SPI MOSI signal */ - GPIO_PADREGC_PAD10FNCSEL_NCE10 = 2, /*!< NCE10 : IOM/MSPI nCE group 10 */ - GPIO_PADREGC_PAD10FNCSEL_GPIO10 = 3, /*!< GPIO10 : Configure as GPIO10 */ - GPIO_PADREGC_PAD10FNCSEL_PDMCLK = 4, /*!< PDMCLK : PDM serial clock out */ - GPIO_PADREGC_PAD10FNCSEL_UA1RTS = 5, /*!< UA1RTS : Configure as the UART1 RTS output signal */ -} GPIO_PADREGC_PAD10FNCSEL_Enum; - -/* =========================================== GPIO PADREGC PAD10STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGC_PAD10STRNG */ - GPIO_PADREGC_PAD10STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGC_PAD10STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGC_PAD10STRNG_Enum; - -/* =========================================== GPIO PADREGC PAD10INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGC_PAD10INPEN */ - GPIO_PADREGC_PAD10INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGC_PAD10INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGC_PAD10INPEN_Enum; - -/* ============================================ GPIO PADREGC PAD10PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGC_PAD10PULL */ - GPIO_PADREGC_PAD10PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGC_PAD10PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGC_PAD10PULL_Enum; - -/* ============================================ GPIO PADREGC PAD9RSEL [14..15] ============================================= */ -typedef enum { /*!< GPIO_PADREGC_PAD9RSEL */ - GPIO_PADREGC_PAD9RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ - GPIO_PADREGC_PAD9RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ - GPIO_PADREGC_PAD9RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ - GPIO_PADREGC_PAD9RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ -} GPIO_PADREGC_PAD9RSEL_Enum; - -/* =========================================== GPIO PADREGC PAD9FNCSEL [11..13] ============================================ */ -typedef enum { /*!< GPIO_PADREGC_PAD9FNCSEL */ - GPIO_PADREGC_PAD9FNCSEL_M1SDAWIR3 = 0, /*!< M1SDAWIR3 : Configure as the IOMSTR1 I2C SDA or SPI WIR3 signal */ - GPIO_PADREGC_PAD9FNCSEL_M1MISO = 1, /*!< M1MISO : Configure as the IOMSTR1 SPI MISO signal */ - GPIO_PADREGC_PAD9FNCSEL_NCE9 = 2, /*!< NCE9 : IOM/MSPI nCE group 9 */ - GPIO_PADREGC_PAD9FNCSEL_GPIO9 = 3, /*!< GPIO9 : Configure as GPIO9 */ - GPIO_PADREGC_PAD9FNCSEL_SCCIO = 4, /*!< SCCIO : SCARD data I/O connection */ - GPIO_PADREGC_PAD9FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as UART1 RX input signal */ -} GPIO_PADREGC_PAD9FNCSEL_Enum; - -/* ============================================ GPIO PADREGC PAD9STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGC_PAD9STRNG */ - GPIO_PADREGC_PAD9STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGC_PAD9STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGC_PAD9STRNG_Enum; - -/* ============================================= GPIO PADREGC PAD9INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGC_PAD9INPEN */ - GPIO_PADREGC_PAD9INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGC_PAD9INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGC_PAD9INPEN_Enum; - -/* ============================================= GPIO PADREGC PAD9PULL [8..8] ============================================== */ -typedef enum { /*!< GPIO_PADREGC_PAD9PULL */ - GPIO_PADREGC_PAD9PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGC_PAD9PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGC_PAD9PULL_Enum; - -/* ============================================= GPIO PADREGC PAD8RSEL [6..7] ============================================== */ -typedef enum { /*!< GPIO_PADREGC_PAD8RSEL */ - GPIO_PADREGC_PAD8RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ - GPIO_PADREGC_PAD8RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ - GPIO_PADREGC_PAD8RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ - GPIO_PADREGC_PAD8RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ -} GPIO_PADREGC_PAD8RSEL_Enum; - -/* ============================================ GPIO PADREGC PAD8FNCSEL [3..5] ============================================= */ -typedef enum { /*!< GPIO_PADREGC_PAD8FNCSEL */ - GPIO_PADREGC_PAD8FNCSEL_M1SCL = 0, /*!< M1SCL : Configure as the IOMSTR1 I2C SCL signal */ - GPIO_PADREGC_PAD8FNCSEL_M1SCK = 1, /*!< M1SCK : Configure as the IOMSTR1 SPI SCK signal */ - GPIO_PADREGC_PAD8FNCSEL_NCE8 = 2, /*!< NCE8 : IOM/MSPI nCE group 8 */ - GPIO_PADREGC_PAD8FNCSEL_GPIO8 = 3, /*!< GPIO8 : Configure as GPIO8 */ - GPIO_PADREGC_PAD8FNCSEL_SCCLK = 4, /*!< SCCLK : SCARD serial clock output */ - GPIO_PADREGC_PAD8FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output signal */ -} GPIO_PADREGC_PAD8FNCSEL_Enum; - -/* ============================================= GPIO PADREGC PAD8STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGC_PAD8STRNG */ - GPIO_PADREGC_PAD8STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGC_PAD8STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGC_PAD8STRNG_Enum; - -/* ============================================= GPIO PADREGC PAD8INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGC_PAD8INPEN */ - GPIO_PADREGC_PAD8INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGC_PAD8INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGC_PAD8INPEN_Enum; - -/* ============================================= GPIO PADREGC PAD8PULL [0..0] ============================================== */ -typedef enum { /*!< GPIO_PADREGC_PAD8PULL */ - GPIO_PADREGC_PAD8PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGC_PAD8PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGC_PAD8PULL_Enum; - -/* ======================================================== PADREGD ======================================================== */ -/* =========================================== GPIO PADREGD PAD15FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGD_PAD15FNCSEL */ - GPIO_PADREGD_PAD15FNCSEL_ADCD1N = 0, /*!< ADCD1N : Configure as the analog ADC differential pair 1 N input - signal */ - GPIO_PADREGD_PAD15FNCSEL_NCE15 = 1, /*!< NCE15 : IOM/MSPI nCE group 15 */ - GPIO_PADREGD_PAD15FNCSEL_UART1RX = 2, /*!< UART1RX : Configure as the UART1 RX signal */ - GPIO_PADREGD_PAD15FNCSEL_GPIO15 = 3, /*!< GPIO15 : Configure as GPIO15 */ - GPIO_PADREGD_PAD15FNCSEL_PDMDATA = 4, /*!< PDMDATA : PDM serial data input */ - GPIO_PADREGD_PAD15FNCSEL_EXTXT = 5, /*!< EXTXT : Configure as the external XTAL oscillator input */ - GPIO_PADREGD_PAD15FNCSEL_SWDIO = 6, /*!< SWDIO : Configure as an alternate port for the SWDIO I/O signal */ - GPIO_PADREGD_PAD15FNCSEL_SWO = 7, /*!< SWO : Configure as an SWO (Serial Wire Trace output) */ -} GPIO_PADREGD_PAD15FNCSEL_Enum; - -/* =========================================== GPIO PADREGD PAD15STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGD_PAD15STRNG */ - GPIO_PADREGD_PAD15STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGD_PAD15STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGD_PAD15STRNG_Enum; - -/* =========================================== GPIO PADREGD PAD15INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGD_PAD15INPEN */ - GPIO_PADREGD_PAD15INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGD_PAD15INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGD_PAD15INPEN_Enum; - -/* ============================================ GPIO PADREGD PAD15PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGD_PAD15PULL */ - GPIO_PADREGD_PAD15PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGD_PAD15PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGD_PAD15PULL_Enum; - -/* =========================================== GPIO PADREGD PAD14FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGD_PAD14FNCSEL */ - GPIO_PADREGD_PAD14FNCSEL_ADCD1P = 0, /*!< ADCD1P : Configure as the analog ADC differential pair 1 P input - signal */ - GPIO_PADREGD_PAD14FNCSEL_NCE14 = 1, /*!< NCE14 : IOM/MSPI nCE group 14 */ - GPIO_PADREGD_PAD14FNCSEL_UART1TX = 2, /*!< UART1TX : Configure as the UART1 TX output signal */ - GPIO_PADREGD_PAD14FNCSEL_GPIO14 = 3, /*!< GPIO14 : Configure as GPIO14 */ - GPIO_PADREGD_PAD14FNCSEL_PDMCLK = 4, /*!< PDMCLK : PDM serial clock output */ - GPIO_PADREGD_PAD14FNCSEL_EXTHFS = 5, /*!< EXTHFS : Configure as the External HFRC oscillator input select */ - GPIO_PADREGD_PAD14FNCSEL_SWDCK = 6, /*!< SWDCK : Configure as the alternate input for the SWDCK input - signal */ - GPIO_PADREGD_PAD14FNCSEL_32kHzXT = 7, /*!< 32kHzXT : Configure as the 32kHz crystal output signal */ -} GPIO_PADREGD_PAD14FNCSEL_Enum; - -/* =========================================== GPIO PADREGD PAD14STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGD_PAD14STRNG */ - GPIO_PADREGD_PAD14STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGD_PAD14STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGD_PAD14STRNG_Enum; - -/* =========================================== GPIO PADREGD PAD14INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGD_PAD14INPEN */ - GPIO_PADREGD_PAD14INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGD_PAD14INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGD_PAD14INPEN_Enum; - -/* ============================================ GPIO PADREGD PAD14PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGD_PAD14PULL */ - GPIO_PADREGD_PAD14PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGD_PAD14PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGD_PAD14PULL_Enum; - -/* =========================================== GPIO PADREGD PAD13FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGD_PAD13FNCSEL */ - GPIO_PADREGD_PAD13FNCSEL_ADCD0PSE8 = 0, /*!< ADCD0PSE8 : Configure as the ADC Differential pair 0 P, or Single - Ended input 8 analog input signal. Determination of the - D0P vs SE8 usage is done when the particular channel is - selected within the ADC module */ - GPIO_PADREGD_PAD13FNCSEL_NCE13 = 1, /*!< NCE13 : IOM/MSPI nCE group 13 */ - GPIO_PADREGD_PAD13FNCSEL_CT2 = 2, /*!< CT2 : CTIMER connection 2 */ - GPIO_PADREGD_PAD13FNCSEL_GPIO13 = 3, /*!< GPIO13 : Configure as GPIO13 */ - GPIO_PADREGD_PAD13FNCSEL_I2SBCLK = 4, /*!< I2SBCLK : I2C interface bit clock */ - GPIO_PADREGD_PAD13FNCSEL_EXTHFB = 5, /*!< EXTHFB : Configure as the external HFRC oscillator input */ - GPIO_PADREGD_PAD13FNCSEL_UA0RTS = 6, /*!< UA0RTS : Configure as the UART0 RTS signal output */ - GPIO_PADREGD_PAD13FNCSEL_UART1RX = 7, /*!< UART1RX : Configure as the UART1 RX input signal */ -} GPIO_PADREGD_PAD13FNCSEL_Enum; - -/* =========================================== GPIO PADREGD PAD13STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGD_PAD13STRNG */ - GPIO_PADREGD_PAD13STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGD_PAD13STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGD_PAD13STRNG_Enum; - -/* ============================================ GPIO PADREGD PAD13INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGD_PAD13INPEN */ - GPIO_PADREGD_PAD13INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGD_PAD13INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGD_PAD13INPEN_Enum; - -/* ============================================= GPIO PADREGD PAD13PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGD_PAD13PULL */ - GPIO_PADREGD_PAD13PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGD_PAD13PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGD_PAD13PULL_Enum; - -/* ============================================ GPIO PADREGD PAD12FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGD_PAD12FNCSEL */ - GPIO_PADREGD_PAD12FNCSEL_ADCD0NSE9 = 0, /*!< ADCD0NSE9 : Configure as the ADC Differential pair 0 N, or Single - Ended input 9 analog input signal. Determination of the - D0N vs SE9 usage is done when the particular channel is - selected within the ADC module */ - GPIO_PADREGD_PAD12FNCSEL_NCE12 = 1, /*!< NCE12 : IOM/MSPI nCE group 12 */ - GPIO_PADREGD_PAD12FNCSEL_CT0 = 2, /*!< CT0 : CTIMER connection 0 */ - GPIO_PADREGD_PAD12FNCSEL_GPIO12 = 3, /*!< GPIO12 : Configure as GPIO12 */ - GPIO_PADREGD_PAD12FNCSEL_SLnCE = 4, /*!< SLnCE : Configure as the IOSLAVE SPI nCE signal */ - GPIO_PADREGD_PAD12FNCSEL_PDMCLK = 5, /*!< PDMCLK : PDM serial clock output */ - GPIO_PADREGD_PAD12FNCSEL_UA0CTS = 6, /*!< UA0CTS : Configure as the UART0 CTS input signal */ - GPIO_PADREGD_PAD12FNCSEL_UART1TX = 7, /*!< UART1TX : Configure as the UART1 TX output signal */ -} GPIO_PADREGD_PAD12FNCSEL_Enum; - -/* ============================================ GPIO PADREGD PAD12STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGD_PAD12STRNG */ - GPIO_PADREGD_PAD12STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGD_PAD12STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGD_PAD12STRNG_Enum; - -/* ============================================ GPIO PADREGD PAD12INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGD_PAD12INPEN */ - GPIO_PADREGD_PAD12INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGD_PAD12INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGD_PAD12INPEN_Enum; - -/* ============================================= GPIO PADREGD PAD12PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGD_PAD12PULL */ - GPIO_PADREGD_PAD12PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGD_PAD12PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGD_PAD12PULL_Enum; - -/* ======================================================== PADREGE ======================================================== */ -/* =========================================== GPIO PADREGE PAD19FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGE_PAD19FNCSEL */ - GPIO_PADREGE_PAD19FNCSEL_CMPRF0 = 0, /*!< CMPRF0 : Configure as the analog comparator reference 0 signal */ - GPIO_PADREGE_PAD19FNCSEL_NCE19 = 1, /*!< NCE19 : IOM/MSPI nCE group 19 */ - GPIO_PADREGE_PAD19FNCSEL_CT6 = 2, /*!< CT6 : CTIMER conenction 6 */ - GPIO_PADREGE_PAD19FNCSEL_GPIO19 = 3, /*!< GPIO19 : Configure as GPIO19 */ - GPIO_PADREGE_PAD19FNCSEL_SCCLK = 4, /*!< SCCLK : SCARD serial clock */ - GPIO_PADREGE_PAD19FNCSEL_ANATEST1 = 5, /*!< ANATEST1 : Configure as the ANATEST1 I/O signal */ - GPIO_PADREGE_PAD19FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as the UART1 RX input signal */ - GPIO_PADREGE_PAD19FNCSEL_I2SBCLK = 7, /*!< I2SBCLK : Configure as the PDM I2S bit clock input signal */ -} GPIO_PADREGE_PAD19FNCSEL_Enum; - -/* =========================================== GPIO PADREGE PAD19STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGE_PAD19STRNG */ - GPIO_PADREGE_PAD19STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGE_PAD19STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGE_PAD19STRNG_Enum; - -/* =========================================== GPIO PADREGE PAD19INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGE_PAD19INPEN */ - GPIO_PADREGE_PAD19INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGE_PAD19INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGE_PAD19INPEN_Enum; - -/* ============================================ GPIO PADREGE PAD19PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGE_PAD19PULL */ - GPIO_PADREGE_PAD19PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGE_PAD19PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGE_PAD19PULL_Enum; - -/* =========================================== GPIO PADREGE PAD18FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGE_PAD18FNCSEL */ - GPIO_PADREGE_PAD18FNCSEL_CMPIN1 = 0, /*!< CMPIN1 : Configure as the analog comparator input 1 signal */ - GPIO_PADREGE_PAD18FNCSEL_NCE18 = 1, /*!< NCE18 : IOM/MSPI nCE group 18 */ - GPIO_PADREGE_PAD18FNCSEL_CT4 = 2, /*!< CT4 : CTIMER connection 4 */ - GPIO_PADREGE_PAD18FNCSEL_GPIO18 = 3, /*!< GPIO18 : Configure as GPIO18 */ - GPIO_PADREGE_PAD18FNCSEL_UA0RTS = 4, /*!< UA0RTS : Configure as UART0 RTS output signal */ - GPIO_PADREGE_PAD18FNCSEL_ANATEST2 = 5, /*!< ANATEST2 : Configure as ANATEST2 I/O signal */ - GPIO_PADREGE_PAD18FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as UART1 TX output signal */ - GPIO_PADREGE_PAD18FNCSEL_SCCIO = 7, /*!< SCCIO : SCARD data input/output connectin */ -} GPIO_PADREGE_PAD18FNCSEL_Enum; - -/* =========================================== GPIO PADREGE PAD18STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGE_PAD18STRNG */ - GPIO_PADREGE_PAD18STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGE_PAD18STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGE_PAD18STRNG_Enum; - -/* =========================================== GPIO PADREGE PAD18INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGE_PAD18INPEN */ - GPIO_PADREGE_PAD18INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGE_PAD18INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGE_PAD18INPEN_Enum; - -/* ============================================ GPIO PADREGE PAD18PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGE_PAD18PULL */ - GPIO_PADREGE_PAD18PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGE_PAD18PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGE_PAD18PULL_Enum; - -/* =========================================== GPIO PADREGE PAD17FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGE_PAD17FNCSEL */ - GPIO_PADREGE_PAD17FNCSEL_CMPRF1 = 0, /*!< CMPRF1 : Configure as the analog comparator reference signal - 1 input signal */ - GPIO_PADREGE_PAD17FNCSEL_NCE17 = 1, /*!< NCE17 : IOM/MSPI nCE group 17 */ - GPIO_PADREGE_PAD17FNCSEL_TRIG1 = 2, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */ - GPIO_PADREGE_PAD17FNCSEL_GPIO17 = 3, /*!< GPIO17 : Configure as GPIO17 */ - GPIO_PADREGE_PAD17FNCSEL_SCCCLK = 4, /*!< SCCCLK : SCARD serial clock output */ - GPIO_PADREGE_PAD17FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as UART0 RX input signal */ - GPIO_PADREGE_PAD17FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as UART1 CTS input signal */ -} GPIO_PADREGE_PAD17FNCSEL_Enum; - -/* =========================================== GPIO PADREGE PAD17STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGE_PAD17STRNG */ - GPIO_PADREGE_PAD17STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGE_PAD17STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGE_PAD17STRNG_Enum; - -/* ============================================ GPIO PADREGE PAD17INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGE_PAD17INPEN */ - GPIO_PADREGE_PAD17INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGE_PAD17INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGE_PAD17INPEN_Enum; - -/* ============================================= GPIO PADREGE PAD17PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGE_PAD17PULL */ - GPIO_PADREGE_PAD17PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGE_PAD17PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGE_PAD17PULL_Enum; - -/* ============================================ GPIO PADREGE PAD16FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGE_PAD16FNCSEL */ - GPIO_PADREGE_PAD16FNCSEL_ADCSE0 = 0, /*!< ADCSE0 : Configure as the analog ADC single ended port 0 input - signal */ - GPIO_PADREGE_PAD16FNCSEL_NCE16 = 1, /*!< NCE16 : IOM/MSPI nCE group 16 */ - GPIO_PADREGE_PAD16FNCSEL_TRIG0 = 2, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */ - GPIO_PADREGE_PAD16FNCSEL_GPIO16 = 3, /*!< GPIO16 : Configure as GPIO16 */ - GPIO_PADREGE_PAD16FNCSEL_SCCRST = 4, /*!< SCCRST : SCARD reset output */ - GPIO_PADREGE_PAD16FNCSEL_CMPIN0 = 5, /*!< CMPIN0 : Configure as comparator input 0 signal */ - GPIO_PADREGE_PAD16FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as UART0 TX output signal */ - GPIO_PADREGE_PAD16FNCSEL_UA1RTS = 7, /*!< UA1RTS : Configure as UART1 RTS output signal */ -} GPIO_PADREGE_PAD16FNCSEL_Enum; - -/* ============================================ GPIO PADREGE PAD16STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGE_PAD16STRNG */ - GPIO_PADREGE_PAD16STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGE_PAD16STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGE_PAD16STRNG_Enum; - -/* ============================================ GPIO PADREGE PAD16INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGE_PAD16INPEN */ - GPIO_PADREGE_PAD16INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGE_PAD16INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGE_PAD16INPEN_Enum; - -/* ============================================= GPIO PADREGE PAD16PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGE_PAD16PULL */ - GPIO_PADREGE_PAD16PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGE_PAD16PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGE_PAD16PULL_Enum; - -/* ======================================================== PADREGF ======================================================== */ -/* =========================================== GPIO PADREGF PAD23FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGF_PAD23FNCSEL */ - GPIO_PADREGF_PAD23FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as the UART0 RX signal */ - GPIO_PADREGF_PAD23FNCSEL_NCE23 = 1, /*!< NCE23 : IOM/MSPI nCE group 23 */ - GPIO_PADREGF_PAD23FNCSEL_CT14 = 2, /*!< CT14 : CTIMER connection 14 */ - GPIO_PADREGF_PAD23FNCSEL_GPIO23 = 3, /*!< GPIO23 : Configure as GPIO23 */ - GPIO_PADREGF_PAD23FNCSEL_I2SWCLK = 4, /*!< I2SWCLK : I2S word clock input */ - GPIO_PADREGF_PAD23FNCSEL_CMPOUT = 5, /*!< CMPOUT : Configure as voltage comparitor output */ - GPIO_PADREGF_PAD23FNCSEL_MSPI3 = 6, /*!< MSPI3 : MSPI data connection 3 */ - GPIO_PADREGF_PAD23FNCSEL_EXTXT = 7, /*!< EXTXT : External XTAL osacillatgor input */ -} GPIO_PADREGF_PAD23FNCSEL_Enum; - -/* =========================================== GPIO PADREGF PAD23STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGF_PAD23STRNG */ - GPIO_PADREGF_PAD23STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGF_PAD23STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGF_PAD23STRNG_Enum; - -/* =========================================== GPIO PADREGF PAD23INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGF_PAD23INPEN */ - GPIO_PADREGF_PAD23INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGF_PAD23INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGF_PAD23INPEN_Enum; - -/* ============================================ GPIO PADREGF PAD23PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGF_PAD23PULL */ - GPIO_PADREGF_PAD23PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGF_PAD23PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGF_PAD23PULL_Enum; - -/* =========================================== GPIO PADREGF PAD22FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGF_PAD22FNCSEL */ - GPIO_PADREGF_PAD22FNCSEL_UART0TX = 0, /*!< UART0TX : Configure as the UART0 TX signal */ - GPIO_PADREGF_PAD22FNCSEL_NCE22 = 1, /*!< NCE22 : IOM/MSPI nCE group 22 */ - GPIO_PADREGF_PAD22FNCSEL_CT12 = 2, /*!< CT12 : CTIMER connection 12 */ - GPIO_PADREGF_PAD22FNCSEL_GPIO22 = 3, /*!< GPIO22 : Configure as GPIO22 */ - GPIO_PADREGF_PAD22FNCSEL_PDM_CLK = 4, /*!< PDM_CLK : Configure as the PDM CLK output */ - GPIO_PADREGF_PAD22FNCSEL_EXTLF = 5, /*!< EXTLF : External LFRC input */ - GPIO_PADREGF_PAD22FNCSEL_MSPI0 = 6, /*!< MSPI0 : MSPI data connection 0 */ - GPIO_PADREGF_PAD22FNCSEL_SWO = 7, /*!< SWO : Configure as the serial trace data output signal */ -} GPIO_PADREGF_PAD22FNCSEL_Enum; - -/* =========================================== GPIO PADREGF PAD22STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGF_PAD22STRNG */ - GPIO_PADREGF_PAD22STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGF_PAD22STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGF_PAD22STRNG_Enum; - -/* =========================================== GPIO PADREGF PAD22INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGF_PAD22INPEN */ - GPIO_PADREGF_PAD22INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGF_PAD22INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGF_PAD22INPEN_Enum; - -/* ============================================ GPIO PADREGF PAD22PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGF_PAD22PULL */ - GPIO_PADREGF_PAD22PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGF_PAD22PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGF_PAD22PULL_Enum; - -/* =========================================== GPIO PADREGF PAD21FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGF_PAD21FNCSEL */ - GPIO_PADREGF_PAD21FNCSEL_SWDIO = 0, /*!< SWDIO : Configure as the serial wire debug data signal */ - GPIO_PADREGF_PAD21FNCSEL_NCE21 = 1, /*!< NCE21 : IOM/MSPI nCE group 21 */ - GPIO_PADREGF_PAD21FNCSEL_GPIO21 = 3, /*!< GPIO21 : Configure as GPIO21 */ - GPIO_PADREGF_PAD21FNCSEL_UART0RX = 4, /*!< UART0RX : Configure as UART0 RX input signal */ - GPIO_PADREGF_PAD21FNCSEL_UART1RX = 5, /*!< UART1RX : Configure as UART1 RX input signal */ - GPIO_PADREGF_PAD21FNCSEL_I2SBCLK = 6, /*!< I2SBCLK : I2S byte clock input */ - GPIO_PADREGF_PAD21FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as UART1 CTS input signal */ -} GPIO_PADREGF_PAD21FNCSEL_Enum; - -/* =========================================== GPIO PADREGF PAD21STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGF_PAD21STRNG */ - GPIO_PADREGF_PAD21STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGF_PAD21STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGF_PAD21STRNG_Enum; - -/* ============================================ GPIO PADREGF PAD21INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGF_PAD21INPEN */ - GPIO_PADREGF_PAD21INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGF_PAD21INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGF_PAD21INPEN_Enum; - -/* ============================================= GPIO PADREGF PAD21PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGF_PAD21PULL */ - GPIO_PADREGF_PAD21PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGF_PAD21PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGF_PAD21PULL_Enum; - -/* ============================================ GPIO PADREGF PAD20FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGF_PAD20FNCSEL */ - GPIO_PADREGF_PAD20FNCSEL_SWDCK = 0, /*!< SWDCK : Configure as the serial wire debug clock signal */ - GPIO_PADREGF_PAD20FNCSEL_NCE20 = 1, /*!< NCE20 : IOM/MSPI nCE group 20 */ - GPIO_PADREGF_PAD20FNCSEL_GPIO20 = 3, /*!< GPIO20 : Configure as GPIO20 */ - GPIO_PADREGF_PAD20FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as UART0 TX output signal */ - GPIO_PADREGF_PAD20FNCSEL_UART1TX = 5, /*!< UART1TX : Configure as UART1 TX output signal */ - GPIO_PADREGF_PAD20FNCSEL_I2SBCLK = 6, /*!< I2SBCLK : I2S byte clock input */ - GPIO_PADREGF_PAD20FNCSEL_UA1RTS = 7, /*!< UA1RTS : Configure as UART1 RTS output signal */ -} GPIO_PADREGF_PAD20FNCSEL_Enum; - -/* ============================================ GPIO PADREGF PAD20STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGF_PAD20STRNG */ - GPIO_PADREGF_PAD20STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGF_PAD20STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGF_PAD20STRNG_Enum; - -/* ============================================ GPIO PADREGF PAD20INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGF_PAD20INPEN */ - GPIO_PADREGF_PAD20INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGF_PAD20INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGF_PAD20INPEN_Enum; - -/* ============================================= GPIO PADREGF PAD20PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGF_PAD20PULL */ - GPIO_PADREGF_PAD20PULL_DIS = 0, /*!< DIS : Pulldown disabled */ - GPIO_PADREGF_PAD20PULL_EN = 1, /*!< EN : Pulldown enabled */ -} GPIO_PADREGF_PAD20PULL_Enum; - -/* ======================================================== PADREGG ======================================================== */ -/* ============================================ GPIO PADREGG PAD27RSEL [30..31] ============================================ */ -typedef enum { /*!< GPIO_PADREGG_PAD27RSEL */ - GPIO_PADREGG_PAD27RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ - GPIO_PADREGG_PAD27RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ - GPIO_PADREGG_PAD27RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ - GPIO_PADREGG_PAD27RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ -} GPIO_PADREGG_PAD27RSEL_Enum; - -/* =========================================== GPIO PADREGG PAD27FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGG_PAD27FNCSEL */ - GPIO_PADREGG_PAD27FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as UART0 RX input signal */ - GPIO_PADREGG_PAD27FNCSEL_NCE27 = 1, /*!< NCE27 : IOM/MSPI nCE group 27 */ - GPIO_PADREGG_PAD27FNCSEL_CT5 = 2, /*!< CT5 : CTIMER connection 5 */ - GPIO_PADREGG_PAD27FNCSEL_GPIO27 = 3, /*!< GPIO27 : Configure as GPIO27 */ - GPIO_PADREGG_PAD27FNCSEL_M2SCL = 4, /*!< M2SCL : Configure as I2C clock I/O signal from IOMSTR2 */ - GPIO_PADREGG_PAD27FNCSEL_M2SCK = 5, /*!< M2SCK : Configure as SPI clock output signal from IOMSTR2 */ -} GPIO_PADREGG_PAD27FNCSEL_Enum; - -/* =========================================== GPIO PADREGG PAD27STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGG_PAD27STRNG */ - GPIO_PADREGG_PAD27STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGG_PAD27STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGG_PAD27STRNG_Enum; - -/* =========================================== GPIO PADREGG PAD27INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGG_PAD27INPEN */ - GPIO_PADREGG_PAD27INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGG_PAD27INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGG_PAD27INPEN_Enum; - -/* ============================================ GPIO PADREGG PAD27PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGG_PAD27PULL */ - GPIO_PADREGG_PAD27PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGG_PAD27PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGG_PAD27PULL_Enum; - -/* =========================================== GPIO PADREGG PAD26FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGG_PAD26FNCSEL */ - GPIO_PADREGG_PAD26FNCSEL_EXTHF = 0, /*!< EXTHF : Configure as the external HFRC oscillator input */ - GPIO_PADREGG_PAD26FNCSEL_NCE26 = 1, /*!< NCE26 : IOM/MSPI nCE group 26 */ - GPIO_PADREGG_PAD26FNCSEL_CT3 = 2, /*!< CT3 : CTIMER connection 3 */ - GPIO_PADREGG_PAD26FNCSEL_GPIO26 = 3, /*!< GPIO26 : Configure as GPIO26 */ - GPIO_PADREGG_PAD26FNCSEL_SCCRST = 4, /*!< SCCRST : SCARD reset output */ - GPIO_PADREGG_PAD26FNCSEL_MSPI1 = 5, /*!< MSPI1 : MSPI data connection 1 */ - GPIO_PADREGG_PAD26FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as UART0 TX output signal */ - GPIO_PADREGG_PAD26FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as UART1 CTS input signal */ -} GPIO_PADREGG_PAD26FNCSEL_Enum; - -/* =========================================== GPIO PADREGG PAD26STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGG_PAD26STRNG */ - GPIO_PADREGG_PAD26STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGG_PAD26STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGG_PAD26STRNG_Enum; - -/* =========================================== GPIO PADREGG PAD26INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGG_PAD26INPEN */ - GPIO_PADREGG_PAD26INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGG_PAD26INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGG_PAD26INPEN_Enum; - -/* ============================================ GPIO PADREGG PAD26PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGG_PAD26PULL */ - GPIO_PADREGG_PAD26PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGG_PAD26PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGG_PAD26PULL_Enum; - -/* ============================================ GPIO PADREGG PAD25RSEL [14..15] ============================================ */ -typedef enum { /*!< GPIO_PADREGG_PAD25RSEL */ - GPIO_PADREGG_PAD25RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ - GPIO_PADREGG_PAD25RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ - GPIO_PADREGG_PAD25RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ - GPIO_PADREGG_PAD25RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ -} GPIO_PADREGG_PAD25RSEL_Enum; - -/* =========================================== GPIO PADREGG PAD25FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGG_PAD25FNCSEL */ - GPIO_PADREGG_PAD25FNCSEL_UART1RX = 0, /*!< UART1RX : Configure as UART1 RX input signal */ - GPIO_PADREGG_PAD25FNCSEL_NCE25 = 1, /*!< NCE25 : IOM/MSPI nCE group 25 */ - GPIO_PADREGG_PAD25FNCSEL_CT1 = 2, /*!< CT1 : CTIMER connection 1 */ - GPIO_PADREGG_PAD25FNCSEL_GPIO25 = 3, /*!< GPIO25 : Configure as GPIO25 */ - GPIO_PADREGG_PAD25FNCSEL_M2SDAWIR3 = 4, /*!< M2SDAWIR3 : Configure as the IOMSTR2 I2C SDA or SPI WIR3 signal */ - GPIO_PADREGG_PAD25FNCSEL_M2MISO = 5, /*!< M2MISO : Configure as the IOMSTR2 SPI MISO input signal */ -} GPIO_PADREGG_PAD25FNCSEL_Enum; - -/* =========================================== GPIO PADREGG PAD25STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGG_PAD25STRNG */ - GPIO_PADREGG_PAD25STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGG_PAD25STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGG_PAD25STRNG_Enum; - -/* ============================================ GPIO PADREGG PAD25INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGG_PAD25INPEN */ - GPIO_PADREGG_PAD25INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGG_PAD25INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGG_PAD25INPEN_Enum; - -/* ============================================= GPIO PADREGG PAD25PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGG_PAD25PULL */ - GPIO_PADREGG_PAD25PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGG_PAD25PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGG_PAD25PULL_Enum; - -/* ============================================ GPIO PADREGG PAD24FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGG_PAD24FNCSEL */ - GPIO_PADREGG_PAD24FNCSEL_UART1TX = 0, /*!< UART1TX : Configure as UART1 TX output signal */ - GPIO_PADREGG_PAD24FNCSEL_NCE24 = 1, /*!< NCE24 : IOM/MSPI nCE group 24 */ - GPIO_PADREGG_PAD24FNCSEL_MSPI8 = 2, /*!< MSPI8 : MSPI data connection 8 */ - GPIO_PADREGG_PAD24FNCSEL_GPIO24 = 3, /*!< GPIO24 : Configure as GPIO24 */ - GPIO_PADREGG_PAD24FNCSEL_UA0CTS = 4, /*!< UA0CTS : Configure as UART0 CTS input signal */ - GPIO_PADREGG_PAD24FNCSEL_CT21 = 5, /*!< CT21 : CTIMER connection 21 */ - GPIO_PADREGG_PAD24FNCSEL_32kHzXT = 6, /*!< 32kHzXT : Configure as the 32kHz crystal output signal */ - GPIO_PADREGG_PAD24FNCSEL_SWO = 7, /*!< SWO : Configure as the serial trace data output signal */ -} GPIO_PADREGG_PAD24FNCSEL_Enum; - -/* ============================================ GPIO PADREGG PAD24STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGG_PAD24STRNG */ - GPIO_PADREGG_PAD24STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGG_PAD24STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGG_PAD24STRNG_Enum; - -/* ============================================ GPIO PADREGG PAD24INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGG_PAD24INPEN */ - GPIO_PADREGG_PAD24INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGG_PAD24INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGG_PAD24INPEN_Enum; - -/* ============================================= GPIO PADREGG PAD24PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGG_PAD24PULL */ - GPIO_PADREGG_PAD24PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGG_PAD24PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGG_PAD24PULL_Enum; - -/* ======================================================== PADREGH ======================================================== */ -/* =========================================== GPIO PADREGH PAD31FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGH_PAD31FNCSEL */ - GPIO_PADREGH_PAD31FNCSEL_ADCSE3 = 0, /*!< ADCSE3 : Configure as the analog input for ADC single ended - input 3 */ - GPIO_PADREGH_PAD31FNCSEL_NCE31 = 1, /*!< NCE31 : IOM/MSPI nCE group 31 */ - GPIO_PADREGH_PAD31FNCSEL_CT13 = 2, /*!< CT13 : CTIMER connection 13 */ - GPIO_PADREGH_PAD31FNCSEL_GPIO31 = 3, /*!< GPIO31 : Configure as GPIO31 */ - GPIO_PADREGH_PAD31FNCSEL_UART0RX = 4, /*!< UART0RX : Configure as the UART0 RX input signal */ - GPIO_PADREGH_PAD31FNCSEL_SCCCLK = 5, /*!< SCCCLK : SCARD serial clock output */ - GPIO_PADREGH_PAD31FNCSEL_UA1RTS = 7, /*!< UA1RTS : Configure as UART1 RTS output signal */ -} GPIO_PADREGH_PAD31FNCSEL_Enum; - -/* =========================================== GPIO PADREGH PAD31STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGH_PAD31STRNG */ - GPIO_PADREGH_PAD31STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGH_PAD31STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGH_PAD31STRNG_Enum; - -/* =========================================== GPIO PADREGH PAD31INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGH_PAD31INPEN */ - GPIO_PADREGH_PAD31INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGH_PAD31INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGH_PAD31INPEN_Enum; - -/* ============================================ GPIO PADREGH PAD31PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGH_PAD31PULL */ - GPIO_PADREGH_PAD31PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGH_PAD31PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGH_PAD31PULL_Enum; - -/* =========================================== GPIO PADREGH PAD30FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGH_PAD30FNCSEL */ - GPIO_PADREGH_PAD30FNCSEL_ANATEST1 = 0, /*!< ANATEST1 : Configure as the ANATEST1 I/O signal */ - GPIO_PADREGH_PAD30FNCSEL_NCE30 = 1, /*!< NCE30 : IOM/MSPI nCE group 30 */ - GPIO_PADREGH_PAD30FNCSEL_CT11 = 2, /*!< CT11 : CTIMER connection 11 */ - GPIO_PADREGH_PAD30FNCSEL_GPIO30 = 3, /*!< GPIO30 : Configure as GPIO30 */ - GPIO_PADREGH_PAD30FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as UART0 TX output signal */ - GPIO_PADREGH_PAD30FNCSEL_UA1RTS = 5, /*!< UA1RTS : Configure as UART1 RTS output signal */ - GPIO_PADREGH_PAD30FNCSEL_I2S_DAT = 7, /*!< I2S_DAT : Configure as the PDM I2S Data output signal */ -} GPIO_PADREGH_PAD30FNCSEL_Enum; - -/* =========================================== GPIO PADREGH PAD30STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGH_PAD30STRNG */ - GPIO_PADREGH_PAD30STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGH_PAD30STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGH_PAD30STRNG_Enum; - -/* =========================================== GPIO PADREGH PAD30INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGH_PAD30INPEN */ - GPIO_PADREGH_PAD30INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGH_PAD30INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGH_PAD30INPEN_Enum; - -/* ============================================ GPIO PADREGH PAD30PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGH_PAD30PULL */ - GPIO_PADREGH_PAD30PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGH_PAD30PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGH_PAD30PULL_Enum; - -/* =========================================== GPIO PADREGH PAD29FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGH_PAD29FNCSEL */ - GPIO_PADREGH_PAD29FNCSEL_ADCSE1 = 0, /*!< ADCSE1 : Configure as the analog input for ADC single ended - input 1 */ - GPIO_PADREGH_PAD29FNCSEL_NCE29 = 1, /*!< NCE29 : IOM/MSPI nCE group 29 */ - GPIO_PADREGH_PAD29FNCSEL_CT9 = 2, /*!< CT9 : CTIMER connection 9 */ - GPIO_PADREGH_PAD29FNCSEL_GPIO29 = 3, /*!< GPIO29 : Configure as GPIO29 */ - GPIO_PADREGH_PAD29FNCSEL_UA0CTS = 4, /*!< UA0CTS : Configure as the UART0 CTS input signal */ - GPIO_PADREGH_PAD29FNCSEL_UA1CTS = 5, /*!< UA1CTS : Configure as the UART1 CTS input signal */ - GPIO_PADREGH_PAD29FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the UART0 RX input signal */ - GPIO_PADREGH_PAD29FNCSEL_PDM_DATA = 7, /*!< PDM_DATA : Configure as PDM DATA input */ -} GPIO_PADREGH_PAD29FNCSEL_Enum; - -/* =========================================== GPIO PADREGH PAD29STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGH_PAD29STRNG */ - GPIO_PADREGH_PAD29STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGH_PAD29STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGH_PAD29STRNG_Enum; - -/* ============================================ GPIO PADREGH PAD29INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGH_PAD29INPEN */ - GPIO_PADREGH_PAD29INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGH_PAD29INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGH_PAD29INPEN_Enum; - -/* ============================================= GPIO PADREGH PAD29PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGH_PAD29PULL */ - GPIO_PADREGH_PAD29PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGH_PAD29PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGH_PAD29PULL_Enum; - -/* ============================================ GPIO PADREGH PAD28FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGH_PAD28FNCSEL */ - GPIO_PADREGH_PAD28FNCSEL_I2S_WCLK = 0, /*!< I2S_WCLK : Configure as the PDM I2S Word Clock input */ - GPIO_PADREGH_PAD28FNCSEL_NCE28 = 1, /*!< NCE28 : IOM/MSPI nCE group 28 */ - GPIO_PADREGH_PAD28FNCSEL_CT7 = 2, /*!< CT7 : CTIMER connection 7 */ - GPIO_PADREGH_PAD28FNCSEL_GPIO28 = 3, /*!< GPIO28 : Configure as GPIO28 */ - GPIO_PADREGH_PAD28FNCSEL_M2MOSI = 5, /*!< M2MOSI : Configure as the IOMSTR2 SPI MOSI output signal */ - GPIO_PADREGH_PAD28FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as the UART0 TX output signal */ -} GPIO_PADREGH_PAD28FNCSEL_Enum; - -/* ============================================ GPIO PADREGH PAD28STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGH_PAD28STRNG */ - GPIO_PADREGH_PAD28STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGH_PAD28STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGH_PAD28STRNG_Enum; - -/* ============================================ GPIO PADREGH PAD28INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGH_PAD28INPEN */ - GPIO_PADREGH_PAD28INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGH_PAD28INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGH_PAD28INPEN_Enum; - -/* ============================================= GPIO PADREGH PAD28PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGH_PAD28PULL */ - GPIO_PADREGH_PAD28PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGH_PAD28PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGH_PAD28PULL_Enum; - -/* ======================================================== PADREGI ======================================================== */ -/* =========================================== GPIO PADREGI PAD35FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGI_PAD35FNCSEL */ - GPIO_PADREGI_PAD35FNCSEL_ADCSE7 = 0, /*!< ADCSE7 : Configure as the analog input for ADC single ended - input 7 */ - GPIO_PADREGI_PAD35FNCSEL_NCE35 = 1, /*!< NCE35 : IOM/MSPI nCE group 35 */ - GPIO_PADREGI_PAD35FNCSEL_UART1TX = 2, /*!< UART1TX : Configure as the UART1 TX signal */ - GPIO_PADREGI_PAD35FNCSEL_GPIO35 = 3, /*!< GPIO35 : Configure as GPIO35 */ - GPIO_PADREGI_PAD35FNCSEL_I2SDAT = 4, /*!< I2SDAT : I2S serial data output */ - GPIO_PADREGI_PAD35FNCSEL_CT27 = 5, /*!< CT27 : CTIMER connection 27 */ - GPIO_PADREGI_PAD35FNCSEL_UA0RTS = 6, /*!< UA0RTS : Configure as the UART0 RTS output */ -} GPIO_PADREGI_PAD35FNCSEL_Enum; - -/* =========================================== GPIO PADREGI PAD35STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGI_PAD35STRNG */ - GPIO_PADREGI_PAD35STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGI_PAD35STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGI_PAD35STRNG_Enum; - -/* =========================================== GPIO PADREGI PAD35INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGI_PAD35INPEN */ - GPIO_PADREGI_PAD35INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGI_PAD35INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGI_PAD35INPEN_Enum; - -/* ============================================ GPIO PADREGI PAD35PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGI_PAD35PULL */ - GPIO_PADREGI_PAD35PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGI_PAD35PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGI_PAD35PULL_Enum; - -/* =========================================== GPIO PADREGI PAD34FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGI_PAD34FNCSEL */ - GPIO_PADREGI_PAD34FNCSEL_ADCSE6 = 0, /*!< ADCSE6 : Configure as the analog input for ADC single ended - input 6 */ - GPIO_PADREGI_PAD34FNCSEL_NCE34 = 1, /*!< NCE34 : IOM/MSPI nCE group 34 */ - GPIO_PADREGI_PAD34FNCSEL_UA1RTS = 2, /*!< UA1RTS : Configure as the UART1 RTS output */ - GPIO_PADREGI_PAD34FNCSEL_GPIO34 = 3, /*!< GPIO34 : Configure as GPIO34 */ - GPIO_PADREGI_PAD34FNCSEL_CMPRF2 = 4, /*!< CMPRF2 : Configure as the analog comparator reference 2 signal */ - GPIO_PADREGI_PAD34FNCSEL_UA0RTS = 5, /*!< UA0RTS : Configure as the UART0 RTS output */ - GPIO_PADREGI_PAD34FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the UART0 RX input */ - GPIO_PADREGI_PAD34FNCSEL_PDMDATA = 7, /*!< PDMDATA : PDM serial data input */ -} GPIO_PADREGI_PAD34FNCSEL_Enum; - -/* =========================================== GPIO PADREGI PAD34STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGI_PAD34STRNG */ - GPIO_PADREGI_PAD34STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGI_PAD34STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGI_PAD34STRNG_Enum; - -/* =========================================== GPIO PADREGI PAD34INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGI_PAD34INPEN */ - GPIO_PADREGI_PAD34INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGI_PAD34INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGI_PAD34INPEN_Enum; - -/* ============================================ GPIO PADREGI PAD34PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGI_PAD34PULL */ - GPIO_PADREGI_PAD34PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGI_PAD34PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGI_PAD34PULL_Enum; - -/* =========================================== GPIO PADREGI PAD33FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGI_PAD33FNCSEL */ - GPIO_PADREGI_PAD33FNCSEL_ADCSE5 = 0, /*!< ADCSE5 : Configure as the analog ADC single ended port 5 input - signal */ - GPIO_PADREGI_PAD33FNCSEL_NCE33 = 1, /*!< NCE33 : IOM/MSPI nCE group 33 */ - GPIO_PADREGI_PAD33FNCSEL_32kHzXT = 2, /*!< 32kHzXT : Configure as the 32kHz crystal output signal */ - GPIO_PADREGI_PAD33FNCSEL_GPIO33 = 3, /*!< GPIO33 : Configure as GPIO33 */ - GPIO_PADREGI_PAD33FNCSEL_UA0CTS = 5, /*!< UA0CTS : Configure as the UART0 CTS input */ - GPIO_PADREGI_PAD33FNCSEL_CT23 = 6, /*!< CT23 : CTIMER connection 23 */ - GPIO_PADREGI_PAD33FNCSEL_SWO = 7, /*!< SWO : Configure as the serial trace data output signal */ -} GPIO_PADREGI_PAD33FNCSEL_Enum; - -/* =========================================== GPIO PADREGI PAD33STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGI_PAD33STRNG */ - GPIO_PADREGI_PAD33STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGI_PAD33STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGI_PAD33STRNG_Enum; - -/* ============================================ GPIO PADREGI PAD33INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGI_PAD33INPEN */ - GPIO_PADREGI_PAD33INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGI_PAD33INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGI_PAD33INPEN_Enum; - -/* ============================================= GPIO PADREGI PAD33PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGI_PAD33PULL */ - GPIO_PADREGI_PAD33PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGI_PAD33PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGI_PAD33PULL_Enum; - -/* ============================================ GPIO PADREGI PAD32FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGI_PAD32FNCSEL */ - GPIO_PADREGI_PAD32FNCSEL_ADCSE4 = 0, /*!< ADCSE4 : Configure as the analog input for ADC single ended - input 4 */ - GPIO_PADREGI_PAD32FNCSEL_NCE32 = 1, /*!< NCE32 : IOM/MSPI nCE group 32 */ - GPIO_PADREGI_PAD32FNCSEL_CT15 = 2, /*!< CT15 : CTIMER connection 15 */ - GPIO_PADREGI_PAD32FNCSEL_GPIO32 = 3, /*!< GPIO32 : Configure as GPIO32 */ - GPIO_PADREGI_PAD32FNCSEL_SCCIO = 4, /*!< SCCIO : SCARD serial data input/output */ - GPIO_PADREGI_PAD32FNCSEL_EXTLF = 5, /*!< EXTLF : External input to the LFRC oscillator */ - GPIO_PADREGI_PAD32FNCSEL_UA1CTS = 7, /*!< UA1CTS : Configure as the UART1 CTS input */ -} GPIO_PADREGI_PAD32FNCSEL_Enum; - -/* ============================================ GPIO PADREGI PAD32STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGI_PAD32STRNG */ - GPIO_PADREGI_PAD32STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGI_PAD32STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGI_PAD32STRNG_Enum; - -/* ============================================ GPIO PADREGI PAD32INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGI_PAD32INPEN */ - GPIO_PADREGI_PAD32INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGI_PAD32INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGI_PAD32INPEN_Enum; - -/* ============================================= GPIO PADREGI PAD32PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGI_PAD32PULL */ - GPIO_PADREGI_PAD32PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGI_PAD32PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGI_PAD32PULL_Enum; - -/* ======================================================== PADREGJ ======================================================== */ -/* ============================================ GPIO PADREGJ PAD39RSEL [30..31] ============================================ */ -typedef enum { /*!< GPIO_PADREGJ_PAD39RSEL */ - GPIO_PADREGJ_PAD39RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ - GPIO_PADREGJ_PAD39RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ - GPIO_PADREGJ_PAD39RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ - GPIO_PADREGJ_PAD39RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ -} GPIO_PADREGJ_PAD39RSEL_Enum; - -/* =========================================== GPIO PADREGJ PAD39FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGJ_PAD39FNCSEL */ - GPIO_PADREGJ_PAD39FNCSEL_UART0TX = 0, /*!< UART0TX : Configure as the UART0 TX output signal */ - GPIO_PADREGJ_PAD39FNCSEL_UART1TX = 1, /*!< UART1TX : Configure as the UART1 TX output signal */ - GPIO_PADREGJ_PAD39FNCSEL_CT25 = 2, /*!< CT25 : CTIMER connection 25 */ - GPIO_PADREGJ_PAD39FNCSEL_GPIO39 = 3, /*!< GPIO39 : Configure as GPIO39 */ - GPIO_PADREGJ_PAD39FNCSEL_M4SCL = 4, /*!< M4SCL : Configure as the IOMSTR4 I2C SCL signal */ - GPIO_PADREGJ_PAD39FNCSEL_M4SCK = 5, /*!< M4SCK : Configure as the IOMSTR4 SPI SCK signal */ -} GPIO_PADREGJ_PAD39FNCSEL_Enum; - -/* =========================================== GPIO PADREGJ PAD39STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGJ_PAD39STRNG */ - GPIO_PADREGJ_PAD39STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGJ_PAD39STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGJ_PAD39STRNG_Enum; - -/* =========================================== GPIO PADREGJ PAD39INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGJ_PAD39INPEN */ - GPIO_PADREGJ_PAD39INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGJ_PAD39INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGJ_PAD39INPEN_Enum; - -/* ============================================ GPIO PADREGJ PAD39PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGJ_PAD39PULL */ - GPIO_PADREGJ_PAD39PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGJ_PAD39PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGJ_PAD39PULL_Enum; - -/* =========================================== GPIO PADREGJ PAD38FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGJ_PAD38FNCSEL */ - GPIO_PADREGJ_PAD38FNCSEL_TRIG3 = 0, /*!< TRIG3 : Configure as the ADC Trigger 3 signal */ - GPIO_PADREGJ_PAD38FNCSEL_NCE38 = 1, /*!< NCE38 : IOM/MSPI nCE group 38 */ - GPIO_PADREGJ_PAD38FNCSEL_UA0CTS = 2, /*!< UA0CTS : Configure as the UART0 CTS signal */ - GPIO_PADREGJ_PAD38FNCSEL_GPIO38 = 3, /*!< GPIO38 : Configure as GPIO38 */ - GPIO_PADREGJ_PAD38FNCSEL_M3MOSI = 5, /*!< M3MOSI : Configure as the IOMSTR3 SPI MOSI output signal */ - GPIO_PADREGJ_PAD38FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as the UART1 RX input signal */ -} GPIO_PADREGJ_PAD38FNCSEL_Enum; - -/* =========================================== GPIO PADREGJ PAD38STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGJ_PAD38STRNG */ - GPIO_PADREGJ_PAD38STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGJ_PAD38STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGJ_PAD38STRNG_Enum; - -/* =========================================== GPIO PADREGJ PAD38INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGJ_PAD38INPEN */ - GPIO_PADREGJ_PAD38INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGJ_PAD38INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGJ_PAD38INPEN_Enum; - -/* ============================================ GPIO PADREGJ PAD38PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGJ_PAD38PULL */ - GPIO_PADREGJ_PAD38PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGJ_PAD38PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGJ_PAD38PULL_Enum; - -/* =========================================== GPIO PADREGJ PAD37PWRDN [15..15] ============================================ */ -typedef enum { /*!< GPIO_PADREGJ_PAD37PWRDN */ - GPIO_PADREGJ_PAD37PWRDN_DIS = 0, /*!< DIS : Power switch disabled */ - GPIO_PADREGJ_PAD37PWRDN_EN = 1, /*!< EN : Power switch enabled (switch to GND) */ -} GPIO_PADREGJ_PAD37PWRDN_Enum; - -/* =========================================== GPIO PADREGJ PAD37FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGJ_PAD37FNCSEL */ - GPIO_PADREGJ_PAD37FNCSEL_TRIG2 = 0, /*!< TRIG2 : Configure as the ADC Trigger 2 signal */ - GPIO_PADREGJ_PAD37FNCSEL_NCE37 = 1, /*!< NCE37 : IOM/MSPI nCE group 37 */ - GPIO_PADREGJ_PAD37FNCSEL_UA0RTS = 2, /*!< UA0RTS : Configure as the UART0 RTS output signal */ - GPIO_PADREGJ_PAD37FNCSEL_GPIO37 = 3, /*!< GPIO37 : Configure as GPIO37 */ - GPIO_PADREGJ_PAD37FNCSEL_SCCIO = 4, /*!< SCCIO : SCARD serial data input/output */ - GPIO_PADREGJ_PAD37FNCSEL_UART1TX = 5, /*!< UART1TX : Configure as the UART1 TX output signal */ - GPIO_PADREGJ_PAD37FNCSEL_PDMCLK = 6, /*!< PDMCLK : Configure as the PDM CLK output signal */ - GPIO_PADREGJ_PAD37FNCSEL_CT29 = 7, /*!< CT29 : CTIMER connection 29 */ -} GPIO_PADREGJ_PAD37FNCSEL_Enum; - -/* =========================================== GPIO PADREGJ PAD37STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGJ_PAD37STRNG */ - GPIO_PADREGJ_PAD37STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGJ_PAD37STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGJ_PAD37STRNG_Enum; - -/* ============================================ GPIO PADREGJ PAD37INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGJ_PAD37INPEN */ - GPIO_PADREGJ_PAD37INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGJ_PAD37INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGJ_PAD37INPEN_Enum; - -/* ============================================= GPIO PADREGJ PAD37PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGJ_PAD37PULL */ - GPIO_PADREGJ_PAD37PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGJ_PAD37PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGJ_PAD37PULL_Enum; - -/* ============================================ GPIO PADREGJ PAD36FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGJ_PAD36FNCSEL */ - GPIO_PADREGJ_PAD36FNCSEL_TRIG1 = 0, /*!< TRIG1 : Configure as the ADC Trigger 1 signal */ - GPIO_PADREGJ_PAD36FNCSEL_NCE36 = 1, /*!< NCE36 : IOM/MSPI nCE group 36 */ - GPIO_PADREGJ_PAD36FNCSEL_UART1RX = 2, /*!< UART1RX : Configure as the UART1 RX input signal */ - GPIO_PADREGJ_PAD36FNCSEL_GPIO36 = 3, /*!< GPIO36 : Configure as GPIO36 */ - GPIO_PADREGJ_PAD36FNCSEL_32kHzXT = 4, /*!< 32kHzXT : Configure as the 32kHz output clock from the crystal */ - GPIO_PADREGJ_PAD36FNCSEL_UA1CTS = 5, /*!< UA1CTS : Configure as the UART1 CTS input signal */ - GPIO_PADREGJ_PAD36FNCSEL_UA0CTS = 6, /*!< UA0CTS : Configure as the UART0 CTS input signal */ - GPIO_PADREGJ_PAD36FNCSEL_PDMDATA = 7, /*!< PDMDATA : PDM serial data input */ -} GPIO_PADREGJ_PAD36FNCSEL_Enum; - -/* ============================================ GPIO PADREGJ PAD36STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGJ_PAD36STRNG */ - GPIO_PADREGJ_PAD36STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGJ_PAD36STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGJ_PAD36STRNG_Enum; - -/* ============================================ GPIO PADREGJ PAD36INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGJ_PAD36INPEN */ - GPIO_PADREGJ_PAD36INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGJ_PAD36INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGJ_PAD36INPEN_Enum; - -/* ============================================= GPIO PADREGJ PAD36PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGJ_PAD36PULL */ - GPIO_PADREGJ_PAD36PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGJ_PAD36PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGJ_PAD36PULL_Enum; - -/* ======================================================== PADREGK ======================================================== */ -/* ============================================ GPIO PADREGK PAD43RSEL [30..31] ============================================ */ -typedef enum { /*!< GPIO_PADREGK_PAD43RSEL */ - GPIO_PADREGK_PAD43RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ - GPIO_PADREGK_PAD43RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ - GPIO_PADREGK_PAD43RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ - GPIO_PADREGK_PAD43RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ -} GPIO_PADREGK_PAD43RSEL_Enum; - -/* =========================================== GPIO PADREGK PAD43FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGK_PAD43FNCSEL */ - GPIO_PADREGK_PAD43FNCSEL_UART1RX = 0, /*!< UART1RX : Configure as the UART1 RX input signal */ - GPIO_PADREGK_PAD43FNCSEL_NCE43 = 1, /*!< NCE43 : IOM/MSPI nCE group 43 */ - GPIO_PADREGK_PAD43FNCSEL_CT18 = 2, /*!< CT18 : CTIMER connection 18 */ - GPIO_PADREGK_PAD43FNCSEL_GPIO43 = 3, /*!< GPIO43 : Configure as GPIO43 */ - GPIO_PADREGK_PAD43FNCSEL_M3SDAWIR3 = 4, /*!< M3SDAWIR3 : Configure as the IOMSTR3 I2C SDA or SPI WIR3 signal */ - GPIO_PADREGK_PAD43FNCSEL_M3MISO = 5, /*!< M3MISO : Configure as the IOMSTR3 SPI MISO signal */ -} GPIO_PADREGK_PAD43FNCSEL_Enum; - -/* =========================================== GPIO PADREGK PAD43STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGK_PAD43STRNG */ - GPIO_PADREGK_PAD43STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGK_PAD43STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGK_PAD43STRNG_Enum; - -/* =========================================== GPIO PADREGK PAD43INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGK_PAD43INPEN */ - GPIO_PADREGK_PAD43INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGK_PAD43INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGK_PAD43INPEN_Enum; - -/* ============================================ GPIO PADREGK PAD43PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGK_PAD43PULL */ - GPIO_PADREGK_PAD43PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGK_PAD43PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGK_PAD43PULL_Enum; - -/* ============================================ GPIO PADREGK PAD42RSEL [22..23] ============================================ */ -typedef enum { /*!< GPIO_PADREGK_PAD42RSEL */ - GPIO_PADREGK_PAD42RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ - GPIO_PADREGK_PAD42RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ - GPIO_PADREGK_PAD42RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ - GPIO_PADREGK_PAD42RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ -} GPIO_PADREGK_PAD42RSEL_Enum; - -/* =========================================== GPIO PADREGK PAD42FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGK_PAD42FNCSEL */ - GPIO_PADREGK_PAD42FNCSEL_UART1TX = 0, /*!< UART1TX : Configure as the UART1 TX output signal */ - GPIO_PADREGK_PAD42FNCSEL_NCE42 = 1, /*!< NCE42 : IOM/MSPI nCE group 42 */ - GPIO_PADREGK_PAD42FNCSEL_CT16 = 2, /*!< CT16 : CTIMER connection 16 */ - GPIO_PADREGK_PAD42FNCSEL_GPIO42 = 3, /*!< GPIO42 : Configure as GPIO42 */ - GPIO_PADREGK_PAD42FNCSEL_M3SCL = 4, /*!< M3SCL : Configure as the IOMSTR3 I2C SCL clock I/O signal */ - GPIO_PADREGK_PAD42FNCSEL_M3SCK = 5, /*!< M3SCK : Configure as the IOMSTR3 SPI SCK output */ -} GPIO_PADREGK_PAD42FNCSEL_Enum; - -/* =========================================== GPIO PADREGK PAD42STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGK_PAD42STRNG */ - GPIO_PADREGK_PAD42STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGK_PAD42STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGK_PAD42STRNG_Enum; - -/* =========================================== GPIO PADREGK PAD42INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGK_PAD42INPEN */ - GPIO_PADREGK_PAD42INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGK_PAD42INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGK_PAD42INPEN_Enum; - -/* ============================================ GPIO PADREGK PAD42PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGK_PAD42PULL */ - GPIO_PADREGK_PAD42PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGK_PAD42PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGK_PAD42PULL_Enum; - -/* =========================================== GPIO PADREGK PAD41PWRDN [15..15] ============================================ */ -typedef enum { /*!< GPIO_PADREGK_PAD41PWRDN */ - GPIO_PADREGK_PAD41PWRDN_DIS = 0, /*!< DIS : Power switch disabled */ - GPIO_PADREGK_PAD41PWRDN_EN = 1, /*!< EN : Power switch enabled (Switch pad to VSS) */ -} GPIO_PADREGK_PAD41PWRDN_Enum; - -/* =========================================== GPIO PADREGK PAD41FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGK_PAD41FNCSEL */ - GPIO_PADREGK_PAD41FNCSEL_NCE41 = 0, /*!< NCE41 : IOM/MSPI nCE group 41 */ - GPIO_PADREGK_PAD41FNCSEL_SWO = 2, /*!< SWO : Configure as the serial wire debug SWO signal */ - GPIO_PADREGK_PAD41FNCSEL_GPIO41 = 3, /*!< GPIO41 : Configure as GPIO41 */ - GPIO_PADREGK_PAD41FNCSEL_I2SWCLK = 4, /*!< I2SWCLK : I2S word clock input */ - GPIO_PADREGK_PAD41FNCSEL_UA1RTS = 5, /*!< UA1RTS : Configure as the UART1 RTS output signal */ - GPIO_PADREGK_PAD41FNCSEL_UART0TX = 6, /*!< UART0TX : Configure as the UART0 TX output signal */ - GPIO_PADREGK_PAD41FNCSEL_UA0RTS = 7, /*!< UA0RTS : Configure as the UART0 RTS output signal */ -} GPIO_PADREGK_PAD41FNCSEL_Enum; - -/* =========================================== GPIO PADREGK PAD41STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGK_PAD41STRNG */ - GPIO_PADREGK_PAD41STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGK_PAD41STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGK_PAD41STRNG_Enum; - -/* ============================================ GPIO PADREGK PAD41INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGK_PAD41INPEN */ - GPIO_PADREGK_PAD41INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGK_PAD41INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGK_PAD41INPEN_Enum; - -/* ============================================= GPIO PADREGK PAD41PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGK_PAD41PULL */ - GPIO_PADREGK_PAD41PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGK_PAD41PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGK_PAD41PULL_Enum; - -/* ============================================= GPIO PADREGK PAD40RSEL [6..7] ============================================= */ -typedef enum { /*!< GPIO_PADREGK_PAD40RSEL */ - GPIO_PADREGK_PAD40RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ - GPIO_PADREGK_PAD40RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ - GPIO_PADREGK_PAD40RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ - GPIO_PADREGK_PAD40RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ -} GPIO_PADREGK_PAD40RSEL_Enum; - -/* ============================================ GPIO PADREGK PAD40FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGK_PAD40FNCSEL */ - GPIO_PADREGK_PAD40FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as the UART0 RX input signal */ - GPIO_PADREGK_PAD40FNCSEL_UART1RX = 1, /*!< UART1RX : Configure as the UART1 RX input signal */ - GPIO_PADREGK_PAD40FNCSEL_TRIG0 = 2, /*!< TRIG0 : Configure as the ADC Trigger 0 signal */ - GPIO_PADREGK_PAD40FNCSEL_GPIO40 = 3, /*!< GPIO40 : Configure as GPIO40 */ - GPIO_PADREGK_PAD40FNCSEL_M4SDAWIR3 = 4, /*!< M4SDAWIR3 : Configure as the IOMSTR4 I2C SDA or SPI WIR3 signal */ - GPIO_PADREGK_PAD40FNCSEL_M4MISO = 5, /*!< M4MISO : Configure as the IOMSTR4 SPI MISO input signal */ -} GPIO_PADREGK_PAD40FNCSEL_Enum; - -/* ============================================ GPIO PADREGK PAD40STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGK_PAD40STRNG */ - GPIO_PADREGK_PAD40STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGK_PAD40STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGK_PAD40STRNG_Enum; - -/* ============================================ GPIO PADREGK PAD40INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGK_PAD40INPEN */ - GPIO_PADREGK_PAD40INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGK_PAD40INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGK_PAD40INPEN_Enum; - -/* ============================================= GPIO PADREGK PAD40PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGK_PAD40PULL */ - GPIO_PADREGK_PAD40PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGK_PAD40PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGK_PAD40PULL_Enum; - -/* ======================================================== PADREGL ======================================================== */ -/* =========================================== GPIO PADREGL PAD47FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGL_PAD47FNCSEL */ - GPIO_PADREGL_PAD47FNCSEL_32kHzXT = 0, /*!< 32kHzXT : Configure as the 32kHz output clock from the crystal */ - GPIO_PADREGL_PAD47FNCSEL_NCE47 = 1, /*!< NCE47 : IOM/MSPI nCE group 47 */ - GPIO_PADREGL_PAD47FNCSEL_CT26 = 2, /*!< CT26 : CTIMER connection 26 */ - GPIO_PADREGL_PAD47FNCSEL_GPIO47 = 3, /*!< GPIO47 : Configure as GPIO47 */ - GPIO_PADREGL_PAD47FNCSEL_M5MOSI = 5, /*!< M5MOSI : Configure as the IOMSTR5 SPI MOSI output signal */ - GPIO_PADREGL_PAD47FNCSEL_UART1RX = 6, /*!< UART1RX : Configure as the UART1 RX input signal */ -} GPIO_PADREGL_PAD47FNCSEL_Enum; - -/* =========================================== GPIO PADREGL PAD47STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGL_PAD47STRNG */ - GPIO_PADREGL_PAD47STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGL_PAD47STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGL_PAD47STRNG_Enum; - -/* =========================================== GPIO PADREGL PAD47INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGL_PAD47INPEN */ - GPIO_PADREGL_PAD47INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGL_PAD47INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGL_PAD47INPEN_Enum; - -/* ============================================ GPIO PADREGL PAD47PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGL_PAD47PULL */ - GPIO_PADREGL_PAD47PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGL_PAD47PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGL_PAD47PULL_Enum; - -/* =========================================== GPIO PADREGL PAD46FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGL_PAD46FNCSEL */ - GPIO_PADREGL_PAD46FNCSEL_32khz_XT = 0, /*!< 32khz_XT : Configure as the 32kHz output clock from the crystal */ - GPIO_PADREGL_PAD46FNCSEL_NCE46 = 1, /*!< NCE46 : IOM/MSPI nCE group 46 */ - GPIO_PADREGL_PAD46FNCSEL_CT24 = 2, /*!< CT24 : CTIMER connection 24 */ - GPIO_PADREGL_PAD46FNCSEL_GPIO46 = 3, /*!< GPIO46 : Configure as GPIO46 */ - GPIO_PADREGL_PAD46FNCSEL_SCCRST = 4, /*!< SCCRST : SCARD reset output */ - GPIO_PADREGL_PAD46FNCSEL_PDMCLK = 5, /*!< PDMCLK : PDM serial clock output */ - GPIO_PADREGL_PAD46FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output signal */ - GPIO_PADREGL_PAD46FNCSEL_SWO = 7, /*!< SWO : Configure as the serial wire debug SWO signal */ -} GPIO_PADREGL_PAD46FNCSEL_Enum; - -/* =========================================== GPIO PADREGL PAD46STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGL_PAD46STRNG */ - GPIO_PADREGL_PAD46STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGL_PAD46STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGL_PAD46STRNG_Enum; - -/* =========================================== GPIO PADREGL PAD46INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGL_PAD46INPEN */ - GPIO_PADREGL_PAD46INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGL_PAD46INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGL_PAD46INPEN_Enum; - -/* ============================================ GPIO PADREGL PAD46PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGL_PAD46PULL */ - GPIO_PADREGL_PAD46PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGL_PAD46PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGL_PAD46PULL_Enum; - -/* =========================================== GPIO PADREGL PAD45FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGL_PAD45FNCSEL */ - GPIO_PADREGL_PAD45FNCSEL_UA1CTS = 0, /*!< UA1CTS : Configure as the UART1 CTS input signal */ - GPIO_PADREGL_PAD45FNCSEL_NCE45 = 1, /*!< NCE45 : IOM/MSPI nCE group 45 */ - GPIO_PADREGL_PAD45FNCSEL_CT22 = 2, /*!< CT22 : CTIMER connection 22 */ - GPIO_PADREGL_PAD45FNCSEL_GPIO45 = 3, /*!< GPIO45 : Configure as GPIO45 */ - GPIO_PADREGL_PAD45FNCSEL_I2SDAT = 4, /*!< I2SDAT : I2S serial data output */ - GPIO_PADREGL_PAD45FNCSEL_PDMDATA = 5, /*!< PDMDATA : PDM serial data input */ - GPIO_PADREGL_PAD45FNCSEL_UART0RX = 6, /*!< UART0RX : Configure as the SPI channel 5 nCE signal from IOMSTR5 */ - GPIO_PADREGL_PAD45FNCSEL_SWO = 7, /*!< SWO : Configure as the serial wire debug SWO signal */ -} GPIO_PADREGL_PAD45FNCSEL_Enum; - -/* =========================================== GPIO PADREGL PAD45STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGL_PAD45STRNG */ - GPIO_PADREGL_PAD45STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGL_PAD45STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGL_PAD45STRNG_Enum; - -/* ============================================ GPIO PADREGL PAD45INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGL_PAD45INPEN */ - GPIO_PADREGL_PAD45INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGL_PAD45INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGL_PAD45INPEN_Enum; - -/* ============================================= GPIO PADREGL PAD45PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGL_PAD45PULL */ - GPIO_PADREGL_PAD45PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGL_PAD45PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGL_PAD45PULL_Enum; - -/* ============================================ GPIO PADREGL PAD44FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGL_PAD44FNCSEL */ - GPIO_PADREGL_PAD44FNCSEL_UA1RTS = 0, /*!< UA1RTS : Configure as the UART1 RTS output signal */ - GPIO_PADREGL_PAD44FNCSEL_NCE44 = 1, /*!< NCE44 : IOM/MSPI nCE group 44 */ - GPIO_PADREGL_PAD44FNCSEL_CT20 = 2, /*!< CT20 : CTIMER connection 20 */ - GPIO_PADREGL_PAD44FNCSEL_GPIO44 = 3, /*!< GPIO44 : Configure as GPIO44 */ - GPIO_PADREGL_PAD44FNCSEL_M4MOSI = 5, /*!< M4MOSI : Configure as the IOMSTR4 SPI MOSI signal */ - GPIO_PADREGL_PAD44FNCSEL_M5nCE6 = 6, /*!< M5nCE6 : Configure as the SPI channel 6 nCE signal from IOMSTR5 */ -} GPIO_PADREGL_PAD44FNCSEL_Enum; - -/* ============================================ GPIO PADREGL PAD44STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGL_PAD44STRNG */ - GPIO_PADREGL_PAD44STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGL_PAD44STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGL_PAD44STRNG_Enum; - -/* ============================================ GPIO PADREGL PAD44INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGL_PAD44INPEN */ - GPIO_PADREGL_PAD44INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGL_PAD44INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGL_PAD44INPEN_Enum; - -/* ============================================= GPIO PADREGL PAD44PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGL_PAD44PULL */ - GPIO_PADREGL_PAD44PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGL_PAD44PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGL_PAD44PULL_Enum; - -/* ======================================================== PADREGM ======================================================== */ -/* =========================================== GPIO PADREGM PAD51FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGM_PAD51FNCSEL */ - GPIO_PADREGM_PAD51FNCSEL_MSPI1_0 = 0, /*!< MSPI1_0 : Configure as the MSPI1 0 signal */ - GPIO_PADREGM_PAD51FNCSEL_NCE51 = 1, /*!< NCE51 : IOM/MSPI nCE group 51 */ - GPIO_PADREGM_PAD51FNCSEL_CT1 = 2, /*!< CT1 : CTIMER connection 1 */ - GPIO_PADREGM_PAD51FNCSEL_GPIO51 = 3, /*!< GPIO51 : Configure as GPIO51 */ -} GPIO_PADREGM_PAD51FNCSEL_Enum; - -/* =========================================== GPIO PADREGM PAD51STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGM_PAD51STRNG */ - GPIO_PADREGM_PAD51STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGM_PAD51STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGM_PAD51STRNG_Enum; - -/* =========================================== GPIO PADREGM PAD51INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGM_PAD51INPEN */ - GPIO_PADREGM_PAD51INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGM_PAD51INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGM_PAD51INPEN_Enum; - -/* ============================================ GPIO PADREGM PAD51PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGM_PAD51PULL */ - GPIO_PADREGM_PAD51PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGM_PAD51PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGM_PAD51PULL_Enum; - -/* =========================================== GPIO PADREGM PAD50FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGM_PAD50FNCSEL */ - GPIO_PADREGM_PAD50FNCSEL_SWO = 0, /*!< SWO : Configure as the SWO output */ - GPIO_PADREGM_PAD50FNCSEL_NCE50 = 1, /*!< NCE50 : IOM/MSPI nCE group 50 */ - GPIO_PADREGM_PAD50FNCSEL_CT0 = 2, /*!< CT0 : CTIMER connection 0 */ - GPIO_PADREGM_PAD50FNCSEL_GPIO50 = 3, /*!< GPIO50 : Configure as GPIO50 */ - GPIO_PADREGM_PAD50FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as the UART0 TX output */ - GPIO_PADREGM_PAD50FNCSEL_UART0RX = 5, /*!< UART0RX : Configure as the UART0 RX input */ - GPIO_PADREGM_PAD50FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output */ - GPIO_PADREGM_PAD50FNCSEL_UART1RX = 7, /*!< UART1RX : Configure as the UART1 RX input */ -} GPIO_PADREGM_PAD50FNCSEL_Enum; - -/* =========================================== GPIO PADREGM PAD50STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGM_PAD50STRNG */ - GPIO_PADREGM_PAD50STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGM_PAD50STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGM_PAD50STRNG_Enum; - -/* =========================================== GPIO PADREGM PAD50INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGM_PAD50INPEN */ - GPIO_PADREGM_PAD50INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGM_PAD50INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGM_PAD50INPEN_Enum; - -/* ============================================ GPIO PADREGM PAD50PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGM_PAD50PULL */ - GPIO_PADREGM_PAD50PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGM_PAD50PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGM_PAD50PULL_Enum; - -/* ============================================ GPIO PADREGM PAD49RSEL [14..15] ============================================ */ -typedef enum { /*!< GPIO_PADREGM_PAD49RSEL */ - GPIO_PADREGM_PAD49RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ - GPIO_PADREGM_PAD49RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ - GPIO_PADREGM_PAD49RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ - GPIO_PADREGM_PAD49RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ -} GPIO_PADREGM_PAD49RSEL_Enum; - -/* =========================================== GPIO PADREGM PAD49FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGM_PAD49FNCSEL */ - GPIO_PADREGM_PAD49FNCSEL_UART0RX = 0, /*!< UART0RX : Configure as the UART0 RX input signal */ - GPIO_PADREGM_PAD49FNCSEL_NCE49 = 1, /*!< NCE49 : IOM/MSPPI nCE group 49 */ - GPIO_PADREGM_PAD49FNCSEL_CT30 = 2, /*!< CT30 : CTIMER connection 30 */ - GPIO_PADREGM_PAD49FNCSEL_GPIO49 = 3, /*!< GPIO49 : Configure as GPIO49 */ - GPIO_PADREGM_PAD49FNCSEL_M5SDAWIR3 = 4, /*!< M5SDAWIR3 : Configure as the IOMSTR5 I2C SDA or SPI WIR3 signal */ - GPIO_PADREGM_PAD49FNCSEL_M5MISO = 5, /*!< M5MISO : Configure as the IOMSTR5 SPI MISO input signal */ -} GPIO_PADREGM_PAD49FNCSEL_Enum; - -/* =========================================== GPIO PADREGM PAD49STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGM_PAD49STRNG */ - GPIO_PADREGM_PAD49STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGM_PAD49STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGM_PAD49STRNG_Enum; - -/* ============================================ GPIO PADREGM PAD49INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGM_PAD49INPEN */ - GPIO_PADREGM_PAD49INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGM_PAD49INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGM_PAD49INPEN_Enum; - -/* ============================================= GPIO PADREGM PAD49PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGM_PAD49PULL */ - GPIO_PADREGM_PAD49PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGM_PAD49PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGM_PAD49PULL_Enum; - -/* ============================================= GPIO PADREGM PAD48RSEL [6..7] ============================================= */ -typedef enum { /*!< GPIO_PADREGM_PAD48RSEL */ - GPIO_PADREGM_PAD48RSEL_PULL1_5K = 0, /*!< PULL1_5K : Pullup is ~1.5 KOhms */ - GPIO_PADREGM_PAD48RSEL_PULL6K = 1, /*!< PULL6K : Pullup is ~6 KOhms */ - GPIO_PADREGM_PAD48RSEL_PULL12K = 2, /*!< PULL12K : Pullup is ~12 KOhms */ - GPIO_PADREGM_PAD48RSEL_PULL24K = 3, /*!< PULL24K : Pullup is ~24 KOhms */ -} GPIO_PADREGM_PAD48RSEL_Enum; - -/* ============================================ GPIO PADREGM PAD48FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGM_PAD48FNCSEL */ - GPIO_PADREGM_PAD48FNCSEL_UART0TX = 0, /*!< UART0TX : Configure as the UART0 TX output signal */ - GPIO_PADREGM_PAD48FNCSEL_NCE48 = 1, /*!< NCE48 : IOM/MSPI nCE group 48 */ - GPIO_PADREGM_PAD48FNCSEL_CT28 = 2, /*!< CT28 : CTIMER conenction 28 */ - GPIO_PADREGM_PAD48FNCSEL_GPIO48 = 3, /*!< GPIO48 : Configure as GPIO48 */ - GPIO_PADREGM_PAD48FNCSEL_M5SCL = 4, /*!< M5SCL : Configure as the IOMSTR5 I2C SCL clock I/O signal */ - GPIO_PADREGM_PAD48FNCSEL_M5SCK = 5, /*!< M5SCK : Configure as the IOMSTR5 SPI SCK output */ -} GPIO_PADREGM_PAD48FNCSEL_Enum; - -/* ============================================ GPIO PADREGM PAD48STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGM_PAD48STRNG */ - GPIO_PADREGM_PAD48STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGM_PAD48STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGM_PAD48STRNG_Enum; - -/* ============================================ GPIO PADREGM PAD48INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGM_PAD48INPEN */ - GPIO_PADREGM_PAD48INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGM_PAD48INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGM_PAD48INPEN_Enum; - -/* ============================================= GPIO PADREGM PAD48PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGM_PAD48PULL */ - GPIO_PADREGM_PAD48PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGM_PAD48PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGM_PAD48PULL_Enum; - -/* ======================================================== PADREGN ======================================================== */ -/* =========================================== GPIO PADREGN PAD55FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGN_PAD55FNCSEL */ - GPIO_PADREGN_PAD55FNCSEL_MSPI1_4 = 0, /*!< MSPI1_4 : Configure as the MSPI1 4 signal */ - GPIO_PADREGN_PAD55FNCSEL_NCE55 = 1, /*!< NCE55 : IOM/MSPI nCE group 55 */ - GPIO_PADREGN_PAD55FNCSEL_CT5 = 2, /*!< CT5 : CTIMER connection 5 */ - GPIO_PADREGN_PAD55FNCSEL_GPIO55 = 3, /*!< GPIO55 : Configure as GPIO55 */ -} GPIO_PADREGN_PAD55FNCSEL_Enum; - -/* =========================================== GPIO PADREGN PAD55STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGN_PAD55STRNG */ - GPIO_PADREGN_PAD55STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGN_PAD55STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGN_PAD55STRNG_Enum; - -/* =========================================== GPIO PADREGN PAD55INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGN_PAD55INPEN */ - GPIO_PADREGN_PAD55INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGN_PAD55INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGN_PAD55INPEN_Enum; - -/* ============================================ GPIO PADREGN PAD55PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGN_PAD55PULL */ - GPIO_PADREGN_PAD55PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGN_PAD55PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGN_PAD55PULL_Enum; - -/* =========================================== GPIO PADREGN PAD54FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGN_PAD54FNCSEL */ - GPIO_PADREGN_PAD54FNCSEL_MSPI1_3 = 0, /*!< MSPI1_3 : Configure as the MSPI1 3 signal */ - GPIO_PADREGN_PAD54FNCSEL_NCE54 = 1, /*!< NCE54 : IOM/MSPI nCE group 54 */ - GPIO_PADREGN_PAD54FNCSEL_CT4 = 2, /*!< CT4 : CTIMER connection 4 */ - GPIO_PADREGN_PAD54FNCSEL_GPIO54 = 3, /*!< GPIO54 : Configure as GPIO54 */ -} GPIO_PADREGN_PAD54FNCSEL_Enum; - -/* =========================================== GPIO PADREGN PAD54STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGN_PAD54STRNG */ - GPIO_PADREGN_PAD54STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGN_PAD54STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGN_PAD54STRNG_Enum; - -/* =========================================== GPIO PADREGN PAD54INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGN_PAD54INPEN */ - GPIO_PADREGN_PAD54INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGN_PAD54INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGN_PAD54INPEN_Enum; - -/* ============================================ GPIO PADREGN PAD54PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGN_PAD54PULL */ - GPIO_PADREGN_PAD54PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGN_PAD54PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGN_PAD54PULL_Enum; - -/* =========================================== GPIO PADREGN PAD53FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGN_PAD53FNCSEL */ - GPIO_PADREGN_PAD53FNCSEL_MSPI1_2 = 0, /*!< MSPI1_2 : Configure as the MSPI1 2 signal */ - GPIO_PADREGN_PAD53FNCSEL_NCE53 = 1, /*!< NCE53 : IOM/MSPI nCE group 53 */ - GPIO_PADREGN_PAD53FNCSEL_CT3 = 2, /*!< CT3 : CTIMER connection 3 */ - GPIO_PADREGN_PAD53FNCSEL_GPIO53 = 3, /*!< GPIO53 : Configure as GPIO53 */ -} GPIO_PADREGN_PAD53FNCSEL_Enum; - -/* =========================================== GPIO PADREGN PAD53STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGN_PAD53STRNG */ - GPIO_PADREGN_PAD53STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGN_PAD53STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGN_PAD53STRNG_Enum; - -/* ============================================ GPIO PADREGN PAD53INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGN_PAD53INPEN */ - GPIO_PADREGN_PAD53INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGN_PAD53INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGN_PAD53INPEN_Enum; - -/* ============================================= GPIO PADREGN PAD53PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGN_PAD53PULL */ - GPIO_PADREGN_PAD53PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGN_PAD53PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGN_PAD53PULL_Enum; - -/* ============================================ GPIO PADREGN PAD52FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGN_PAD52FNCSEL */ - GPIO_PADREGN_PAD52FNCSEL_MSPI1_1 = 0, /*!< MSPI1_1 : Configure as the MSPI1 1 signal */ - GPIO_PADREGN_PAD52FNCSEL_NCE52 = 1, /*!< NCE52 : IOM/MSPI nCE group 52 */ - GPIO_PADREGN_PAD52FNCSEL_CT2 = 2, /*!< CT2 : CTIMER connection 2 */ - GPIO_PADREGN_PAD52FNCSEL_GPIO52 = 3, /*!< GPIO52 : Configure as GPIO52 */ -} GPIO_PADREGN_PAD52FNCSEL_Enum; - -/* ============================================ GPIO PADREGN PAD52STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGN_PAD52STRNG */ - GPIO_PADREGN_PAD52STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGN_PAD52STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGN_PAD52STRNG_Enum; - -/* ============================================ GPIO PADREGN PAD52INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGN_PAD52INPEN */ - GPIO_PADREGN_PAD52INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGN_PAD52INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGN_PAD52INPEN_Enum; - -/* ============================================= GPIO PADREGN PAD52PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGN_PAD52PULL */ - GPIO_PADREGN_PAD52PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGN_PAD52PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGN_PAD52PULL_Enum; - -/* ======================================================== PADREGO ======================================================== */ -/* =========================================== GPIO PADREGO PAD59FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGO_PAD59FNCSEL */ - GPIO_PADREGO_PAD59FNCSEL_MSPI1_8 = 0, /*!< MSPI1_8 : Configure as the MSPI1 8 signal */ - GPIO_PADREGO_PAD59FNCSEL_NCE59 = 1, /*!< NCE59 : IOM/MSPI nCE group 59 */ - GPIO_PADREGO_PAD59FNCSEL_CT9 = 2, /*!< CT9 : CTIMER connection 9 */ - GPIO_PADREGO_PAD59FNCSEL_GPIO59 = 3, /*!< GPIO59 : Configure as GPIO59 */ -} GPIO_PADREGO_PAD59FNCSEL_Enum; - -/* =========================================== GPIO PADREGO PAD59STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGO_PAD59STRNG */ - GPIO_PADREGO_PAD59STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGO_PAD59STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGO_PAD59STRNG_Enum; - -/* =========================================== GPIO PADREGO PAD59INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGO_PAD59INPEN */ - GPIO_PADREGO_PAD59INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGO_PAD59INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGO_PAD59INPEN_Enum; - -/* ============================================ GPIO PADREGO PAD59PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGO_PAD59PULL */ - GPIO_PADREGO_PAD59PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGO_PAD59PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGO_PAD59PULL_Enum; - -/* =========================================== GPIO PADREGO PAD58FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGO_PAD58FNCSEL */ - GPIO_PADREGO_PAD58FNCSEL_MSPI1_7 = 0, /*!< MSPI1_7 : Configure as the MSPI1 7 signal */ - GPIO_PADREGO_PAD58FNCSEL_NCE58 = 1, /*!< NCE58 : IOM/MSPI nCE group 58 */ - GPIO_PADREGO_PAD58FNCSEL_CT8 = 2, /*!< CT8 : CTIMER connection 8 */ - GPIO_PADREGO_PAD58FNCSEL_GPIO58 = 3, /*!< GPIO58 : Configure as GPIO58 */ -} GPIO_PADREGO_PAD58FNCSEL_Enum; - -/* =========================================== GPIO PADREGO PAD58STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGO_PAD58STRNG */ - GPIO_PADREGO_PAD58STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGO_PAD58STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGO_PAD58STRNG_Enum; - -/* =========================================== GPIO PADREGO PAD58INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGO_PAD58INPEN */ - GPIO_PADREGO_PAD58INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGO_PAD58INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGO_PAD58INPEN_Enum; - -/* ============================================ GPIO PADREGO PAD58PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGO_PAD58PULL */ - GPIO_PADREGO_PAD58PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGO_PAD58PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGO_PAD58PULL_Enum; - -/* =========================================== GPIO PADREGO PAD57FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGO_PAD57FNCSEL */ - GPIO_PADREGO_PAD57FNCSEL_MSPI1_6 = 0, /*!< MSPI1_6 : Configure as the MSPI1 6 signal */ - GPIO_PADREGO_PAD57FNCSEL_NCE57 = 1, /*!< NCE57 : IOM/MSPI nCE group 57 */ - GPIO_PADREGO_PAD57FNCSEL_CT7 = 2, /*!< CT7 : CTIMER connection 7 */ - GPIO_PADREGO_PAD57FNCSEL_GPIO57 = 3, /*!< GPIO57 : Configure as GPIO57 */ -} GPIO_PADREGO_PAD57FNCSEL_Enum; - -/* =========================================== GPIO PADREGO PAD57STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGO_PAD57STRNG */ - GPIO_PADREGO_PAD57STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGO_PAD57STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGO_PAD57STRNG_Enum; - -/* ============================================ GPIO PADREGO PAD57INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGO_PAD57INPEN */ - GPIO_PADREGO_PAD57INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGO_PAD57INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGO_PAD57INPEN_Enum; - -/* ============================================= GPIO PADREGO PAD57PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGO_PAD57PULL */ - GPIO_PADREGO_PAD57PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGO_PAD57PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGO_PAD57PULL_Enum; - -/* ============================================ GPIO PADREGO PAD56FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGO_PAD56FNCSEL */ - GPIO_PADREGO_PAD56FNCSEL_MSPI1_5 = 0, /*!< MSPI1_5 : Configure as the MSPI1 5 signal */ - GPIO_PADREGO_PAD56FNCSEL_NCE56 = 1, /*!< NCE56 : IOM/MSPI nCE group 56 */ - GPIO_PADREGO_PAD56FNCSEL_CT6 = 2, /*!< CT6 : CTIMER connection 6 */ - GPIO_PADREGO_PAD56FNCSEL_GPIO56 = 3, /*!< GPIO56 : Configure as GPIO56 */ -} GPIO_PADREGO_PAD56FNCSEL_Enum; - -/* ============================================ GPIO PADREGO PAD56STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGO_PAD56STRNG */ - GPIO_PADREGO_PAD56STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGO_PAD56STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGO_PAD56STRNG_Enum; - -/* ============================================ GPIO PADREGO PAD56INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGO_PAD56INPEN */ - GPIO_PADREGO_PAD56INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGO_PAD56INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGO_PAD56INPEN_Enum; - -/* ============================================= GPIO PADREGO PAD56PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGO_PAD56PULL */ - GPIO_PADREGO_PAD56PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGO_PAD56PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGO_PAD56PULL_Enum; - -/* ======================================================== PADREGP ======================================================== */ -/* =========================================== GPIO PADREGP PAD63FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGP_PAD63FNCSEL */ - GPIO_PADREGP_PAD63FNCSEL_SWO = 0, /*!< SWO : Configure as the SWO output */ - GPIO_PADREGP_PAD63FNCSEL_NCE63 = 1, /*!< NCE63 : IOM/MSPI nCE group 63 */ - GPIO_PADREGP_PAD63FNCSEL_CT13 = 2, /*!< CT13 : CTIMER connection 13 */ - GPIO_PADREGP_PAD63FNCSEL_GPIO63 = 3, /*!< GPIO63 : Configure as GPIO63 */ - GPIO_PADREGP_PAD63FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as the UART0 TX output */ - GPIO_PADREGP_PAD63FNCSEL_UART0RX = 5, /*!< UART0RX : Configure as the UART0 RX input */ - GPIO_PADREGP_PAD63FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output */ - GPIO_PADREGP_PAD63FNCSEL_UART1RX = 7, /*!< UART1RX : Configure as the UART1 RX input */ -} GPIO_PADREGP_PAD63FNCSEL_Enum; - -/* =========================================== GPIO PADREGP PAD63STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGP_PAD63STRNG */ - GPIO_PADREGP_PAD63STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGP_PAD63STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGP_PAD63STRNG_Enum; - -/* =========================================== GPIO PADREGP PAD63INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGP_PAD63INPEN */ - GPIO_PADREGP_PAD63INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGP_PAD63INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGP_PAD63INPEN_Enum; - -/* ============================================ GPIO PADREGP PAD63PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGP_PAD63PULL */ - GPIO_PADREGP_PAD63PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGP_PAD63PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGP_PAD63PULL_Enum; - -/* =========================================== GPIO PADREGP PAD62FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGP_PAD62FNCSEL */ - GPIO_PADREGP_PAD62FNCSEL_SWO = 0, /*!< SWO : Configure as the SWO output */ - GPIO_PADREGP_PAD62FNCSEL_NCE62 = 1, /*!< NCE62 : IOM/MSPI nCE group 62 */ - GPIO_PADREGP_PAD62FNCSEL_CT12 = 2, /*!< CT12 : CTIMER connection 12 */ - GPIO_PADREGP_PAD62FNCSEL_GPIO62 = 3, /*!< GPIO62 : Configure as GPIO62 */ - GPIO_PADREGP_PAD62FNCSEL_UA0CTS = 4, /*!< UA0CTS : Configure as the UART0 CTS input */ - GPIO_PADREGP_PAD62FNCSEL_UA0RTS = 5, /*!< UA0RTS : Configure as the UART0 RTS output */ - GPIO_PADREGP_PAD62FNCSEL_UA1CTS = 6, /*!< UA1CTS : Configure as the UART1 CTS input */ - GPIO_PADREGP_PAD62FNCSEL_UA1RTS = 7, /*!< UA1RTS : Configure as the UART1 RTS output */ -} GPIO_PADREGP_PAD62FNCSEL_Enum; - -/* =========================================== GPIO PADREGP PAD62STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGP_PAD62STRNG */ - GPIO_PADREGP_PAD62STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGP_PAD62STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGP_PAD62STRNG_Enum; - -/* =========================================== GPIO PADREGP PAD62INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGP_PAD62INPEN */ - GPIO_PADREGP_PAD62INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGP_PAD62INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGP_PAD62INPEN_Enum; - -/* ============================================ GPIO PADREGP PAD62PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGP_PAD62PULL */ - GPIO_PADREGP_PAD62PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGP_PAD62PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGP_PAD62PULL_Enum; - -/* =========================================== GPIO PADREGP PAD61FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGP_PAD61FNCSEL */ - GPIO_PADREGP_PAD61FNCSEL_SWO = 0, /*!< SWO : Configure as the SWO output */ - GPIO_PADREGP_PAD61FNCSEL_NCE61 = 1, /*!< NCE61 : IOM/MSPI nCE group 61 */ - GPIO_PADREGP_PAD61FNCSEL_CT11 = 2, /*!< CT11 : CTIMER connection 11 */ - GPIO_PADREGP_PAD61FNCSEL_GPIO61 = 3, /*!< GPIO61 : Configure as GPIO61 */ - GPIO_PADREGP_PAD61FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as the UART0 TX output */ - GPIO_PADREGP_PAD61FNCSEL_UART0RX = 5, /*!< UART0RX : Configure as the UART0 RX input */ - GPIO_PADREGP_PAD61FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output */ - GPIO_PADREGP_PAD61FNCSEL_UART1RX = 7, /*!< UART1RX : Configure as the UART1 RX input */ -} GPIO_PADREGP_PAD61FNCSEL_Enum; - -/* =========================================== GPIO PADREGP PAD61STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGP_PAD61STRNG */ - GPIO_PADREGP_PAD61STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGP_PAD61STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGP_PAD61STRNG_Enum; - -/* ============================================ GPIO PADREGP PAD61INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGP_PAD61INPEN */ - GPIO_PADREGP_PAD61INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGP_PAD61INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGP_PAD61INPEN_Enum; - -/* ============================================= GPIO PADREGP PAD61PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGP_PAD61PULL */ - GPIO_PADREGP_PAD61PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGP_PAD61PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGP_PAD61PULL_Enum; - -/* ============================================ GPIO PADREGP PAD60FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGP_PAD60FNCSEL */ - GPIO_PADREGP_PAD60FNCSEL_MSPI1_9 = 0, /*!< MSPI1_9 : Configure as the MSPI1 9 signal */ - GPIO_PADREGP_PAD60FNCSEL_NCE60 = 1, /*!< NCE60 : IOM/MSPI nCE group 60 */ - GPIO_PADREGP_PAD60FNCSEL_CT10 = 2, /*!< CT10 : CTIMER connection 10 */ - GPIO_PADREGP_PAD60FNCSEL_GPIO60 = 3, /*!< GPIO60 : Configure as GPIO60 */ -} GPIO_PADREGP_PAD60FNCSEL_Enum; - -/* ============================================ GPIO PADREGP PAD60STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGP_PAD60STRNG */ - GPIO_PADREGP_PAD60STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGP_PAD60STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGP_PAD60STRNG_Enum; - -/* ============================================ GPIO PADREGP PAD60INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGP_PAD60INPEN */ - GPIO_PADREGP_PAD60INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGP_PAD60INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGP_PAD60INPEN_Enum; - -/* ============================================= GPIO PADREGP PAD60PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGP_PAD60PULL */ - GPIO_PADREGP_PAD60PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGP_PAD60PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGP_PAD60PULL_Enum; - -/* ======================================================== PADREGQ ======================================================== */ -/* =========================================== GPIO PADREGQ PAD67FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGQ_PAD67FNCSEL */ - GPIO_PADREGQ_PAD67FNCSEL_MSPI2_3 = 0, /*!< MSPI2_3 : Configure as the MSPI2 3 signal */ - GPIO_PADREGQ_PAD67FNCSEL_NCE67 = 1, /*!< NCE67 : IOM/MSPI nCE group 67 */ - GPIO_PADREGQ_PAD67FNCSEL_CT17 = 2, /*!< CT17 : CTIMER connection 17 */ - GPIO_PADREGQ_PAD67FNCSEL_GPIO67 = 3, /*!< GPIO67 : Configure as GPIO67 */ -} GPIO_PADREGQ_PAD67FNCSEL_Enum; - -/* =========================================== GPIO PADREGQ PAD67STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGQ_PAD67STRNG */ - GPIO_PADREGQ_PAD67STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGQ_PAD67STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGQ_PAD67STRNG_Enum; - -/* =========================================== GPIO PADREGQ PAD67INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGQ_PAD67INPEN */ - GPIO_PADREGQ_PAD67INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGQ_PAD67INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGQ_PAD67INPEN_Enum; - -/* ============================================ GPIO PADREGQ PAD67PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGQ_PAD67PULL */ - GPIO_PADREGQ_PAD67PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGQ_PAD67PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGQ_PAD67PULL_Enum; - -/* =========================================== GPIO PADREGQ PAD66FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGQ_PAD66FNCSEL */ - GPIO_PADREGQ_PAD66FNCSEL_MSPI2_2 = 0, /*!< MSPI2_2 : Configure as the MSPI2 2 signal */ - GPIO_PADREGQ_PAD66FNCSEL_NCE66 = 1, /*!< NCE66 : IOM/MSPI nCE group 66 */ - GPIO_PADREGQ_PAD66FNCSEL_CT16 = 2, /*!< CT16 : CTIMER connection 16 */ - GPIO_PADREGQ_PAD66FNCSEL_GPIO66 = 3, /*!< GPIO66 : Configure as GPIO66 */ -} GPIO_PADREGQ_PAD66FNCSEL_Enum; - -/* =========================================== GPIO PADREGQ PAD66STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGQ_PAD66STRNG */ - GPIO_PADREGQ_PAD66STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGQ_PAD66STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGQ_PAD66STRNG_Enum; - -/* =========================================== GPIO PADREGQ PAD66INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGQ_PAD66INPEN */ - GPIO_PADREGQ_PAD66INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGQ_PAD66INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGQ_PAD66INPEN_Enum; - -/* ============================================ GPIO PADREGQ PAD66PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGQ_PAD66PULL */ - GPIO_PADREGQ_PAD66PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGQ_PAD66PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGQ_PAD66PULL_Enum; - -/* =========================================== GPIO PADREGQ PAD65FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGQ_PAD65FNCSEL */ - GPIO_PADREGQ_PAD65FNCSEL_MSPI2_1 = 0, /*!< MSPI2_1 : Configure as the MSPI2 1 signal */ - GPIO_PADREGQ_PAD65FNCSEL_NCE65 = 1, /*!< NCE65 : IOM/MSPI nCE group 65 */ - GPIO_PADREGQ_PAD65FNCSEL_CT15 = 2, /*!< CT15 : CTIMER connection 15 */ - GPIO_PADREGQ_PAD65FNCSEL_GPIO65 = 3, /*!< GPIO65 : Configure as GPIO65 */ -} GPIO_PADREGQ_PAD65FNCSEL_Enum; - -/* =========================================== GPIO PADREGQ PAD65STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGQ_PAD65STRNG */ - GPIO_PADREGQ_PAD65STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGQ_PAD65STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGQ_PAD65STRNG_Enum; - -/* ============================================ GPIO PADREGQ PAD65INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGQ_PAD65INPEN */ - GPIO_PADREGQ_PAD65INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGQ_PAD65INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGQ_PAD65INPEN_Enum; - -/* ============================================= GPIO PADREGQ PAD65PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGQ_PAD65PULL */ - GPIO_PADREGQ_PAD65PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGQ_PAD65PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGQ_PAD65PULL_Enum; - -/* ============================================ GPIO PADREGQ PAD64FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGQ_PAD64FNCSEL */ - GPIO_PADREGQ_PAD64FNCSEL_MSPI2_0 = 0, /*!< MSPI2_0 : Configure as the MSPI2 0 signal */ - GPIO_PADREGQ_PAD64FNCSEL_NCE64 = 1, /*!< NCE64 : IOM/MSPI nCE group 64 */ - GPIO_PADREGQ_PAD64FNCSEL_CT14 = 2, /*!< CT14 : CTIMER connection 14 */ - GPIO_PADREGQ_PAD64FNCSEL_GPIO64 = 3, /*!< GPIO64 : Configure as GPIO64 */ -} GPIO_PADREGQ_PAD64FNCSEL_Enum; - -/* ============================================ GPIO PADREGQ PAD64STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGQ_PAD64STRNG */ - GPIO_PADREGQ_PAD64STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGQ_PAD64STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGQ_PAD64STRNG_Enum; - -/* ============================================ GPIO PADREGQ PAD64INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGQ_PAD64INPEN */ - GPIO_PADREGQ_PAD64INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGQ_PAD64INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGQ_PAD64INPEN_Enum; - -/* ============================================= GPIO PADREGQ PAD64PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGQ_PAD64PULL */ - GPIO_PADREGQ_PAD64PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGQ_PAD64PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGQ_PAD64PULL_Enum; - -/* ======================================================== PADREGR ======================================================== */ -/* =========================================== GPIO PADREGR PAD71FNCSEL [27..29] =========================================== */ -typedef enum { /*!< GPIO_PADREGR_PAD71FNCSEL */ - GPIO_PADREGR_PAD71FNCSEL_SWO = 0, /*!< SWO : Configure as the SWO output */ - GPIO_PADREGR_PAD71FNCSEL_NCE71 = 1, /*!< NCE71 : IOM/MSPI nCE group 71 */ - GPIO_PADREGR_PAD71FNCSEL_CT21 = 2, /*!< CT21 : CTIMER connection 21 */ - GPIO_PADREGR_PAD71FNCSEL_GPIO71 = 3, /*!< GPIO71 : Configure as GPIO71 */ - GPIO_PADREGR_PAD71FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as the UART0 TX output */ - GPIO_PADREGR_PAD71FNCSEL_UART0RX = 5, /*!< UART0RX : Configure as the UART0 RX input */ - GPIO_PADREGR_PAD71FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output */ - GPIO_PADREGR_PAD71FNCSEL_UART1RX = 7, /*!< UART1RX : Configure as the UART1 RX input */ -} GPIO_PADREGR_PAD71FNCSEL_Enum; - -/* =========================================== GPIO PADREGR PAD71STRNG [26..26] ============================================ */ -typedef enum { /*!< GPIO_PADREGR_PAD71STRNG */ - GPIO_PADREGR_PAD71STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGR_PAD71STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGR_PAD71STRNG_Enum; - -/* =========================================== GPIO PADREGR PAD71INPEN [25..25] ============================================ */ -typedef enum { /*!< GPIO_PADREGR_PAD71INPEN */ - GPIO_PADREGR_PAD71INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGR_PAD71INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGR_PAD71INPEN_Enum; - -/* ============================================ GPIO PADREGR PAD71PULL [24..24] ============================================ */ -typedef enum { /*!< GPIO_PADREGR_PAD71PULL */ - GPIO_PADREGR_PAD71PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGR_PAD71PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGR_PAD71PULL_Enum; - -/* =========================================== GPIO PADREGR PAD70FNCSEL [19..21] =========================================== */ -typedef enum { /*!< GPIO_PADREGR_PAD70FNCSEL */ - GPIO_PADREGR_PAD70FNCSEL_SWO = 0, /*!< SWO : Configure as the SWO output */ - GPIO_PADREGR_PAD70FNCSEL_NCE70 = 1, /*!< NCE70 : IOM/MSPI nCE group 70 */ - GPIO_PADREGR_PAD70FNCSEL_CT20 = 2, /*!< CT20 : CTIMER connection 20 */ - GPIO_PADREGR_PAD70FNCSEL_GPIO70 = 3, /*!< GPIO70 : Configure as GPIO70 */ - GPIO_PADREGR_PAD70FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as the UART0 TX output */ - GPIO_PADREGR_PAD70FNCSEL_UART0RX = 5, /*!< UART0RX : Configure as the UART0 RX input */ - GPIO_PADREGR_PAD70FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output */ - GPIO_PADREGR_PAD70FNCSEL_UART1RX = 7, /*!< UART1RX : Configure as the UART1 RX input */ -} GPIO_PADREGR_PAD70FNCSEL_Enum; - -/* =========================================== GPIO PADREGR PAD70STRNG [18..18] ============================================ */ -typedef enum { /*!< GPIO_PADREGR_PAD70STRNG */ - GPIO_PADREGR_PAD70STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGR_PAD70STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGR_PAD70STRNG_Enum; - -/* =========================================== GPIO PADREGR PAD70INPEN [17..17] ============================================ */ -typedef enum { /*!< GPIO_PADREGR_PAD70INPEN */ - GPIO_PADREGR_PAD70INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGR_PAD70INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGR_PAD70INPEN_Enum; - -/* ============================================ GPIO PADREGR PAD70PULL [16..16] ============================================ */ -typedef enum { /*!< GPIO_PADREGR_PAD70PULL */ - GPIO_PADREGR_PAD70PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGR_PAD70PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGR_PAD70PULL_Enum; - -/* =========================================== GPIO PADREGR PAD69FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGR_PAD69FNCSEL */ - GPIO_PADREGR_PAD69FNCSEL_SWO = 0, /*!< SWO : Configure as the SWO output */ - GPIO_PADREGR_PAD69FNCSEL_NCE69 = 1, /*!< NCE69 : IOM/MSPI nCE group 69 */ - GPIO_PADREGR_PAD69FNCSEL_CT19 = 2, /*!< CT19 : CTIMER connection 19 */ - GPIO_PADREGR_PAD69FNCSEL_GPIO69 = 3, /*!< GPIO69 : Configure as GPIO69 */ - GPIO_PADREGR_PAD69FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as the UART0 TX output */ - GPIO_PADREGR_PAD69FNCSEL_UART0RX = 5, /*!< UART0RX : Configure as the UART0 RX input */ - GPIO_PADREGR_PAD69FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output */ - GPIO_PADREGR_PAD69FNCSEL_UART1RX = 7, /*!< UART1RX : Configure as the UART1 RX input */ -} GPIO_PADREGR_PAD69FNCSEL_Enum; - -/* =========================================== GPIO PADREGR PAD69STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGR_PAD69STRNG */ - GPIO_PADREGR_PAD69STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGR_PAD69STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGR_PAD69STRNG_Enum; - -/* ============================================ GPIO PADREGR PAD69INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGR_PAD69INPEN */ - GPIO_PADREGR_PAD69INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGR_PAD69INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGR_PAD69INPEN_Enum; - -/* ============================================= GPIO PADREGR PAD69PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGR_PAD69PULL */ - GPIO_PADREGR_PAD69PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGR_PAD69PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGR_PAD69PULL_Enum; - -/* ============================================ GPIO PADREGR PAD68FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGR_PAD68FNCSEL */ - GPIO_PADREGR_PAD68FNCSEL_MSPI2_4 = 0, /*!< MSPI2_4 : Configure as the MSPI2 4 signal */ - GPIO_PADREGR_PAD68FNCSEL_NCE68 = 1, /*!< NCE68 : IOM/MSPI nCE group 68 */ - GPIO_PADREGR_PAD68FNCSEL_CT18 = 2, /*!< CT18 : CTIMER connection 18 */ - GPIO_PADREGR_PAD68FNCSEL_GPIO68 = 3, /*!< GPIO68 : Configure as GPIO68 */ -} GPIO_PADREGR_PAD68FNCSEL_Enum; - -/* ============================================ GPIO PADREGR PAD68STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGR_PAD68STRNG */ - GPIO_PADREGR_PAD68STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGR_PAD68STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGR_PAD68STRNG_Enum; - -/* ============================================ GPIO PADREGR PAD68INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGR_PAD68INPEN */ - GPIO_PADREGR_PAD68INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGR_PAD68INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGR_PAD68INPEN_Enum; - -/* ============================================= GPIO PADREGR PAD68PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGR_PAD68PULL */ - GPIO_PADREGR_PAD68PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGR_PAD68PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGR_PAD68PULL_Enum; - -/* ======================================================== PADREGS ======================================================== */ -/* =========================================== GPIO PADREGS PAD73FNCSEL [11..13] =========================================== */ -typedef enum { /*!< GPIO_PADREGS_PAD73FNCSEL */ - GPIO_PADREGS_PAD73FNCSEL_SWO = 0, /*!< SWO : Configure as the SWO output */ - GPIO_PADREGS_PAD73FNCSEL_NCE73 = 1, /*!< NCE73 : IOM/MSPI nCE group 73 */ - GPIO_PADREGS_PAD73FNCSEL_CT23 = 2, /*!< CT23 : CTIMER connection 23 */ - GPIO_PADREGS_PAD73FNCSEL_GPIO73 = 3, /*!< GPIO73 : Configure as GPIO73 */ - GPIO_PADREGS_PAD73FNCSEL_UA0CTS = 4, /*!< UA0CTS : Configure as the UART0 CTS input */ - GPIO_PADREGS_PAD73FNCSEL_UA0RTS = 5, /*!< UA0RTS : Configure as the UART0 RTS output */ - GPIO_PADREGS_PAD73FNCSEL_UA1CTS = 6, /*!< UA1CTS : Configure as the UART1 CTS input */ - GPIO_PADREGS_PAD73FNCSEL_UA1RTS = 7, /*!< UA1RTS : Configure as the UART1 RTS output */ -} GPIO_PADREGS_PAD73FNCSEL_Enum; - -/* =========================================== GPIO PADREGS PAD73STRNG [10..10] ============================================ */ -typedef enum { /*!< GPIO_PADREGS_PAD73STRNG */ - GPIO_PADREGS_PAD73STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGS_PAD73STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGS_PAD73STRNG_Enum; - -/* ============================================ GPIO PADREGS PAD73INPEN [9..9] ============================================= */ -typedef enum { /*!< GPIO_PADREGS_PAD73INPEN */ - GPIO_PADREGS_PAD73INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGS_PAD73INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGS_PAD73INPEN_Enum; - -/* ============================================= GPIO PADREGS PAD73PULL [8..8] ============================================= */ -typedef enum { /*!< GPIO_PADREGS_PAD73PULL */ - GPIO_PADREGS_PAD73PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGS_PAD73PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGS_PAD73PULL_Enum; - -/* ============================================ GPIO PADREGS PAD72FNCSEL [3..5] ============================================ */ -typedef enum { /*!< GPIO_PADREGS_PAD72FNCSEL */ - GPIO_PADREGS_PAD72FNCSEL_SWO = 0, /*!< SWO : Configure as the SWO output */ - GPIO_PADREGS_PAD72FNCSEL_NCE72 = 1, /*!< NCE72 : IOM/MSPI nCE group 72 */ - GPIO_PADREGS_PAD72FNCSEL_CT22 = 2, /*!< CT22 : CTIMER connection 22 */ - GPIO_PADREGS_PAD72FNCSEL_GPIO72 = 3, /*!< GPIO72 : Configure as GPIO72 */ - GPIO_PADREGS_PAD72FNCSEL_UART0TX = 4, /*!< UART0TX : Configure as the UART0 TX output */ - GPIO_PADREGS_PAD72FNCSEL_UART0RX = 5, /*!< UART0RX : Configure as the UART0 RX input */ - GPIO_PADREGS_PAD72FNCSEL_UART1TX = 6, /*!< UART1TX : Configure as the UART1 TX output */ - GPIO_PADREGS_PAD72FNCSEL_UART1RX = 7, /*!< UART1RX : Configure as the UART1 RX input */ -} GPIO_PADREGS_PAD72FNCSEL_Enum; - -/* ============================================ GPIO PADREGS PAD72STRNG [2..2] ============================================= */ -typedef enum { /*!< GPIO_PADREGS_PAD72STRNG */ - GPIO_PADREGS_PAD72STRNG_LOW = 0, /*!< LOW : Low drive strength */ - GPIO_PADREGS_PAD72STRNG_HIGH = 1, /*!< HIGH : High drive strength */ -} GPIO_PADREGS_PAD72STRNG_Enum; - -/* ============================================ GPIO PADREGS PAD72INPEN [1..1] ============================================= */ -typedef enum { /*!< GPIO_PADREGS_PAD72INPEN */ - GPIO_PADREGS_PAD72INPEN_DIS = 0, /*!< DIS : Pad input disabled */ - GPIO_PADREGS_PAD72INPEN_EN = 1, /*!< EN : Pad input enabled */ -} GPIO_PADREGS_PAD72INPEN_Enum; - -/* ============================================= GPIO PADREGS PAD72PULL [0..0] ============================================= */ -typedef enum { /*!< GPIO_PADREGS_PAD72PULL */ - GPIO_PADREGS_PAD72PULL_DIS = 0, /*!< DIS : Pullup disabled */ - GPIO_PADREGS_PAD72PULL_EN = 1, /*!< EN : Pullup enabled */ -} GPIO_PADREGS_PAD72PULL_Enum; - -/* ========================================================= CFGA ========================================================== */ -/* ============================================= GPIO CFGA GPIO7INTD [31..31] ============================================== */ -typedef enum { /*!< GPIO_CFGA_GPIO7INTD */ - GPIO_CFGA_GPIO7INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD7FNCSEL = NCE7 - nCE polarity active - low */ - GPIO_CFGA_GPIO7INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD7FNCSEL = NCE7 - nCE polarity active - high */ -} GPIO_CFGA_GPIO7INTD_Enum; - -/* ============================================ GPIO CFGA GPIO7OUTCFG [29..30] ============================================= */ -typedef enum { /*!< GPIO_CFGA_GPIO7OUTCFG */ - GPIO_CFGA_GPIO7OUTCFG_DIS = 0, /*!< DIS : Applies when PAD7FNCSEL = GPIO - Output disabled */ - GPIO_CFGA_GPIO7OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD7FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGA_GPIO7OUTCFG_OD = 2, /*!< OD : Applies when PAD7FNCSEL = GPIO - Output is open drain */ - GPIO_CFGA_GPIO7OUTCFG_TS = 3, /*!< TS : Applies when PAD7FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGA_GPIO7OUTCFG_Enum; - -/* ============================================= GPIO CFGA GPIO7INCFG [28..28] ============================================= */ -typedef enum { /*!< GPIO_CFGA_GPIO7INCFG */ - GPIO_CFGA_GPIO7INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGA_GPIO7INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGA_GPIO7INCFG_Enum; - -/* ============================================= GPIO CFGA GPIO6INTD [27..27] ============================================== */ -typedef enum { /*!< GPIO_CFGA_GPIO6INTD */ - GPIO_CFGA_GPIO6INTD_INTDIS = 0, /*!< INTDIS : Applies when GPIO6INCFG = 1 - No interrupt on GPIO - transition */ - GPIO_CFGA_GPIO6INTD_INTBOTH = 1, /*!< INTBOTH : Applies when GPIO6INCFG = 1 - Interrupt on either - low to high or high to low GPIO transition */ -} GPIO_CFGA_GPIO6INTD_Enum; - -/* ============================================ GPIO CFGA GPIO6OUTCFG [25..26] ============================================= */ -typedef enum { /*!< GPIO_CFGA_GPIO6OUTCFG */ - GPIO_CFGA_GPIO6OUTCFG_DIS = 0, /*!< DIS : Applies when PAD6FNCSEL = GPIO - Output disabled */ - GPIO_CFGA_GPIO6OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD6FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGA_GPIO6OUTCFG_OD = 2, /*!< OD : Applies when PAD6FNCSEL = GPIO - Output is open drain */ - GPIO_CFGA_GPIO6OUTCFG_TS = 3, /*!< TS : Applies when PAD6FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGA_GPIO6OUTCFG_Enum; - -/* ============================================= GPIO CFGA GPIO6INCFG [24..24] ============================================= */ -typedef enum { /*!< GPIO_CFGA_GPIO6INCFG */ - GPIO_CFGA_GPIO6INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGA_GPIO6INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGA_GPIO6INCFG_Enum; - -/* ============================================= GPIO CFGA GPIO5INTD [23..23] ============================================== */ -typedef enum { /*!< GPIO_CFGA_GPIO5INTD */ - GPIO_CFGA_GPIO5INTD_INTDIS = 0, /*!< INTDIS : Applies when GPIO5INCFG = 1 - No interrupt on GPIO - transition */ - GPIO_CFGA_GPIO5INTD_INTBOTH = 1, /*!< INTBOTH : Applies when GPIO5INCFG = 1 - Interrupt on either - low to high or high to low GPIO transition */ -} GPIO_CFGA_GPIO5INTD_Enum; - -/* ============================================ GPIO CFGA GPIO5OUTCFG [21..22] ============================================= */ -typedef enum { /*!< GPIO_CFGA_GPIO5OUTCFG */ - GPIO_CFGA_GPIO5OUTCFG_DIS = 0, /*!< DIS : Applies when PAD5FNCSEL = GPIO - Output disabled */ - GPIO_CFGA_GPIO5OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD5FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGA_GPIO5OUTCFG_OD = 2, /*!< OD : Applies when PAD5FNCSEL = GPIO - Output is open drain */ - GPIO_CFGA_GPIO5OUTCFG_TS = 3, /*!< TS : Applies when PAD5FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGA_GPIO5OUTCFG_Enum; - -/* ============================================= GPIO CFGA GPIO5INCFG [20..20] ============================================= */ -typedef enum { /*!< GPIO_CFGA_GPIO5INCFG */ - GPIO_CFGA_GPIO5INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGA_GPIO5INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGA_GPIO5INCFG_Enum; - -/* ============================================= GPIO CFGA GPIO4INTD [19..19] ============================================== */ -typedef enum { /*!< GPIO_CFGA_GPIO4INTD */ - GPIO_CFGA_GPIO4INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD4FNCSEL = NCE4 - nCE polarity active - low */ - GPIO_CFGA_GPIO4INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD4FNCSEL = NCE4 - nCE polarity active - high */ -} GPIO_CFGA_GPIO4INTD_Enum; - -/* ============================================ GPIO CFGA GPIO4OUTCFG [17..18] ============================================= */ -typedef enum { /*!< GPIO_CFGA_GPIO4OUTCFG */ - GPIO_CFGA_GPIO4OUTCFG_DIS = 0, /*!< DIS : Applies when PAD4FNCSEL = GPIO - Output disabled */ - GPIO_CFGA_GPIO4OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD4FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGA_GPIO4OUTCFG_OD = 2, /*!< OD : Applies when PAD4FNCSEL = GPIO - Output is open drain */ - GPIO_CFGA_GPIO4OUTCFG_TS = 3, /*!< TS : Applies when PAD4FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGA_GPIO4OUTCFG_Enum; - -/* ============================================= GPIO CFGA GPIO4INCFG [16..16] ============================================= */ -typedef enum { /*!< GPIO_CFGA_GPIO4INCFG */ - GPIO_CFGA_GPIO4INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGA_GPIO4INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGA_GPIO4INCFG_Enum; - -/* ============================================= GPIO CFGA GPIO3INTD [15..15] ============================================== */ -typedef enum { /*!< GPIO_CFGA_GPIO3INTD */ - GPIO_CFGA_GPIO3INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD3FNCSEL = NCE3 - nCE polarity active - low */ - GPIO_CFGA_GPIO3INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD3FNCSEL = NCE3 - nCE polarity active - high */ -} GPIO_CFGA_GPIO3INTD_Enum; - -/* ============================================ GPIO CFGA GPIO3OUTCFG [13..14] ============================================= */ -typedef enum { /*!< GPIO_CFGA_GPIO3OUTCFG */ - GPIO_CFGA_GPIO3OUTCFG_DIS = 0, /*!< DIS : Applies when PAD3FNCSEL = GPIO - Output disabled */ - GPIO_CFGA_GPIO3OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD3FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGA_GPIO3OUTCFG_OD = 2, /*!< OD : Applies when PAD3FNCSEL = GPIO - Output is open drain */ - GPIO_CFGA_GPIO3OUTCFG_TS = 3, /*!< TS : Applies when PAD3FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGA_GPIO3OUTCFG_Enum; - -/* ============================================= GPIO CFGA GPIO3INCFG [12..12] ============================================= */ -typedef enum { /*!< GPIO_CFGA_GPIO3INCFG */ - GPIO_CFGA_GPIO3INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGA_GPIO3INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGA_GPIO3INCFG_Enum; - -/* ============================================= GPIO CFGA GPIO2INTD [11..11] ============================================== */ -typedef enum { /*!< GPIO_CFGA_GPIO2INTD */ - GPIO_CFGA_GPIO2INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD2FNCSEL = NCE2 - nCE polarity active - low */ - GPIO_CFGA_GPIO2INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD2FNCSEL = NCE2 - nCE polarity active - high */ -} GPIO_CFGA_GPIO2INTD_Enum; - -/* ============================================= GPIO CFGA GPIO2OUTCFG [9..10] ============================================= */ -typedef enum { /*!< GPIO_CFGA_GPIO2OUTCFG */ - GPIO_CFGA_GPIO2OUTCFG_DIS = 0, /*!< DIS : Applies when PAD2FNCSEL = GPIO - Output disabled */ - GPIO_CFGA_GPIO2OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD2FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGA_GPIO2OUTCFG_OD = 2, /*!< OD : Applies when PAD2FNCSEL = GPIO - Output is open drain */ - GPIO_CFGA_GPIO2OUTCFG_TS = 3, /*!< TS : Applies when PAD2FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGA_GPIO2OUTCFG_Enum; - -/* ============================================== GPIO CFGA GPIO2INCFG [8..8] ============================================== */ -typedef enum { /*!< GPIO_CFGA_GPIO2INCFG */ - GPIO_CFGA_GPIO2INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGA_GPIO2INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGA_GPIO2INCFG_Enum; - -/* ============================================== GPIO CFGA GPIO1INTD [7..7] =============================================== */ -typedef enum { /*!< GPIO_CFGA_GPIO1INTD */ - GPIO_CFGA_GPIO1INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD1FNCSEL = NCE1 - nCE polarity active - low */ - GPIO_CFGA_GPIO1INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD1FNCSEL = NCE1 - nCE polarity active - high */ -} GPIO_CFGA_GPIO1INTD_Enum; - -/* ============================================= GPIO CFGA GPIO1OUTCFG [5..6] ============================================== */ -typedef enum { /*!< GPIO_CFGA_GPIO1OUTCFG */ - GPIO_CFGA_GPIO1OUTCFG_DIS = 0, /*!< DIS : Applies when PAD1FNCSEL = GPIO - Output disabled */ - GPIO_CFGA_GPIO1OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD1FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGA_GPIO1OUTCFG_OD = 2, /*!< OD : Applies when PAD1FNCSEL = GPIO - Output is open drain */ - GPIO_CFGA_GPIO1OUTCFG_TS = 3, /*!< TS : Applies when PAD1FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGA_GPIO1OUTCFG_Enum; - -/* ============================================== GPIO CFGA GPIO1INCFG [4..4] ============================================== */ -typedef enum { /*!< GPIO_CFGA_GPIO1INCFG */ - GPIO_CFGA_GPIO1INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGA_GPIO1INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGA_GPIO1INCFG_Enum; - -/* ============================================== GPIO CFGA GPIO0INTD [3..3] =============================================== */ -typedef enum { /*!< GPIO_CFGA_GPIO0INTD */ - GPIO_CFGA_GPIO0INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD0FNCSEL = NCE0 - nCE polarity active - low */ - GPIO_CFGA_GPIO0INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD0FNCSEL = NCE0 - nCE polarity active - high */ -} GPIO_CFGA_GPIO0INTD_Enum; - -/* ============================================= GPIO CFGA GPIO0OUTCFG [1..2] ============================================== */ -typedef enum { /*!< GPIO_CFGA_GPIO0OUTCFG */ - GPIO_CFGA_GPIO0OUTCFG_DIS = 0, /*!< DIS : Applies when PAD0FNCSEL = GPIO - Output disabled */ - GPIO_CFGA_GPIO0OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD0FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGA_GPIO0OUTCFG_OD = 2, /*!< OD : Applies when PAD0FNCSEL = GPIO - Output is open drain */ - GPIO_CFGA_GPIO0OUTCFG_TS = 3, /*!< TS : Applies when PAD0FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGA_GPIO0OUTCFG_Enum; - -/* ============================================== GPIO CFGA GPIO0INCFG [0..0] ============================================== */ -typedef enum { /*!< GPIO_CFGA_GPIO0INCFG */ - GPIO_CFGA_GPIO0INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGA_GPIO0INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGA_GPIO0INCFG_Enum; - -/* ========================================================= CFGB ========================================================== */ -/* ============================================= GPIO CFGB GPIO15INTD [31..31] ============================================= */ -typedef enum { /*!< GPIO_CFGB_GPIO15INTD */ - GPIO_CFGB_GPIO15INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD15FNCSEL = NCE15 - nCE polarity active - low */ - GPIO_CFGB_GPIO15INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD15FNCSEL = NCE15 - nCE polarity active - high */ -} GPIO_CFGB_GPIO15INTD_Enum; - -/* ============================================ GPIO CFGB GPIO15OUTCFG [29..30] ============================================ */ -typedef enum { /*!< GPIO_CFGB_GPIO15OUTCFG */ - GPIO_CFGB_GPIO15OUTCFG_DIS = 0, /*!< DIS : Applies when PAD15FNCSEL = GPIO - Output disabled */ - GPIO_CFGB_GPIO15OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD15FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGB_GPIO15OUTCFG_OD = 2, /*!< OD : Applies when PAD15FNCSEL = GPIO - Output is open drain */ - GPIO_CFGB_GPIO15OUTCFG_TS = 3, /*!< TS : Applies when PAD15FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGB_GPIO15OUTCFG_Enum; - -/* ============================================ GPIO CFGB GPIO15INCFG [28..28] ============================================= */ -typedef enum { /*!< GPIO_CFGB_GPIO15INCFG */ - GPIO_CFGB_GPIO15INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGB_GPIO15INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGB_GPIO15INCFG_Enum; - -/* ============================================= GPIO CFGB GPIO14INTD [27..27] ============================================= */ -typedef enum { /*!< GPIO_CFGB_GPIO14INTD */ - GPIO_CFGB_GPIO14INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD14FNCSEL = NCE14 - nCE polarity active - low */ - GPIO_CFGB_GPIO14INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD14FNCSEL = NCE14 - nCE polarity active - high */ -} GPIO_CFGB_GPIO14INTD_Enum; - -/* ============================================ GPIO CFGB GPIO14OUTCFG [25..26] ============================================ */ -typedef enum { /*!< GPIO_CFGB_GPIO14OUTCFG */ - GPIO_CFGB_GPIO14OUTCFG_DIS = 0, /*!< DIS : Applies when PAD14FNCSEL = GPIO - Output disabled */ - GPIO_CFGB_GPIO14OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD14FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGB_GPIO14OUTCFG_OD = 2, /*!< OD : Applies when PAD14FNCSEL = GPIO - Output is open drain */ - GPIO_CFGB_GPIO14OUTCFG_TS = 3, /*!< TS : Applies when PAD14FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGB_GPIO14OUTCFG_Enum; - -/* ============================================ GPIO CFGB GPIO14INCFG [24..24] ============================================= */ -typedef enum { /*!< GPIO_CFGB_GPIO14INCFG */ - GPIO_CFGB_GPIO14INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGB_GPIO14INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGB_GPIO14INCFG_Enum; - -/* ============================================= GPIO CFGB GPIO13INTD [23..23] ============================================= */ -typedef enum { /*!< GPIO_CFGB_GPIO13INTD */ - GPIO_CFGB_GPIO13INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD13FNCSEL = NCE13 - nCE polarity active - low */ - GPIO_CFGB_GPIO13INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD13FNCSEL = NCE13 - nCE polarity active - high */ -} GPIO_CFGB_GPIO13INTD_Enum; - -/* ============================================ GPIO CFGB GPIO13OUTCFG [21..22] ============================================ */ -typedef enum { /*!< GPIO_CFGB_GPIO13OUTCFG */ - GPIO_CFGB_GPIO13OUTCFG_DIS = 0, /*!< DIS : Applies when PAD13FNCSEL = GPIO - Output disabled */ - GPIO_CFGB_GPIO13OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD13FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGB_GPIO13OUTCFG_OD = 2, /*!< OD : Applies when PAD13FNCSEL = GPIO - Output is open drain */ - GPIO_CFGB_GPIO13OUTCFG_TS = 3, /*!< TS : Applies when PAD13FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGB_GPIO13OUTCFG_Enum; - -/* ============================================ GPIO CFGB GPIO13INCFG [20..20] ============================================= */ -typedef enum { /*!< GPIO_CFGB_GPIO13INCFG */ - GPIO_CFGB_GPIO13INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGB_GPIO13INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGB_GPIO13INCFG_Enum; - -/* ============================================= GPIO CFGB GPIO12INTD [19..19] ============================================= */ -typedef enum { /*!< GPIO_CFGB_GPIO12INTD */ - GPIO_CFGB_GPIO12INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD12FNCSEL = NCE12 - nCE polarity active - low */ - GPIO_CFGB_GPIO12INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD12FNCSEL = NCE12 - nCE polarity active - high */ -} GPIO_CFGB_GPIO12INTD_Enum; - -/* ============================================ GPIO CFGB GPIO12OUTCFG [17..18] ============================================ */ -typedef enum { /*!< GPIO_CFGB_GPIO12OUTCFG */ - GPIO_CFGB_GPIO12OUTCFG_DIS = 0, /*!< DIS : Applies when PAD12FNCSEL = GPIO - Output disabled */ - GPIO_CFGB_GPIO12OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD12FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGB_GPIO12OUTCFG_OD = 2, /*!< OD : Applies when PAD12FNCSEL = GPIO - Output is open drain */ - GPIO_CFGB_GPIO12OUTCFG_TS = 3, /*!< TS : Applies when PAD12FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGB_GPIO12OUTCFG_Enum; - -/* ============================================ GPIO CFGB GPIO12INCFG [16..16] ============================================= */ -typedef enum { /*!< GPIO_CFGB_GPIO12INCFG */ - GPIO_CFGB_GPIO12INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGB_GPIO12INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGB_GPIO12INCFG_Enum; - -/* ============================================= GPIO CFGB GPIO11INTD [15..15] ============================================= */ -typedef enum { /*!< GPIO_CFGB_GPIO11INTD */ - GPIO_CFGB_GPIO11INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD11FNCSEL = NCE11 - nCE polarity active - low */ - GPIO_CFGB_GPIO11INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD11FNCSEL = NCE11 - nCE polarity active - high */ -} GPIO_CFGB_GPIO11INTD_Enum; - -/* ============================================ GPIO CFGB GPIO11OUTCFG [13..14] ============================================ */ -typedef enum { /*!< GPIO_CFGB_GPIO11OUTCFG */ - GPIO_CFGB_GPIO11OUTCFG_DIS = 0, /*!< DIS : Applies when PAD11FNCSEL = GPIO - Output disabled */ - GPIO_CFGB_GPIO11OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD11FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGB_GPIO11OUTCFG_OD = 2, /*!< OD : Applies when PAD11FNCSEL = GPIO - Output is open drain */ - GPIO_CFGB_GPIO11OUTCFG_TS = 3, /*!< TS : Applies when PAD11FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGB_GPIO11OUTCFG_Enum; - -/* ============================================ GPIO CFGB GPIO11INCFG [12..12] ============================================= */ -typedef enum { /*!< GPIO_CFGB_GPIO11INCFG */ - GPIO_CFGB_GPIO11INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGB_GPIO11INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGB_GPIO11INCFG_Enum; - -/* ============================================= GPIO CFGB GPIO10INTD [11..11] ============================================= */ -typedef enum { /*!< GPIO_CFGB_GPIO10INTD */ - GPIO_CFGB_GPIO10INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD10FNCSEL = NCE10 - nCE polarity active - low */ - GPIO_CFGB_GPIO10INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD10FNCSEL = NCE10 - nCE polarity active - high */ -} GPIO_CFGB_GPIO10INTD_Enum; - -/* ============================================ GPIO CFGB GPIO10OUTCFG [9..10] ============================================= */ -typedef enum { /*!< GPIO_CFGB_GPIO10OUTCFG */ - GPIO_CFGB_GPIO10OUTCFG_DIS = 0, /*!< DIS : Applies when PAD10FNCSEL = GPIO - Output disabled */ - GPIO_CFGB_GPIO10OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD10FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGB_GPIO10OUTCFG_OD = 2, /*!< OD : Applies when PAD10FNCSEL = GPIO - Output is open drain */ - GPIO_CFGB_GPIO10OUTCFG_TS = 3, /*!< TS : Applies when PAD10FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGB_GPIO10OUTCFG_Enum; - -/* ============================================= GPIO CFGB GPIO10INCFG [8..8] ============================================== */ -typedef enum { /*!< GPIO_CFGB_GPIO10INCFG */ - GPIO_CFGB_GPIO10INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGB_GPIO10INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGB_GPIO10INCFG_Enum; - -/* ============================================== GPIO CFGB GPIO9INTD [7..7] =============================================== */ -typedef enum { /*!< GPIO_CFGB_GPIO9INTD */ - GPIO_CFGB_GPIO9INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD9FNCSEL = NCE9 - nCE polarity active - low */ - GPIO_CFGB_GPIO9INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD9FNCSEL = NCE9 - nCE polarity active - high */ -} GPIO_CFGB_GPIO9INTD_Enum; - -/* ============================================= GPIO CFGB GPIO9OUTCFG [5..6] ============================================== */ -typedef enum { /*!< GPIO_CFGB_GPIO9OUTCFG */ - GPIO_CFGB_GPIO9OUTCFG_DIS = 0, /*!< DIS : Applies when PAD9FNCSEL = GPIO - Output disabled */ - GPIO_CFGB_GPIO9OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD9FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGB_GPIO9OUTCFG_OD = 2, /*!< OD : Applies when PAD9FNCSEL = GPIO - Output is open drain */ - GPIO_CFGB_GPIO9OUTCFG_TS = 3, /*!< TS : Applies when PAD9FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGB_GPIO9OUTCFG_Enum; - -/* ============================================== GPIO CFGB GPIO9INCFG [4..4] ============================================== */ -typedef enum { /*!< GPIO_CFGB_GPIO9INCFG */ - GPIO_CFGB_GPIO9INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGB_GPIO9INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGB_GPIO9INCFG_Enum; - -/* ============================================== GPIO CFGB GPIO8INTD [3..3] =============================================== */ -typedef enum { /*!< GPIO_CFGB_GPIO8INTD */ - GPIO_CFGB_GPIO8INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD8FNCSEL = NCE8 - nCE polarity active - low */ - GPIO_CFGB_GPIO8INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD8FNCSEL = NCE8 - nCE polarity active - high */ -} GPIO_CFGB_GPIO8INTD_Enum; - -/* ============================================= GPIO CFGB GPIO8OUTCFG [1..2] ============================================== */ -typedef enum { /*!< GPIO_CFGB_GPIO8OUTCFG */ - GPIO_CFGB_GPIO8OUTCFG_DIS = 0, /*!< DIS : Applies when PAD8FNCSEL = GPIO - Output disabled */ - GPIO_CFGB_GPIO8OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD8FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGB_GPIO8OUTCFG_OD = 2, /*!< OD : Applies when PAD8FNCSEL = GPIO - Output is open drain */ - GPIO_CFGB_GPIO8OUTCFG_TS = 3, /*!< TS : Applies when PAD8FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGB_GPIO8OUTCFG_Enum; - -/* ============================================== GPIO CFGB GPIO8INCFG [0..0] ============================================== */ -typedef enum { /*!< GPIO_CFGB_GPIO8INCFG */ - GPIO_CFGB_GPIO8INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGB_GPIO8INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGB_GPIO8INCFG_Enum; - -/* ========================================================= CFGC ========================================================== */ -/* ============================================= GPIO CFGC GPIO23INTD [31..31] ============================================= */ -typedef enum { /*!< GPIO_CFGC_GPIO23INTD */ - GPIO_CFGC_GPIO23INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD23FNCSEL = NCE23 - nCE polarity active - low */ - GPIO_CFGC_GPIO23INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD23FNCSEL = NCE23 - nCE polarity active - high */ -} GPIO_CFGC_GPIO23INTD_Enum; - -/* ============================================ GPIO CFGC GPIO23OUTCFG [29..30] ============================================ */ -typedef enum { /*!< GPIO_CFGC_GPIO23OUTCFG */ - GPIO_CFGC_GPIO23OUTCFG_DIS = 0, /*!< DIS : Applies when PAD23FNCSEL = GPIO - Output disabled */ - GPIO_CFGC_GPIO23OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD23FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGC_GPIO23OUTCFG_OD = 2, /*!< OD : Applies when PAD23FNCSEL = GPIO - Output is open drain */ - GPIO_CFGC_GPIO23OUTCFG_TS = 3, /*!< TS : Applies when PAD23FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGC_GPIO23OUTCFG_Enum; - -/* ============================================ GPIO CFGC GPIO23INCFG [28..28] ============================================= */ -typedef enum { /*!< GPIO_CFGC_GPIO23INCFG */ - GPIO_CFGC_GPIO23INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGC_GPIO23INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGC_GPIO23INCFG_Enum; - -/* ============================================= GPIO CFGC GPIO22INTD [27..27] ============================================= */ -typedef enum { /*!< GPIO_CFGC_GPIO22INTD */ - GPIO_CFGC_GPIO22INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD22FNCSEL = NCE22 - nCE polarity active - low */ - GPIO_CFGC_GPIO22INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD22FNCSEL = NCE22 - nCE polarity active - high */ -} GPIO_CFGC_GPIO22INTD_Enum; - -/* ============================================ GPIO CFGC GPIO22OUTCFG [25..26] ============================================ */ -typedef enum { /*!< GPIO_CFGC_GPIO22OUTCFG */ - GPIO_CFGC_GPIO22OUTCFG_DIS = 0, /*!< DIS : Applies when PAD22FNCSEL = GPIO - Output disabled */ - GPIO_CFGC_GPIO22OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD22FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGC_GPIO22OUTCFG_OD = 2, /*!< OD : Applies when PAD22FNCSEL = GPIO - Output is open drain */ - GPIO_CFGC_GPIO22OUTCFG_TS = 3, /*!< TS : Applies when PAD22FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGC_GPIO22OUTCFG_Enum; - -/* ============================================ GPIO CFGC GPIO22INCFG [24..24] ============================================= */ -typedef enum { /*!< GPIO_CFGC_GPIO22INCFG */ - GPIO_CFGC_GPIO22INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGC_GPIO22INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGC_GPIO22INCFG_Enum; - -/* ============================================= GPIO CFGC GPIO21INTD [23..23] ============================================= */ -typedef enum { /*!< GPIO_CFGC_GPIO21INTD */ - GPIO_CFGC_GPIO21INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD21FNCSEL = NCE21 - nCE polarity active - low */ - GPIO_CFGC_GPIO21INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD21FNCSEL = NCE21 - nCE polarity active - high */ -} GPIO_CFGC_GPIO21INTD_Enum; - -/* ============================================ GPIO CFGC GPIO21OUTCFG [21..22] ============================================ */ -typedef enum { /*!< GPIO_CFGC_GPIO21OUTCFG */ - GPIO_CFGC_GPIO21OUTCFG_DIS = 0, /*!< DIS : Applies when PAD21FNCSEL = GPIO - Output disabled */ - GPIO_CFGC_GPIO21OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD21FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGC_GPIO21OUTCFG_OD = 2, /*!< OD : Applies when PAD21FNCSEL = GPIO - Output is open drain */ - GPIO_CFGC_GPIO21OUTCFG_TS = 3, /*!< TS : Applies when PAD21FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGC_GPIO21OUTCFG_Enum; - -/* ============================================ GPIO CFGC GPIO21INCFG [20..20] ============================================= */ -typedef enum { /*!< GPIO_CFGC_GPIO21INCFG */ - GPIO_CFGC_GPIO21INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGC_GPIO21INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGC_GPIO21INCFG_Enum; - -/* ============================================= GPIO CFGC GPIO20INTD [19..19] ============================================= */ -typedef enum { /*!< GPIO_CFGC_GPIO20INTD */ - GPIO_CFGC_GPIO20INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD20FNCSEL = NCE20 - nCE polarity active - low */ - GPIO_CFGC_GPIO20INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD20FNCSEL = NCE20 - nCE polarity active - high */ -} GPIO_CFGC_GPIO20INTD_Enum; - -/* ============================================ GPIO CFGC GPIO20OUTCFG [17..18] ============================================ */ -typedef enum { /*!< GPIO_CFGC_GPIO20OUTCFG */ - GPIO_CFGC_GPIO20OUTCFG_DIS = 0, /*!< DIS : Applies when PAD20FNCSEL = GPIO - Output disabled */ - GPIO_CFGC_GPIO20OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD20FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGC_GPIO20OUTCFG_OD = 2, /*!< OD : Applies when PAD20FNCSEL = GPIO - Output is open drain */ - GPIO_CFGC_GPIO20OUTCFG_TS = 3, /*!< TS : Applies when PAD20FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGC_GPIO20OUTCFG_Enum; - -/* ============================================ GPIO CFGC GPIO20INCFG [16..16] ============================================= */ -typedef enum { /*!< GPIO_CFGC_GPIO20INCFG */ - GPIO_CFGC_GPIO20INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGC_GPIO20INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGC_GPIO20INCFG_Enum; - -/* ============================================= GPIO CFGC GPIO19INTD [15..15] ============================================= */ -typedef enum { /*!< GPIO_CFGC_GPIO19INTD */ - GPIO_CFGC_GPIO19INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD19FNCSEL = NCE19 - nCE polarity active - low */ - GPIO_CFGC_GPIO19INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD19FNCSEL = NCE19 - nCE polarity active - high */ -} GPIO_CFGC_GPIO19INTD_Enum; - -/* ============================================ GPIO CFGC GPIO19OUTCFG [13..14] ============================================ */ -typedef enum { /*!< GPIO_CFGC_GPIO19OUTCFG */ - GPIO_CFGC_GPIO19OUTCFG_DIS = 0, /*!< DIS : Applies when PAD19FNCSEL = GPIO - Output disabled */ - GPIO_CFGC_GPIO19OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD19FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGC_GPIO19OUTCFG_OD = 2, /*!< OD : Applies when PAD19FNCSEL = GPIO - Output is open drain */ - GPIO_CFGC_GPIO19OUTCFG_TS = 3, /*!< TS : Applies when PAD19FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGC_GPIO19OUTCFG_Enum; - -/* ============================================ GPIO CFGC GPIO19INCFG [12..12] ============================================= */ -typedef enum { /*!< GPIO_CFGC_GPIO19INCFG */ - GPIO_CFGC_GPIO19INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGC_GPIO19INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGC_GPIO19INCFG_Enum; - -/* ============================================= GPIO CFGC GPIO18INTD [11..11] ============================================= */ -typedef enum { /*!< GPIO_CFGC_GPIO18INTD */ - GPIO_CFGC_GPIO18INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD18FNCSEL = NCE18 - nCE polarity active - low */ - GPIO_CFGC_GPIO18INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD18FNCSEL = NCE18 - nCE polarity active - high */ -} GPIO_CFGC_GPIO18INTD_Enum; - -/* ============================================ GPIO CFGC GPIO18OUTCFG [9..10] ============================================= */ -typedef enum { /*!< GPIO_CFGC_GPIO18OUTCFG */ - GPIO_CFGC_GPIO18OUTCFG_DIS = 0, /*!< DIS : Applies when PAD18FNCSEL = GPIO - Output disabled */ - GPIO_CFGC_GPIO18OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD18FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGC_GPIO18OUTCFG_OD = 2, /*!< OD : Applies when PAD18FNCSEL = GPIO - Output is open drain */ - GPIO_CFGC_GPIO18OUTCFG_TS = 3, /*!< TS : Applies when PAD18FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGC_GPIO18OUTCFG_Enum; - -/* ============================================= GPIO CFGC GPIO18INCFG [8..8] ============================================== */ -typedef enum { /*!< GPIO_CFGC_GPIO18INCFG */ - GPIO_CFGC_GPIO18INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGC_GPIO18INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGC_GPIO18INCFG_Enum; - -/* ============================================== GPIO CFGC GPIO17INTD [7..7] ============================================== */ -typedef enum { /*!< GPIO_CFGC_GPIO17INTD */ - GPIO_CFGC_GPIO17INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD17FNCSEL = NCE17 - nCE polarity active - low */ - GPIO_CFGC_GPIO17INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD17FNCSEL = NCE17 - nCE polarity active - high */ -} GPIO_CFGC_GPIO17INTD_Enum; - -/* ============================================= GPIO CFGC GPIO17OUTCFG [5..6] ============================================= */ -typedef enum { /*!< GPIO_CFGC_GPIO17OUTCFG */ - GPIO_CFGC_GPIO17OUTCFG_DIS = 0, /*!< DIS : Applies when PAD17FNCSEL = GPIO - Output disabled */ - GPIO_CFGC_GPIO17OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD17FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGC_GPIO17OUTCFG_OD = 2, /*!< OD : Applies when PAD17FNCSEL = GPIO - Output is open drain */ - GPIO_CFGC_GPIO17OUTCFG_TS = 3, /*!< TS : Applies when PAD17FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGC_GPIO17OUTCFG_Enum; - -/* ============================================= GPIO CFGC GPIO17INCFG [4..4] ============================================== */ -typedef enum { /*!< GPIO_CFGC_GPIO17INCFG */ - GPIO_CFGC_GPIO17INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGC_GPIO17INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGC_GPIO17INCFG_Enum; - -/* ============================================== GPIO CFGC GPIO16INTD [3..3] ============================================== */ -typedef enum { /*!< GPIO_CFGC_GPIO16INTD */ - GPIO_CFGC_GPIO16INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD16FNCSEL = NCE16 - nCE polarity active - low */ - GPIO_CFGC_GPIO16INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD16FNCSEL = NCE16 - nCE polarity active - high */ -} GPIO_CFGC_GPIO16INTD_Enum; - -/* ============================================= GPIO CFGC GPIO16OUTCFG [1..2] ============================================= */ -typedef enum { /*!< GPIO_CFGC_GPIO16OUTCFG */ - GPIO_CFGC_GPIO16OUTCFG_DIS = 0, /*!< DIS : Applies when PAD16FNCSEL = GPIO - Output disabled */ - GPIO_CFGC_GPIO16OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD16FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGC_GPIO16OUTCFG_OD = 2, /*!< OD : Applies when PAD16FNCSEL = GPIO - Output is open drain */ - GPIO_CFGC_GPIO16OUTCFG_TS = 3, /*!< TS : Applies when PAD16FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGC_GPIO16OUTCFG_Enum; - -/* ============================================= GPIO CFGC GPIO16INCFG [0..0] ============================================== */ -typedef enum { /*!< GPIO_CFGC_GPIO16INCFG */ - GPIO_CFGC_GPIO16INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGC_GPIO16INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGC_GPIO16INCFG_Enum; - -/* ========================================================= CFGD ========================================================== */ -/* ============================================= GPIO CFGD GPIO31INTD [31..31] ============================================= */ -typedef enum { /*!< GPIO_CFGD_GPIO31INTD */ - GPIO_CFGD_GPIO31INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD31FNCSEL = NCE31 - nCE polarity active - low */ - GPIO_CFGD_GPIO31INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD31FNCSEL = NCE31 - nCE polarity active - high */ -} GPIO_CFGD_GPIO31INTD_Enum; - -/* ============================================ GPIO CFGD GPIO31OUTCFG [29..30] ============================================ */ -typedef enum { /*!< GPIO_CFGD_GPIO31OUTCFG */ - GPIO_CFGD_GPIO31OUTCFG_DIS = 0, /*!< DIS : Applies when PAD31FNCSEL = GPIO - Output disabled */ - GPIO_CFGD_GPIO31OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD31FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGD_GPIO31OUTCFG_OD = 2, /*!< OD : Applies when PAD31FNCSEL = GPIO - Output is open drain */ - GPIO_CFGD_GPIO31OUTCFG_TS = 3, /*!< TS : Applies when PAD31FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGD_GPIO31OUTCFG_Enum; - -/* ============================================ GPIO CFGD GPIO31INCFG [28..28] ============================================= */ -typedef enum { /*!< GPIO_CFGD_GPIO31INCFG */ - GPIO_CFGD_GPIO31INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGD_GPIO31INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGD_GPIO31INCFG_Enum; - -/* ============================================= GPIO CFGD GPIO30INTD [27..27] ============================================= */ -typedef enum { /*!< GPIO_CFGD_GPIO30INTD */ - GPIO_CFGD_GPIO30INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD30FNCSEL = NCE30 - nCE polarity active - low */ - GPIO_CFGD_GPIO30INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD30FNCSEL = NCE30 - nCE polarity active - high */ -} GPIO_CFGD_GPIO30INTD_Enum; - -/* ============================================ GPIO CFGD GPIO30OUTCFG [25..26] ============================================ */ -typedef enum { /*!< GPIO_CFGD_GPIO30OUTCFG */ - GPIO_CFGD_GPIO30OUTCFG_DIS = 0, /*!< DIS : Applies when PAD30FNCSEL = GPIO - Output disabled */ - GPIO_CFGD_GPIO30OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD30FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGD_GPIO30OUTCFG_OD = 2, /*!< OD : Applies when PAD30FNCSEL = GPIO - Output is open drain */ - GPIO_CFGD_GPIO30OUTCFG_TS = 3, /*!< TS : Applies when PAD30FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGD_GPIO30OUTCFG_Enum; - -/* ============================================ GPIO CFGD GPIO30INCFG [24..24] ============================================= */ -typedef enum { /*!< GPIO_CFGD_GPIO30INCFG */ - GPIO_CFGD_GPIO30INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGD_GPIO30INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGD_GPIO30INCFG_Enum; - -/* ============================================= GPIO CFGD GPIO29INTD [23..23] ============================================= */ -typedef enum { /*!< GPIO_CFGD_GPIO29INTD */ - GPIO_CFGD_GPIO29INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD29FNCSEL = NCE29 - nCE polarity active - low */ - GPIO_CFGD_GPIO29INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD29FNCSEL = NCE29 - nCE polarity active - high */ -} GPIO_CFGD_GPIO29INTD_Enum; - -/* ============================================ GPIO CFGD GPIO29OUTCFG [21..22] ============================================ */ -typedef enum { /*!< GPIO_CFGD_GPIO29OUTCFG */ - GPIO_CFGD_GPIO29OUTCFG_DIS = 0, /*!< DIS : Applies when PAD29FNCSEL = GPIO - Output disabled */ - GPIO_CFGD_GPIO29OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD29FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGD_GPIO29OUTCFG_OD = 2, /*!< OD : Applies when PAD29FNCSEL = GPIO - Output is open drain */ - GPIO_CFGD_GPIO29OUTCFG_TS = 3, /*!< TS : Applies when PAD29FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGD_GPIO29OUTCFG_Enum; - -/* ============================================ GPIO CFGD GPIO29INCFG [20..20] ============================================= */ -typedef enum { /*!< GPIO_CFGD_GPIO29INCFG */ - GPIO_CFGD_GPIO29INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGD_GPIO29INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGD_GPIO29INCFG_Enum; - -/* ============================================= GPIO CFGD GPIO28INTD [19..19] ============================================= */ -typedef enum { /*!< GPIO_CFGD_GPIO28INTD */ - GPIO_CFGD_GPIO28INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD28FNCSEL = NCE28 - nCE polarity active - low */ - GPIO_CFGD_GPIO28INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD28FNCSEL = NCE28 - nCE polarity active - high */ -} GPIO_CFGD_GPIO28INTD_Enum; - -/* ============================================ GPIO CFGD GPIO28OUTCFG [17..18] ============================================ */ -typedef enum { /*!< GPIO_CFGD_GPIO28OUTCFG */ - GPIO_CFGD_GPIO28OUTCFG_DIS = 0, /*!< DIS : Applies when PAD28FNCSEL = GPIO - Output disabled */ - GPIO_CFGD_GPIO28OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD28FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGD_GPIO28OUTCFG_OD = 2, /*!< OD : Applies when PAD28FNCSEL = GPIO - Output is open drain */ - GPIO_CFGD_GPIO28OUTCFG_TS = 3, /*!< TS : Applies when PAD28FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGD_GPIO28OUTCFG_Enum; - -/* ============================================ GPIO CFGD GPIO28INCFG [16..16] ============================================= */ -typedef enum { /*!< GPIO_CFGD_GPIO28INCFG */ - GPIO_CFGD_GPIO28INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGD_GPIO28INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGD_GPIO28INCFG_Enum; - -/* ============================================= GPIO CFGD GPIO27INTD [15..15] ============================================= */ -typedef enum { /*!< GPIO_CFGD_GPIO27INTD */ - GPIO_CFGD_GPIO27INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD27FNCSEL = NCE27 - nCE polarity active - low */ - GPIO_CFGD_GPIO27INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD27FNCSEL = NCE27 - nCE polarity active - high */ -} GPIO_CFGD_GPIO27INTD_Enum; - -/* ============================================ GPIO CFGD GPIO27OUTCFG [13..14] ============================================ */ -typedef enum { /*!< GPIO_CFGD_GPIO27OUTCFG */ - GPIO_CFGD_GPIO27OUTCFG_DIS = 0, /*!< DIS : Applies when PAD27FNCSEL = GPIO - Output disabled */ - GPIO_CFGD_GPIO27OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD27FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGD_GPIO27OUTCFG_OD = 2, /*!< OD : Applies when PAD27FNCSEL = GPIO - Output is open drain */ - GPIO_CFGD_GPIO27OUTCFG_TS = 3, /*!< TS : Applies when PAD27FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGD_GPIO27OUTCFG_Enum; - -/* ============================================ GPIO CFGD GPIO27INCFG [12..12] ============================================= */ -typedef enum { /*!< GPIO_CFGD_GPIO27INCFG */ - GPIO_CFGD_GPIO27INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGD_GPIO27INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGD_GPIO27INCFG_Enum; - -/* ============================================= GPIO CFGD GPIO26INTD [11..11] ============================================= */ -typedef enum { /*!< GPIO_CFGD_GPIO26INTD */ - GPIO_CFGD_GPIO26INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD26FNCSEL = NCE26 - nCE polarity active - low */ - GPIO_CFGD_GPIO26INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD26FNCSEL = NCE26 - nCE polarity active - high */ -} GPIO_CFGD_GPIO26INTD_Enum; - -/* ============================================ GPIO CFGD GPIO26OUTCFG [9..10] ============================================= */ -typedef enum { /*!< GPIO_CFGD_GPIO26OUTCFG */ - GPIO_CFGD_GPIO26OUTCFG_DIS = 0, /*!< DIS : Applies when PAD26FNCSEL = GPIO - Output disabled */ - GPIO_CFGD_GPIO26OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD26FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGD_GPIO26OUTCFG_OD = 2, /*!< OD : Applies when PAD26FNCSEL = GPIO - Output is open drain */ - GPIO_CFGD_GPIO26OUTCFG_TS = 3, /*!< TS : Applies when PAD26FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGD_GPIO26OUTCFG_Enum; - -/* ============================================= GPIO CFGD GPIO26INCFG [8..8] ============================================== */ -typedef enum { /*!< GPIO_CFGD_GPIO26INCFG */ - GPIO_CFGD_GPIO26INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGD_GPIO26INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGD_GPIO26INCFG_Enum; - -/* ============================================== GPIO CFGD GPIO25INTD [7..7] ============================================== */ -typedef enum { /*!< GPIO_CFGD_GPIO25INTD */ - GPIO_CFGD_GPIO25INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD25FNCSEL = NCE25 - nCE polarity active - low */ - GPIO_CFGD_GPIO25INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD25FNCSEL = NCE25 - nCE polarity active - high */ -} GPIO_CFGD_GPIO25INTD_Enum; - -/* ============================================= GPIO CFGD GPIO25OUTCFG [5..6] ============================================= */ -typedef enum { /*!< GPIO_CFGD_GPIO25OUTCFG */ - GPIO_CFGD_GPIO25OUTCFG_DIS = 0, /*!< DIS : Applies when PAD25FNCSEL = GPIO - Output disabled */ - GPIO_CFGD_GPIO25OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD25FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGD_GPIO25OUTCFG_OD = 2, /*!< OD : Applies when PAD25FNCSEL = GPIO - Output is open drain */ - GPIO_CFGD_GPIO25OUTCFG_TS = 3, /*!< TS : Applies when PAD25FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGD_GPIO25OUTCFG_Enum; - -/* ============================================= GPIO CFGD GPIO25INCFG [4..4] ============================================== */ -typedef enum { /*!< GPIO_CFGD_GPIO25INCFG */ - GPIO_CFGD_GPIO25INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGD_GPIO25INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGD_GPIO25INCFG_Enum; - -/* ============================================== GPIO CFGD GPIO24INTD [3..3] ============================================== */ -typedef enum { /*!< GPIO_CFGD_GPIO24INTD */ - GPIO_CFGD_GPIO24INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD24FNCSEL = NCE24 - nCE polarity active - low */ - GPIO_CFGD_GPIO24INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD24FNCSEL = NCE24 - nCE polarity active - high */ -} GPIO_CFGD_GPIO24INTD_Enum; - -/* ============================================= GPIO CFGD GPIO24OUTCFG [1..2] ============================================= */ -typedef enum { /*!< GPIO_CFGD_GPIO24OUTCFG */ - GPIO_CFGD_GPIO24OUTCFG_DIS = 0, /*!< DIS : Applies when PAD24FNCSEL = GPIO - Output disabled */ - GPIO_CFGD_GPIO24OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD24FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGD_GPIO24OUTCFG_OD = 2, /*!< OD : Applies when PAD24FNCSEL = GPIO - Output is open drain */ - GPIO_CFGD_GPIO24OUTCFG_TS = 3, /*!< TS : Applies when PAD24FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGD_GPIO24OUTCFG_Enum; - -/* ============================================= GPIO CFGD GPIO24INCFG [0..0] ============================================== */ -typedef enum { /*!< GPIO_CFGD_GPIO24INCFG */ - GPIO_CFGD_GPIO24INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGD_GPIO24INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGD_GPIO24INCFG_Enum; - -/* ========================================================= CFGE ========================================================== */ -/* ============================================= GPIO CFGE GPIO39INTD [31..31] ============================================= */ -typedef enum { /*!< GPIO_CFGE_GPIO39INTD */ - GPIO_CFGE_GPIO39INTD_INTDIS = 0, /*!< INTDIS : Applies when GPIO39INCFG = 1 - No interrupt on GPIO - transition */ - GPIO_CFGE_GPIO39INTD_INTBOTH = 1, /*!< INTBOTH : Applies when GPIO39INCFG = 1 - Interrupt on either - low to high or high to low GPIO transition */ -} GPIO_CFGE_GPIO39INTD_Enum; - -/* ============================================ GPIO CFGE GPIO39OUTCFG [29..30] ============================================ */ -typedef enum { /*!< GPIO_CFGE_GPIO39OUTCFG */ - GPIO_CFGE_GPIO39OUTCFG_DIS = 0, /*!< DIS : Applies when PAD39FNCSEL = GPIO - Output disabled */ - GPIO_CFGE_GPIO39OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD39FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGE_GPIO39OUTCFG_OD = 2, /*!< OD : Applies when PAD39FNCSEL = GPIO - Output is open drain */ - GPIO_CFGE_GPIO39OUTCFG_TS = 3, /*!< TS : Applies when PAD39FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGE_GPIO39OUTCFG_Enum; - -/* ============================================ GPIO CFGE GPIO39INCFG [28..28] ============================================= */ -typedef enum { /*!< GPIO_CFGE_GPIO39INCFG */ - GPIO_CFGE_GPIO39INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGE_GPIO39INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGE_GPIO39INCFG_Enum; - -/* ============================================= GPIO CFGE GPIO38INTD [27..27] ============================================= */ -typedef enum { /*!< GPIO_CFGE_GPIO38INTD */ - GPIO_CFGE_GPIO38INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD38FNCSEL = NCE38 - nCE polarity active - low */ - GPIO_CFGE_GPIO38INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD38FNCSEL = NCE38 - nCE polarity active - high */ -} GPIO_CFGE_GPIO38INTD_Enum; - -/* ============================================ GPIO CFGE GPIO38OUTCFG [25..26] ============================================ */ -typedef enum { /*!< GPIO_CFGE_GPIO38OUTCFG */ - GPIO_CFGE_GPIO38OUTCFG_DIS = 0, /*!< DIS : Applies when PAD38FNCSEL = GPIO - Output disabled */ - GPIO_CFGE_GPIO38OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD38FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGE_GPIO38OUTCFG_OD = 2, /*!< OD : Applies when PAD38FNCSEL = GPIO - Output is open drain */ - GPIO_CFGE_GPIO38OUTCFG_TS = 3, /*!< TS : Applies when PAD38FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGE_GPIO38OUTCFG_Enum; - -/* ============================================ GPIO CFGE GPIO38INCFG [24..24] ============================================= */ -typedef enum { /*!< GPIO_CFGE_GPIO38INCFG */ - GPIO_CFGE_GPIO38INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGE_GPIO38INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGE_GPIO38INCFG_Enum; - -/* ============================================= GPIO CFGE GPIO37INTD [23..23] ============================================= */ -typedef enum { /*!< GPIO_CFGE_GPIO37INTD */ - GPIO_CFGE_GPIO37INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD37FNCSEL = NCE37 - nCE polarity active - low */ - GPIO_CFGE_GPIO37INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD37FNCSEL = NCE37 - nCE polarity active - high */ -} GPIO_CFGE_GPIO37INTD_Enum; - -/* ============================================ GPIO CFGE GPIO37OUTCFG [21..22] ============================================ */ -typedef enum { /*!< GPIO_CFGE_GPIO37OUTCFG */ - GPIO_CFGE_GPIO37OUTCFG_DIS = 0, /*!< DIS : Applies when PAD37FNCSEL = GPIO - Output disabled */ - GPIO_CFGE_GPIO37OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD37FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGE_GPIO37OUTCFG_OD = 2, /*!< OD : Applies when PAD37FNCSEL = GPIO - Output is open drain */ - GPIO_CFGE_GPIO37OUTCFG_TS = 3, /*!< TS : Applies when PAD37FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGE_GPIO37OUTCFG_Enum; - -/* ============================================ GPIO CFGE GPIO37INCFG [20..20] ============================================= */ -typedef enum { /*!< GPIO_CFGE_GPIO37INCFG */ - GPIO_CFGE_GPIO37INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGE_GPIO37INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGE_GPIO37INCFG_Enum; - -/* ============================================= GPIO CFGE GPIO36INTD [19..19] ============================================= */ -typedef enum { /*!< GPIO_CFGE_GPIO36INTD */ - GPIO_CFGE_GPIO36INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD36FNCSEL = NCE36 - nCE polarity active - low */ - GPIO_CFGE_GPIO36INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD36FNCSEL = NCE36 - nCE polarity active - high */ -} GPIO_CFGE_GPIO36INTD_Enum; - -/* ============================================ GPIO CFGE GPIO36OUTCFG [17..18] ============================================ */ -typedef enum { /*!< GPIO_CFGE_GPIO36OUTCFG */ - GPIO_CFGE_GPIO36OUTCFG_DIS = 0, /*!< DIS : Applies when PAD36FNCSEL = GPIO - Output disabled */ - GPIO_CFGE_GPIO36OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD36FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGE_GPIO36OUTCFG_OD = 2, /*!< OD : Applies when PAD36FNCSEL = GPIO - Output is open drain */ - GPIO_CFGE_GPIO36OUTCFG_TS = 3, /*!< TS : Applies when PAD36FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGE_GPIO36OUTCFG_Enum; - -/* ============================================ GPIO CFGE GPIO36INCFG [16..16] ============================================= */ -typedef enum { /*!< GPIO_CFGE_GPIO36INCFG */ - GPIO_CFGE_GPIO36INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGE_GPIO36INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGE_GPIO36INCFG_Enum; - -/* ============================================= GPIO CFGE GPIO35INTD [15..15] ============================================= */ -typedef enum { /*!< GPIO_CFGE_GPIO35INTD */ - GPIO_CFGE_GPIO35INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD35FNCSEL = NCE35 - nCE polarity active - low */ - GPIO_CFGE_GPIO35INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD35FNCSEL = NCE35 - nCE polarity active - high */ -} GPIO_CFGE_GPIO35INTD_Enum; - -/* ============================================ GPIO CFGE GPIO35OUTCFG [13..14] ============================================ */ -typedef enum { /*!< GPIO_CFGE_GPIO35OUTCFG */ - GPIO_CFGE_GPIO35OUTCFG_DIS = 0, /*!< DIS : Applies when PAD35FNCSEL = GPIO - Output disabled */ - GPIO_CFGE_GPIO35OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD35FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGE_GPIO35OUTCFG_OD = 2, /*!< OD : Applies when PAD35FNCSEL = GPIO - Output is open drain */ - GPIO_CFGE_GPIO35OUTCFG_TS = 3, /*!< TS : Applies when PAD35FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGE_GPIO35OUTCFG_Enum; - -/* ============================================ GPIO CFGE GPIO35INCFG [12..12] ============================================= */ -typedef enum { /*!< GPIO_CFGE_GPIO35INCFG */ - GPIO_CFGE_GPIO35INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGE_GPIO35INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGE_GPIO35INCFG_Enum; - -/* ============================================= GPIO CFGE GPIO34INTD [11..11] ============================================= */ -typedef enum { /*!< GPIO_CFGE_GPIO34INTD */ - GPIO_CFGE_GPIO34INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD34FNCSEL = NCE34 - nCE polarity active - low */ - GPIO_CFGE_GPIO34INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD34FNCSEL = NCE34 - nCE polarity active - high */ -} GPIO_CFGE_GPIO34INTD_Enum; - -/* ============================================ GPIO CFGE GPIO34OUTCFG [9..10] ============================================= */ -typedef enum { /*!< GPIO_CFGE_GPIO34OUTCFG */ - GPIO_CFGE_GPIO34OUTCFG_DIS = 0, /*!< DIS : Applies when PAD34FNCSEL = GPIO - Output disabled */ - GPIO_CFGE_GPIO34OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD34FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGE_GPIO34OUTCFG_OD = 2, /*!< OD : Applies when PAD34FNCSEL = GPIO - Output is open drain */ - GPIO_CFGE_GPIO34OUTCFG_TS = 3, /*!< TS : Applies when PAD34FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGE_GPIO34OUTCFG_Enum; - -/* ============================================= GPIO CFGE GPIO34INCFG [8..8] ============================================== */ -typedef enum { /*!< GPIO_CFGE_GPIO34INCFG */ - GPIO_CFGE_GPIO34INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGE_GPIO34INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGE_GPIO34INCFG_Enum; - -/* ============================================== GPIO CFGE GPIO33INTD [7..7] ============================================== */ -typedef enum { /*!< GPIO_CFGE_GPIO33INTD */ - GPIO_CFGE_GPIO33INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD33FNCSEL = NCE33 - nCE polarity active - low */ - GPIO_CFGE_GPIO33INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD33FNCSEL = NCE33 - nCE polarity active - high */ -} GPIO_CFGE_GPIO33INTD_Enum; - -/* ============================================= GPIO CFGE GPIO33OUTCFG [5..6] ============================================= */ -typedef enum { /*!< GPIO_CFGE_GPIO33OUTCFG */ - GPIO_CFGE_GPIO33OUTCFG_DIS = 0, /*!< DIS : Applies when PAD33FNCSEL = GPIO - Output disabled */ - GPIO_CFGE_GPIO33OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD33FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGE_GPIO33OUTCFG_OD = 2, /*!< OD : Applies when PAD33FNCSEL = GPIO - Output is open drain */ - GPIO_CFGE_GPIO33OUTCFG_TS = 3, /*!< TS : Applies when PAD33FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGE_GPIO33OUTCFG_Enum; - -/* ============================================= GPIO CFGE GPIO33INCFG [4..4] ============================================== */ -typedef enum { /*!< GPIO_CFGE_GPIO33INCFG */ - GPIO_CFGE_GPIO33INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGE_GPIO33INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGE_GPIO33INCFG_Enum; - -/* ============================================== GPIO CFGE GPIO32INTD [3..3] ============================================== */ -typedef enum { /*!< GPIO_CFGE_GPIO32INTD */ - GPIO_CFGE_GPIO32INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD32FNCSEL = NCE32 - nCE polarity active - low */ - GPIO_CFGE_GPIO32INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD32FNCSEL = NCE32 - nCE polarity active - high */ -} GPIO_CFGE_GPIO32INTD_Enum; - -/* ============================================= GPIO CFGE GPIO32OUTCFG [1..2] ============================================= */ -typedef enum { /*!< GPIO_CFGE_GPIO32OUTCFG */ - GPIO_CFGE_GPIO32OUTCFG_DIS = 0, /*!< DIS : Applies when PAD32FNCSEL = GPIO - Output disabled */ - GPIO_CFGE_GPIO32OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD32FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGE_GPIO32OUTCFG_OD = 2, /*!< OD : Applies when PAD32FNCSEL = GPIO - Output is open drain */ - GPIO_CFGE_GPIO32OUTCFG_TS = 3, /*!< TS : Applies when PAD32FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGE_GPIO32OUTCFG_Enum; - -/* ============================================= GPIO CFGE GPIO32INCFG [0..0] ============================================== */ -typedef enum { /*!< GPIO_CFGE_GPIO32INCFG */ - GPIO_CFGE_GPIO32INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGE_GPIO32INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGE_GPIO32INCFG_Enum; - -/* ========================================================= CFGF ========================================================== */ -/* ============================================= GPIO CFGF GPIO47INTD [31..31] ============================================= */ -typedef enum { /*!< GPIO_CFGF_GPIO47INTD */ - GPIO_CFGF_GPIO47INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD47FNCSEL = NCE47 - nCE polarity active - low */ - GPIO_CFGF_GPIO47INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD47FNCSEL = NCE47 - nCE polarity active - high */ -} GPIO_CFGF_GPIO47INTD_Enum; - -/* ============================================ GPIO CFGF GPIO47OUTCFG [29..30] ============================================ */ -typedef enum { /*!< GPIO_CFGF_GPIO47OUTCFG */ - GPIO_CFGF_GPIO47OUTCFG_DIS = 0, /*!< DIS : Applies when PAD47FNCSEL = GPIO - Output disabled */ - GPIO_CFGF_GPIO47OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD47FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGF_GPIO47OUTCFG_OD = 2, /*!< OD : Applies when PAD47FNCSEL = GPIO - Output is open drain */ - GPIO_CFGF_GPIO47OUTCFG_TS = 3, /*!< TS : Applies when PAD47FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGF_GPIO47OUTCFG_Enum; - -/* ============================================ GPIO CFGF GPIO47INCFG [28..28] ============================================= */ -typedef enum { /*!< GPIO_CFGF_GPIO47INCFG */ - GPIO_CFGF_GPIO47INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGF_GPIO47INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGF_GPIO47INCFG_Enum; - -/* ============================================= GPIO CFGF GPIO46INTD [27..27] ============================================= */ -typedef enum { /*!< GPIO_CFGF_GPIO46INTD */ - GPIO_CFGF_GPIO46INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD46FNCSEL = NCE46 - nCE polarity active - low */ - GPIO_CFGF_GPIO46INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD46FNCSEL = NCE46 - nCE polarity active - high */ -} GPIO_CFGF_GPIO46INTD_Enum; - -/* ============================================ GPIO CFGF GPIO46OUTCFG [25..26] ============================================ */ -typedef enum { /*!< GPIO_CFGF_GPIO46OUTCFG */ - GPIO_CFGF_GPIO46OUTCFG_DIS = 0, /*!< DIS : Applies when PAD46FNCSEL = GPIO - Output disabled */ - GPIO_CFGF_GPIO46OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD46FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGF_GPIO46OUTCFG_OD = 2, /*!< OD : Applies when PAD46FNCSEL = GPIO - Output is open drain */ - GPIO_CFGF_GPIO46OUTCFG_TS = 3, /*!< TS : Applies when PAD46FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGF_GPIO46OUTCFG_Enum; - -/* ============================================ GPIO CFGF GPIO46INCFG [24..24] ============================================= */ -typedef enum { /*!< GPIO_CFGF_GPIO46INCFG */ - GPIO_CFGF_GPIO46INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGF_GPIO46INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGF_GPIO46INCFG_Enum; - -/* ============================================= GPIO CFGF GPIO45INTD [23..23] ============================================= */ -typedef enum { /*!< GPIO_CFGF_GPIO45INTD */ - GPIO_CFGF_GPIO45INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD45FNCSEL = NCE45 - nCE polarity active - low */ - GPIO_CFGF_GPIO45INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD45FNCSEL = NCE45 - nCE polarity active - high */ -} GPIO_CFGF_GPIO45INTD_Enum; - -/* ============================================ GPIO CFGF GPIO45OUTCFG [21..22] ============================================ */ -typedef enum { /*!< GPIO_CFGF_GPIO45OUTCFG */ - GPIO_CFGF_GPIO45OUTCFG_DIS = 0, /*!< DIS : Applies when PAD45FNCSEL = GPIO - Output disabled */ - GPIO_CFGF_GPIO45OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD45FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGF_GPIO45OUTCFG_OD = 2, /*!< OD : Applies when PAD45FNCSEL = GPIO - Output is open drain */ - GPIO_CFGF_GPIO45OUTCFG_TS = 3, /*!< TS : Applies when PAD45FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGF_GPIO45OUTCFG_Enum; - -/* ============================================ GPIO CFGF GPIO45INCFG [20..20] ============================================= */ -typedef enum { /*!< GPIO_CFGF_GPIO45INCFG */ - GPIO_CFGF_GPIO45INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGF_GPIO45INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGF_GPIO45INCFG_Enum; - -/* ============================================= GPIO CFGF GPIO44INTD [19..19] ============================================= */ -typedef enum { /*!< GPIO_CFGF_GPIO44INTD */ - GPIO_CFGF_GPIO44INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD44FNCSEL = NCE44 - nCE polarity active - low */ - GPIO_CFGF_GPIO44INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD44FNCSEL = NCE44 - nCE polarity active - high */ -} GPIO_CFGF_GPIO44INTD_Enum; - -/* ============================================ GPIO CFGF GPIO44OUTCFG [17..18] ============================================ */ -typedef enum { /*!< GPIO_CFGF_GPIO44OUTCFG */ - GPIO_CFGF_GPIO44OUTCFG_DIS = 0, /*!< DIS : Applies when PAD44FNCSEL = GPIO - Output disabled */ - GPIO_CFGF_GPIO44OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD44FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGF_GPIO44OUTCFG_OD = 2, /*!< OD : Applies when PAD44FNCSEL = GPIO - Output is open drain */ - GPIO_CFGF_GPIO44OUTCFG_TS = 3, /*!< TS : Applies when PAD44FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGF_GPIO44OUTCFG_Enum; - -/* ============================================ GPIO CFGF GPIO44INCFG [16..16] ============================================= */ -typedef enum { /*!< GPIO_CFGF_GPIO44INCFG */ - GPIO_CFGF_GPIO44INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGF_GPIO44INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGF_GPIO44INCFG_Enum; - -/* ============================================= GPIO CFGF GPIO43INTD [15..15] ============================================= */ -typedef enum { /*!< GPIO_CFGF_GPIO43INTD */ - GPIO_CFGF_GPIO43INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD43FNCSEL = NCE43 - nCE polarity active - low */ - GPIO_CFGF_GPIO43INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD43FNCSEL = NCE43 - nCE polarity active - high */ -} GPIO_CFGF_GPIO43INTD_Enum; - -/* ============================================ GPIO CFGF GPIO43OUTCFG [13..14] ============================================ */ -typedef enum { /*!< GPIO_CFGF_GPIO43OUTCFG */ - GPIO_CFGF_GPIO43OUTCFG_DIS = 0, /*!< DIS : Applies when PAD43FNCSEL = GPIO - Output disabled */ - GPIO_CFGF_GPIO43OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD43FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGF_GPIO43OUTCFG_OD = 2, /*!< OD : Applies when PAD43FNCSEL = GPIO - Output is open drain */ - GPIO_CFGF_GPIO43OUTCFG_TS = 3, /*!< TS : Applies when PAD43FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGF_GPIO43OUTCFG_Enum; - -/* ============================================ GPIO CFGF GPIO43INCFG [12..12] ============================================= */ -typedef enum { /*!< GPIO_CFGF_GPIO43INCFG */ - GPIO_CFGF_GPIO43INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGF_GPIO43INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGF_GPIO43INCFG_Enum; - -/* ============================================= GPIO CFGF GPIO42INTD [11..11] ============================================= */ -typedef enum { /*!< GPIO_CFGF_GPIO42INTD */ - GPIO_CFGF_GPIO42INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD42FNCSEL = NCE42 - nCE polarity active - low */ - GPIO_CFGF_GPIO42INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD42FNCSEL = NCE42 - nCE polarity active - high */ -} GPIO_CFGF_GPIO42INTD_Enum; - -/* ============================================ GPIO CFGF GPIO42OUTCFG [9..10] ============================================= */ -typedef enum { /*!< GPIO_CFGF_GPIO42OUTCFG */ - GPIO_CFGF_GPIO42OUTCFG_DIS = 0, /*!< DIS : Applies when PAD42FNCSEL = GPIO - Output disabled */ - GPIO_CFGF_GPIO42OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD42FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGF_GPIO42OUTCFG_OD = 2, /*!< OD : Applies when PAD42FNCSEL = GPIO - Output is open drain */ - GPIO_CFGF_GPIO42OUTCFG_TS = 3, /*!< TS : Applies when PAD42FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGF_GPIO42OUTCFG_Enum; - -/* ============================================= GPIO CFGF GPIO42INCFG [8..8] ============================================== */ -typedef enum { /*!< GPIO_CFGF_GPIO42INCFG */ - GPIO_CFGF_GPIO42INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGF_GPIO42INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGF_GPIO42INCFG_Enum; - -/* ============================================== GPIO CFGF GPIO41INTD [7..7] ============================================== */ -typedef enum { /*!< GPIO_CFGF_GPIO41INTD */ - GPIO_CFGF_GPIO41INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD41FNCSEL = NCE41 - nCE polarity active - low */ - GPIO_CFGF_GPIO41INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD41FNCSEL = NCE41 - nCE polarity active - high */ -} GPIO_CFGF_GPIO41INTD_Enum; - -/* ============================================= GPIO CFGF GPIO41OUTCFG [5..6] ============================================= */ -typedef enum { /*!< GPIO_CFGF_GPIO41OUTCFG */ - GPIO_CFGF_GPIO41OUTCFG_DIS = 0, /*!< DIS : Applies when PAD41FNCSEL = GPIO - Output disabled */ - GPIO_CFGF_GPIO41OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD41FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGF_GPIO41OUTCFG_OD = 2, /*!< OD : Applies when PAD41FNCSEL = GPIO - Output is open drain */ - GPIO_CFGF_GPIO41OUTCFG_TS = 3, /*!< TS : Applies when PAD41FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGF_GPIO41OUTCFG_Enum; - -/* ============================================= GPIO CFGF GPIO41INCFG [4..4] ============================================== */ -typedef enum { /*!< GPIO_CFGF_GPIO41INCFG */ - GPIO_CFGF_GPIO41INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGF_GPIO41INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGF_GPIO41INCFG_Enum; - -/* ============================================== GPIO CFGF GPIO40INTD [3..3] ============================================== */ -typedef enum { /*!< GPIO_CFGF_GPIO40INTD */ - GPIO_CFGF_GPIO40INTD_INTDIS = 0, /*!< INTDIS : Applies when GPIO40INCFG = 1 - No interrupt on GPIO - transition */ - GPIO_CFGF_GPIO40INTD_INTBOTH = 1, /*!< INTBOTH : Applies when GPIO40INCFG = 1 - Interrupt on either - low to high or high to low GPIO transition */ -} GPIO_CFGF_GPIO40INTD_Enum; - -/* ============================================= GPIO CFGF GPIO40OUTCFG [1..2] ============================================= */ -typedef enum { /*!< GPIO_CFGF_GPIO40OUTCFG */ - GPIO_CFGF_GPIO40OUTCFG_DIS = 0, /*!< DIS : Applies when PAD40FNCSEL = GPIO - Output disabled */ - GPIO_CFGF_GPIO40OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD40FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGF_GPIO40OUTCFG_OD = 2, /*!< OD : Applies when PAD40FNCSEL = GPIO - Output is open drain */ - GPIO_CFGF_GPIO40OUTCFG_TS = 3, /*!< TS : Applies when PAD40FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGF_GPIO40OUTCFG_Enum; - -/* ============================================= GPIO CFGF GPIO40INCFG [0..0] ============================================== */ -typedef enum { /*!< GPIO_CFGF_GPIO40INCFG */ - GPIO_CFGF_GPIO40INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGF_GPIO40INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGF_GPIO40INCFG_Enum; - -/* ========================================================= CFGG ========================================================== */ -/* ============================================= GPIO CFGG GPIO55INTD [31..31] ============================================= */ -typedef enum { /*!< GPIO_CFGG_GPIO55INTD */ - GPIO_CFGG_GPIO55INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD55FNCSEL = NCE55 - nCE polarity active - low */ - GPIO_CFGG_GPIO55INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD55FNCSEL = NCE55 - nCE polarity active - high */ -} GPIO_CFGG_GPIO55INTD_Enum; - -/* ============================================ GPIO CFGG GPIO55OUTCFG [29..30] ============================================ */ -typedef enum { /*!< GPIO_CFGG_GPIO55OUTCFG */ - GPIO_CFGG_GPIO55OUTCFG_DIS = 0, /*!< DIS : Applies when PAD55FNCSEL = GPIO - Output disabled */ - GPIO_CFGG_GPIO55OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD55FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGG_GPIO55OUTCFG_OD = 2, /*!< OD : Applies when PAD55FNCSEL = GPIO - Output is open drain */ - GPIO_CFGG_GPIO55OUTCFG_TS = 3, /*!< TS : Applies when PAD55FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGG_GPIO55OUTCFG_Enum; - -/* ============================================ GPIO CFGG GPIO55INCFG [28..28] ============================================= */ -typedef enum { /*!< GPIO_CFGG_GPIO55INCFG */ - GPIO_CFGG_GPIO55INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGG_GPIO55INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGG_GPIO55INCFG_Enum; - -/* ============================================= GPIO CFGG GPIO54INTD [27..27] ============================================= */ -typedef enum { /*!< GPIO_CFGG_GPIO54INTD */ - GPIO_CFGG_GPIO54INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD54FNCSEL = NCE54 - nCE polarity active - low */ - GPIO_CFGG_GPIO54INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD54FNCSEL = NCE54 - nCE polarity active - high */ -} GPIO_CFGG_GPIO54INTD_Enum; - -/* ============================================ GPIO CFGG GPIO54OUTCFG [25..26] ============================================ */ -typedef enum { /*!< GPIO_CFGG_GPIO54OUTCFG */ - GPIO_CFGG_GPIO54OUTCFG_DIS = 0, /*!< DIS : Applies when PAD54FNCSEL = GPIO - Output disabled */ - GPIO_CFGG_GPIO54OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD54FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGG_GPIO54OUTCFG_OD = 2, /*!< OD : Applies when PAD54FNCSEL = GPIO - Output is open drain */ - GPIO_CFGG_GPIO54OUTCFG_TS = 3, /*!< TS : Applies when PAD54FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGG_GPIO54OUTCFG_Enum; - -/* ============================================ GPIO CFGG GPIO54INCFG [24..24] ============================================= */ -typedef enum { /*!< GPIO_CFGG_GPIO54INCFG */ - GPIO_CFGG_GPIO54INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGG_GPIO54INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGG_GPIO54INCFG_Enum; - -/* ============================================= GPIO CFGG GPIO53INTD [23..23] ============================================= */ -typedef enum { /*!< GPIO_CFGG_GPIO53INTD */ - GPIO_CFGG_GPIO53INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD53FNCSEL = NCE53 - nCE polarity active - low */ - GPIO_CFGG_GPIO53INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD53FNCSEL = NCE53 - nCE polarity active - high */ -} GPIO_CFGG_GPIO53INTD_Enum; - -/* ============================================ GPIO CFGG GPIO53OUTCFG [21..22] ============================================ */ -typedef enum { /*!< GPIO_CFGG_GPIO53OUTCFG */ - GPIO_CFGG_GPIO53OUTCFG_DIS = 0, /*!< DIS : Applies when PAD53FNCSEL = GPIO - Output disabled */ - GPIO_CFGG_GPIO53OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD53FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGG_GPIO53OUTCFG_OD = 2, /*!< OD : Applies when PAD53FNCSEL = GPIO - Output is open drain */ - GPIO_CFGG_GPIO53OUTCFG_TS = 3, /*!< TS : Applies when PAD53FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGG_GPIO53OUTCFG_Enum; - -/* ============================================ GPIO CFGG GPIO53INCFG [20..20] ============================================= */ -typedef enum { /*!< GPIO_CFGG_GPIO53INCFG */ - GPIO_CFGG_GPIO53INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGG_GPIO53INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGG_GPIO53INCFG_Enum; - -/* ============================================= GPIO CFGG GPIO52INTD [19..19] ============================================= */ -typedef enum { /*!< GPIO_CFGG_GPIO52INTD */ - GPIO_CFGG_GPIO52INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD52FNCSEL = NCE52 - nCE polarity active - low */ - GPIO_CFGG_GPIO52INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD52FNCSEL = NCE52 - nCE polarity active - high */ -} GPIO_CFGG_GPIO52INTD_Enum; - -/* ============================================ GPIO CFGG GPIO52OUTCFG [17..18] ============================================ */ -typedef enum { /*!< GPIO_CFGG_GPIO52OUTCFG */ - GPIO_CFGG_GPIO52OUTCFG_DIS = 0, /*!< DIS : Applies when PAD52FNCSEL = GPIO - Output disabled */ - GPIO_CFGG_GPIO52OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD52FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGG_GPIO52OUTCFG_OD = 2, /*!< OD : Applies when PAD52FNCSEL = GPIO - Output is open drain */ - GPIO_CFGG_GPIO52OUTCFG_TS = 3, /*!< TS : Applies when PAD52FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGG_GPIO52OUTCFG_Enum; - -/* ============================================ GPIO CFGG GPIO52INCFG [16..16] ============================================= */ -typedef enum { /*!< GPIO_CFGG_GPIO52INCFG */ - GPIO_CFGG_GPIO52INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGG_GPIO52INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGG_GPIO52INCFG_Enum; - -/* ============================================= GPIO CFGG GPIO51INTD [15..15] ============================================= */ -typedef enum { /*!< GPIO_CFGG_GPIO51INTD */ - GPIO_CFGG_GPIO51INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD51FNCSEL = NCE51 - nCE polarity active - low */ - GPIO_CFGG_GPIO51INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD51FNCSEL = NCE51 - nCE polarity active - high */ -} GPIO_CFGG_GPIO51INTD_Enum; - -/* ============================================ GPIO CFGG GPIO51OUTCFG [13..14] ============================================ */ -typedef enum { /*!< GPIO_CFGG_GPIO51OUTCFG */ - GPIO_CFGG_GPIO51OUTCFG_DIS = 0, /*!< DIS : Applies when PAD51FNCSEL = GPIO - Output disabled */ - GPIO_CFGG_GPIO51OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD51FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGG_GPIO51OUTCFG_OD = 2, /*!< OD : Applies when PAD51FNCSEL = GPIO - Output is open drain */ - GPIO_CFGG_GPIO51OUTCFG_TS = 3, /*!< TS : Applies when PAD51FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGG_GPIO51OUTCFG_Enum; - -/* ============================================ GPIO CFGG GPIO51INCFG [12..12] ============================================= */ -typedef enum { /*!< GPIO_CFGG_GPIO51INCFG */ - GPIO_CFGG_GPIO51INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGG_GPIO51INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGG_GPIO51INCFG_Enum; - -/* ============================================= GPIO CFGG GPIO50INTD [11..11] ============================================= */ -typedef enum { /*!< GPIO_CFGG_GPIO50INTD */ - GPIO_CFGG_GPIO50INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD50FNCSEL = NCE50 - nCE polarity active - low */ - GPIO_CFGG_GPIO50INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD50FNCSEL = NCE50 - nCE polarity active - high */ -} GPIO_CFGG_GPIO50INTD_Enum; - -/* ============================================ GPIO CFGG GPIO50OUTCFG [9..10] ============================================= */ -typedef enum { /*!< GPIO_CFGG_GPIO50OUTCFG */ - GPIO_CFGG_GPIO50OUTCFG_DIS = 0, /*!< DIS : Applies when PAD50FNCSEL = GPIO - Output disabled */ - GPIO_CFGG_GPIO50OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD50FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGG_GPIO50OUTCFG_OD = 2, /*!< OD : Applies when PAD50FNCSEL = GPIO - Output is open drain */ - GPIO_CFGG_GPIO50OUTCFG_TS = 3, /*!< TS : Applies when PAD50FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGG_GPIO50OUTCFG_Enum; - -/* ============================================= GPIO CFGG GPIO50INCFG [8..8] ============================================== */ -typedef enum { /*!< GPIO_CFGG_GPIO50INCFG */ - GPIO_CFGG_GPIO50INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGG_GPIO50INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGG_GPIO50INCFG_Enum; - -/* ============================================== GPIO CFGG GPIO49INTD [7..7] ============================================== */ -typedef enum { /*!< GPIO_CFGG_GPIO49INTD */ - GPIO_CFGG_GPIO49INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD49FNCSEL = NCE49 - nCE polarity active - low */ - GPIO_CFGG_GPIO49INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD49FNCSEL = NCE49 - nCE polarity active - high */ -} GPIO_CFGG_GPIO49INTD_Enum; - -/* ============================================= GPIO CFGG GPIO49OUTCFG [5..6] ============================================= */ -typedef enum { /*!< GPIO_CFGG_GPIO49OUTCFG */ - GPIO_CFGG_GPIO49OUTCFG_DIS = 0, /*!< DIS : Applies when PAD49FNCSEL = GPIO - Output disabled */ - GPIO_CFGG_GPIO49OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD49FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGG_GPIO49OUTCFG_OD = 2, /*!< OD : Applies when PAD49FNCSEL = GPIO - Output is open drain */ - GPIO_CFGG_GPIO49OUTCFG_TS = 3, /*!< TS : Applies when PAD49FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGG_GPIO49OUTCFG_Enum; - -/* ============================================= GPIO CFGG GPIO49INCFG [4..4] ============================================== */ -typedef enum { /*!< GPIO_CFGG_GPIO49INCFG */ - GPIO_CFGG_GPIO49INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGG_GPIO49INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGG_GPIO49INCFG_Enum; - -/* ============================================== GPIO CFGG GPIO48INTD [3..3] ============================================== */ -typedef enum { /*!< GPIO_CFGG_GPIO48INTD */ - GPIO_CFGG_GPIO48INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD48FNCSEL = NCE48 - nCE polarity active - low */ - GPIO_CFGG_GPIO48INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD48FNCSEL = NCE48 - nCE polarity active - high */ -} GPIO_CFGG_GPIO48INTD_Enum; - -/* ============================================= GPIO CFGG GPIO48OUTCFG [1..2] ============================================= */ -typedef enum { /*!< GPIO_CFGG_GPIO48OUTCFG */ - GPIO_CFGG_GPIO48OUTCFG_DIS = 0, /*!< DIS : Applies when PAD48FNCSEL = GPIO - Output disabled */ - GPIO_CFGG_GPIO48OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD48FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGG_GPIO48OUTCFG_OD = 2, /*!< OD : Applies when PAD48FNCSEL = GPIO - Output is open drain */ - GPIO_CFGG_GPIO48OUTCFG_TS = 3, /*!< TS : Applies when PAD48FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGG_GPIO48OUTCFG_Enum; - -/* ============================================= GPIO CFGG GPIO48INCFG [0..0] ============================================== */ -typedef enum { /*!< GPIO_CFGG_GPIO48INCFG */ - GPIO_CFGG_GPIO48INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGG_GPIO48INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGG_GPIO48INCFG_Enum; - -/* ========================================================= CFGH ========================================================== */ -/* ============================================= GPIO CFGH GPIO63INTD [31..31] ============================================= */ -typedef enum { /*!< GPIO_CFGH_GPIO63INTD */ - GPIO_CFGH_GPIO63INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD63FNCSEL = NCE63 - nCE polarity active - low */ - GPIO_CFGH_GPIO63INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD63FNCSEL = NCE63 - nCE polarity active - high */ -} GPIO_CFGH_GPIO63INTD_Enum; - -/* ============================================ GPIO CFGH GPIO63OUTCFG [29..30] ============================================ */ -typedef enum { /*!< GPIO_CFGH_GPIO63OUTCFG */ - GPIO_CFGH_GPIO63OUTCFG_DIS = 0, /*!< DIS : Applies when PAD63FNCSEL = GPIO - Output disabled */ - GPIO_CFGH_GPIO63OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD63FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGH_GPIO63OUTCFG_OD = 2, /*!< OD : Applies when PAD63FNCSEL = GPIO - Output is open drain */ - GPIO_CFGH_GPIO63OUTCFG_TS = 3, /*!< TS : Applies when PAD63FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGH_GPIO63OUTCFG_Enum; - -/* ============================================ GPIO CFGH GPIO63INCFG [28..28] ============================================= */ -typedef enum { /*!< GPIO_CFGH_GPIO63INCFG */ - GPIO_CFGH_GPIO63INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGH_GPIO63INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGH_GPIO63INCFG_Enum; - -/* ============================================= GPIO CFGH GPIO62INTD [27..27] ============================================= */ -typedef enum { /*!< GPIO_CFGH_GPIO62INTD */ - GPIO_CFGH_GPIO62INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD62FNCSEL = NCE62 - nCE polarity active - low */ - GPIO_CFGH_GPIO62INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD62FNCSEL = NCE62 - nCE polarity active - high */ -} GPIO_CFGH_GPIO62INTD_Enum; - -/* ============================================ GPIO CFGH GPIO62OUTCFG [25..26] ============================================ */ -typedef enum { /*!< GPIO_CFGH_GPIO62OUTCFG */ - GPIO_CFGH_GPIO62OUTCFG_DIS = 0, /*!< DIS : Applies when PAD62FNCSEL = GPIO - Output disabled */ - GPIO_CFGH_GPIO62OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD62FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGH_GPIO62OUTCFG_OD = 2, /*!< OD : Applies when PAD62FNCSEL = GPIO - Output is open drain */ - GPIO_CFGH_GPIO62OUTCFG_TS = 3, /*!< TS : Applies when PAD62FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGH_GPIO62OUTCFG_Enum; - -/* ============================================ GPIO CFGH GPIO62INCFG [24..24] ============================================= */ -typedef enum { /*!< GPIO_CFGH_GPIO62INCFG */ - GPIO_CFGH_GPIO62INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGH_GPIO62INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGH_GPIO62INCFG_Enum; - -/* ============================================= GPIO CFGH GPIO61INTD [23..23] ============================================= */ -typedef enum { /*!< GPIO_CFGH_GPIO61INTD */ - GPIO_CFGH_GPIO61INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD61FNCSEL = NCE61 - nCE polarity active - low */ - GPIO_CFGH_GPIO61INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD61FNCSEL = NCE61 - nCE polarity active - high */ -} GPIO_CFGH_GPIO61INTD_Enum; - -/* ============================================ GPIO CFGH GPIO61OUTCFG [21..22] ============================================ */ -typedef enum { /*!< GPIO_CFGH_GPIO61OUTCFG */ - GPIO_CFGH_GPIO61OUTCFG_DIS = 0, /*!< DIS : Applies when PAD61FNCSEL = GPIO - Output disabled */ - GPIO_CFGH_GPIO61OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD61FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGH_GPIO61OUTCFG_OD = 2, /*!< OD : Applies when PAD61FNCSEL = GPIO - Output is open drain */ - GPIO_CFGH_GPIO61OUTCFG_TS = 3, /*!< TS : Applies when PAD61FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGH_GPIO61OUTCFG_Enum; - -/* ============================================ GPIO CFGH GPIO61INCFG [20..20] ============================================= */ -typedef enum { /*!< GPIO_CFGH_GPIO61INCFG */ - GPIO_CFGH_GPIO61INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGH_GPIO61INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGH_GPIO61INCFG_Enum; - -/* ============================================= GPIO CFGH GPIO60INTD [19..19] ============================================= */ -typedef enum { /*!< GPIO_CFGH_GPIO60INTD */ - GPIO_CFGH_GPIO60INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD60FNCSEL = NCE60 - nCE polarity active - low */ - GPIO_CFGH_GPIO60INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD60FNCSEL = NCE60 - nCE polarity active - high */ -} GPIO_CFGH_GPIO60INTD_Enum; - -/* ============================================ GPIO CFGH GPIO60OUTCFG [17..18] ============================================ */ -typedef enum { /*!< GPIO_CFGH_GPIO60OUTCFG */ - GPIO_CFGH_GPIO60OUTCFG_DIS = 0, /*!< DIS : Applies when PAD60FNCSEL = GPIO - Output disabled */ - GPIO_CFGH_GPIO60OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD60FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGH_GPIO60OUTCFG_OD = 2, /*!< OD : Applies when PAD60FNCSEL = GPIO - Output is open drain */ - GPIO_CFGH_GPIO60OUTCFG_TS = 3, /*!< TS : Applies when PAD60FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGH_GPIO60OUTCFG_Enum; - -/* ============================================ GPIO CFGH GPIO60INCFG [16..16] ============================================= */ -typedef enum { /*!< GPIO_CFGH_GPIO60INCFG */ - GPIO_CFGH_GPIO60INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGH_GPIO60INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGH_GPIO60INCFG_Enum; - -/* ============================================= GPIO CFGH GPIO59INTD [15..15] ============================================= */ -typedef enum { /*!< GPIO_CFGH_GPIO59INTD */ - GPIO_CFGH_GPIO59INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD59FNCSEL = NCE59 - nCE polarity active - low */ - GPIO_CFGH_GPIO59INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD59FNCSEL = NCE59 - nCE polarity active - high */ -} GPIO_CFGH_GPIO59INTD_Enum; - -/* ============================================ GPIO CFGH GPIO59OUTCFG [13..14] ============================================ */ -typedef enum { /*!< GPIO_CFGH_GPIO59OUTCFG */ - GPIO_CFGH_GPIO59OUTCFG_DIS = 0, /*!< DIS : Applies when PAD59FNCSEL = GPIO - Output disabled */ - GPIO_CFGH_GPIO59OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD59FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGH_GPIO59OUTCFG_OD = 2, /*!< OD : Applies when PAD59FNCSEL = GPIO - Output is open drain */ - GPIO_CFGH_GPIO59OUTCFG_TS = 3, /*!< TS : Applies when PAD59FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGH_GPIO59OUTCFG_Enum; - -/* ============================================ GPIO CFGH GPIO59INCFG [12..12] ============================================= */ -typedef enum { /*!< GPIO_CFGH_GPIO59INCFG */ - GPIO_CFGH_GPIO59INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGH_GPIO59INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGH_GPIO59INCFG_Enum; - -/* ============================================= GPIO CFGH GPIO58INTD [11..11] ============================================= */ -typedef enum { /*!< GPIO_CFGH_GPIO58INTD */ - GPIO_CFGH_GPIO58INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD58FNCSEL = NCE58 - nCE polarity active - low */ - GPIO_CFGH_GPIO58INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD58FNCSEL = NCE58 - nCE polarity active - high */ -} GPIO_CFGH_GPIO58INTD_Enum; - -/* ============================================ GPIO CFGH GPIO58OUTCFG [9..10] ============================================= */ -typedef enum { /*!< GPIO_CFGH_GPIO58OUTCFG */ - GPIO_CFGH_GPIO58OUTCFG_DIS = 0, /*!< DIS : Applies when PAD58FNCSEL = GPIO - Output disabled */ - GPIO_CFGH_GPIO58OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD58FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGH_GPIO58OUTCFG_OD = 2, /*!< OD : Applies when PAD58FNCSEL = GPIO - Output is open drain */ - GPIO_CFGH_GPIO58OUTCFG_TS = 3, /*!< TS : Applies when PAD58FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGH_GPIO58OUTCFG_Enum; - -/* ============================================= GPIO CFGH GPIO58INCFG [8..8] ============================================== */ -typedef enum { /*!< GPIO_CFGH_GPIO58INCFG */ - GPIO_CFGH_GPIO58INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGH_GPIO58INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGH_GPIO58INCFG_Enum; - -/* ============================================== GPIO CFGH GPIO57INTD [7..7] ============================================== */ -typedef enum { /*!< GPIO_CFGH_GPIO57INTD */ - GPIO_CFGH_GPIO57INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD57FNCSEL = NCE57 - nCE polarity active - low */ - GPIO_CFGH_GPIO57INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD57FNCSEL = NCE57 - nCE polarity active - high */ -} GPIO_CFGH_GPIO57INTD_Enum; - -/* ============================================= GPIO CFGH GPIO57OUTCFG [5..6] ============================================= */ -typedef enum { /*!< GPIO_CFGH_GPIO57OUTCFG */ - GPIO_CFGH_GPIO57OUTCFG_DIS = 0, /*!< DIS : Applies when PAD57FNCSEL = GPIO - Output disabled */ - GPIO_CFGH_GPIO57OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD57FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGH_GPIO57OUTCFG_OD = 2, /*!< OD : Applies when PAD57FNCSEL = GPIO - Output is open drain */ - GPIO_CFGH_GPIO57OUTCFG_TS = 3, /*!< TS : Applies when PAD57FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGH_GPIO57OUTCFG_Enum; - -/* ============================================= GPIO CFGH GPIO57INCFG [4..4] ============================================== */ -typedef enum { /*!< GPIO_CFGH_GPIO57INCFG */ - GPIO_CFGH_GPIO57INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGH_GPIO57INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGH_GPIO57INCFG_Enum; - -/* ============================================== GPIO CFGH GPIO56INTD [3..3] ============================================== */ -typedef enum { /*!< GPIO_CFGH_GPIO56INTD */ - GPIO_CFGH_GPIO56INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD56FNCSEL = NCE56 - nCE polarity active - low */ - GPIO_CFGH_GPIO56INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD56FNCSEL = NCE56 - nCE polarity active - high */ -} GPIO_CFGH_GPIO56INTD_Enum; - -/* ============================================= GPIO CFGH GPIO56OUTCFG [1..2] ============================================= */ -typedef enum { /*!< GPIO_CFGH_GPIO56OUTCFG */ - GPIO_CFGH_GPIO56OUTCFG_DIS = 0, /*!< DIS : Applies when PAD56FNCSEL = GPIO - Output disabled */ - GPIO_CFGH_GPIO56OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD56FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGH_GPIO56OUTCFG_OD = 2, /*!< OD : Applies when PAD56FNCSEL = GPIO - Output is open drain */ - GPIO_CFGH_GPIO56OUTCFG_TS = 3, /*!< TS : Applies when PAD56FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGH_GPIO56OUTCFG_Enum; - -/* ============================================= GPIO CFGH GPIO56INCFG [0..0] ============================================== */ -typedef enum { /*!< GPIO_CFGH_GPIO56INCFG */ - GPIO_CFGH_GPIO56INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGH_GPIO56INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGH_GPIO56INCFG_Enum; - -/* ========================================================= CFGI ========================================================== */ -/* ============================================= GPIO CFGI GPIO71INTD [31..31] ============================================= */ -typedef enum { /*!< GPIO_CFGI_GPIO71INTD */ - GPIO_CFGI_GPIO71INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD71FNCSEL = NCE71 - nCE polarity active - low */ - GPIO_CFGI_GPIO71INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD71FNCSEL = NCE71 - nCE polarity active - high */ -} GPIO_CFGI_GPIO71INTD_Enum; - -/* ============================================ GPIO CFGI GPIO71OUTCFG [29..30] ============================================ */ -typedef enum { /*!< GPIO_CFGI_GPIO71OUTCFG */ - GPIO_CFGI_GPIO71OUTCFG_DIS = 0, /*!< DIS : Applies when PAD71FNCSEL = GPIO - Output disabled */ - GPIO_CFGI_GPIO71OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD71FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGI_GPIO71OUTCFG_OD = 2, /*!< OD : Applies when PAD71FNCSEL = GPIO - Output is open drain */ - GPIO_CFGI_GPIO71OUTCFG_TS = 3, /*!< TS : Applies when PAD71FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGI_GPIO71OUTCFG_Enum; - -/* ============================================ GPIO CFGI GPIO71INCFG [28..28] ============================================= */ -typedef enum { /*!< GPIO_CFGI_GPIO71INCFG */ - GPIO_CFGI_GPIO71INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGI_GPIO71INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGI_GPIO71INCFG_Enum; - -/* ============================================= GPIO CFGI GPIO70INTD [27..27] ============================================= */ -typedef enum { /*!< GPIO_CFGI_GPIO70INTD */ - GPIO_CFGI_GPIO70INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD70FNCSEL = NCE70 - nCE polarity active - low */ - GPIO_CFGI_GPIO70INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD70FNCSEL = NCE70 - nCE polarity active - high */ -} GPIO_CFGI_GPIO70INTD_Enum; - -/* ============================================ GPIO CFGI GPIO70OUTCFG [25..26] ============================================ */ -typedef enum { /*!< GPIO_CFGI_GPIO70OUTCFG */ - GPIO_CFGI_GPIO70OUTCFG_DIS = 0, /*!< DIS : Applies when PAD70FNCSEL = GPIO - Output disabled */ - GPIO_CFGI_GPIO70OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD70FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGI_GPIO70OUTCFG_OD = 2, /*!< OD : Applies when PAD70FNCSEL = GPIO - Output is open drain */ - GPIO_CFGI_GPIO70OUTCFG_TS = 3, /*!< TS : Applies when PAD70FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGI_GPIO70OUTCFG_Enum; - -/* ============================================ GPIO CFGI GPIO70INCFG [24..24] ============================================= */ -typedef enum { /*!< GPIO_CFGI_GPIO70INCFG */ - GPIO_CFGI_GPIO70INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGI_GPIO70INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGI_GPIO70INCFG_Enum; - -/* ============================================= GPIO CFGI GPIO69INTD [23..23] ============================================= */ -typedef enum { /*!< GPIO_CFGI_GPIO69INTD */ - GPIO_CFGI_GPIO69INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD69FNCSEL = NCE69 - nCE polarity active - low */ - GPIO_CFGI_GPIO69INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD69FNCSEL = NCE69 - nCE polarity active - high */ -} GPIO_CFGI_GPIO69INTD_Enum; - -/* ============================================ GPIO CFGI GPIO69OUTCFG [21..22] ============================================ */ -typedef enum { /*!< GPIO_CFGI_GPIO69OUTCFG */ - GPIO_CFGI_GPIO69OUTCFG_DIS = 0, /*!< DIS : Applies when PAD69FNCSEL = GPIO - Output disabled */ - GPIO_CFGI_GPIO69OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD69FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGI_GPIO69OUTCFG_OD = 2, /*!< OD : Applies when PAD69FNCSEL = GPIO - Output is open drain */ - GPIO_CFGI_GPIO69OUTCFG_TS = 3, /*!< TS : Applies when PAD69FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGI_GPIO69OUTCFG_Enum; - -/* ============================================ GPIO CFGI GPIO69INCFG [20..20] ============================================= */ -typedef enum { /*!< GPIO_CFGI_GPIO69INCFG */ - GPIO_CFGI_GPIO69INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGI_GPIO69INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGI_GPIO69INCFG_Enum; - -/* ============================================= GPIO CFGI GPIO68INTD [19..19] ============================================= */ -typedef enum { /*!< GPIO_CFGI_GPIO68INTD */ - GPIO_CFGI_GPIO68INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD68FNCSEL = NCE68 - nCE polarity active - low */ - GPIO_CFGI_GPIO68INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD68FNCSEL = NCE68 - nCE polarity active - high */ -} GPIO_CFGI_GPIO68INTD_Enum; - -/* ============================================ GPIO CFGI GPIO68OUTCFG [17..18] ============================================ */ -typedef enum { /*!< GPIO_CFGI_GPIO68OUTCFG */ - GPIO_CFGI_GPIO68OUTCFG_DIS = 0, /*!< DIS : Applies when PAD68FNCSEL = GPIO - Output disabled */ - GPIO_CFGI_GPIO68OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD68FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGI_GPIO68OUTCFG_OD = 2, /*!< OD : Applies when PAD68FNCSEL = GPIO - Output is open drain */ - GPIO_CFGI_GPIO68OUTCFG_TS = 3, /*!< TS : Applies when PAD68FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGI_GPIO68OUTCFG_Enum; - -/* ============================================ GPIO CFGI GPIO68INCFG [16..16] ============================================= */ -typedef enum { /*!< GPIO_CFGI_GPIO68INCFG */ - GPIO_CFGI_GPIO68INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGI_GPIO68INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGI_GPIO68INCFG_Enum; - -/* ============================================= GPIO CFGI GPIO67INTD [15..15] ============================================= */ -typedef enum { /*!< GPIO_CFGI_GPIO67INTD */ - GPIO_CFGI_GPIO67INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD67FNCSEL = NCE67 - nCE polarity active - low */ - GPIO_CFGI_GPIO67INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD67FNCSEL = NCE67 - nCE polarity active - high */ -} GPIO_CFGI_GPIO67INTD_Enum; - -/* ============================================ GPIO CFGI GPIO67OUTCFG [13..14] ============================================ */ -typedef enum { /*!< GPIO_CFGI_GPIO67OUTCFG */ - GPIO_CFGI_GPIO67OUTCFG_DIS = 0, /*!< DIS : Applies when PAD67FNCSEL = GPIO - Output disabled */ - GPIO_CFGI_GPIO67OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD67FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGI_GPIO67OUTCFG_OD = 2, /*!< OD : Applies when PAD67FNCSEL = GPIO - Output is open drain */ - GPIO_CFGI_GPIO67OUTCFG_TS = 3, /*!< TS : Applies when PAD67FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGI_GPIO67OUTCFG_Enum; - -/* ============================================ GPIO CFGI GPIO67INCFG [12..12] ============================================= */ -typedef enum { /*!< GPIO_CFGI_GPIO67INCFG */ - GPIO_CFGI_GPIO67INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGI_GPIO67INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGI_GPIO67INCFG_Enum; - -/* ============================================= GPIO CFGI GPIO66INTD [11..11] ============================================= */ -typedef enum { /*!< GPIO_CFGI_GPIO66INTD */ - GPIO_CFGI_GPIO66INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD66FNCSEL = NCE66 - nCE polarity active - low */ - GPIO_CFGI_GPIO66INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD66FNCSEL = NCE66 - nCE polarity active - high */ -} GPIO_CFGI_GPIO66INTD_Enum; - -/* ============================================ GPIO CFGI GPIO66OUTCFG [9..10] ============================================= */ -typedef enum { /*!< GPIO_CFGI_GPIO66OUTCFG */ - GPIO_CFGI_GPIO66OUTCFG_DIS = 0, /*!< DIS : Applies when PAD66FNCSEL = GPIO - Output disabled */ - GPIO_CFGI_GPIO66OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD66FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGI_GPIO66OUTCFG_OD = 2, /*!< OD : Applies when PAD66FNCSEL = GPIO - Output is open drain */ - GPIO_CFGI_GPIO66OUTCFG_TS = 3, /*!< TS : Applies when PAD66FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGI_GPIO66OUTCFG_Enum; - -/* ============================================= GPIO CFGI GPIO66INCFG [8..8] ============================================== */ -typedef enum { /*!< GPIO_CFGI_GPIO66INCFG */ - GPIO_CFGI_GPIO66INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGI_GPIO66INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGI_GPIO66INCFG_Enum; - -/* ============================================== GPIO CFGI GPIO65INTD [7..7] ============================================== */ -typedef enum { /*!< GPIO_CFGI_GPIO65INTD */ - GPIO_CFGI_GPIO65INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD65FNCSEL = NCE65 - nCE polarity active - low */ - GPIO_CFGI_GPIO65INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD65FNCSEL = NCE65 - nCE polarity active - high */ -} GPIO_CFGI_GPIO65INTD_Enum; - -/* ============================================= GPIO CFGI GPIO65OUTCFG [5..6] ============================================= */ -typedef enum { /*!< GPIO_CFGI_GPIO65OUTCFG */ - GPIO_CFGI_GPIO65OUTCFG_DIS = 0, /*!< DIS : Applies when PAD65FNCSEL = GPIO - Output disabled */ - GPIO_CFGI_GPIO65OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD65FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGI_GPIO65OUTCFG_OD = 2, /*!< OD : Applies when PAD65FNCSEL = GPIO - Output is open drain */ - GPIO_CFGI_GPIO65OUTCFG_TS = 3, /*!< TS : Applies when PAD65FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGI_GPIO65OUTCFG_Enum; - -/* ============================================= GPIO CFGI GPIO65INCFG [4..4] ============================================== */ -typedef enum { /*!< GPIO_CFGI_GPIO65INCFG */ - GPIO_CFGI_GPIO65INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGI_GPIO65INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGI_GPIO65INCFG_Enum; - -/* ============================================== GPIO CFGI GPIO64INTD [3..3] ============================================== */ -typedef enum { /*!< GPIO_CFGI_GPIO64INTD */ - GPIO_CFGI_GPIO64INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD64FNCSEL = NCE64 - nCE polarity active - low */ - GPIO_CFGI_GPIO64INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD64FNCSEL = NCE64 - nCE polarity active - high */ -} GPIO_CFGI_GPIO64INTD_Enum; - -/* ============================================= GPIO CFGI GPIO64OUTCFG [1..2] ============================================= */ -typedef enum { /*!< GPIO_CFGI_GPIO64OUTCFG */ - GPIO_CFGI_GPIO64OUTCFG_DIS = 0, /*!< DIS : Applies when PAD64FNCSEL = GPIO - Output disabled */ - GPIO_CFGI_GPIO64OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD64FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGI_GPIO64OUTCFG_OD = 2, /*!< OD : Applies when PAD64FNCSEL = GPIO - Output is open drain */ - GPIO_CFGI_GPIO64OUTCFG_TS = 3, /*!< TS : Applies when PAD64FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGI_GPIO64OUTCFG_Enum; - -/* ============================================= GPIO CFGI GPIO64INCFG [0..0] ============================================== */ -typedef enum { /*!< GPIO_CFGI_GPIO64INCFG */ - GPIO_CFGI_GPIO64INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGI_GPIO64INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGI_GPIO64INCFG_Enum; - -/* ========================================================= CFGJ ========================================================== */ -/* ============================================== GPIO CFGJ GPIO73INTD [7..7] ============================================== */ -typedef enum { /*!< GPIO_CFGJ_GPIO73INTD */ - GPIO_CFGJ_GPIO73INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD73FNCSEL = NCE73 - nCE polarity active - low */ - GPIO_CFGJ_GPIO73INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD73FNCSEL = NCE73 - nCE polarity active - high */ -} GPIO_CFGJ_GPIO73INTD_Enum; - -/* ============================================= GPIO CFGJ GPIO73OUTCFG [5..6] ============================================= */ -typedef enum { /*!< GPIO_CFGJ_GPIO73OUTCFG */ - GPIO_CFGJ_GPIO73OUTCFG_DIS = 0, /*!< DIS : Applies when PAD73FNCSEL = GPIO - Output disabled */ - GPIO_CFGJ_GPIO73OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD73FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGJ_GPIO73OUTCFG_OD = 2, /*!< OD : Applies when PAD73FNCSEL = GPIO - Output is open drain */ - GPIO_CFGJ_GPIO73OUTCFG_TS = 3, /*!< TS : Applies when PAD73FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGJ_GPIO73OUTCFG_Enum; - -/* ============================================= GPIO CFGJ GPIO73INCFG [4..4] ============================================== */ -typedef enum { /*!< GPIO_CFGJ_GPIO73INCFG */ - GPIO_CFGJ_GPIO73INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGJ_GPIO73INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGJ_GPIO73INCFG_Enum; - -/* ============================================== GPIO CFGJ GPIO72INTD [3..3] ============================================== */ -typedef enum { /*!< GPIO_CFGJ_GPIO72INTD */ - GPIO_CFGJ_GPIO72INTD_nCELOW = 0, /*!< nCELOW : Applies when PAD72FNCSEL = NCE72 - nCE polarity active - low */ - GPIO_CFGJ_GPIO72INTD_nCEHIGH = 1, /*!< nCEHIGH : Applies when PAD72FNCSEL = NCE72 - nCE polarity active - high */ -} GPIO_CFGJ_GPIO72INTD_Enum; - -/* ============================================= GPIO CFGJ GPIO72OUTCFG [1..2] ============================================= */ -typedef enum { /*!< GPIO_CFGJ_GPIO72OUTCFG */ - GPIO_CFGJ_GPIO72OUTCFG_DIS = 0, /*!< DIS : Applies when PAD72FNCSEL = GPIO - Output disabled */ - GPIO_CFGJ_GPIO72OUTCFG_PUSHPULL = 1, /*!< PUSHPULL : Applies when PAD72FNCSEL = GPIO - Output is push-pull */ - GPIO_CFGJ_GPIO72OUTCFG_OD = 2, /*!< OD : Applies when PAD72FNCSEL = GPIO - Output is open drain */ - GPIO_CFGJ_GPIO72OUTCFG_TS = 3, /*!< TS : Applies when PAD72FNCSEL = GPIO - Output is tri-state */ -} GPIO_CFGJ_GPIO72OUTCFG_Enum; - -/* ============================================= GPIO CFGJ GPIO72INCFG [0..0] ============================================== */ -typedef enum { /*!< GPIO_CFGJ_GPIO72INCFG */ - GPIO_CFGJ_GPIO72INCFG_READ = 0, /*!< READ : Read the GPIO pin data */ - GPIO_CFGJ_GPIO72INCFG_RDZERO = 1, /*!< RDZERO : INTD = 0 - Readback will always be zero */ -} GPIO_CFGJ_GPIO72INCFG_Enum; - -/* ======================================================== PADKEY ========================================================= */ -/* ============================================== GPIO PADKEY PADKEY [0..31] =============================================== */ -typedef enum { /*!< GPIO_PADKEY_PADKEY */ - GPIO_PADKEY_PADKEY_Key = 115, /*!< Key : Key */ -} GPIO_PADKEY_PADKEY_Enum; - -/* ========================================================== RDA ========================================================== */ -/* ========================================================== RDB ========================================================== */ -/* ========================================================== RDC ========================================================== */ -/* ========================================================== WTA ========================================================== */ -/* ========================================================== WTB ========================================================== */ -/* ========================================================== WTC ========================================================== */ -/* ========================================================= WTSA ========================================================== */ -/* ========================================================= WTSB ========================================================== */ -/* ========================================================= WTSC ========================================================== */ -/* ========================================================= WTCA ========================================================== */ -/* ========================================================= WTCB ========================================================== */ -/* ========================================================= WTCC ========================================================== */ -/* ========================================================== ENA ========================================================== */ -/* ========================================================== ENB ========================================================== */ -/* ========================================================== ENC ========================================================== */ -/* ========================================================= ENSA ========================================================== */ -/* ========================================================= ENSB ========================================================== */ -/* ========================================================= ENSC ========================================================== */ -/* ========================================================= ENCA ========================================================== */ -/* ========================================================= ENCB ========================================================== */ -/* ========================================================= ENCC ========================================================== */ -/* ======================================================== STMRCAP ======================================================== */ -/* ============================================= GPIO STMRCAP STPOL3 [31..31] ============================================== */ -typedef enum { /*!< GPIO_STMRCAP_STPOL3 */ - GPIO_STMRCAP_STPOL3_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ - GPIO_STMRCAP_STPOL3_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ -} GPIO_STMRCAP_STPOL3_Enum; - -/* ============================================= GPIO STMRCAP STPOL2 [23..23] ============================================== */ -typedef enum { /*!< GPIO_STMRCAP_STPOL2 */ - GPIO_STMRCAP_STPOL2_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ - GPIO_STMRCAP_STPOL2_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ -} GPIO_STMRCAP_STPOL2_Enum; - -/* ============================================= GPIO STMRCAP STPOL1 [15..15] ============================================== */ -typedef enum { /*!< GPIO_STMRCAP_STPOL1 */ - GPIO_STMRCAP_STPOL1_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ - GPIO_STMRCAP_STPOL1_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ -} GPIO_STMRCAP_STPOL1_Enum; - -/* ============================================== GPIO STMRCAP STPOL0 [7..7] =============================================== */ -typedef enum { /*!< GPIO_STMRCAP_STPOL0 */ - GPIO_STMRCAP_STPOL0_CAPLH = 0, /*!< CAPLH : Capture on low to high GPIO transition */ - GPIO_STMRCAP_STPOL0_CAPHL = 1, /*!< CAPHL : Capture on high to low GPIO transition */ -} GPIO_STMRCAP_STPOL0_Enum; - -/* ======================================================== IOM0IRQ ======================================================== */ -/* ======================================================== IOM1IRQ ======================================================== */ -/* ======================================================== IOM2IRQ ======================================================== */ -/* ======================================================== IOM3IRQ ======================================================== */ -/* ======================================================== IOM4IRQ ======================================================== */ -/* ======================================================== IOM5IRQ ======================================================== */ -/* ======================================================= BLEIFIRQ ======================================================== */ -/* ======================================================== GPIOOBS ======================================================== */ -/* ====================================================== ALTPADCFGA ======================================================= */ -/* =========================================== GPIO ALTPADCFGA PAD3_SR [28..28] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGA_PAD3_SR */ - GPIO_ALTPADCFGA_PAD3_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGA_PAD3_SR_Enum; - -/* =========================================== GPIO ALTPADCFGA PAD2_SR [20..20] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGA_PAD2_SR */ - GPIO_ALTPADCFGA_PAD2_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGA_PAD2_SR_Enum; - -/* =========================================== GPIO ALTPADCFGA PAD1_SR [12..12] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGA_PAD1_SR */ - GPIO_ALTPADCFGA_PAD1_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGA_PAD1_SR_Enum; - -/* ============================================ GPIO ALTPADCFGA PAD0_SR [4..4] ============================================= */ -typedef enum { /*!< GPIO_ALTPADCFGA_PAD0_SR */ - GPIO_ALTPADCFGA_PAD0_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGA_PAD0_SR_Enum; - -/* ====================================================== ALTPADCFGB ======================================================= */ -/* =========================================== GPIO ALTPADCFGB PAD7_SR [28..28] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGB_PAD7_SR */ - GPIO_ALTPADCFGB_PAD7_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGB_PAD7_SR_Enum; - -/* =========================================== GPIO ALTPADCFGB PAD6_SR [20..20] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGB_PAD6_SR */ - GPIO_ALTPADCFGB_PAD6_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGB_PAD6_SR_Enum; - -/* =========================================== GPIO ALTPADCFGB PAD5_SR [12..12] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGB_PAD5_SR */ - GPIO_ALTPADCFGB_PAD5_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGB_PAD5_SR_Enum; - -/* ============================================ GPIO ALTPADCFGB PAD4_SR [4..4] ============================================= */ -typedef enum { /*!< GPIO_ALTPADCFGB_PAD4_SR */ - GPIO_ALTPADCFGB_PAD4_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGB_PAD4_SR_Enum; - -/* ====================================================== ALTPADCFGC ======================================================= */ -/* =========================================== GPIO ALTPADCFGC PAD11_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGC_PAD11_SR */ - GPIO_ALTPADCFGC_PAD11_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGC_PAD11_SR_Enum; - -/* =========================================== GPIO ALTPADCFGC PAD10_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGC_PAD10_SR */ - GPIO_ALTPADCFGC_PAD10_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGC_PAD10_SR_Enum; - -/* =========================================== GPIO ALTPADCFGC PAD9_SR [12..12] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGC_PAD9_SR */ - GPIO_ALTPADCFGC_PAD9_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGC_PAD9_SR_Enum; - -/* ============================================ GPIO ALTPADCFGC PAD8_SR [4..4] ============================================= */ -typedef enum { /*!< GPIO_ALTPADCFGC_PAD8_SR */ - GPIO_ALTPADCFGC_PAD8_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGC_PAD8_SR_Enum; - -/* ====================================================== ALTPADCFGD ======================================================= */ -/* =========================================== GPIO ALTPADCFGD PAD15_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGD_PAD15_SR */ - GPIO_ALTPADCFGD_PAD15_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGD_PAD15_SR_Enum; - -/* =========================================== GPIO ALTPADCFGD PAD14_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGD_PAD14_SR */ - GPIO_ALTPADCFGD_PAD14_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGD_PAD14_SR_Enum; - -/* =========================================== GPIO ALTPADCFGD PAD13_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGD_PAD13_SR */ - GPIO_ALTPADCFGD_PAD13_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGD_PAD13_SR_Enum; - -/* ============================================ GPIO ALTPADCFGD PAD12_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGD_PAD12_SR */ - GPIO_ALTPADCFGD_PAD12_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGD_PAD12_SR_Enum; - -/* ====================================================== ALTPADCFGE ======================================================= */ -/* =========================================== GPIO ALTPADCFGE PAD19_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGE_PAD19_SR */ - GPIO_ALTPADCFGE_PAD19_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGE_PAD19_SR_Enum; - -/* =========================================== GPIO ALTPADCFGE PAD18_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGE_PAD18_SR */ - GPIO_ALTPADCFGE_PAD18_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGE_PAD18_SR_Enum; - -/* =========================================== GPIO ALTPADCFGE PAD17_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGE_PAD17_SR */ - GPIO_ALTPADCFGE_PAD17_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGE_PAD17_SR_Enum; - -/* ============================================ GPIO ALTPADCFGE PAD16_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGE_PAD16_SR */ - GPIO_ALTPADCFGE_PAD16_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGE_PAD16_SR_Enum; - -/* ====================================================== ALTPADCFGF ======================================================= */ -/* =========================================== GPIO ALTPADCFGF PAD23_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGF_PAD23_SR */ - GPIO_ALTPADCFGF_PAD23_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGF_PAD23_SR_Enum; - -/* =========================================== GPIO ALTPADCFGF PAD22_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGF_PAD22_SR */ - GPIO_ALTPADCFGF_PAD22_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGF_PAD22_SR_Enum; - -/* =========================================== GPIO ALTPADCFGF PAD21_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGF_PAD21_SR */ - GPIO_ALTPADCFGF_PAD21_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGF_PAD21_SR_Enum; - -/* ============================================ GPIO ALTPADCFGF PAD20_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGF_PAD20_SR */ - GPIO_ALTPADCFGF_PAD20_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGF_PAD20_SR_Enum; - -/* ====================================================== ALTPADCFGG ======================================================= */ -/* =========================================== GPIO ALTPADCFGG PAD27_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGG_PAD27_SR */ - GPIO_ALTPADCFGG_PAD27_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGG_PAD27_SR_Enum; - -/* =========================================== GPIO ALTPADCFGG PAD26_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGG_PAD26_SR */ - GPIO_ALTPADCFGG_PAD26_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGG_PAD26_SR_Enum; - -/* =========================================== GPIO ALTPADCFGG PAD25_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGG_PAD25_SR */ - GPIO_ALTPADCFGG_PAD25_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGG_PAD25_SR_Enum; - -/* ============================================ GPIO ALTPADCFGG PAD24_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGG_PAD24_SR */ - GPIO_ALTPADCFGG_PAD24_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGG_PAD24_SR_Enum; - -/* ====================================================== ALTPADCFGH ======================================================= */ -/* =========================================== GPIO ALTPADCFGH PAD31_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGH_PAD31_SR */ - GPIO_ALTPADCFGH_PAD31_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGH_PAD31_SR_Enum; - -/* =========================================== GPIO ALTPADCFGH PAD30_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGH_PAD30_SR */ - GPIO_ALTPADCFGH_PAD30_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGH_PAD30_SR_Enum; - -/* =========================================== GPIO ALTPADCFGH PAD29_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGH_PAD29_SR */ - GPIO_ALTPADCFGH_PAD29_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGH_PAD29_SR_Enum; - -/* ============================================ GPIO ALTPADCFGH PAD28_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGH_PAD28_SR */ - GPIO_ALTPADCFGH_PAD28_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGH_PAD28_SR_Enum; - -/* ====================================================== ALTPADCFGI ======================================================= */ -/* =========================================== GPIO ALTPADCFGI PAD35_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGI_PAD35_SR */ - GPIO_ALTPADCFGI_PAD35_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGI_PAD35_SR_Enum; - -/* =========================================== GPIO ALTPADCFGI PAD34_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGI_PAD34_SR */ - GPIO_ALTPADCFGI_PAD34_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGI_PAD34_SR_Enum; - -/* =========================================== GPIO ALTPADCFGI PAD33_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGI_PAD33_SR */ - GPIO_ALTPADCFGI_PAD33_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGI_PAD33_SR_Enum; - -/* ============================================ GPIO ALTPADCFGI PAD32_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGI_PAD32_SR */ - GPIO_ALTPADCFGI_PAD32_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGI_PAD32_SR_Enum; - -/* ====================================================== ALTPADCFGJ ======================================================= */ -/* =========================================== GPIO ALTPADCFGJ PAD39_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGJ_PAD39_SR */ - GPIO_ALTPADCFGJ_PAD39_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGJ_PAD39_SR_Enum; - -/* =========================================== GPIO ALTPADCFGJ PAD38_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGJ_PAD38_SR */ - GPIO_ALTPADCFGJ_PAD38_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGJ_PAD38_SR_Enum; - -/* =========================================== GPIO ALTPADCFGJ PAD37_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGJ_PAD37_SR */ - GPIO_ALTPADCFGJ_PAD37_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGJ_PAD37_SR_Enum; - -/* ============================================ GPIO ALTPADCFGJ PAD36_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGJ_PAD36_SR */ - GPIO_ALTPADCFGJ_PAD36_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGJ_PAD36_SR_Enum; - -/* ====================================================== ALTPADCFGK ======================================================= */ -/* =========================================== GPIO ALTPADCFGK PAD43_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGK_PAD43_SR */ - GPIO_ALTPADCFGK_PAD43_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGK_PAD43_SR_Enum; - -/* =========================================== GPIO ALTPADCFGK PAD42_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGK_PAD42_SR */ - GPIO_ALTPADCFGK_PAD42_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGK_PAD42_SR_Enum; - -/* =========================================== GPIO ALTPADCFGK PAD41_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGK_PAD41_SR */ - GPIO_ALTPADCFGK_PAD41_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGK_PAD41_SR_Enum; - -/* ============================================ GPIO ALTPADCFGK PAD40_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGK_PAD40_SR */ - GPIO_ALTPADCFGK_PAD40_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGK_PAD40_SR_Enum; - -/* ====================================================== ALTPADCFGL ======================================================= */ -/* =========================================== GPIO ALTPADCFGL PAD47_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGL_PAD47_SR */ - GPIO_ALTPADCFGL_PAD47_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGL_PAD47_SR_Enum; - -/* =========================================== GPIO ALTPADCFGL PAD46_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGL_PAD46_SR */ - GPIO_ALTPADCFGL_PAD46_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGL_PAD46_SR_Enum; - -/* =========================================== GPIO ALTPADCFGL PAD45_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGL_PAD45_SR */ - GPIO_ALTPADCFGL_PAD45_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGL_PAD45_SR_Enum; - -/* ============================================ GPIO ALTPADCFGL PAD44_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGL_PAD44_SR */ - GPIO_ALTPADCFGL_PAD44_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGL_PAD44_SR_Enum; - -/* ====================================================== ALTPADCFGM ======================================================= */ -/* =========================================== GPIO ALTPADCFGM PAD51_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGM_PAD51_SR */ - GPIO_ALTPADCFGM_PAD51_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGM_PAD51_SR_Enum; - -/* =========================================== GPIO ALTPADCFGM PAD50_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGM_PAD50_SR */ - GPIO_ALTPADCFGM_PAD50_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGM_PAD50_SR_Enum; - -/* =========================================== GPIO ALTPADCFGM PAD49_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGM_PAD49_SR */ - GPIO_ALTPADCFGM_PAD49_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGM_PAD49_SR_Enum; - -/* ============================================ GPIO ALTPADCFGM PAD48_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGM_PAD48_SR */ - GPIO_ALTPADCFGM_PAD48_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGM_PAD48_SR_Enum; - -/* ====================================================== ALTPADCFGN ======================================================= */ -/* =========================================== GPIO ALTPADCFGN PAD55_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGN_PAD55_SR */ - GPIO_ALTPADCFGN_PAD55_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGN_PAD55_SR_Enum; - -/* =========================================== GPIO ALTPADCFGN PAD54_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGN_PAD54_SR */ - GPIO_ALTPADCFGN_PAD54_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGN_PAD54_SR_Enum; - -/* =========================================== GPIO ALTPADCFGN PAD53_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGN_PAD53_SR */ - GPIO_ALTPADCFGN_PAD53_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGN_PAD53_SR_Enum; - -/* ============================================ GPIO ALTPADCFGN PAD52_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGN_PAD52_SR */ - GPIO_ALTPADCFGN_PAD52_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGN_PAD52_SR_Enum; - -/* ====================================================== ALTPADCFGO ======================================================= */ -/* =========================================== GPIO ALTPADCFGO PAD59_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGO_PAD59_SR */ - GPIO_ALTPADCFGO_PAD59_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGO_PAD59_SR_Enum; - -/* =========================================== GPIO ALTPADCFGO PAD58_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGO_PAD58_SR */ - GPIO_ALTPADCFGO_PAD58_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGO_PAD58_SR_Enum; - -/* =========================================== GPIO ALTPADCFGO PAD57_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGO_PAD57_SR */ - GPIO_ALTPADCFGO_PAD57_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGO_PAD57_SR_Enum; - -/* ============================================ GPIO ALTPADCFGO PAD56_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGO_PAD56_SR */ - GPIO_ALTPADCFGO_PAD56_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGO_PAD56_SR_Enum; - -/* ====================================================== ALTPADCFGP ======================================================= */ -/* =========================================== GPIO ALTPADCFGP PAD63_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGP_PAD63_SR */ - GPIO_ALTPADCFGP_PAD63_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGP_PAD63_SR_Enum; - -/* =========================================== GPIO ALTPADCFGP PAD62_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGP_PAD62_SR */ - GPIO_ALTPADCFGP_PAD62_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGP_PAD62_SR_Enum; - -/* =========================================== GPIO ALTPADCFGP PAD61_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGP_PAD61_SR */ - GPIO_ALTPADCFGP_PAD61_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGP_PAD61_SR_Enum; - -/* ============================================ GPIO ALTPADCFGP PAD60_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGP_PAD60_SR */ - GPIO_ALTPADCFGP_PAD60_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGP_PAD60_SR_Enum; - -/* ====================================================== ALTPADCFGQ ======================================================= */ -/* =========================================== GPIO ALTPADCFGQ PAD67_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGQ_PAD67_SR */ - GPIO_ALTPADCFGQ_PAD67_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGQ_PAD67_SR_Enum; - -/* =========================================== GPIO ALTPADCFGQ PAD66_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGQ_PAD66_SR */ - GPIO_ALTPADCFGQ_PAD66_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGQ_PAD66_SR_Enum; - -/* =========================================== GPIO ALTPADCFGQ PAD65_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGQ_PAD65_SR */ - GPIO_ALTPADCFGQ_PAD65_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGQ_PAD65_SR_Enum; - -/* ============================================ GPIO ALTPADCFGQ PAD64_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGQ_PAD64_SR */ - GPIO_ALTPADCFGQ_PAD64_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGQ_PAD64_SR_Enum; - -/* ====================================================== ALTPADCFGR ======================================================= */ -/* =========================================== GPIO ALTPADCFGR PAD71_SR [28..28] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGR_PAD71_SR */ - GPIO_ALTPADCFGR_PAD71_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGR_PAD71_SR_Enum; - -/* =========================================== GPIO ALTPADCFGR PAD70_SR [20..20] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGR_PAD70_SR */ - GPIO_ALTPADCFGR_PAD70_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGR_PAD70_SR_Enum; - -/* =========================================== GPIO ALTPADCFGR PAD69_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGR_PAD69_SR */ - GPIO_ALTPADCFGR_PAD69_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGR_PAD69_SR_Enum; - -/* ============================================ GPIO ALTPADCFGR PAD68_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGR_PAD68_SR */ - GPIO_ALTPADCFGR_PAD68_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGR_PAD68_SR_Enum; - -/* ====================================================== ALTPADCFGS ======================================================= */ -/* =========================================== GPIO ALTPADCFGS PAD73_SR [12..12] =========================================== */ -typedef enum { /*!< GPIO_ALTPADCFGS_PAD73_SR */ - GPIO_ALTPADCFGS_PAD73_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGS_PAD73_SR_Enum; - -/* ============================================ GPIO ALTPADCFGS PAD72_SR [4..4] ============================================ */ -typedef enum { /*!< GPIO_ALTPADCFGS_PAD72_SR */ - GPIO_ALTPADCFGS_PAD72_SR_SR_EN = 1, /*!< SR_EN : Enables Slew rate control on pad */ -} GPIO_ALTPADCFGS_PAD72_SR_Enum; - -/* ========================================================= SCDET ========================================================= */ -/* ======================================================== CTENCFG ======================================================== */ -/* ============================================== GPIO CTENCFG EN31 [31..31] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN31 */ - GPIO_CTENCFG_EN31_DIS = 1, /*!< DIS : Disable CT31 for output */ - GPIO_CTENCFG_EN31_EN = 0, /*!< EN : Enable CT31 for output */ -} GPIO_CTENCFG_EN31_Enum; - -/* ============================================== GPIO CTENCFG EN30 [30..30] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN30 */ - GPIO_CTENCFG_EN30_DIS = 1, /*!< DIS : Disable CT30 for output */ - GPIO_CTENCFG_EN30_EN = 0, /*!< EN : Enable CT30 for output */ -} GPIO_CTENCFG_EN30_Enum; - -/* ============================================== GPIO CTENCFG EN29 [29..29] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN29 */ - GPIO_CTENCFG_EN29_DIS = 1, /*!< DIS : Disable CT29 for output */ - GPIO_CTENCFG_EN29_EN = 0, /*!< EN : Enable CT29 for output */ -} GPIO_CTENCFG_EN29_Enum; - -/* ============================================== GPIO CTENCFG EN28 [28..28] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN28 */ - GPIO_CTENCFG_EN28_DIS = 1, /*!< DIS : Disable CT28 for output */ - GPIO_CTENCFG_EN28_EN = 0, /*!< EN : Enable CT28 for output */ -} GPIO_CTENCFG_EN28_Enum; - -/* ============================================== GPIO CTENCFG EN27 [27..27] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN27 */ - GPIO_CTENCFG_EN27_DIS = 1, /*!< DIS : Disable CT27 for output */ - GPIO_CTENCFG_EN27_EN = 0, /*!< EN : Enable CT27 for output */ -} GPIO_CTENCFG_EN27_Enum; - -/* ============================================== GPIO CTENCFG EN26 [26..26] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN26 */ - GPIO_CTENCFG_EN26_DIS = 1, /*!< DIS : Disable CT26 for output */ - GPIO_CTENCFG_EN26_EN = 0, /*!< EN : Enable CT26 for output */ -} GPIO_CTENCFG_EN26_Enum; - -/* ============================================== GPIO CTENCFG EN25 [25..25] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN25 */ - GPIO_CTENCFG_EN25_DIS = 1, /*!< DIS : Disable CT25 for output */ - GPIO_CTENCFG_EN25_EN = 0, /*!< EN : Enable CT25 for output */ -} GPIO_CTENCFG_EN25_Enum; - -/* ============================================== GPIO CTENCFG EN24 [24..24] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN24 */ - GPIO_CTENCFG_EN24_DIS = 1, /*!< DIS : Disable CT24 for output */ - GPIO_CTENCFG_EN24_EN = 0, /*!< EN : Enable CT24 for output */ -} GPIO_CTENCFG_EN24_Enum; - -/* ============================================== GPIO CTENCFG EN23 [23..23] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN23 */ - GPIO_CTENCFG_EN23_DIS = 1, /*!< DIS : Disable CT23 for output */ - GPIO_CTENCFG_EN23_EN = 0, /*!< EN : Enable CT23 for output */ -} GPIO_CTENCFG_EN23_Enum; - -/* ============================================== GPIO CTENCFG EN22 [22..22] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN22 */ - GPIO_CTENCFG_EN22_DIS = 1, /*!< DIS : Disable CT22 for output */ - GPIO_CTENCFG_EN22_EN = 0, /*!< EN : Enable CT22 for output */ -} GPIO_CTENCFG_EN22_Enum; - -/* ============================================== GPIO CTENCFG EN21 [21..21] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN21 */ - GPIO_CTENCFG_EN21_DIS = 1, /*!< DIS : Disable CT21 for output */ - GPIO_CTENCFG_EN21_EN = 0, /*!< EN : Enable CT21 for output */ -} GPIO_CTENCFG_EN21_Enum; - -/* ============================================== GPIO CTENCFG EN20 [20..20] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN20 */ - GPIO_CTENCFG_EN20_DIS = 1, /*!< DIS : Disable CT20 for output */ - GPIO_CTENCFG_EN20_EN = 0, /*!< EN : Enable CT20 for output */ -} GPIO_CTENCFG_EN20_Enum; - -/* ============================================== GPIO CTENCFG EN19 [19..19] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN19 */ - GPIO_CTENCFG_EN19_DIS = 1, /*!< DIS : Disable CT19 for output */ - GPIO_CTENCFG_EN19_EN = 0, /*!< EN : Enable CT19 for output */ -} GPIO_CTENCFG_EN19_Enum; - -/* ============================================== GPIO CTENCFG EN18 [18..18] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN18 */ - GPIO_CTENCFG_EN18_DIS = 1, /*!< DIS : Disable CT18 for output */ - GPIO_CTENCFG_EN18_EN = 0, /*!< EN : Enable CT18 for output */ -} GPIO_CTENCFG_EN18_Enum; - -/* ============================================== GPIO CTENCFG EN17 [17..17] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN17 */ - GPIO_CTENCFG_EN17_DIS = 1, /*!< DIS : Disable CT17 for output */ - GPIO_CTENCFG_EN17_EN = 0, /*!< EN : Enable CT17 for output */ -} GPIO_CTENCFG_EN17_Enum; - -/* ============================================== GPIO CTENCFG EN16 [16..16] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN16 */ - GPIO_CTENCFG_EN16_DIS = 1, /*!< DIS : Disable CT16 for output */ - GPIO_CTENCFG_EN16_EN = 0, /*!< EN : Enable CT16 for output */ -} GPIO_CTENCFG_EN16_Enum; - -/* ============================================== GPIO CTENCFG EN15 [15..15] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN15 */ - GPIO_CTENCFG_EN15_DIS = 1, /*!< DIS : Disable CT15 for output */ - GPIO_CTENCFG_EN15_EN = 0, /*!< EN : Enable CT15 for output */ -} GPIO_CTENCFG_EN15_Enum; - -/* ============================================== GPIO CTENCFG EN14 [14..14] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN14 */ - GPIO_CTENCFG_EN14_DIS = 1, /*!< DIS : Disable CT14 for output */ - GPIO_CTENCFG_EN14_EN = 0, /*!< EN : Enable CT14 for output */ -} GPIO_CTENCFG_EN14_Enum; - -/* ============================================== GPIO CTENCFG EN13 [13..13] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN13 */ - GPIO_CTENCFG_EN13_DIS = 1, /*!< DIS : Disable CT13 for output */ - GPIO_CTENCFG_EN13_EN = 0, /*!< EN : Enable CT13 for output */ -} GPIO_CTENCFG_EN13_Enum; - -/* ============================================== GPIO CTENCFG EN12 [12..12] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN12 */ - GPIO_CTENCFG_EN12_DIS = 1, /*!< DIS : Disable CT12 for output */ - GPIO_CTENCFG_EN12_EN = 0, /*!< EN : Enable CT12 for output */ -} GPIO_CTENCFG_EN12_Enum; - -/* ============================================== GPIO CTENCFG EN11 [11..11] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN11 */ - GPIO_CTENCFG_EN11_DIS = 1, /*!< DIS : Disable CT11 for output */ - GPIO_CTENCFG_EN11_EN = 0, /*!< EN : Enable CT11 for output */ -} GPIO_CTENCFG_EN11_Enum; - -/* ============================================== GPIO CTENCFG EN10 [10..10] =============================================== */ -typedef enum { /*!< GPIO_CTENCFG_EN10 */ - GPIO_CTENCFG_EN10_DIS = 1, /*!< DIS : Disable CT10 for output */ - GPIO_CTENCFG_EN10_EN = 0, /*!< EN : Enable CT10 for output */ -} GPIO_CTENCFG_EN10_Enum; - -/* ================================================ GPIO CTENCFG EN9 [9..9] ================================================ */ -typedef enum { /*!< GPIO_CTENCFG_EN9 */ - GPIO_CTENCFG_EN9_DIS = 0, /*!< DIS : Disable CT9 for output */ -} GPIO_CTENCFG_EN9_Enum; - -/* ================================================ GPIO CTENCFG EN8 [8..8] ================================================ */ -typedef enum { /*!< GPIO_CTENCFG_EN8 */ - GPIO_CTENCFG_EN8_DIS = 1, /*!< DIS : Disable CT8 for output */ - GPIO_CTENCFG_EN8_EN = 0, /*!< EN : Enable CT8 for output */ -} GPIO_CTENCFG_EN8_Enum; - -/* ================================================ GPIO CTENCFG EN7 [7..7] ================================================ */ -typedef enum { /*!< GPIO_CTENCFG_EN7 */ - GPIO_CTENCFG_EN7_DIS = 1, /*!< DIS : Disable CT7 for output */ - GPIO_CTENCFG_EN7_EN = 0, /*!< EN : Enable CT7 for output */ -} GPIO_CTENCFG_EN7_Enum; - -/* ================================================ GPIO CTENCFG EN6 [6..6] ================================================ */ -typedef enum { /*!< GPIO_CTENCFG_EN6 */ - GPIO_CTENCFG_EN6_DIS = 1, /*!< DIS : Disable CT6 for output */ - GPIO_CTENCFG_EN6_EN = 0, /*!< EN : Enable CT6 for output */ -} GPIO_CTENCFG_EN6_Enum; - -/* ================================================ GPIO CTENCFG EN5 [5..5] ================================================ */ -typedef enum { /*!< GPIO_CTENCFG_EN5 */ - GPIO_CTENCFG_EN5_DIS = 1, /*!< DIS : Disable CT5 for output */ - GPIO_CTENCFG_EN5_EN = 0, /*!< EN : Enable CT5 for output */ -} GPIO_CTENCFG_EN5_Enum; - -/* ================================================ GPIO CTENCFG EN4 [4..4] ================================================ */ -typedef enum { /*!< GPIO_CTENCFG_EN4 */ - GPIO_CTENCFG_EN4_DIS = 1, /*!< DIS : Disable CT4 for output */ - GPIO_CTENCFG_EN4_EN = 0, /*!< EN : Enable CT4 for output */ -} GPIO_CTENCFG_EN4_Enum; - -/* ================================================ GPIO CTENCFG EN3 [3..3] ================================================ */ -typedef enum { /*!< GPIO_CTENCFG_EN3 */ - GPIO_CTENCFG_EN3_DIS = 1, /*!< DIS : Disable CT3 for output */ - GPIO_CTENCFG_EN3_EN = 0, /*!< EN : Enable CT3 for output */ -} GPIO_CTENCFG_EN3_Enum; - -/* ================================================ GPIO CTENCFG EN2 [2..2] ================================================ */ -typedef enum { /*!< GPIO_CTENCFG_EN2 */ - GPIO_CTENCFG_EN2_DIS = 1, /*!< DIS : Disable CT2 for output */ - GPIO_CTENCFG_EN2_EN = 0, /*!< EN : Enable CT2 for output */ -} GPIO_CTENCFG_EN2_Enum; - -/* ================================================ GPIO CTENCFG EN1 [1..1] ================================================ */ -typedef enum { /*!< GPIO_CTENCFG_EN1 */ - GPIO_CTENCFG_EN1_DIS = 1, /*!< DIS : Disable CT1 for output */ - GPIO_CTENCFG_EN1_EN = 0, /*!< EN : Enable CT1 for output */ -} GPIO_CTENCFG_EN1_Enum; - -/* ================================================ GPIO CTENCFG EN0 [0..0] ================================================ */ -typedef enum { /*!< GPIO_CTENCFG_EN0 */ - GPIO_CTENCFG_EN0_DIS = 1, /*!< DIS : Disable CT0 for output */ - GPIO_CTENCFG_EN0_EN = 0, /*!< EN : Enable CT0 for output */ -} GPIO_CTENCFG_EN0_Enum; - -/* ======================================================== INT0EN ========================================================= */ -/* ======================================================= INT0STAT ======================================================== */ -/* ======================================================== INT0CLR ======================================================== */ -/* ======================================================== INT0SET ======================================================== */ -/* ======================================================== INT1EN ========================================================= */ -/* ======================================================= INT1STAT ======================================================== */ -/* ======================================================== INT1CLR ======================================================== */ -/* ======================================================== INT1SET ======================================================== */ -/* ======================================================== INT2EN ========================================================= */ -/* ======================================================= INT2STAT ======================================================== */ -/* ======================================================== INT2CLR ======================================================== */ -/* ======================================================== INT2SET ======================================================== */ -/* ======================================================== DBGCTRL ======================================================== */ - - -/* =========================================================================================================================== */ -/* ================ IOM0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= FIFO ========================================================== */ -/* ======================================================== FIFOPTR ======================================================== */ -/* ======================================================== FIFOTHR ======================================================== */ -/* ======================================================== FIFOPOP ======================================================== */ -/* ======================================================= FIFOPUSH ======================================================== */ -/* ======================================================= FIFOCTRL ======================================================== */ -/* ======================================================== FIFOLOC ======================================================== */ -/* ========================================================= INTEN ========================================================= */ -/* ======================================================== INTSTAT ======================================================== */ -/* ======================================================== INTCLR ========================================================= */ -/* ======================================================== INTSET ========================================================= */ -/* ======================================================== CLKCFG ========================================================= */ -/* ============================================== IOM0 CLKCFG DIVEN [12..12] =============================================== */ -typedef enum { /*!< IOM0_CLKCFG_DIVEN */ - IOM0_CLKCFG_DIVEN_DIS = 0, /*!< DIS : Disable TOTPER division. */ - IOM0_CLKCFG_DIVEN_EN = 1, /*!< EN : Enable TOTPER division. */ -} IOM0_CLKCFG_DIVEN_Enum; - -/* =============================================== IOM0 CLKCFG DIV3 [11..11] =============================================== */ -typedef enum { /*!< IOM0_CLKCFG_DIV3 */ - IOM0_CLKCFG_DIV3_DIS = 0, /*!< DIS : Select divide by 1. */ - IOM0_CLKCFG_DIV3_EN = 1, /*!< EN : Select divide by 3. */ -} IOM0_CLKCFG_DIV3_Enum; - -/* =============================================== IOM0 CLKCFG FSEL [8..10] ================================================ */ -typedef enum { /*!< IOM0_CLKCFG_FSEL */ - IOM0_CLKCFG_FSEL_MIN_PWR = 0, /*!< MIN_PWR : Selects the minimum power clock. This setting should - be used whenever the IOM is not active. */ - IOM0_CLKCFG_FSEL_HFRC = 1, /*!< HFRC : Selects the HFRC as the input clock. */ - IOM0_CLKCFG_FSEL_HFRC_DIV2 = 2, /*!< HFRC_DIV2 : Selects the HFRC / 2 as the input clock. */ - IOM0_CLKCFG_FSEL_HFRC_DIV4 = 3, /*!< HFRC_DIV4 : Selects the HFRC / 4 as the input clock. */ - IOM0_CLKCFG_FSEL_HFRC_DIV8 = 4, /*!< HFRC_DIV8 : Selects the HFRC / 8 as the input clock. */ - IOM0_CLKCFG_FSEL_HFRC_DIV16 = 5, /*!< HFRC_DIV16 : Selects the HFRC / 16 as the input clock. */ - IOM0_CLKCFG_FSEL_HFRC_DIV32 = 6, /*!< HFRC_DIV32 : Selects the HFRC / 32 as the input clock. */ - IOM0_CLKCFG_FSEL_HFRC_DIV64 = 7, /*!< HFRC_DIV64 : Selects the HFRC / 64 as the input clock. */ -} IOM0_CLKCFG_FSEL_Enum; - -/* ====================================================== SUBMODCTRL ======================================================= */ -/* =========================================== IOM0 SUBMODCTRL SMOD1TYPE [5..7] ============================================ */ -typedef enum { /*!< IOM0_SUBMODCTRL_SMOD1TYPE */ - IOM0_SUBMODCTRL_SMOD1TYPE_MSPI = 0, /*!< MSPI : SPI Master submodule */ - IOM0_SUBMODCTRL_SMOD1TYPE_I2C_MASTER = 1, /*!< I2C_MASTER : MI2C submodule */ - IOM0_SUBMODCTRL_SMOD1TYPE_SSPI = 2, /*!< SSPI : SPI Slave submodule */ - IOM0_SUBMODCTRL_SMOD1TYPE_SI2C = 3, /*!< SI2C : I2C Slave submodule */ - IOM0_SUBMODCTRL_SMOD1TYPE_NA = 7, /*!< NA : NOT INSTALLED */ -} IOM0_SUBMODCTRL_SMOD1TYPE_Enum; - -/* =========================================== IOM0 SUBMODCTRL SMOD0TYPE [1..3] ============================================ */ -typedef enum { /*!< IOM0_SUBMODCTRL_SMOD0TYPE */ - IOM0_SUBMODCTRL_SMOD0TYPE_SPI_MASTER = 0, /*!< SPI_MASTER : MSPI submodule */ - IOM0_SUBMODCTRL_SMOD0TYPE_I2C_MASTER = 1, /*!< I2C_MASTER : I2C Master submodule */ - IOM0_SUBMODCTRL_SMOD0TYPE_SSPI = 2, /*!< SSPI : SPI Slave submodule */ - IOM0_SUBMODCTRL_SMOD0TYPE_SI2C = 3, /*!< SI2C : I2C Slave submodule */ - IOM0_SUBMODCTRL_SMOD0TYPE_NA = 7, /*!< NA : NOT INSTALLED */ -} IOM0_SUBMODCTRL_SMOD0TYPE_Enum; - -/* ========================================================== CMD ========================================================== */ -/* ================================================== IOM0 CMD CMD [0..4] ================================================== */ -typedef enum { /*!< IOM0_CMD_CMD */ - IOM0_CMD_CMD_WRITE = 1, /*!< WRITE : Write command using count of offset bytes specified - in the OFFSETCNT field */ - IOM0_CMD_CMD_READ = 2, /*!< READ : Read command using count of offset bytes specified in - the OFFSETCNT field */ - IOM0_CMD_CMD_TMW = 3, /*!< TMW : SPI only. Test mode to do constant write operations. Useful - for debug and power measurements. Will continually send - data in OFFSET field */ - IOM0_CMD_CMD_TMR = 4, /*!< TMR : SPI Only. Test mode to do constant read operations. Useful - for debug and power measurements. Will continually read - data from external input */ -} IOM0_CMD_CMD_Enum; - -/* ========================================================== DCX ========================================================== */ -/* ================================================= IOM0 DCX DCXEN [4..4] ================================================= */ -typedef enum { /*!< IOM0_DCX_DCXEN */ - IOM0_DCX_DCXEN_DIS = 0, /*!< DIS : Disable DCX. */ -} IOM0_DCX_DCXEN_Enum; - -/* ======================================================= OFFSETHI ======================================================== */ -/* ======================================================== CMDSTAT ======================================================== */ -/* ============================================== IOM0 CMDSTAT CMDSTAT [5..7] ============================================== */ -typedef enum { /*!< IOM0_CMDSTAT_CMDSTAT */ - IOM0_CMDSTAT_CMDSTAT_ERR = 1, /*!< ERR : Error encountered with command */ - IOM0_CMDSTAT_CMDSTAT_ACTIVE = 2, /*!< ACTIVE : Actively processing command */ - IOM0_CMDSTAT_CMDSTAT_IDLE = 4, /*!< IDLE : Idle state, no active command, no error */ - IOM0_CMDSTAT_CMDSTAT_WAIT = 6, /*!< WAIT : Command in progress, but waiting on data from host */ -} IOM0_CMDSTAT_CMDSTAT_Enum; - -/* ======================================================= DMATRIGEN ======================================================= */ -/* ====================================================== DMATRIGSTAT ====================================================== */ -/* ======================================================== DMACFG ========================================================= */ -/* ============================================== IOM0 DMACFG DPWROFF [9..9] =============================================== */ -typedef enum { /*!< IOM0_DMACFG_DPWROFF */ - IOM0_DMACFG_DPWROFF_DIS = 0, /*!< DIS : Power off disabled */ - IOM0_DMACFG_DPWROFF_EN = 1, /*!< EN : Power off enabled */ -} IOM0_DMACFG_DPWROFF_Enum; - -/* =============================================== IOM0 DMACFG DMAPRI [8..8] =============================================== */ -typedef enum { /*!< IOM0_DMACFG_DMAPRI */ - IOM0_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ - IOM0_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ -} IOM0_DMACFG_DMAPRI_Enum; - -/* =============================================== IOM0 DMACFG DMADIR [1..1] =============================================== */ -typedef enum { /*!< IOM0_DMACFG_DMADIR */ - IOM0_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction. To be set when - doing IOM read operations, ie reading data from external - devices. */ - IOM0_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction. To be set when doing - IOM write operations, ie writing data to external devices. */ -} IOM0_DMACFG_DMADIR_Enum; - -/* =============================================== IOM0 DMACFG DMAEN [0..0] ================================================ */ -typedef enum { /*!< IOM0_DMACFG_DMAEN */ - IOM0_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */ - IOM0_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */ -} IOM0_DMACFG_DMAEN_Enum; - -/* ====================================================== DMATOTCOUNT ====================================================== */ -/* ====================================================== DMATARGADDR ====================================================== */ -/* ======================================================== DMASTAT ======================================================== */ -/* ========================================================= CQCFG ========================================================= */ -/* ============================================= IOM0 CQCFG MSPIFLGSEL [2..3] ============================================== */ -typedef enum { /*!< IOM0_CQCFG_MSPIFLGSEL */ - IOM0_CQCFG_MSPIFLGSEL_MSPI0FLGSEL = 0, /*!< MSPI0FLGSEL : Selects MPSI0 as source of signals used in CGFLAG[11:8]. */ - IOM0_CQCFG_MSPIFLGSEL_MSPI1FLGSEL = 1, /*!< MSPI1FLGSEL : Selects MPSI1 as source of signals used in CGFLAG[11:8]. */ - IOM0_CQCFG_MSPIFLGSEL_MSPI2FLGSEL = 2, /*!< MSPI2FLGSEL : Selects MPSI2 as source of signals used in CGFLAG[11:8]. */ -} IOM0_CQCFG_MSPIFLGSEL_Enum; - -/* ================================================ IOM0 CQCFG CQPRI [1..1] ================================================ */ -typedef enum { /*!< IOM0_CQCFG_CQPRI */ - IOM0_CQCFG_CQPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ - IOM0_CQCFG_CQPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ -} IOM0_CQCFG_CQPRI_Enum; - -/* ================================================ IOM0 CQCFG CQEN [0..0] ================================================= */ -typedef enum { /*!< IOM0_CQCFG_CQEN */ - IOM0_CQCFG_CQEN_DIS = 0, /*!< DIS : Disable CQ Function */ - IOM0_CQCFG_CQEN_EN = 1, /*!< EN : Enable CQ Function */ -} IOM0_CQCFG_CQEN_Enum; - -/* ======================================================== CQADDR ========================================================= */ -/* ======================================================== CQSTAT ========================================================= */ -/* ======================================================== CQFLAGS ======================================================== */ -/* ====================================================== CQSETCLEAR ======================================================= */ -/* ======================================================= CQPAUSEEN ======================================================= */ -/* ============================================= IOM0 CQPAUSEEN CQPEN [0..15] ============================================== */ -typedef enum { /*!< IOM0_CQPAUSEEN_CQPEN */ - IOM0_CQPAUSEEN_CQPEN_IDXEQ = 32768, /*!< IDXEQ : Pauses the command queue when the current index matches - the last index */ - IOM0_CQPAUSEEN_CQPEN_BLEXOREN = 16384, /*!< BLEXOREN : Pause command queue when input BLE bit XORed with - SWFLAG4 is '1' */ - IOM0_CQPAUSEEN_CQPEN_IOMXOREN = 8192, /*!< IOMXOREN : Pause command queue when input IOM bit XORed with - SWFLAG3 is '1' */ - IOM0_CQPAUSEEN_CQPEN_GPIOXOREN = 4096, /*!< GPIOXOREN : Pause command queue when input GPIO irq_bit XORed - with SWFLAG2 is '1' */ - IOM0_CQPAUSEEN_CQPEN_MSPI1XNOREN = 2048, /*!< MSPI1XNOREN : Pause command queue when selected MSPI input bit - 1 (buffer 1 ready) XNORed with SWFLAG1 is '1'. MSPI used - is selected in CQCFG.MSPIFLGSEL field. */ - IOM0_CQPAUSEEN_CQPEN_MSPI0XNOREN = 1024, /*!< MSPI0XNOREN : Pause command queue when selected MSPI input bit - 0 (buffer 0 ready) XNORed with SWFLAG1 is '1'. MSPI used - is selected in CQCFG.MSPIFLGSEL field. */ - IOM0_CQPAUSEEN_CQPEN_MSPI1XOREN = 512, /*!< MSPI1XOREN : Pause command queue when selected MSPI input bit - 1 (buffer 1 ready) XORed with SWFLAG1 is '1'. MSPI used - is selected in CQCFG.MSPIFLGSEL field. */ - IOM0_CQPAUSEEN_CQPEN_MSPI0XOREN = 256, /*!< MSPI0XOREN : Pause command queue when selected MSPI input bit - 0 (buffer 0 ready) XORed with SWFLAG1 is '1'. MSPI used - is selected in CQCFG.MSPIFLGSEL field. */ - IOM0_CQPAUSEEN_CQPEN_SWFLAGEN7 = 128, /*!< SWFLAGEN7 : Pause the command queue when software flag bit 7 - is '1'. */ - IOM0_CQPAUSEEN_CQPEN_SWFLAGEN6 = 64, /*!< SWFLAGEN6 : Pause the command queue when software flag bit 6 - is '1' */ - IOM0_CQPAUSEEN_CQPEN_SWFLAGEN5 = 32, /*!< SWFLAGEN5 : Pause the command queue when software flag bit 5 - is '1' */ - IOM0_CQPAUSEEN_CQPEN_SWFLAGEN4 = 16, /*!< SWFLAGEN4 : Pause the command queue when software flag bit 4 - is '1' */ - IOM0_CQPAUSEEN_CQPEN_SWFLAGEN3 = 8, /*!< SWFLAGEN3 : Pause the command queue when software flag bit 3 - is '1' */ - IOM0_CQPAUSEEN_CQPEN_SWFLAGEN2 = 4, /*!< SWFLAGEN2 : Pause the command queue when software flag bit 2 - is '1' */ - IOM0_CQPAUSEEN_CQPEN_SWFLAGEN1 = 2, /*!< SWFLAGEN1 : Pause the command queue when software flag bit 1 - is '1' */ - IOM0_CQPAUSEEN_CQPEN_SWFLAGEN0 = 1, /*!< SWFLAGEN0 : Pause the command queue when software flag bit 0 - is '1' */ -} IOM0_CQPAUSEEN_CQPEN_Enum; - -/* ======================================================= CQCURIDX ======================================================== */ -/* ======================================================= CQENDIDX ======================================================== */ -/* ======================================================== STATUS ========================================================= */ -/* =============================================== IOM0 STATUS IDLEST [2..2] =============================================== */ -typedef enum { /*!< IOM0_STATUS_IDLEST */ - IOM0_STATUS_IDLEST_IDLE = 1, /*!< IDLE : The I/O state machine is in the idle state. */ -} IOM0_STATUS_IDLEST_Enum; - -/* =============================================== IOM0 STATUS CMDACT [1..1] =============================================== */ -typedef enum { /*!< IOM0_STATUS_CMDACT */ - IOM0_STATUS_CMDACT_ACTIVE = 1, /*!< ACTIVE : An I/O command is active. Indicates the active module - has an active command and is processing this. De-asserted - when the command is completed. */ -} IOM0_STATUS_CMDACT_Enum; - -/* ================================================ IOM0 STATUS ERR [0..0] ================================================= */ -typedef enum { /*!< IOM0_STATUS_ERR */ - IOM0_STATUS_ERR_ERROR = 1, /*!< ERROR : Bit has been deprecated and will always return 0. */ -} IOM0_STATUS_ERR_Enum; - -/* ======================================================== MSPICFG ======================================================== */ -/* ============================================= IOM0 MSPICFG SPILSB [23..23] ============================================== */ -typedef enum { /*!< IOM0_MSPICFG_SPILSB */ - IOM0_MSPICFG_SPILSB_MSB = 0, /*!< MSB : Send and receive MSB bit first */ - IOM0_MSPICFG_SPILSB_LSB = 1, /*!< LSB : Send and receive LSB bit first */ -} IOM0_MSPICFG_SPILSB_Enum; - -/* ============================================= IOM0 MSPICFG RDFCPOL [22..22] ============================================= */ -typedef enum { /*!< IOM0_MSPICFG_RDFCPOL */ - IOM0_MSPICFG_RDFCPOL_HIGH = 0, /*!< HIGH : Flow control signal high creates flow control. */ - IOM0_MSPICFG_RDFCPOL_LOW = 1, /*!< LOW : Flow control signal low creates flow control. */ -} IOM0_MSPICFG_RDFCPOL_Enum; - -/* ============================================= IOM0 MSPICFG WTFCPOL [21..21] ============================================= */ -typedef enum { /*!< IOM0_MSPICFG_WTFCPOL */ - IOM0_MSPICFG_WTFCPOL_HIGH = 0, /*!< HIGH : Flow control signal high(1) creates flow control and - byte transfers will stop until the flow control signal - goes low. */ - IOM0_MSPICFG_WTFCPOL_LOW = 1, /*!< LOW : Flow control signal low(0) creates flow control and byte - transfers will stop until the flow control signal goes - high(1). */ -} IOM0_MSPICFG_WTFCPOL_Enum; - -/* ============================================= IOM0 MSPICFG WTFCIRQ [20..20] ============================================= */ -typedef enum { /*!< IOM0_MSPICFG_WTFCIRQ */ - IOM0_MSPICFG_WTFCIRQ_MISO = 0, /*!< MISO : MISO is used as the write mode flow control signal. */ - IOM0_MSPICFG_WTFCIRQ_IRQ = 1, /*!< IRQ : IRQ is used as the write mode flow control signal. */ -} IOM0_MSPICFG_WTFCIRQ_Enum; - -/* ============================================= IOM0 MSPICFG MOSIINV [18..18] ============================================= */ -typedef enum { /*!< IOM0_MSPICFG_MOSIINV */ - IOM0_MSPICFG_MOSIINV_NORMAL = 0, /*!< NORMAL : MOSI is set to 0 in read mode and 1 in write mode. */ - IOM0_MSPICFG_MOSIINV_INVERT = 1, /*!< INVERT : MOSI is set to 1 in read mode and 0 in write mode. */ -} IOM0_MSPICFG_MOSIINV_Enum; - -/* ============================================== IOM0 MSPICFG RDFC [17..17] =============================================== */ -typedef enum { /*!< IOM0_MSPICFG_RDFC */ - IOM0_MSPICFG_RDFC_DIS = 0, /*!< DIS : Read mode flow control disabled. */ - IOM0_MSPICFG_RDFC_EN = 1, /*!< EN : Read mode flow control enabled. */ -} IOM0_MSPICFG_RDFC_Enum; - -/* ============================================== IOM0 MSPICFG WTFC [16..16] =============================================== */ -typedef enum { /*!< IOM0_MSPICFG_WTFC */ - IOM0_MSPICFG_WTFC_DIS = 0, /*!< DIS : Write mode flow control disabled. */ - IOM0_MSPICFG_WTFC_EN = 1, /*!< EN : Write mode flow control enabled. */ -} IOM0_MSPICFG_WTFC_Enum; - -/* =============================================== IOM0 MSPICFG SPHA [1..1] ================================================ */ -typedef enum { /*!< IOM0_MSPICFG_SPHA */ - IOM0_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0, /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge. */ - IOM0_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1, /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock - edge. */ -} IOM0_MSPICFG_SPHA_Enum; - -/* =============================================== IOM0 MSPICFG SPOL [0..0] ================================================ */ -typedef enum { /*!< IOM0_MSPICFG_SPOL */ - IOM0_MSPICFG_SPOL_CLK_BASE_0 = 0, /*!< CLK_BASE_0 : The base value of the clock is 0. */ - IOM0_MSPICFG_SPOL_CLK_BASE_1 = 1, /*!< CLK_BASE_1 : The base value of the clock is 1. */ -} IOM0_MSPICFG_SPOL_Enum; - -/* ======================================================== MI2CCFG ======================================================== */ -/* =============================================== IOM0 MI2CCFG ARBEN [2..2] =============================================== */ -typedef enum { /*!< IOM0_MI2CCFG_ARBEN */ - IOM0_MI2CCFG_ARBEN_ARBEN = 1, /*!< ARBEN : Enable multi-master bus arbitration support for this - i2c master */ - IOM0_MI2CCFG_ARBEN_ARBDIS = 0, /*!< ARBDIS : Disable multi-master bus arbitration support for this - i2c master */ -} IOM0_MI2CCFG_ARBEN_Enum; - -/* ============================================== IOM0 MI2CCFG I2CLSB [1..1] =============================================== */ -typedef enum { /*!< IOM0_MI2CCFG_I2CLSB */ - IOM0_MI2CCFG_I2CLSB_MSBFIRST = 0, /*!< MSBFIRST : Byte data is transmitted MSB first onto the bus/read - from the bus */ - IOM0_MI2CCFG_I2CLSB_LSBFIRST = 1, /*!< LSBFIRST : Byte data is transmitted LSB first onto the bus/read - from the bus */ -} IOM0_MI2CCFG_I2CLSB_Enum; - -/* ============================================== IOM0 MI2CCFG ADDRSZ [0..0] =============================================== */ -typedef enum { /*!< IOM0_MI2CCFG_ADDRSZ */ - IOM0_MI2CCFG_ADDRSZ_ADDRSZ7 = 0, /*!< ADDRSZ7 : Use 7b addressing for I2C master transactions */ - IOM0_MI2CCFG_ADDRSZ_ADDRSZ10 = 1, /*!< ADDRSZ10 : Use 10b addressing for I2C master transactions */ -} IOM0_MI2CCFG_ADDRSZ_Enum; - -/* ======================================================== DEVCFG ========================================================= */ -/* ======================================================== IOMDBG ========================================================= */ - - -/* =========================================================================================================================== */ -/* ================ IOSLAVE ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== FIFOPTR ======================================================== */ -/* ======================================================== FIFOCFG ======================================================== */ -/* ======================================================== FIFOTHR ======================================================== */ -/* ========================================================= FUPD ========================================================== */ -/* ======================================================== FIFOCTR ======================================================== */ -/* ======================================================== FIFOINC ======================================================== */ -/* ========================================================== CFG ========================================================== */ -/* ============================================== IOSLAVE CFG IFCEN [31..31] =============================================== */ -typedef enum { /*!< IOSLAVE_CFG_IFCEN */ - IOSLAVE_CFG_IFCEN_DIS = 0, /*!< DIS : Disable the IOSLAVE */ - IOSLAVE_CFG_IFCEN_EN = 1, /*!< EN : Enable the IOSLAVE */ -} IOSLAVE_CFG_IFCEN_Enum; - -/* ============================================== IOSLAVE CFG STARTRD [4..4] =============================================== */ -typedef enum { /*!< IOSLAVE_CFG_STARTRD */ - IOSLAVE_CFG_STARTRD_LATE = 0, /*!< LATE : Initiate I/O RAM read late in each transferred byte. */ - IOSLAVE_CFG_STARTRD_EARLY = 1, /*!< EARLY : Initiate I/O RAM read early in each transferred byte. */ -} IOSLAVE_CFG_STARTRD_Enum; - -/* ================================================ IOSLAVE CFG LSB [2..2] ================================================= */ -typedef enum { /*!< IOSLAVE_CFG_LSB */ - IOSLAVE_CFG_LSB_MSB_FIRST = 0, /*!< MSB_FIRST : Data is assumed to be sent and received with MSB - first. */ - IOSLAVE_CFG_LSB_LSB_FIRST = 1, /*!< LSB_FIRST : Data is assumed to be sent and received with LSB - first. */ -} IOSLAVE_CFG_LSB_Enum; - -/* ================================================ IOSLAVE CFG SPOL [1..1] ================================================ */ -typedef enum { /*!< IOSLAVE_CFG_SPOL */ - IOSLAVE_CFG_SPOL_SPI_MODES_0_3 = 0, /*!< SPI_MODES_0_3 : Polarity 0, handles SPI modes 0 and 3. */ - IOSLAVE_CFG_SPOL_SPI_MODES_1_2 = 1, /*!< SPI_MODES_1_2 : Polarity 1, handles SPI modes 1 and 2. */ -} IOSLAVE_CFG_SPOL_Enum; - -/* =============================================== IOSLAVE CFG IFCSEL [0..0] =============================================== */ -typedef enum { /*!< IOSLAVE_CFG_IFCSEL */ - IOSLAVE_CFG_IFCSEL_I2C = 0, /*!< I2C : Selects I2C interface for the IO Slave. */ - IOSLAVE_CFG_IFCSEL_SPI = 1, /*!< SPI : Selects SPI interface for the IO Slave. */ -} IOSLAVE_CFG_IFCSEL_Enum; - -/* ========================================================= PRENC ========================================================= */ -/* ======================================================= IOINTCTL ======================================================== */ -/* ======================================================== GENADD ========================================================= */ -/* ========================================================= INTEN ========================================================= */ -/* ======================================================== INTSTAT ======================================================== */ -/* ======================================================== INTCLR ========================================================= */ -/* ======================================================== INTSET ========================================================= */ -/* ====================================================== REGACCINTEN ====================================================== */ -/* ===================================================== REGACCINTSTAT ===================================================== */ -/* ===================================================== REGACCINTCLR ====================================================== */ -/* ===================================================== REGACCINTSET ====================================================== */ - - -/* =========================================================================================================================== */ -/* ================ MCUCTRL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CHIPPN ========================================================= */ -/* ============================================ MCUCTRL CHIPPN PARTNUM [0..31] ============================================= */ -typedef enum { /*!< MCUCTRL_CHIPPN_PARTNUM */ - MCUCTRL_CHIPPN_PARTNUM_APOLLO3 = 100663296,/*!< APOLLO3 : Apollo3 part number is 0x06xxxxxx. */ - MCUCTRL_CHIPPN_PARTNUM_APOLLO2 = 50331648,/*!< APOLLO2 : Apollo2 part number is 0x03xxxxxx. */ - MCUCTRL_CHIPPN_PARTNUM_APOLLO = 16777216,/*!< APOLLO : Apollo part number is 0x01xxxxxx. */ - MCUCTRL_CHIPPN_PARTNUM_PN_M = -16777216,/*!< PN_M : Mask for the part number field. */ - MCUCTRL_CHIPPN_PARTNUM_PN_S = 24, /*!< PN_S : Bit position for the part number field. */ - MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_M = 15728640,/*!< FLASHSIZE_M : Mask for the FLASH_SIZE field.Values:0: 16KB1: - 32KB2: 64KB3: 128KB4: 256KB5: 512KB6: 1MB7: 2MB8: 1.5MB */ - MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_S = 20, /*!< FLASHSIZE_S : Bit position for the FLASH_SIZE field. */ - MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_M = 983040,/*!< SRAMSIZE_M : Mask for the SRAM_SIZE field.Values:0: 16KB1: 32KB2: - 64KB3: 128KB4: 256KB5: 512KB6: 1MB7: 384KB8: 768KB */ - MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_S = 16, /*!< SRAMSIZE_S : Bit position for the SRAM_SIZE field. */ - MCUCTRL_CHIPPN_PARTNUM_REV_M = 65280, /*!< REV_M : Mask for the revision field. Bits [15:12] are major - rev, [11:8] are minor rev.Values:0: Major Rev A, Minor - Rev 01: Major Rev B, Minor Rev 1 */ - MCUCTRL_CHIPPN_PARTNUM_REV_S = 8, /*!< REV_S : Bit position for the revision field. */ - MCUCTRL_CHIPPN_PARTNUM_PKG_M = 192, /*!< PKG_M : Mask for the package field.Values:0: SIP1: QFN2: BGA3: - CSP */ - MCUCTRL_CHIPPN_PARTNUM_PKG_S = 6, /*!< PKG_S : Bit position for the package field. */ - MCUCTRL_CHIPPN_PARTNUM_PINS_M = 56, /*!< PINS_M : Mask for the pins field.Values:0: 25 pins1: 49 pins2: - 64 pins3: 81 pins */ - MCUCTRL_CHIPPN_PARTNUM_PINS_S = 3, /*!< PINS_S : Bit position for the pins field. */ - MCUCTRL_CHIPPN_PARTNUM_TEMP_S = 1, /*!< TEMP_S : Bit position for the temperature field. */ - MCUCTRL_CHIPPN_PARTNUM_QUAL_S = 0, /*!< QUAL_S : Bit position for the qualified field. */ -} MCUCTRL_CHIPPN_PARTNUM_Enum; - -/* ======================================================== CHIPID0 ======================================================== */ -/* ============================================ MCUCTRL CHIPID0 CHIPID0 [0..31] ============================================ */ -typedef enum { /*!< MCUCTRL_CHIPID0_CHIPID0 */ - MCUCTRL_CHIPID0_CHIPID0_APOLLO3 = 0, /*!< APOLLO3 : Apollo3 CHIPID0. */ -} MCUCTRL_CHIPID0_CHIPID0_Enum; - -/* ======================================================== CHIPID1 ======================================================== */ -/* ============================================ MCUCTRL CHIPID1 CHIPID1 [0..31] ============================================ */ -typedef enum { /*!< MCUCTRL_CHIPID1_CHIPID1 */ - MCUCTRL_CHIPID1_CHIPID1_APOLLO3 = 0, /*!< APOLLO3 : Apollo3 CHIPID1. */ -} MCUCTRL_CHIPID1_CHIPID1_Enum; - -/* ======================================================== CHIPREV ======================================================== */ -/* ============================================= MCUCTRL CHIPREV REVMAJ [4..7] ============================================= */ -typedef enum { /*!< MCUCTRL_CHIPREV_REVMAJ */ - MCUCTRL_CHIPREV_REVMAJ_C = 3, /*!< C : Apollo3 revision C */ - MCUCTRL_CHIPREV_REVMAJ_B = 2, /*!< B : Apollo3 revision B */ - MCUCTRL_CHIPREV_REVMAJ_A = 1, /*!< A : Apollo3 revision A */ -} MCUCTRL_CHIPREV_REVMAJ_Enum; - -/* ============================================= MCUCTRL CHIPREV REVMIN [0..3] ============================================= */ -typedef enum { /*!< MCUCTRL_CHIPREV_REVMIN */ - MCUCTRL_CHIPREV_REVMIN_REV1 = 2, /*!< REV1 : Apollo3 minor rev 1. */ - MCUCTRL_CHIPREV_REVMIN_REV0 = 1, /*!< REV0 : Apollo3 minor rev 0. Minor revision value, succeeding - minor revisions will increment from this value. */ -} MCUCTRL_CHIPREV_REVMIN_Enum; - -/* ======================================================= VENDORID ======================================================== */ -/* =========================================== MCUCTRL VENDORID VENDORID [0..31] =========================================== */ -typedef enum { /*!< MCUCTRL_VENDORID_VENDORID */ - MCUCTRL_VENDORID_VENDORID_AMBIQ = 1095582289,/*!< AMBIQ : Ambiq Vendor ID 'AMBQ' */ -} MCUCTRL_VENDORID_VENDORID_Enum; - -/* ========================================================== SKU ========================================================== */ -/* ===================================================== FEATUREENABLE ===================================================== */ -/* ======================================== MCUCTRL FEATUREENABLE BURSTAVAIL [6..6] ======================================== */ -typedef enum { /*!< MCUCTRL_FEATUREENABLE_BURSTAVAIL */ - MCUCTRL_FEATUREENABLE_BURSTAVAIL_AVAIL = 1, /*!< AVAIL : Burst functionality available */ - MCUCTRL_FEATUREENABLE_BURSTAVAIL_NOTAVAIL = 0,/*!< NOTAVAIL : Burst functionality not available */ -} MCUCTRL_FEATUREENABLE_BURSTAVAIL_Enum; - -/* ========================================= MCUCTRL FEATUREENABLE BURSTREQ [4..4] ========================================= */ -typedef enum { /*!< MCUCTRL_FEATUREENABLE_BURSTREQ */ - MCUCTRL_FEATUREENABLE_BURSTREQ_EN = 1, /*!< EN : Enable the Burst functionality */ - MCUCTRL_FEATUREENABLE_BURSTREQ_DIS = 0, /*!< DIS : Disable the Burst functionality */ -} MCUCTRL_FEATUREENABLE_BURSTREQ_Enum; - -/* ========================================= MCUCTRL FEATUREENABLE BLEAVAIL [2..2] ========================================= */ -typedef enum { /*!< MCUCTRL_FEATUREENABLE_BLEAVAIL */ - MCUCTRL_FEATUREENABLE_BLEAVAIL_AVAIL = 1, /*!< AVAIL : BLE functionality available */ - MCUCTRL_FEATUREENABLE_BLEAVAIL_NOTAVAIL = 0, /*!< NOTAVAIL : BLE functionality not available */ -} MCUCTRL_FEATUREENABLE_BLEAVAIL_Enum; - -/* ========================================== MCUCTRL FEATUREENABLE BLEREQ [0..0] ========================================== */ -typedef enum { /*!< MCUCTRL_FEATUREENABLE_BLEREQ */ - MCUCTRL_FEATUREENABLE_BLEREQ_EN = 1, /*!< EN : Enable the BLE functionality */ - MCUCTRL_FEATUREENABLE_BLEREQ_DIS = 0, /*!< DIS : Disable the BLE functionality */ -} MCUCTRL_FEATUREENABLE_BLEREQ_Enum; - -/* ======================================================= DEBUGGER ======================================================== */ -/* ================================================= DMASRAMWRITEPROTECT2 ================================================== */ -/* ======================================================== BODCTRL ======================================================== */ -/* ======================================================= ADCPWRDLY ======================================================= */ -/* ======================================================== ADCCAL ========================================================= */ -/* ========================================== MCUCTRL ADCCAL ADCCALIBRATED [1..1] ========================================== */ -typedef enum { /*!< MCUCTRL_ADCCAL_ADCCALIBRATED */ - MCUCTRL_ADCCAL_ADCCALIBRATED_FALSE = 0, /*!< FALSE : ADC is not calibrated */ - MCUCTRL_ADCCAL_ADCCALIBRATED_TRUE = 1, /*!< TRUE : ADC is calibrated */ -} MCUCTRL_ADCCAL_ADCCALIBRATED_Enum; - -/* =========================================== MCUCTRL ADCCAL CALONPWRUP [0..0] ============================================ */ -typedef enum { /*!< MCUCTRL_ADCCAL_CALONPWRUP */ - MCUCTRL_ADCCAL_CALONPWRUP_DIS = 0, /*!< DIS : Disable automatic calibration on initial power up */ - MCUCTRL_ADCCAL_CALONPWRUP_EN = 1, /*!< EN : Enable automatic calibration on initial power up */ -} MCUCTRL_ADCCAL_CALONPWRUP_Enum; - -/* ====================================================== ADCBATTLOAD ====================================================== */ -/* ========================================== MCUCTRL ADCBATTLOAD BATTLOAD [0..0] ========================================== */ -typedef enum { /*!< MCUCTRL_ADCBATTLOAD_BATTLOAD */ - MCUCTRL_ADCBATTLOAD_BATTLOAD_DIS = 0, /*!< DIS : Battery load is disconnected */ - MCUCTRL_ADCBATTLOAD_BATTLOAD_EN = 1, /*!< EN : Battery load is enabled */ -} MCUCTRL_ADCBATTLOAD_BATTLOAD_Enum; - -/* ======================================================== ADCTRIM ======================================================== */ -/* ====================================================== ADCREFCOMP ======================================================= */ -/* ======================================================= XTALCTRL ======================================================== */ -/* ========================================== MCUCTRL XTALCTRL PWDBODXTAL [5..5] =========================================== */ -typedef enum { /*!< MCUCTRL_XTALCTRL_PWDBODXTAL */ - MCUCTRL_XTALCTRL_PWDBODXTAL_PWRUPBOD = 0, /*!< PWRUPBOD : Power up xtal on BOD */ - MCUCTRL_XTALCTRL_PWDBODXTAL_PWRDNBOD = 1, /*!< PWRDNBOD : Power down XTAL on BOD. */ -} MCUCTRL_XTALCTRL_PWDBODXTAL_Enum; - -/* ========================================= MCUCTRL XTALCTRL PDNBCMPRXTAL [4..4] ========================================== */ -typedef enum { /*!< MCUCTRL_XTALCTRL_PDNBCMPRXTAL */ - MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRUPCOMP = 1, /*!< PWRUPCOMP : Power up XTAL oscillator comparator. */ - MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRDNCOMP = 0, /*!< PWRDNCOMP : Power down XTAL oscillator comparator. */ -} MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Enum; - -/* ========================================= MCUCTRL XTALCTRL PDNBCOREXTAL [3..3] ========================================== */ -typedef enum { /*!< MCUCTRL_XTALCTRL_PDNBCOREXTAL */ - MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRUPCORE = 1, /*!< PWRUPCORE : Power up XTAL oscillator core. */ - MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRDNCORE = 0, /*!< PWRDNCORE : Power down XTAL oscillator core. */ -} MCUCTRL_XTALCTRL_PDNBCOREXTAL_Enum; - -/* ========================================== MCUCTRL XTALCTRL BYPCMPRXTAL [2..2] ========================================== */ -typedef enum { /*!< MCUCTRL_XTALCTRL_BYPCMPRXTAL */ - MCUCTRL_XTALCTRL_BYPCMPRXTAL_USECOMP = 0, /*!< USECOMP : Use the XTAL oscillator comparator. */ - MCUCTRL_XTALCTRL_BYPCMPRXTAL_BYPCOMP = 1, /*!< BYPCOMP : Bypass the XTAL oscillator comparator. */ -} MCUCTRL_XTALCTRL_BYPCMPRXTAL_Enum; - -/* ========================================= MCUCTRL XTALCTRL FDBKDSBLXTAL [1..1] ========================================== */ -typedef enum { /*!< MCUCTRL_XTALCTRL_FDBKDSBLXTAL */ - MCUCTRL_XTALCTRL_FDBKDSBLXTAL_EN = 0, /*!< EN : Enable XTAL oscillator comparator. */ - MCUCTRL_XTALCTRL_FDBKDSBLXTAL_DIS = 1, /*!< DIS : Disable XTAL oscillator comparator. */ -} MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Enum; - -/* ============================================ MCUCTRL XTALCTRL XTALSWE [0..0] ============================================ */ -typedef enum { /*!< MCUCTRL_XTALCTRL_XTALSWE */ - MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_DIS = 0, /*!< OVERRIDE_DIS : XTAL Software Override Disable. */ - MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_EN = 1, /*!< OVERRIDE_EN : XTAL Software Override Enable. */ -} MCUCTRL_XTALCTRL_XTALSWE_Enum; - -/* ====================================================== XTALGENCTRL ====================================================== */ -/* ========================================== MCUCTRL XTALGENCTRL ACWARMUP [0..1] ========================================== */ -typedef enum { /*!< MCUCTRL_XTALGENCTRL_ACWARMUP */ - MCUCTRL_XTALGENCTRL_ACWARMUP_SEC1 = 0, /*!< SEC1 : Warmup period of 1-2 seconds */ - MCUCTRL_XTALGENCTRL_ACWARMUP_SEC2 = 1, /*!< SEC2 : Warmup period of 2-4 seconds */ - MCUCTRL_XTALGENCTRL_ACWARMUP_SEC4 = 2, /*!< SEC4 : Warmup period of 4-8 seconds */ - MCUCTRL_XTALGENCTRL_ACWARMUP_SEC8 = 3, /*!< SEC8 : Warmup period of 8-16 seconds */ -} MCUCTRL_XTALGENCTRL_ACWARMUP_Enum; - -/* ======================================================= MISCCTRL ======================================================== */ -/* ====================================================== BOOTLOADER ======================================================= */ -/* ======================================= MCUCTRL BOOTLOADER SECBOOTONRST [30..31] ======================================== */ -typedef enum { /*!< MCUCTRL_BOOTLOADER_SECBOOTONRST */ - MCUCTRL_BOOTLOADER_SECBOOTONRST_DISABLED = 0, /*!< DISABLED : Secure boot disabled */ - MCUCTRL_BOOTLOADER_SECBOOTONRST_ENABLED = 1, /*!< ENABLED : Secure boot enabled */ - MCUCTRL_BOOTLOADER_SECBOOTONRST_ERROR = 2, /*!< ERROR : Error in secure boot configuration */ -} MCUCTRL_BOOTLOADER_SECBOOTONRST_Enum; - -/* ========================================== MCUCTRL BOOTLOADER SECBOOT [28..29] ========================================== */ -typedef enum { /*!< MCUCTRL_BOOTLOADER_SECBOOT */ - MCUCTRL_BOOTLOADER_SECBOOT_DISABLED = 0, /*!< DISABLED : Secure boot disabled */ - MCUCTRL_BOOTLOADER_SECBOOT_ENABLED = 1, /*!< ENABLED : Secure boot enabled */ - MCUCTRL_BOOTLOADER_SECBOOT_ERROR = 2, /*!< ERROR : Error in secure boot configuration */ -} MCUCTRL_BOOTLOADER_SECBOOT_Enum; - -/* ====================================== MCUCTRL BOOTLOADER SECBOOTFEATURE [26..27] ======================================= */ -typedef enum { /*!< MCUCTRL_BOOTLOADER_SECBOOTFEATURE */ - MCUCTRL_BOOTLOADER_SECBOOTFEATURE_DISABLED = 0,/*!< DISABLED : Secure boot disabled */ - MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ENABLED = 1,/*!< ENABLED : Secure boot enabled */ - MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ERROR = 2, /*!< ERROR : Error in secure boot configuration */ -} MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Enum; - -/* ========================================== MCUCTRL BOOTLOADER PROTLOCK [2..2] =========================================== */ -typedef enum { /*!< MCUCTRL_BOOTLOADER_PROTLOCK */ - MCUCTRL_BOOTLOADER_PROTLOCK_LOCK = 1, /*!< LOCK : Enable the secure boot lock */ -} MCUCTRL_BOOTLOADER_PROTLOCK_Enum; - -/* =========================================== MCUCTRL BOOTLOADER SBLOCK [1..1] ============================================ */ -typedef enum { /*!< MCUCTRL_BOOTLOADER_SBLOCK */ - MCUCTRL_BOOTLOADER_SBLOCK_LOCK = 1, /*!< LOCK : Enable the secure boot lock */ -} MCUCTRL_BOOTLOADER_SBLOCK_Enum; - -/* ======================================== MCUCTRL BOOTLOADER BOOTLOADERLOW [0..0] ======================================== */ -typedef enum { /*!< MCUCTRL_BOOTLOADER_BOOTLOADERLOW */ - MCUCTRL_BOOTLOADER_BOOTLOADERLOW_ADDR0 = 1, /*!< ADDR0 : Bootloader code at 0x00000000. */ -} MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Enum; - -/* ====================================================== SHADOWVALID ====================================================== */ -/* ======================================== MCUCTRL SHADOWVALID INFO0_VALID [2..2] ========================================= */ -typedef enum { /*!< MCUCTRL_SHADOWVALID_INFO0_VALID */ - MCUCTRL_SHADOWVALID_INFO0_VALID_VALID = 1, /*!< VALID : Flash info0 (customer) space contains valid data. */ -} MCUCTRL_SHADOWVALID_INFO0_VALID_Enum; - -/* ========================================== MCUCTRL SHADOWVALID BLDSLEEP [1..1] ========================================== */ -typedef enum { /*!< MCUCTRL_SHADOWVALID_BLDSLEEP */ - MCUCTRL_SHADOWVALID_BLDSLEEP_DEEPSLEEP = 1, /*!< DEEPSLEEP : Bootloader will go to deep sleep if no flash image - loaded */ -} MCUCTRL_SHADOWVALID_BLDSLEEP_Enum; - -/* =========================================== MCUCTRL SHADOWVALID VALID [0..0] ============================================ */ -typedef enum { /*!< MCUCTRL_SHADOWVALID_VALID */ - MCUCTRL_SHADOWVALID_VALID_VALID = 1, /*!< VALID : Flash information space contains valid data. */ -} MCUCTRL_SHADOWVALID_VALID_Enum; - -/* ======================================================= SCRATCH0 ======================================================== */ -/* ======================================================= SCRATCH1 ======================================================== */ -/* ==================================================== ICODEFAULTADDR ===================================================== */ -/* ==================================================== DCODEFAULTADDR ===================================================== */ -/* ===================================================== SYSFAULTADDR ====================================================== */ -/* ====================================================== FAULTSTATUS ====================================================== */ -/* ========================================== MCUCTRL FAULTSTATUS SYSFAULT [2..2] ========================================== */ -typedef enum { /*!< MCUCTRL_FAULTSTATUS_SYSFAULT */ - MCUCTRL_FAULTSTATUS_SYSFAULT_NOFAULT = 0, /*!< NOFAULT : No bus fault has been detected. */ - MCUCTRL_FAULTSTATUS_SYSFAULT_FAULT = 1, /*!< FAULT : Bus fault detected. */ -} MCUCTRL_FAULTSTATUS_SYSFAULT_Enum; - -/* ========================================= MCUCTRL FAULTSTATUS DCODEFAULT [1..1] ========================================= */ -typedef enum { /*!< MCUCTRL_FAULTSTATUS_DCODEFAULT */ - MCUCTRL_FAULTSTATUS_DCODEFAULT_NOFAULT = 0, /*!< NOFAULT : No DCODE fault has been detected. */ - MCUCTRL_FAULTSTATUS_DCODEFAULT_FAULT = 1, /*!< FAULT : DCODE fault detected. */ -} MCUCTRL_FAULTSTATUS_DCODEFAULT_Enum; - -/* ========================================= MCUCTRL FAULTSTATUS ICODEFAULT [0..0] ========================================= */ -typedef enum { /*!< MCUCTRL_FAULTSTATUS_ICODEFAULT */ - MCUCTRL_FAULTSTATUS_ICODEFAULT_NOFAULT = 0, /*!< NOFAULT : No ICODE fault has been detected. */ - MCUCTRL_FAULTSTATUS_ICODEFAULT_FAULT = 1, /*!< FAULT : ICODE fault detected. */ -} MCUCTRL_FAULTSTATUS_ICODEFAULT_Enum; - -/* ==================================================== FAULTCAPTUREEN ===================================================== */ -/* ===================================== MCUCTRL FAULTCAPTUREEN FAULTCAPTUREEN [0..0] ====================================== */ -typedef enum { /*!< MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN */ - MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_DIS = 0,/*!< DIS : Disable fault capture. */ - MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_EN = 1, /*!< EN : Enable fault capture. */ -} MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Enum; - -/* ========================================================= DBGR1 ========================================================= */ -/* ========================================================= DBGR2 ========================================================= */ -/* ======================================================= PMUENABLE ======================================================= */ -/* ============================================ MCUCTRL PMUENABLE ENABLE [0..0] ============================================ */ -typedef enum { /*!< MCUCTRL_PMUENABLE_ENABLE */ - MCUCTRL_PMUENABLE_ENABLE_DIS = 0, /*!< DIS : Disable MCU power management. */ - MCUCTRL_PMUENABLE_ENABLE_EN = 1, /*!< EN : Enable MCU power management. */ -} MCUCTRL_PMUENABLE_ENABLE_Enum; - -/* ======================================================= TPIUCTRL ======================================================== */ -/* ============================================ MCUCTRL TPIUCTRL CLKSEL [8..10] ============================================ */ -typedef enum { /*!< MCUCTRL_TPIUCTRL_CLKSEL */ - MCUCTRL_TPIUCTRL_CLKSEL_LOWPWR = 0, /*!< LOWPWR : Low power state. */ - MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV2 = 1, /*!< HFRCDIV2 : Selects HFRC divided by 2 as the source TPIU clk */ - MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV8 = 2, /*!< HFRCDIV8 : Selects HFRC divided by 8 as the source TPIU clk */ - MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV16 = 3, /*!< HFRCDIV16 : Selects HFRC divided by 16 as the source TPIU clk */ - MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV32 = 4, /*!< HFRCDIV32 : Selects HFRC divided by 32 as the source TPIU clk */ -} MCUCTRL_TPIUCTRL_CLKSEL_Enum; - -/* ============================================ MCUCTRL TPIUCTRL ENABLE [0..0] ============================================= */ -typedef enum { /*!< MCUCTRL_TPIUCTRL_ENABLE */ - MCUCTRL_TPIUCTRL_ENABLE_DIS = 0, /*!< DIS : Disable the TPIU. */ - MCUCTRL_TPIUCTRL_ENABLE_EN = 1, /*!< EN : Enable the TPIU. */ -} MCUCTRL_TPIUCTRL_ENABLE_Enum; - -/* ====================================================== OTAPOINTER ======================================================= */ -/* ====================================================== APBDMACTRL ======================================================= */ -/* =========================================== MCUCTRL APBDMACTRL DMAOPT [2..2] ============================================ */ -typedef enum { /*!< MCUCTRL_APBDMACTRL_DMAOPT */ - MCUCTRL_APBDMACTRL_DMAOPT_DISABLE = 0, /*!< DISABLE : DMA will fully serialize DMA operations (Apollo3 A/B - behavior) */ - MCUCTRL_APBDMACTRL_DMAOPT_ENABLE = 1, /*!< ENABLE : DMA will optimize DMA operations to minimize DMA latenchy */ -} MCUCTRL_APBDMACTRL_DMAOPT_Enum; - -/* ========================================= MCUCTRL APBDMACTRL DECODEABORT [1..1] ========================================= */ -typedef enum { /*!< MCUCTRL_APBDMACTRL_DECODEABORT */ - MCUCTRL_APBDMACTRL_DECODEABORT_DISABLE = 0, /*!< DISABLE : Bus operations to powered down peripherals are quietly - discarded */ - MCUCTRL_APBDMACTRL_DECODEABORT_ENABLE = 1, /*!< ENABLE : Bus operations to powered down peripherals result in - a bus fault. */ -} MCUCTRL_APBDMACTRL_DECODEABORT_Enum; - -/* ========================================= MCUCTRL APBDMACTRL DMA_ENABLE [0..0] ========================================== */ -typedef enum { /*!< MCUCTRL_APBDMACTRL_DMA_ENABLE */ - MCUCTRL_APBDMACTRL_DMA_ENABLE_DISABLE = 0, /*!< DISABLE : DMA operations disabled */ - MCUCTRL_APBDMACTRL_DMA_ENABLE_ENABLE = 1, /*!< ENABLE : DMA operations enabled */ -} MCUCTRL_APBDMACTRL_DMA_ENABLE_Enum; - -/* ======================================================= SRAMMODE ======================================================== */ -/* ====================================================== KEXTCLKSEL ======================================================= */ -/* ========================================= MCUCTRL KEXTCLKSEL KEXTCLKSEL [0..31] ========================================= */ -typedef enum { /*!< MCUCTRL_KEXTCLKSEL_KEXTCLKSEL */ - MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Key = 83, /*!< Key : Key */ -} MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Enum; - -/* ======================================================= SIMOBUCK4 ======================================================= */ -/* ======================================================= BLEBUCK2 ======================================================== */ -/* ====================================================== FLASHWPROT0 ====================================================== */ -/* ====================================================== FLASHWPROT1 ====================================================== */ -/* ====================================================== FLASHWPROT2 ====================================================== */ -/* ====================================================== FLASHWPROT3 ====================================================== */ -/* ====================================================== FLASHRPROT0 ====================================================== */ -/* ====================================================== FLASHRPROT1 ====================================================== */ -/* ====================================================== FLASHRPROT2 ====================================================== */ -/* ====================================================== FLASHRPROT3 ====================================================== */ -/* ================================================= DMASRAMWRITEPROTECT0 ================================================== */ -/* ================================================= DMASRAMWRITEPROTECT1 ================================================== */ -/* ================================================== DMASRAMREADPROTECT0 ================================================== */ -/* ================================================== DMASRAMREADPROTECT1 ================================================== */ -/* ================================================== DMASRAMREADPROTECT2 ================================================== */ - - -/* =========================================================================================================================== */ -/* ================ MSPI0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CTRL ========================================================== */ -/* ========================================================== CFG ========================================================== */ -/* ================================================ MSPI0 CFG CPOL [17..17] ================================================ */ -typedef enum { /*!< MSPI0_CFG_CPOL */ - MSPI0_CFG_CPOL_LOW = 0, /*!< LOW : Clock inactive state is low. */ - MSPI0_CFG_CPOL_HIGH = 1, /*!< HIGH : Clock inactive state is high. */ -} MSPI0_CFG_CPOL_Enum; - -/* ================================================ MSPI0 CFG CPHA [16..16] ================================================ */ -typedef enum { /*!< MSPI0_CFG_CPHA */ - MSPI0_CFG_CPHA_MIDDLE = 0, /*!< MIDDLE : Clock toggles in middle of data bit. */ - MSPI0_CFG_CPHA_START = 1, /*!< START : Clock toggles at start of data bit. */ -} MSPI0_CFG_CPHA_Enum; - -/* ================================================ MSPI0 CFG ASIZE [4..5] ================================================= */ -typedef enum { /*!< MSPI0_CFG_ASIZE */ - MSPI0_CFG_ASIZE_A1 = 0, /*!< A1 : Send one address byte */ - MSPI0_CFG_ASIZE_A2 = 1, /*!< A2 : Send two address bytes */ - MSPI0_CFG_ASIZE_A3 = 2, /*!< A3 : Send three address bytes */ - MSPI0_CFG_ASIZE_A4 = 3, /*!< A4 : Send four address bytes */ -} MSPI0_CFG_ASIZE_Enum; - -/* ================================================ MSPI0 CFG DEVCFG [0..3] ================================================ */ -typedef enum { /*!< MSPI0_CFG_DEVCFG */ - MSPI0_CFG_DEVCFG_SERIAL0 = 1, /*!< SERIAL0 : Single bit SPI flash on chip select 0 */ - MSPI0_CFG_DEVCFG_SERIAL1 = 2, /*!< SERIAL1 : Single bit SPI flash on chip select 1 */ - MSPI0_CFG_DEVCFG_DUAL0 = 5, /*!< DUAL0 : Dual SPI flash on chip select 0 */ - MSPI0_CFG_DEVCFG_DUAL1 = 6, /*!< DUAL1 : Dual bit SPI flash on chip select 1 */ - MSPI0_CFG_DEVCFG_QUAD0 = 9, /*!< QUAD0 : Quad SPI flash on chip select 0 */ - MSPI0_CFG_DEVCFG_QUAD1 = 10, /*!< QUAD1 : Quad SPI flash on chip select 1 */ - MSPI0_CFG_DEVCFG_OCTAL0 = 13, /*!< OCTAL0 : Octal SPI flash on chip select 0 */ - MSPI0_CFG_DEVCFG_OCTAL1 = 14, /*!< OCTAL1 : Octal SPI flash on chip select 1 */ - MSPI0_CFG_DEVCFG_QUADPAIRED = 15, /*!< QUADPAIRED : Dual Quad SPI flash on chip selects 0/1. */ - MSPI0_CFG_DEVCFG_QUADPAIRED_SERIAL = 3, /*!< QUADPAIRED_SERIAL : Dual Quad SPI flash on chip selects 0/1, - but transmit in serial mode for initialization operations */ -} MSPI0_CFG_DEVCFG_Enum; - -/* ========================================================= ADDR ========================================================== */ -/* ========================================================= INSTR ========================================================= */ -/* ======================================================== TXFIFO ========================================================= */ -/* ======================================================== RXFIFO ========================================================= */ -/* ======================================================= TXENTRIES ======================================================= */ -/* ======================================================= RXENTRIES ======================================================= */ -/* ======================================================= THRESHOLD ======================================================= */ -/* ======================================================== MSPICFG ======================================================== */ -/* ============================================= MSPI0 MSPICFG CLKDIV [8..13] ============================================== */ -typedef enum { /*!< MSPI0_MSPICFG_CLKDIV */ - MSPI0_MSPICFG_CLKDIV_CLK24 = 2, /*!< CLK24 : 24 MHz MSPI clock */ - MSPI0_MSPICFG_CLKDIV_CLK12 = 4, /*!< CLK12 : 12 MHz MSPI clock */ - MSPI0_MSPICFG_CLKDIV_CLK6 = 8, /*!< CLK6 : 6 MHz MSPI clock */ - MSPI0_MSPICFG_CLKDIV_CLK3 = 16, /*!< CLK3 : 3 MHz MSPI clock */ - MSPI0_MSPICFG_CLKDIV_CLK1_5 = 32, /*!< CLK1_5 : 1.5 MHz MSPI clock */ -} MSPI0_MSPICFG_CLKDIV_Enum; - -/* ============================================== MSPI0 MSPICFG IOMSEL [4..7] ============================================== */ -typedef enum { /*!< MSPI0_MSPICFG_IOMSEL */ - MSPI0_MSPICFG_IOMSEL_IOM0 = 0, /*!< IOM0 : ERROR: desc VALUE MISSING */ - MSPI0_MSPICFG_IOMSEL_IOM1 = 1, /*!< IOM1 : ERROR: desc VALUE MISSING */ - MSPI0_MSPICFG_IOMSEL_IOM2 = 2, /*!< IOM2 : ERROR: desc VALUE MISSING */ - MSPI0_MSPICFG_IOMSEL_IOM3 = 3, /*!< IOM3 : ERROR: desc VALUE MISSING */ - MSPI0_MSPICFG_IOMSEL_IOM4 = 4, /*!< IOM4 : ERROR: desc VALUE MISSING */ - MSPI0_MSPICFG_IOMSEL_IOM5 = 5, /*!< IOM5 : ERROR: desc VALUE MISSING */ - MSPI0_MSPICFG_IOMSEL_MSPI0 = 8, /*!< MSPI0 : ERROR: desc VALUE MISSING */ - MSPI0_MSPICFG_IOMSEL_MSPI1 = 9, /*!< MSPI1 : ERROR: desc VALUE MISSING */ - MSPI0_MSPICFG_IOMSEL_MSPI2 = 10, /*!< MSPI2 : ERROR: desc VALUE MISSING */ - MSPI0_MSPICFG_IOMSEL_DISABLED = 7, /*!< DISABLED : No IOM selected. Signals always zero. */ -} MSPI0_MSPICFG_IOMSEL_Enum; - -/* ============================================== MSPI0 MSPICFG TXNEG [3..3] =============================================== */ -typedef enum { /*!< MSPI0_MSPICFG_TXNEG */ - MSPI0_MSPICFG_TXNEG_NORMAL = 0, /*!< NORMAL : TX launched from posedge internal clock */ - MSPI0_MSPICFG_TXNEG_NEGEDGE = 1, /*!< NEGEDGE : TX data launched from negedge of internal clock */ -} MSPI0_MSPICFG_TXNEG_Enum; - -/* ============================================== MSPI0 MSPICFG RXNEG [2..2] =============================================== */ -typedef enum { /*!< MSPI0_MSPICFG_RXNEG */ - MSPI0_MSPICFG_RXNEG_NORMAL = 0, /*!< NORMAL : RX data sampled on posedge of internal clock */ - MSPI0_MSPICFG_RXNEG_NEGEDGE = 1, /*!< NEGEDGE : RX data sampled on negedge of internal clock */ -} MSPI0_MSPICFG_RXNEG_Enum; - -/* ============================================== MSPI0 MSPICFG RXCAP [1..1] =============================================== */ -typedef enum { /*!< MSPI0_MSPICFG_RXCAP */ - MSPI0_MSPICFG_RXCAP_NORMAL = 0, /*!< NORMAL : RX Capture phase aligns with CPHA setting */ - MSPI0_MSPICFG_RXCAP_DELAY = 1, /*!< DELAY : RX Capture phase is delayed from CPHA setting by one - clock edge */ -} MSPI0_MSPICFG_RXCAP_Enum; - -/* ============================================== MSPI0 MSPICFG APBCLK [0..0] ============================================== */ -typedef enum { /*!< MSPI0_MSPICFG_APBCLK */ - MSPI0_MSPICFG_APBCLK_DIS = 0, /*!< DIS : Disable continuous clock. */ - MSPI0_MSPICFG_APBCLK_EN = 1, /*!< EN : Enable continuous clock. */ -} MSPI0_MSPICFG_APBCLK_Enum; - -/* ======================================================== MSPIDDR ======================================================== */ -/* ======================================================== PADCFG ========================================================= */ -/* ======================================================= PADOUTEN ======================================================== */ -/* ============================================== MSPI0 PADOUTEN OUTEN [0..9] ============================================== */ -typedef enum { /*!< MSPI0_PADOUTEN_OUTEN */ - MSPI0_PADOUTEN_OUTEN_QUAD0 = 271, /*!< QUAD0 : Quad0 (4 data + 1 clock) */ - MSPI0_PADOUTEN_OUTEN_QUAD1 = 496, /*!< QUAD1 : Quad1 (4 data + 1 clock) */ - MSPI0_PADOUTEN_OUTEN_OCTAL = 1023, /*!< OCTAL : Octal (8 data + 1 clock) */ - MSPI0_PADOUTEN_OUTEN_SERIAL0 = 259, /*!< SERIAL0 : Serial (2 data + 1 clock) */ -} MSPI0_PADOUTEN_OUTEN_Enum; - -/* ======================================================= PADOVEREN ======================================================= */ -/* ======================================================== PADOVER ======================================================== */ -/* ========================================================= FLASH ========================================================= */ -/* ============================================= MSPI0 FLASH XIPMIXED [8..10] ============================================== */ -typedef enum { /*!< MSPI0_FLASH_XIPMIXED */ - MSPI0_FLASH_XIPMIXED_NORMAL = 0, /*!< NORMAL : Transfers all proceed using the settings in DEVCFG - register (everything in the same data rate) */ - MSPI0_FLASH_XIPMIXED_D2 = 1, /*!< D2 : Data operations proceed in dual data rate */ - MSPI0_FLASH_XIPMIXED_AD2 = 3, /*!< AD2 : Address and Data operations proceed in dual data rate */ - MSPI0_FLASH_XIPMIXED_D4 = 5, /*!< D4 : Data operations proceed in quad data rate */ - MSPI0_FLASH_XIPMIXED_AD4 = 7, /*!< AD4 : Address and Data operations proceed in quad data rate */ -} MSPI0_FLASH_XIPMIXED_Enum; - -/* =============================================== MSPI0 FLASH XIPACK [2..3] =============================================== */ -typedef enum { /*!< MSPI0_FLASH_XIPACK */ - MSPI0_FLASH_XIPACK_NOACK = 0, /*!< NOACK : No acknowledege sent. Data IOs are tristated the first - turnaround cycle */ - MSPI0_FLASH_XIPACK_ACK = 2, /*!< ACK : Positive acknowledege sent. Data IOs are driven to 0 the - first turnaround cycle to acknowledge XIP mode */ - MSPI0_FLASH_XIPACK_TERMINATE = 3, /*!< TERMINATE : Negative acknowledege sent. Data IOs are driven - to 1 the first turnaround cycle to terminate XIP mode. - XIPSENDI should be reenabled for the next transfer */ -} MSPI0_FLASH_XIPACK_Enum; - -/* ======================================================= XIPINSTR ======================================================== */ -/* ====================================================== SCRAMBLING ======================================================= */ -/* ========================================================= INTEN ========================================================= */ -/* ======================================================== INTSTAT ======================================================== */ -/* ======================================================== INTCLR ========================================================= */ -/* ======================================================== INTSET ========================================================= */ -/* ======================================================== DMACFG ========================================================= */ -/* ============================================== MSPI0 DMACFG DMAPRI [3..4] =============================================== */ -typedef enum { /*!< MSPI0_DMACFG_DMAPRI */ - MSPI0_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ - MSPI0_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ - MSPI0_DMACFG_DMAPRI_AUTO = 2, /*!< AUTO : Auto Priority (priority raised once TX FIFO empties or - RX FIFO fills) */ -} MSPI0_DMACFG_DMAPRI_Enum; - -/* ============================================== MSPI0 DMACFG DMADIR [2..2] =============================================== */ -typedef enum { /*!< MSPI0_DMACFG_DMADIR */ - MSPI0_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction */ - MSPI0_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction */ -} MSPI0_DMACFG_DMADIR_Enum; - -/* =============================================== MSPI0 DMACFG DMAEN [0..1] =============================================== */ -typedef enum { /*!< MSPI0_DMACFG_DMAEN */ - MSPI0_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */ - MSPI0_DMACFG_DMAEN_EN = 3, /*!< EN : Enable HW controlled DMA Function to manage DMA to flash - devices. HW will automatically handle issuance of instruction/address - bytes based on settings in the FLASH register. */ -} MSPI0_DMACFG_DMAEN_Enum; - -/* ======================================================== DMASTAT ======================================================== */ -/* ====================================================== DMATARGADDR ====================================================== */ -/* ====================================================== DMADEVADDR ======================================================= */ -/* ====================================================== DMATOTCOUNT ====================================================== */ -/* ======================================================= DMABCOUNT ======================================================= */ -/* ======================================================= DMATHRESH ======================================================= */ -/* ====================================================== DMABOUNDARY ====================================================== */ -/* ========================================== MSPI0 DMABOUNDARY DMABOUND [12..15] ========================================== */ -typedef enum { /*!< MSPI0_DMABOUNDARY_DMABOUND */ - MSPI0_DMABOUNDARY_DMABOUND_NONE = 0, /*!< NONE : Disable DMA address boundary breaks */ - MSPI0_DMABOUNDARY_DMABOUND_BREAK32 = 1, /*!< BREAK32 : Break at 32 byte boundary (0x20 increments) */ - MSPI0_DMABOUNDARY_DMABOUND_BREAK64 = 2, /*!< BREAK64 : Break at 64 byte boundary (0x40 increments) */ - MSPI0_DMABOUNDARY_DMABOUND_BREAK128 = 3, /*!< BREAK128 : Break at 128 byte boundary (0x80 increments) */ - MSPI0_DMABOUNDARY_DMABOUND_BREAK256 = 4, /*!< BREAK256 : Break at 256 byte boundary (0x100 increments) */ - MSPI0_DMABOUNDARY_DMABOUND_BREAK512 = 5, /*!< BREAK512 : Break at 512 byte boundary (0x200 increments) */ - MSPI0_DMABOUNDARY_DMABOUND_BREAK1K = 6, /*!< BREAK1K : Break at 1KB boundary (0x400 increments) */ - MSPI0_DMABOUNDARY_DMABOUND_BREAK2K = 7, /*!< BREAK2K : Break at 2KB boundary (0x800 increments) */ - MSPI0_DMABOUNDARY_DMABOUND_BREAK4K = 8, /*!< BREAK4K : Break at 4KB boundary (0x1000 increments) */ - MSPI0_DMABOUNDARY_DMABOUND_BREAK8K = 9, /*!< BREAK8K : Break at 8KB boundary (0x2000 increments) */ - MSPI0_DMABOUNDARY_DMABOUND_BREAK16K = 10, /*!< BREAK16K : Break at 16KB boundary (0x4000 increments) */ -} MSPI0_DMABOUNDARY_DMABOUND_Enum; - -/* ========================================================= CQCFG ========================================================= */ -/* =============================================== MSPI0 CQCFG CQPRI [1..1] ================================================ */ -typedef enum { /*!< MSPI0_CQCFG_CQPRI */ - MSPI0_CQCFG_CQPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ - MSPI0_CQCFG_CQPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ -} MSPI0_CQCFG_CQPRI_Enum; - -/* ================================================ MSPI0 CQCFG CQEN [0..0] ================================================ */ -typedef enum { /*!< MSPI0_CQCFG_CQEN */ - MSPI0_CQCFG_CQEN_DIS = 0, /*!< DIS : Disable CQ Function */ - MSPI0_CQCFG_CQEN_EN = 1, /*!< EN : Enable CQ Function */ -} MSPI0_CQCFG_CQEN_Enum; - -/* ======================================================== CQADDR ========================================================= */ -/* ======================================================== CQSTAT ========================================================= */ -/* ======================================================== CQFLAGS ======================================================== */ -/* ============================================= MSPI0 CQFLAGS CQFLAGS [0..15] ============================================= */ -typedef enum { /*!< MSPI0_CQFLAGS_CQFLAGS */ - MSPI0_CQFLAGS_CQFLAGS_STOP = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete. */ - MSPI0_CQFLAGS_CQFLAGS_CQIDX = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match. */ - MSPI0_CQFLAGS_CQFLAGS_BUF1XOREN = 8192, /*!< BUF1XOREN : Buffer 1 Ready Status (from selected IOM/MSPI). - This status is the result of XOR'ing the IOM1START with - the incoming status from the IOM. When high, MSPI can transfer - the buffer. */ - MSPI0_CQFLAGS_CQFLAGS_BUF0XOREN = 4096, /*!< BUF0XOREN : Buffer 0 Ready Status (from selected IOM/MSPI). - This status is the result of XOR'ing the IOM0START with - the incoming status from the IOM. When high, MSPI can transfer - the buffer. */ - MSPI0_CQFLAGS_CQFLAGS_DMACPL = 2048, /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT) */ - MSPI0_CQFLAGS_CQFLAGS_CMDCPL = 1024, /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register) */ - MSPI0_CQFLAGS_CQFLAGS_IOM1READY = 512, /*!< IOM1READY : IOM Buffer 1 Ready Status (from selected IOM). This - status is the result of XNOR'ing the IOM0START with the - incoming status from the IOM. When high, MSPI can send - to the buffer. */ - MSPI0_CQFLAGS_CQFLAGS_IOM0READY = 256, /*!< IOM0READY : IOM Buffer 0 Ready Status (from selected IOM). This - status is the result of XNOR'ing the IOM0START with the - incoming status from the IOM. When high, MSPI can send - to the buffer. */ - MSPI0_CQFLAGS_CQFLAGS_SWFLAG7 = 128, /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause - operations */ - MSPI0_CQFLAGS_CQFLAGS_SWFLAG6 = 64, /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause - operatoins */ - MSPI0_CQFLAGS_CQFLAGS_SWFLAG5 = 32, /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause - operations */ - MSPI0_CQFLAGS_CQFLAGS_SWFLAG4 = 16, /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause - operatoins */ - MSPI0_CQFLAGS_CQFLAGS_SWFLAG3 = 8, /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause - operations */ - MSPI0_CQFLAGS_CQFLAGS_SWFLAG2 = 4, /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause - operatoins */ - MSPI0_CQFLAGS_CQFLAGS_SWFLAG1 = 2, /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause - operations */ - MSPI0_CQFLAGS_CQFLAGS_SWFLAG0 = 1, /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause - operatoins */ -} MSPI0_CQFLAGS_CQFLAGS_Enum; - -/* ====================================================== CQSETCLEAR ======================================================= */ -/* ======================================================== CQPAUSE ======================================================== */ -/* ============================================= MSPI0 CQPAUSE CQMASK [0..15] ============================================== */ -typedef enum { /*!< MSPI0_CQPAUSE_CQMASK */ - MSPI0_CQPAUSE_CQMASK_STOP = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete. */ - MSPI0_CQPAUSE_CQMASK_CQIDX = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match. */ - MSPI0_CQPAUSE_CQMASK_BUF1XOREN = 8192, /*!< BUF1XOREN : Buffer 1 Ready Status (from selected IOM/MSPI). - This status is the result of XOR'ing the IOM1START with - the incoming status from the IOM. When high, MSPI can transfer - the buffer. */ - MSPI0_CQPAUSE_CQMASK_BUF0XOREN = 4096, /*!< BUF0XOREN : Buffer 0 Ready Status (from selected IOM/MSPI). - This status is the result of XOR'ing the IOM0START with - the incoming status from the IOM. When high, MSPI can transfer - the buffer. */ - MSPI0_CQPAUSE_CQMASK_DMACPL = 2048, /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT) */ - MSPI0_CQPAUSE_CQMASK_CMDCPL = 1024, /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register) */ - MSPI0_CQPAUSE_CQMASK_IOM1READY = 512, /*!< IOM1READY : IOM Buffer 1 Ready Status (from selected IOM). This - status is the result of XNOR'ing the IOM0START with the - incoming status from the IOM. When high, MSPI can send - to the buffer. */ - MSPI0_CQPAUSE_CQMASK_IOM0READY = 256, /*!< IOM0READY : IOM Buffer 0 Ready Status (from selected IOM). This - status is the result of XNOR'ing the IOM0START with the - incoming status from the IOM. When high, MSPI can send - to the buffer. */ - MSPI0_CQPAUSE_CQMASK_SWFLAG7 = 128, /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause - operations */ - MSPI0_CQPAUSE_CQMASK_SWFLAG6 = 64, /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause - operatoins */ - MSPI0_CQPAUSE_CQMASK_SWFLAG5 = 32, /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause - operations */ - MSPI0_CQPAUSE_CQMASK_SWFLAG4 = 16, /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause - operatoins */ - MSPI0_CQPAUSE_CQMASK_SWFLAG3 = 8, /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause - operations */ - MSPI0_CQPAUSE_CQMASK_SWFLAG2 = 4, /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause - operatoins */ - MSPI0_CQPAUSE_CQMASK_SWFLAG1 = 2, /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause - operations */ - MSPI0_CQPAUSE_CQMASK_SWFLAG0 = 1, /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause - operatoins */ -} MSPI0_CQPAUSE_CQMASK_Enum; - -/* ======================================================= CQCURIDX ======================================================== */ -/* ======================================================= CQENDIDX ======================================================== */ - - -/* =========================================================================================================================== */ -/* ================ PDM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= PCFG ========================================================== */ -/* =============================================== PDM PCFG LRSWAP [31..31] ================================================ */ -typedef enum { /*!< PDM_PCFG_LRSWAP */ - PDM_PCFG_LRSWAP_EN = 1, /*!< EN : Swap left and right channels (FIFO Read RIGHT_LEFT). */ - PDM_PCFG_LRSWAP_NOSWAP = 0, /*!< NOSWAP : No channel swapping (IFO Read LEFT_RIGHT). */ -} PDM_PCFG_LRSWAP_Enum; - -/* ============================================== PDM PCFG PGARIGHT [26..30] =============================================== */ -typedef enum { /*!< PDM_PCFG_PGARIGHT */ - PDM_PCFG_PGARIGHT_P405DB = 31, /*!< P405DB : 40.5 db gain. */ - PDM_PCFG_PGARIGHT_P390DB = 30, /*!< P390DB : 39.0 db gain. */ - PDM_PCFG_PGARIGHT_P375DB = 29, /*!< P375DB : 37.5 db gain. */ - PDM_PCFG_PGARIGHT_P360DB = 28, /*!< P360DB : 36.0 db gain. */ - PDM_PCFG_PGARIGHT_P345DB = 27, /*!< P345DB : 34.5 db gain. */ - PDM_PCFG_PGARIGHT_P330DB = 26, /*!< P330DB : 33.0 db gain. */ - PDM_PCFG_PGARIGHT_P315DB = 25, /*!< P315DB : 31.5 db gain. */ - PDM_PCFG_PGARIGHT_P300DB = 24, /*!< P300DB : 30.0 db gain. */ - PDM_PCFG_PGARIGHT_P285DB = 23, /*!< P285DB : 28.5 db gain. */ - PDM_PCFG_PGARIGHT_P270DB = 22, /*!< P270DB : 27.0 db gain. */ - PDM_PCFG_PGARIGHT_P255DB = 21, /*!< P255DB : 25.5 db gain. */ - PDM_PCFG_PGARIGHT_P240DB = 20, /*!< P240DB : 24.0 db gain. */ - PDM_PCFG_PGARIGHT_P225DB = 19, /*!< P225DB : 22.5 db gain. */ - PDM_PCFG_PGARIGHT_P210DB = 18, /*!< P210DB : 21.0 db gain. */ - PDM_PCFG_PGARIGHT_P195DB = 17, /*!< P195DB : 19.5 db gain. */ - PDM_PCFG_PGARIGHT_P180DB = 16, /*!< P180DB : 18.0 db gain. */ - PDM_PCFG_PGARIGHT_P165DB = 15, /*!< P165DB : 16.5 db gain. */ - PDM_PCFG_PGARIGHT_P150DB = 14, /*!< P150DB : 15.0 db gain. */ - PDM_PCFG_PGARIGHT_P135DB = 13, /*!< P135DB : 13.5 db gain. */ - PDM_PCFG_PGARIGHT_P120DB = 12, /*!< P120DB : 12.0 db gain. */ - PDM_PCFG_PGARIGHT_P105DB = 11, /*!< P105DB : 10.5 db gain. */ - PDM_PCFG_PGARIGHT_P90DB = 10, /*!< P90DB : 9.0 db gain. */ - PDM_PCFG_PGARIGHT_P75DB = 9, /*!< P75DB : 7.5 db gain. */ - PDM_PCFG_PGARIGHT_P60DB = 8, /*!< P60DB : 6.0 db gain. */ - PDM_PCFG_PGARIGHT_P45DB = 7, /*!< P45DB : 4.5 db gain. */ - PDM_PCFG_PGARIGHT_P30DB = 6, /*!< P30DB : 3.0 db gain. */ - PDM_PCFG_PGARIGHT_P15DB = 5, /*!< P15DB : 1.5 db gain. */ - PDM_PCFG_PGARIGHT_0DB = 4, /*!< 0DB : 0.0 db gain. */ - PDM_PCFG_PGARIGHT_M15DB = 3, /*!< M15DB : -1.5 db gain. */ - PDM_PCFG_PGARIGHT_M300DB = 2, /*!< M300DB : -3.0 db gain. */ - PDM_PCFG_PGARIGHT_M45DB = 1, /*!< M45DB : -4.5 db gain. */ - PDM_PCFG_PGARIGHT_M60DB = 0, /*!< M60DB : -6.0 db gain. */ -} PDM_PCFG_PGARIGHT_Enum; - -/* =============================================== PDM PCFG PGALEFT [21..25] =============================================== */ -typedef enum { /*!< PDM_PCFG_PGALEFT */ - PDM_PCFG_PGALEFT_P405DB = 31, /*!< P405DB : 40.5 db gain. */ - PDM_PCFG_PGALEFT_P390DB = 30, /*!< P390DB : 39.0 db gain. */ - PDM_PCFG_PGALEFT_P375DB = 29, /*!< P375DB : 37.5 db gain. */ - PDM_PCFG_PGALEFT_P360DB = 28, /*!< P360DB : 36.0 db gain. */ - PDM_PCFG_PGALEFT_P345DB = 27, /*!< P345DB : 34.5 db gain. */ - PDM_PCFG_PGALEFT_P330DB = 26, /*!< P330DB : 33.0 db gain. */ - PDM_PCFG_PGALEFT_P315DB = 25, /*!< P315DB : 31.5 db gain. */ - PDM_PCFG_PGALEFT_P300DB = 24, /*!< P300DB : 30.0 db gain. */ - PDM_PCFG_PGALEFT_P285DB = 23, /*!< P285DB : 28.5 db gain. */ - PDM_PCFG_PGALEFT_P270DB = 22, /*!< P270DB : 27.0 db gain. */ - PDM_PCFG_PGALEFT_P255DB = 21, /*!< P255DB : 25.5 db gain. */ - PDM_PCFG_PGALEFT_P240DB = 20, /*!< P240DB : 24.0 db gain. */ - PDM_PCFG_PGALEFT_P225DB = 19, /*!< P225DB : 22.5 db gain. */ - PDM_PCFG_PGALEFT_P210DB = 18, /*!< P210DB : 21.0 db gain. */ - PDM_PCFG_PGALEFT_P195DB = 17, /*!< P195DB : 19.5 db gain. */ - PDM_PCFG_PGALEFT_P180DB = 16, /*!< P180DB : 18.0 db gain. */ - PDM_PCFG_PGALEFT_P165DB = 15, /*!< P165DB : 16.5 db gain. */ - PDM_PCFG_PGALEFT_P150DB = 14, /*!< P150DB : 15.0 db gain. */ - PDM_PCFG_PGALEFT_P135DB = 13, /*!< P135DB : 13.5 db gain. */ - PDM_PCFG_PGALEFT_P120DB = 12, /*!< P120DB : 12.0 db gain. */ - PDM_PCFG_PGALEFT_P105DB = 11, /*!< P105DB : 10.5 db gain. */ - PDM_PCFG_PGALEFT_P90DB = 10, /*!< P90DB : 9.0 db gain. */ - PDM_PCFG_PGALEFT_P75DB = 9, /*!< P75DB : 7.5 db gain. */ - PDM_PCFG_PGALEFT_P60DB = 8, /*!< P60DB : 6.0 db gain. */ - PDM_PCFG_PGALEFT_P45DB = 7, /*!< P45DB : 4.5 db gain. */ - PDM_PCFG_PGALEFT_P30DB = 6, /*!< P30DB : 3.0 db gain. */ - PDM_PCFG_PGALEFT_P15DB = 5, /*!< P15DB : 1.5 db gain. */ - PDM_PCFG_PGALEFT_0DB = 4, /*!< 0DB : 0.0 db gain. */ - PDM_PCFG_PGALEFT_M15DB = 3, /*!< M15DB : -1.5 db gain. */ - PDM_PCFG_PGALEFT_M300DB = 2, /*!< M300DB : -3.0 db gain. */ - PDM_PCFG_PGALEFT_M45DB = 1, /*!< M45DB : -4.5 db gain. */ - PDM_PCFG_PGALEFT_M60DB = 0, /*!< M60DB : -6.0 db gain. */ -} PDM_PCFG_PGALEFT_Enum; - -/* =============================================== PDM PCFG MCLKDIV [17..18] =============================================== */ -typedef enum { /*!< PDM_PCFG_MCLKDIV */ - PDM_PCFG_MCLKDIV_MCKDIV4 = 3, /*!< MCKDIV4 : Divide input clock by 4 */ - PDM_PCFG_MCLKDIV_MCKDIV3 = 2, /*!< MCKDIV3 : Divide input clock by 3 */ - PDM_PCFG_MCLKDIV_MCKDIV2 = 1, /*!< MCKDIV2 : Divide input clock by 2 */ - PDM_PCFG_MCLKDIV_MCKDIV1 = 0, /*!< MCKDIV1 : Divide input clock by 1 */ -} PDM_PCFG_MCLKDIV_Enum; - -/* ================================================ PDM PCFG ADCHPD [9..9] ================================================= */ -typedef enum { /*!< PDM_PCFG_ADCHPD */ - PDM_PCFG_ADCHPD_EN = 0, /*!< EN : Enable high pass filter. */ - PDM_PCFG_ADCHPD_DIS = 1, /*!< DIS : Disable high pass filter. */ -} PDM_PCFG_ADCHPD_Enum; - -/* =============================================== PDM PCFG SOFTMUTE [1..1] ================================================ */ -typedef enum { /*!< PDM_PCFG_SOFTMUTE */ - PDM_PCFG_SOFTMUTE_EN = 1, /*!< EN : Enable Soft Mute. */ - PDM_PCFG_SOFTMUTE_DIS = 0, /*!< DIS : Disable Soft Mute. */ -} PDM_PCFG_SOFTMUTE_Enum; - -/* =============================================== PDM PCFG PDMCOREEN [0..0] =============================================== */ -typedef enum { /*!< PDM_PCFG_PDMCOREEN */ - PDM_PCFG_PDMCOREEN_EN = 1, /*!< EN : Enable Data Streaming. */ - PDM_PCFG_PDMCOREEN_DIS = 0, /*!< DIS : Disable Data Streaming. */ -} PDM_PCFG_PDMCOREEN_Enum; - -/* ========================================================= VCFG ========================================================== */ -/* =============================================== PDM VCFG IOCLKEN [31..31] =============================================== */ -typedef enum { /*!< PDM_VCFG_IOCLKEN */ - PDM_VCFG_IOCLKEN_DIS = 0, /*!< DIS : Disable FIFO read. */ - PDM_VCFG_IOCLKEN_EN = 1, /*!< EN : Enable FIFO read. */ -} PDM_VCFG_IOCLKEN_Enum; - -/* ================================================ PDM VCFG RSTB [30..30] ================================================= */ -typedef enum { /*!< PDM_VCFG_RSTB */ - PDM_VCFG_RSTB_RESET = 0, /*!< RESET : Reset the core. */ - PDM_VCFG_RSTB_NORM = 1, /*!< NORM : Enable the core. */ -} PDM_VCFG_RSTB_Enum; - -/* ============================================== PDM VCFG PDMCLKSEL [27..29] ============================================== */ -typedef enum { /*!< PDM_VCFG_PDMCLKSEL */ - PDM_VCFG_PDMCLKSEL_DISABLE = 0, /*!< DISABLE : Static value. */ - PDM_VCFG_PDMCLKSEL_12MHz = 1, /*!< 12MHz : PDM clock is 12 MHz. */ - PDM_VCFG_PDMCLKSEL_6MHz = 2, /*!< 6MHz : PDM clock is 6 MHz. */ - PDM_VCFG_PDMCLKSEL_3MHz = 3, /*!< 3MHz : PDM clock is 3 MHz. */ - PDM_VCFG_PDMCLKSEL_1_5MHz = 4, /*!< 1_5MHz : PDM clock is 1.5 MHz. */ - PDM_VCFG_PDMCLKSEL_750KHz = 5, /*!< 750KHz : PDM clock is 750 KHz. */ - PDM_VCFG_PDMCLKSEL_375KHz = 6, /*!< 375KHz : PDM clock is 375 KHz. */ - PDM_VCFG_PDMCLKSEL_187KHz = 7, /*!< 187KHz : PDM clock is 187.5 KHz. */ -} PDM_VCFG_PDMCLKSEL_Enum; - -/* ============================================== PDM VCFG PDMCLKEN [26..26] =============================================== */ -typedef enum { /*!< PDM_VCFG_PDMCLKEN */ - PDM_VCFG_PDMCLKEN_DIS = 0, /*!< DIS : Disable serial clock. */ - PDM_VCFG_PDMCLKEN_EN = 1, /*!< EN : Enable serial clock. */ -} PDM_VCFG_PDMCLKEN_Enum; - -/* ================================================ PDM VCFG I2SEN [20..20] ================================================ */ -typedef enum { /*!< PDM_VCFG_I2SEN */ - PDM_VCFG_I2SEN_DIS = 0, /*!< DIS : Disable I2S interface. */ - PDM_VCFG_I2SEN_EN = 1, /*!< EN : Enable I2S interface. */ -} PDM_VCFG_I2SEN_Enum; - -/* =============================================== PDM VCFG BCLKINV [19..19] =============================================== */ -typedef enum { /*!< PDM_VCFG_BCLKINV */ - PDM_VCFG_BCLKINV_INV = 0, /*!< INV : BCLK inverted. */ - PDM_VCFG_BCLKINV_NORM = 1, /*!< NORM : BCLK not inverted. */ -} PDM_VCFG_BCLKINV_Enum; - -/* ============================================== PDM VCFG DMICKDEL [17..17] =============================================== */ -typedef enum { /*!< PDM_VCFG_DMICKDEL */ - PDM_VCFG_DMICKDEL_0CYC = 0, /*!< 0CYC : No delay. */ - PDM_VCFG_DMICKDEL_1CYC = 1, /*!< 1CYC : 1 cycle delay. */ -} PDM_VCFG_DMICKDEL_Enum; - -/* ================================================ PDM VCFG SELAP [16..16] ================================================ */ -typedef enum { /*!< PDM_VCFG_SELAP */ - PDM_VCFG_SELAP_I2S = 1, /*!< I2S : Clock source from I2S BCLK. */ - PDM_VCFG_SELAP_INTERNAL = 0, /*!< INTERNAL : Clock source from internal clock generator. */ -} PDM_VCFG_SELAP_Enum; - -/* ================================================ PDM VCFG PCMPACK [8..8] ================================================ */ -typedef enum { /*!< PDM_VCFG_PCMPACK */ - PDM_VCFG_PCMPACK_DIS = 0, /*!< DIS : Disable PCM packing. */ - PDM_VCFG_PCMPACK_EN = 1, /*!< EN : Enable PCM packing. */ -} PDM_VCFG_PCMPACK_Enum; - -/* ================================================= PDM VCFG CHSET [3..4] ================================================= */ -typedef enum { /*!< PDM_VCFG_CHSET */ - PDM_VCFG_CHSET_DIS = 0, /*!< DIS : Channel disabled. */ - PDM_VCFG_CHSET_LEFT = 1, /*!< LEFT : Mono left channel. */ - PDM_VCFG_CHSET_RIGHT = 2, /*!< RIGHT : Mono right channel. */ - PDM_VCFG_CHSET_STEREO = 3, /*!< STEREO : Stereo channels. */ -} PDM_VCFG_CHSET_Enum; - -/* ======================================================= VOICESTAT ======================================================= */ -/* ======================================================= FIFOREAD ======================================================== */ -/* ======================================================= FIFOFLUSH ======================================================= */ -/* ======================================================== FIFOTHR ======================================================== */ -/* ========================================================= INTEN ========================================================= */ -/* ======================================================== INTSTAT ======================================================== */ -/* ======================================================== INTCLR ========================================================= */ -/* ======================================================== INTSET ========================================================= */ -/* ======================================================= DMATRIGEN ======================================================= */ -/* ====================================================== DMATRIGSTAT ====================================================== */ -/* ======================================================== DMACFG ========================================================= */ -/* =============================================== PDM DMACFG DMAPRI [8..8] ================================================ */ -typedef enum { /*!< PDM_DMACFG_DMAPRI */ - PDM_DMACFG_DMAPRI_LOW = 0, /*!< LOW : Low Priority (service as best effort) */ - PDM_DMACFG_DMAPRI_HIGH = 1, /*!< HIGH : High Priority (service immediately) */ -} PDM_DMACFG_DMAPRI_Enum; - -/* =============================================== PDM DMACFG DMADIR [2..2] ================================================ */ -typedef enum { /*!< PDM_DMACFG_DMADIR */ - PDM_DMACFG_DMADIR_P2M = 0, /*!< P2M : Peripheral to Memory (SRAM) transaction. THe PDM module - will only DMA to memory. */ - PDM_DMACFG_DMADIR_M2P = 1, /*!< M2P : Memory to Peripheral transaction. Not available for PDM - module */ -} PDM_DMACFG_DMADIR_Enum; - -/* ================================================ PDM DMACFG DMAEN [0..0] ================================================ */ -typedef enum { /*!< PDM_DMACFG_DMAEN */ - PDM_DMACFG_DMAEN_DIS = 0, /*!< DIS : Disable DMA Function */ - PDM_DMACFG_DMAEN_EN = 1, /*!< EN : Enable DMA Function */ -} PDM_DMACFG_DMAEN_Enum; - -/* ====================================================== DMATOTCOUNT ====================================================== */ -/* ====================================================== DMATARGADDR ====================================================== */ -/* ======================================================== DMASTAT ======================================================== */ - - -/* =========================================================================================================================== */ -/* ================ PWRCTRL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================= SUPPLYSRC ======================================================= */ -/* ========================================== PWRCTRL SUPPLYSRC BLEBUCKEN [0..0] =========================================== */ -typedef enum { /*!< PWRCTRL_SUPPLYSRC_BLEBUCKEN */ - PWRCTRL_SUPPLYSRC_BLEBUCKEN_EN = 1, /*!< EN : Enable the BLE Buck. */ - PWRCTRL_SUPPLYSRC_BLEBUCKEN_DIS = 0, /*!< DIS : Disable the BLE Buck. */ -} PWRCTRL_SUPPLYSRC_BLEBUCKEN_Enum; - -/* ===================================================== SUPPLYSTATUS ====================================================== */ -/* ========================================= PWRCTRL SUPPLYSTATUS BLEBUCKON [1..1] ========================================= */ -typedef enum { /*!< PWRCTRL_SUPPLYSTATUS_BLEBUCKON */ - PWRCTRL_SUPPLYSTATUS_BLEBUCKON_LDO = 0, /*!< LDO : Indicates the the LDO is supplying the BLE/Burst power - domain */ - PWRCTRL_SUPPLYSTATUS_BLEBUCKON_BUCK = 1, /*!< BUCK : Indicates the the Buck is supplying the BLE/Burst power - domain */ -} PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Enum; - -/* ======================================== PWRCTRL SUPPLYSTATUS SIMOBUCKON [0..0] ========================================= */ -typedef enum { /*!< PWRCTRL_SUPPLYSTATUS_SIMOBUCKON */ - PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_OFF = 0, /*!< OFF : Indicates the the SIMO Buck is OFF. */ - PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_ON = 1, /*!< ON : Indicates the the SIMO Buck is ON. */ -} PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Enum; - -/* ======================================================= DEVPWREN ======================================================== */ -/* =========================================== PWRCTRL DEVPWREN PWRBLEL [15..15] =========================================== */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRBLEL */ - PWRCTRL_DEVPWREN_PWRBLEL_EN = 1, /*!< EN : Power up BLE controller */ - PWRCTRL_DEVPWREN_PWRBLEL_DIS = 0, /*!< DIS : Power down BLE controller */ -} PWRCTRL_DEVPWREN_PWRBLEL_Enum; - -/* =========================================== PWRCTRL DEVPWREN PWRPDM [14..14] ============================================ */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRPDM */ - PWRCTRL_DEVPWREN_PWRPDM_EN = 1, /*!< EN : Power up PDM */ - PWRCTRL_DEVPWREN_PWRPDM_DIS = 0, /*!< DIS : Power down PDM */ -} PWRCTRL_DEVPWREN_PWRPDM_Enum; - -/* ========================================== PWRCTRL DEVPWREN PWRMSPI2 [13..13] =========================================== */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRMSPI2 */ - PWRCTRL_DEVPWREN_PWRMSPI2_EN = 1, /*!< EN : Power up MSPI2 */ - PWRCTRL_DEVPWREN_PWRMSPI2_DIS = 0, /*!< DIS : Power down MSPI2 */ -} PWRCTRL_DEVPWREN_PWRMSPI2_Enum; - -/* ========================================== PWRCTRL DEVPWREN PWRMSPI1 [12..12] =========================================== */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRMSPI1 */ - PWRCTRL_DEVPWREN_PWRMSPI1_EN = 1, /*!< EN : Power up MSPI1 */ - PWRCTRL_DEVPWREN_PWRMSPI1_DIS = 0, /*!< DIS : Power down MSPI1 */ -} PWRCTRL_DEVPWREN_PWRMSPI1_Enum; - -/* ========================================== PWRCTRL DEVPWREN PWRMSPI0 [11..11] =========================================== */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRMSPI0 */ - PWRCTRL_DEVPWREN_PWRMSPI0_EN = 1, /*!< EN : Power up MSPI0 */ - PWRCTRL_DEVPWREN_PWRMSPI0_DIS = 0, /*!< DIS : Power down MSPI0 */ -} PWRCTRL_DEVPWREN_PWRMSPI0_Enum; - -/* ========================================== PWRCTRL DEVPWREN PWRSCARD [10..10] =========================================== */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRSCARD */ - PWRCTRL_DEVPWREN_PWRSCARD_EN = 1, /*!< EN : Power up SCARD */ - PWRCTRL_DEVPWREN_PWRSCARD_DIS = 0, /*!< DIS : Power down SCARD */ -} PWRCTRL_DEVPWREN_PWRSCARD_Enum; - -/* ============================================ PWRCTRL DEVPWREN PWRADC [9..9] ============================================= */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRADC */ - PWRCTRL_DEVPWREN_PWRADC_EN = 1, /*!< EN : Power up ADC */ - PWRCTRL_DEVPWREN_PWRADC_DIS = 0, /*!< DIS : Power Down ADC */ -} PWRCTRL_DEVPWREN_PWRADC_Enum; - -/* =========================================== PWRCTRL DEVPWREN PWRUART1 [8..8] ============================================ */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRUART1 */ - PWRCTRL_DEVPWREN_PWRUART1_EN = 1, /*!< EN : Power up UART 1 */ - PWRCTRL_DEVPWREN_PWRUART1_DIS = 0, /*!< DIS : Power down UART 1 */ -} PWRCTRL_DEVPWREN_PWRUART1_Enum; - -/* =========================================== PWRCTRL DEVPWREN PWRUART0 [7..7] ============================================ */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRUART0 */ - PWRCTRL_DEVPWREN_PWRUART0_EN = 1, /*!< EN : Power up UART 0 */ - PWRCTRL_DEVPWREN_PWRUART0_DIS = 0, /*!< DIS : Power down UART 0 */ -} PWRCTRL_DEVPWREN_PWRUART0_Enum; - -/* ============================================ PWRCTRL DEVPWREN PWRIOM5 [6..6] ============================================ */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM5 */ - PWRCTRL_DEVPWREN_PWRIOM5_EN = 1, /*!< EN : Power up IO Master 5 */ - PWRCTRL_DEVPWREN_PWRIOM5_DIS = 0, /*!< DIS : Power down IO Master 5 */ -} PWRCTRL_DEVPWREN_PWRIOM5_Enum; - -/* ============================================ PWRCTRL DEVPWREN PWRIOM4 [5..5] ============================================ */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM4 */ - PWRCTRL_DEVPWREN_PWRIOM4_EN = 1, /*!< EN : Power up IO Master 4 */ - PWRCTRL_DEVPWREN_PWRIOM4_DIS = 0, /*!< DIS : Power down IO Master 4 */ -} PWRCTRL_DEVPWREN_PWRIOM4_Enum; - -/* ============================================ PWRCTRL DEVPWREN PWRIOM3 [4..4] ============================================ */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM3 */ - PWRCTRL_DEVPWREN_PWRIOM3_EN = 1, /*!< EN : Power up IO Master 3 */ - PWRCTRL_DEVPWREN_PWRIOM3_DIS = 0, /*!< DIS : Power down IO Master 3 */ -} PWRCTRL_DEVPWREN_PWRIOM3_Enum; - -/* ============================================ PWRCTRL DEVPWREN PWRIOM2 [3..3] ============================================ */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM2 */ - PWRCTRL_DEVPWREN_PWRIOM2_EN = 1, /*!< EN : Power up IO Master 2 */ - PWRCTRL_DEVPWREN_PWRIOM2_DIS = 0, /*!< DIS : Power down IO Master 2 */ -} PWRCTRL_DEVPWREN_PWRIOM2_Enum; - -/* ============================================ PWRCTRL DEVPWREN PWRIOM1 [2..2] ============================================ */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM1 */ - PWRCTRL_DEVPWREN_PWRIOM1_EN = 1, /*!< EN : Power up IO Master 1 */ - PWRCTRL_DEVPWREN_PWRIOM1_DIS = 0, /*!< DIS : Power down IO Master 1 */ -} PWRCTRL_DEVPWREN_PWRIOM1_Enum; - -/* ============================================ PWRCTRL DEVPWREN PWRIOM0 [1..1] ============================================ */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOM0 */ - PWRCTRL_DEVPWREN_PWRIOM0_EN = 1, /*!< EN : Power up IO Master 0 */ - PWRCTRL_DEVPWREN_PWRIOM0_DIS = 0, /*!< DIS : Power down IO Master 0 */ -} PWRCTRL_DEVPWREN_PWRIOM0_Enum; - -/* ============================================ PWRCTRL DEVPWREN PWRIOS [0..0] ============================================= */ -typedef enum { /*!< PWRCTRL_DEVPWREN_PWRIOS */ - PWRCTRL_DEVPWREN_PWRIOS_EN = 1, /*!< EN : Power up IO slave */ - PWRCTRL_DEVPWREN_PWRIOS_DIS = 0, /*!< DIS : Power down IO slave */ -} PWRCTRL_DEVPWREN_PWRIOS_Enum; - -/* ===================================================== MEMPWDINSLEEP ===================================================== */ -/* ====================================== PWRCTRL MEMPWDINSLEEP CACHEPWDSLP [31..31] ======================================= */ -typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP */ - PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_EN = 1, /*!< EN : Power down cache in deep sleep */ - PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_DIS = 0, /*!< DIS : Retain cache in deep sleep */ -} PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Enum; - -/* ====================================== PWRCTRL MEMPWDINSLEEP FLASH1PWDSLP [14..14] ====================================== */ -typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP */ - PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_EN = 1, /*!< EN : Flash1 is powered down during deepsleep */ - PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_DIS = 0, /*!< DIS : Flash1 is kept powered on during deepsleep */ -} PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Enum; - -/* ====================================== PWRCTRL MEMPWDINSLEEP FLASH0PWDSLP [13..13] ====================================== */ -typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP */ - PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_EN = 1, /*!< EN : Flash0 is powered down during deepsleep */ - PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_DIS = 0, /*!< DIS : Flash0 is kept powered on during deepsleep */ -} PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Enum; - -/* ======================================= PWRCTRL MEMPWDINSLEEP SRAMPWDSLP [3..12] ======================================== */ -typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_NONE = 0, /*!< NONE : All banks retained */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP0 = 1, /*!< GROUP0 : SRAM GROUP0 powered down (64KB-96KB) */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP1 = 2, /*!< GROUP1 : SRAM GROUP1 powered down (96KB-128KB) */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP2 = 4, /*!< GROUP2 : SRAM GROUP2 powered down (128KB-160KB) */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP3 = 8, /*!< GROUP3 : SRAM GROUP3 powered down (160KB-192KB) */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP4 = 16, /*!< GROUP4 : SRAM GROUP4 powered down (192KB-224KB) */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP5 = 32, /*!< GROUP5 : SRAM GROUP5 powered down (224KB-256KB) */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP6 = 64, /*!< GROUP6 : SRAM GROUP6 powered down (256KB-288KB) */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP7 = 128,/*!< GROUP7 : SRAM GROUP7 powered down (288KB-320KB) */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP8 = 256,/*!< GROUP8 : SRAM GROUP8 powered down (320KB-352KB) */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP9 = 512,/*!< GROUP9 : SRAM GROUP9 powered down (352KB-384KB) */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_SRAM64K = 3, /*!< SRAM64K : Powerdown lower 64k SRAM (64KB-128KB) */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_SRAM128K = 15,/*!< SRAM128K : Powerdown lower 128k SRAM (64KB-192KB) */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER32K = 1022,/*!< ALLBUTLOWER32K : All SRAM banks but lower 32k powered down (96KB-384KB). */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER64K = 1020,/*!< ALLBUTLOWER64K : All banks but lower 64k powered down. */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER128K = 1008,/*!< ALLBUTLOWER128K : All banks but lower 128k powered down. */ - PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALL = 1023, /*!< ALL : All banks powered down. */ -} PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Enum; - -/* ======================================== PWRCTRL MEMPWDINSLEEP DTCMPWDSLP [0..2] ======================================== */ -typedef enum { /*!< PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP */ - PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_NONE = 0, /*!< NONE : All DTCM retained */ - PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM0 = 1,/*!< GROUP0DTCM0 : Group0_DTCM0 powered down in deep sleep (0KB-8KB) */ - PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM1 = 2,/*!< GROUP0DTCM1 : Group0_DTCM1 powered down in deep sleep (8KB-32KB) */ - PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0 = 3, /*!< GROUP0 : Both DTCMs in group0 are powered down in deep sleep - (0KB-32KB) */ - PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALLBUTGROUP0DTCM0 = 6,/*!< ALLBUTGROUP0DTCM0 : Group1 and Group0_DTCM1 are powered down - in deep sleep (8KB-64KB) */ - PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP1 = 4, /*!< GROUP1 : Group1 DTCM powered down in deep sleep (32KB-64KB) */ - PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL = 7, /*!< ALL : All DTCMs powered down in deep sleep (0KB-64KB) */ -} PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Enum; - -/* ======================================================= MEMPWREN ======================================================== */ -/* =========================================== PWRCTRL MEMPWREN CACHEB2 [31..31] =========================================== */ -typedef enum { /*!< PWRCTRL_MEMPWREN_CACHEB2 */ - PWRCTRL_MEMPWREN_CACHEB2_EN = 1, /*!< EN : Power up Cache Bank 2 */ - PWRCTRL_MEMPWREN_CACHEB2_DIS = 0, /*!< DIS : Power down Cache Bank 2 */ -} PWRCTRL_MEMPWREN_CACHEB2_Enum; - -/* =========================================== PWRCTRL MEMPWREN CACHEB0 [30..30] =========================================== */ -typedef enum { /*!< PWRCTRL_MEMPWREN_CACHEB0 */ - PWRCTRL_MEMPWREN_CACHEB0_EN = 1, /*!< EN : Power up Cache Bank 0 */ - PWRCTRL_MEMPWREN_CACHEB0_DIS = 0, /*!< DIS : Power down Cache Bank 0 */ -} PWRCTRL_MEMPWREN_CACHEB0_Enum; - -/* =========================================== PWRCTRL MEMPWREN FLASH1 [14..14] ============================================ */ -typedef enum { /*!< PWRCTRL_MEMPWREN_FLASH1 */ - PWRCTRL_MEMPWREN_FLASH1_EN = 1, /*!< EN : Power up Flash group 1 (1MB-2MB) */ - PWRCTRL_MEMPWREN_FLASH1_DIS = 0, /*!< DIS : Power down Flash group 1 (1MB-2MB) */ -} PWRCTRL_MEMPWREN_FLASH1_Enum; - -/* =========================================== PWRCTRL MEMPWREN FLASH0 [13..13] ============================================ */ -typedef enum { /*!< PWRCTRL_MEMPWREN_FLASH0 */ - PWRCTRL_MEMPWREN_FLASH0_EN = 1, /*!< EN : Power up Flash group 0 (0MB-1MB) */ - PWRCTRL_MEMPWREN_FLASH0_DIS = 0, /*!< DIS : Power down Flash group 0 (0MB-1MB) */ -} PWRCTRL_MEMPWREN_FLASH0_Enum; - -/* ============================================= PWRCTRL MEMPWREN SRAM [3..12] ============================================= */ -typedef enum { /*!< PWRCTRL_MEMPWREN_SRAM */ - PWRCTRL_MEMPWREN_SRAM_NONE = 0, /*!< NONE : Do not power ON any of the SRAM banks */ - PWRCTRL_MEMPWREN_SRAM_GROUP0 = 1, /*!< GROUP0 : Power ON only SRAM 64KB group0 (addr: 0x10010000 - - 0x1001FFFF) */ - PWRCTRL_MEMPWREN_SRAM_GROUP1 = 2, /*!< GROUP1 : Power ON only SRAM 64KB group1 (addr: 0x10020000 - - 0x1002FFFF) */ - PWRCTRL_MEMPWREN_SRAM_GROUP2 = 4, /*!< GROUP2 : Power ON only SRAM 64KB group2 (addr: 0x10030000 - - 0x1003FFFF) */ - PWRCTRL_MEMPWREN_SRAM_GROUP3 = 8, /*!< GROUP3 : Power ON only SRAM 64KB group3 (addr: 0x10040000 - - 0x1004FFFF) */ - PWRCTRL_MEMPWREN_SRAM_GROUP4 = 16, /*!< GROUP4 : Power ON only SRAM 64KB group4 (addr: 0x10050000 - - 0x1005FFFF) */ - PWRCTRL_MEMPWREN_SRAM_GROUP5 = 32, /*!< GROUP5 : Power ON only SRAM 64KB group5 (addr: 0x10060000 - - 0x1006FFFF) */ - PWRCTRL_MEMPWREN_SRAM_GROUP6 = 64, /*!< GROUP6 : Power ON only SRAM 64KB group6 (addr: 0x10070000 - - 0x1007FFFF) */ - PWRCTRL_MEMPWREN_SRAM_GROUP7 = 128, /*!< GROUP7 : Power ON only SRAM 64KB group7 (addr: 0x10080000 - - 0x1008FFFF) */ - PWRCTRL_MEMPWREN_SRAM_GROUP8 = 256, /*!< GROUP8 : Power ON only SRAM 96KB group8 (addr: 0x10090000 - - 0x100A7FFF) */ - PWRCTRL_MEMPWREN_SRAM_GROUP9 = 512, /*!< GROUP9 : Power ON only SRAM 96KB group9 (addr: 0x100A8000 - - 0x100BFFFF) */ - PWRCTRL_MEMPWREN_SRAM_SRAM128K = 3, /*!< SRAM128K : Power ON only lower 128k (addr: 0x10010000 - 0x1002FFFF) */ - PWRCTRL_MEMPWREN_SRAM_SRAM256K = 15, /*!< SRAM256K : Power ON only lower 256k (addr: 0x10010000 - 0x1004FFFF) */ - PWRCTRL_MEMPWREN_SRAM_SRAM512K = 255, /*!< SRAM512K : Power ON only lower 512k (addr: 0x10010000 - 0x1008FFFF) */ - PWRCTRL_MEMPWREN_SRAM_ALL = 1023, /*!< ALL : All SRAM banks (704K) powered ON (addr: 0x10010000 - 0x100BFFFF) */ -} PWRCTRL_MEMPWREN_SRAM_Enum; - -/* ============================================= PWRCTRL MEMPWREN DTCM [0..2] ============================================== */ -typedef enum { /*!< PWRCTRL_MEMPWREN_DTCM */ - PWRCTRL_MEMPWREN_DTCM_NONE = 0, /*!< NONE : Do not enable power to any DTCMs */ - PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM0 = 1, /*!< GROUP0DTCM0 : Power ON only 8KB GROUP0_DTCM0 (0 - 8KB, addr: - 0x10000000 - 0x10001FFF) */ - PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM1 = 2, /*!< GROUP0DTCM1 : Power ON only 24KB GROUP0_DTCM1 (8KB - 32KB, addr: - 0x10002000 - 0x10007FFF) */ - PWRCTRL_MEMPWREN_DTCM_GROUP0 = 3, /*!< GROUP0 : Power ON only DTCMs in 32KB group0 (0 - 32KB, addr: - 0x10000000 - 0x10007FFF) */ - PWRCTRL_MEMPWREN_DTCM_GROUP1 = 4, /*!< GROUP1 : Power ON only DTCMs in 32KB group1 (32KB - 64KB, addr: - 0x10008000 - 0x1000FFFF) */ - PWRCTRL_MEMPWREN_DTCM_ALL = 7, /*!< ALL : Power ON all DTCMs (0 - 64KB, addr: 0x10000000 - 0x1000FFFF) */ -} PWRCTRL_MEMPWREN_DTCM_Enum; - -/* ===================================================== MEMPWRSTATUS ====================================================== */ -/* ===================================================== DEVPWRSTATUS ====================================================== */ -/* ======================================================= SRAMCTRL ======================================================== */ -/* ======================================== PWRCTRL SRAMCTRL SRAMLIGHTSLEEP [8..19] ======================================== */ -typedef enum { /*!< PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP */ - PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_ALL = 255, /*!< ALL : Enable LIGHT SLEEP for ALL SRAMs */ - PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_DIS = 0, /*!< DIS : Disables LIGHT SLEEP for ALL SRAMs */ -} PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Enum; - -/* ======================================= PWRCTRL SRAMCTRL SRAMMASTERCLKGATE [2..2] ======================================= */ -typedef enum { /*!< PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE */ - PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_EN = 1, /*!< EN : Enable Master SRAM Clock Gate */ - PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_DIS = 0, /*!< DIS : Disables Master SRAM Clock Gating */ -} PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Enum; - -/* ========================================== PWRCTRL SRAMCTRL SRAMCLKGATE [1..1] ========================================== */ -typedef enum { /*!< PWRCTRL_SRAMCTRL_SRAMCLKGATE */ - PWRCTRL_SRAMCTRL_SRAMCLKGATE_EN = 1, /*!< EN : Enable Individual SRAM Clock Gating */ - PWRCTRL_SRAMCTRL_SRAMCLKGATE_DIS = 0, /*!< DIS : Disables Individual SRAM Clock Gating */ -} PWRCTRL_SRAMCTRL_SRAMCLKGATE_Enum; - -/* ======================================================= ADCSTATUS ======================================================= */ -/* ========================================================= MISC ========================================================== */ -/* ============================================ PWRCTRL MISC MEMVRLPBLE [6..6] ============================================= */ -typedef enum { /*!< PWRCTRL_MISC_MEMVRLPBLE */ - PWRCTRL_MISC_MEMVRLPBLE_EN = 1, /*!< EN : Mem VR can go to lp mode even when BLE is powered on. */ - PWRCTRL_MISC_MEMVRLPBLE_DIS = 0, /*!< DIS : Mem VR will stay in active mode when BLE is powered on. */ -} PWRCTRL_MISC_MEMVRLPBLE_Enum; - -/* ===================================================== DEVPWREVENTEN ===================================================== */ -/* ======================================= PWRCTRL DEVPWREVENTEN BURSTEVEN [31..31] ======================================== */ -typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BURSTEVEN */ - PWRCTRL_DEVPWREVENTEN_BURSTEVEN_EN = 1, /*!< EN : Enable BURST status event */ - PWRCTRL_DEVPWREVENTEN_BURSTEVEN_DIS = 0, /*!< DIS : Disable BURST status event */ -} PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Enum; - -/* ==================================== PWRCTRL DEVPWREVENTEN BURSTFEATUREEVEN [30..30] ==================================== */ -typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN */ - PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_EN = 1,/*!< EN : Enable BURSTFEATURE status event */ - PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_DIS = 0,/*!< DIS : Disable BURSTFEATURE status event */ -} PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Enum; - -/* ===================================== PWRCTRL DEVPWREVENTEN BLEFEATUREEVEN [29..29] ===================================== */ -typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN */ - PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_EN = 1, /*!< EN : Enable BLEFEATURE status event */ - PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_DIS = 0, /*!< DIS : Disable BLEFEATURE status event */ -} PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Enum; - -/* ========================================= PWRCTRL DEVPWREVENTEN BLELEVEN [8..8] ========================================= */ -typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_BLELEVEN */ - PWRCTRL_DEVPWREVENTEN_BLELEVEN_EN = 1, /*!< EN : Enable BLE power-on status event */ - PWRCTRL_DEVPWREVENTEN_BLELEVEN_DIS = 0, /*!< DIS : Disable BLE power-on status event */ -} PWRCTRL_DEVPWREVENTEN_BLELEVEN_Enum; - -/* ========================================= PWRCTRL DEVPWREVENTEN PDMEVEN [7..7] ========================================== */ -typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_PDMEVEN */ - PWRCTRL_DEVPWREVENTEN_PDMEVEN_EN = 1, /*!< EN : Enable PDM power-on status event */ - PWRCTRL_DEVPWREVENTEN_PDMEVEN_DIS = 0, /*!< DIS : Disable PDM power-on status event */ -} PWRCTRL_DEVPWREVENTEN_PDMEVEN_Enum; - -/* ========================================= PWRCTRL DEVPWREVENTEN MSPIEVEN [6..6] ========================================= */ -typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_MSPIEVEN */ - PWRCTRL_DEVPWREVENTEN_MSPIEVEN_EN = 1, /*!< EN : Enable MSPI power-on status event */ - PWRCTRL_DEVPWREVENTEN_MSPIEVEN_DIS = 0, /*!< DIS : Disable MSPI power-on status event */ -} PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Enum; - -/* ========================================= PWRCTRL DEVPWREVENTEN ADCEVEN [5..5] ========================================== */ -typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_ADCEVEN */ - PWRCTRL_DEVPWREVENTEN_ADCEVEN_EN = 1, /*!< EN : Enable ADC power-on status event */ - PWRCTRL_DEVPWREVENTEN_ADCEVEN_DIS = 0, /*!< DIS : Disable ADC power-on status event */ -} PWRCTRL_DEVPWREVENTEN_ADCEVEN_Enum; - -/* ========================================= PWRCTRL DEVPWREVENTEN HCPCEVEN [4..4] ========================================= */ -typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_HCPCEVEN */ - PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN = 1, /*!< EN : Enable HCPC power-on status event */ - PWRCTRL_DEVPWREVENTEN_HCPCEVEN_DIS = 0, /*!< DIS : Disable HCPC power-on status event */ -} PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Enum; - -/* ========================================= PWRCTRL DEVPWREVENTEN HCPBEVEN [3..3] ========================================= */ -typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_HCPBEVEN */ - PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN = 1, /*!< EN : Enable HCPB power-on status event */ - PWRCTRL_DEVPWREVENTEN_HCPBEVEN_DIS = 0, /*!< DIS : Disable HCPB power-on status event */ -} PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Enum; - -/* ========================================= PWRCTRL DEVPWREVENTEN HCPAEVEN [2..2] ========================================= */ -typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_HCPAEVEN */ - PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN = 1, /*!< EN : Enable HCPA power-on status event */ - PWRCTRL_DEVPWREVENTEN_HCPAEVEN_DIS = 0, /*!< DIS : Disable HCPA power-on status event */ -} PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Enum; - -/* ========================================= PWRCTRL DEVPWREVENTEN MCUHEVEN [1..1] ========================================= */ -typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_MCUHEVEN */ - PWRCTRL_DEVPWREVENTEN_MCUHEVEN_EN = 1, /*!< EN : Enable MCHU power-on status event */ - PWRCTRL_DEVPWREVENTEN_MCUHEVEN_DIS = 0, /*!< DIS : Disable MCUH power-on status event */ -} PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Enum; - -/* ========================================= PWRCTRL DEVPWREVENTEN MCULEVEN [0..0] ========================================= */ -typedef enum { /*!< PWRCTRL_DEVPWREVENTEN_MCULEVEN */ - PWRCTRL_DEVPWREVENTEN_MCULEVEN_EN = 1, /*!< EN : Enable MCUL power-on status event */ - PWRCTRL_DEVPWREVENTEN_MCULEVEN_DIS = 0, /*!< DIS : Disable MCUL power-on status event */ -} PWRCTRL_DEVPWREVENTEN_MCULEVEN_Enum; - -/* ===================================================== MEMPWREVENTEN ===================================================== */ -/* ======================================= PWRCTRL MEMPWREVENTEN CACHEB2EN [31..31] ======================================== */ -typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_CACHEB2EN */ - PWRCTRL_MEMPWREVENTEN_CACHEB2EN_EN = 1, /*!< EN : Enable CACHE BANK 2 status event */ - PWRCTRL_MEMPWREVENTEN_CACHEB2EN_DIS = 0, /*!< DIS : Disable CACHE BANK 2 status event */ -} PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Enum; - -/* ======================================= PWRCTRL MEMPWREVENTEN CACHEB0EN [30..30] ======================================== */ -typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_CACHEB0EN */ - PWRCTRL_MEMPWREVENTEN_CACHEB0EN_EN = 1, /*!< EN : Enable CACHE BANK 0 status event */ - PWRCTRL_MEMPWREVENTEN_CACHEB0EN_DIS = 0, /*!< DIS : Disable CACHE BANK 0 status event */ -} PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Enum; - -/* ======================================== PWRCTRL MEMPWREVENTEN FLASH1EN [14..14] ======================================== */ -typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_FLASH1EN */ - PWRCTRL_MEMPWREVENTEN_FLASH1EN_EN = 1, /*!< EN : Enable FLASH status event */ - PWRCTRL_MEMPWREVENTEN_FLASH1EN_DIS = 0, /*!< DIS : Disables FLASH status event */ -} PWRCTRL_MEMPWREVENTEN_FLASH1EN_Enum; - -/* ======================================== PWRCTRL MEMPWREVENTEN FLASH0EN [13..13] ======================================== */ -typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_FLASH0EN */ - PWRCTRL_MEMPWREVENTEN_FLASH0EN_EN = 1, /*!< EN : Enable FLASH status event */ - PWRCTRL_MEMPWREVENTEN_FLASH0EN_DIS = 0, /*!< DIS : Disables FLASH status event */ -} PWRCTRL_MEMPWREVENTEN_FLASH0EN_Enum; - -/* ========================================= PWRCTRL MEMPWREVENTEN SRAMEN [3..12] ========================================== */ -typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_SRAMEN */ - PWRCTRL_MEMPWREVENTEN_SRAMEN_NONE = 0, /*!< NONE : Disable SRAM power-on status event */ - PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP0EN = 1, /*!< GROUP0EN : Enable SRAM group0 (0KB-32KB) power on status event */ - PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP1EN = 2, /*!< GROUP1EN : Enable SRAM group1 (32KB-64KB) power on status event */ - PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP2EN = 4, /*!< GROUP2EN : Enable SRAM group2 (64KB-96KB) power on status event */ - PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP3EN = 8, /*!< GROUP3EN : Enable SRAM group3 (96KB-128KB) power on status event */ - PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP4EN = 16, /*!< GROUP4EN : Enable SRAM group4 (128KB-160KB) power on status - event */ - PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP5EN = 32, /*!< GROUP5EN : Enable SRAM group5 (160KB-192KB) power on status - event */ - PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP6EN = 64, /*!< GROUP6EN : Enable SRAM group6 (192KB-224KB) power on status - event */ - PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP7EN = 128, /*!< GROUP7EN : Enable SRAM group7 (224KB-256KB) power on status - event */ - PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP8EN = 256, /*!< GROUP8EN : Enable SRAM group8 (256KB-288KB) power on status - event */ - PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP9EN = 512, /*!< GROUP9EN : Enable SRAM group9 (288KB-320KB) power on status - event */ -} PWRCTRL_MEMPWREVENTEN_SRAMEN_Enum; - -/* ========================================== PWRCTRL MEMPWREVENTEN DTCMEN [0..2] ========================================== */ -typedef enum { /*!< PWRCTRL_MEMPWREVENTEN_DTCMEN */ - PWRCTRL_MEMPWREVENTEN_DTCMEN_NONE = 0, /*!< NONE : Do not enable DTCM power-on status event */ - PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM0EN = 1,/*!< GROUP0DTCM0EN : Enable GROUP0_DTCM0 power on status event */ - PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM1EN = 2,/*!< GROUP0DTCM1EN : Enable GROUP0_DTCM1 power on status event */ - PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0EN = 3, /*!< GROUP0EN : Enable DTCMs in group0 power on status event */ - PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP1EN = 4, /*!< GROUP1EN : Enable DTCMs in group1 power on status event */ - PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL = 7, /*!< ALL : Enable all DTCM power on status event */ -} PWRCTRL_MEMPWREVENTEN_DTCMEN_Enum; - - - -/* =========================================================================================================================== */ -/* ================ RSTGEN ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CFG ========================================================== */ -/* ========================================================= SWPOI ========================================================= */ -/* ============================================= RSTGEN SWPOI SWPOIKEY [0..7] ============================================== */ -typedef enum { /*!< RSTGEN_SWPOI_SWPOIKEY */ - RSTGEN_SWPOI_SWPOIKEY_KEYVALUE = 27, /*!< KEYVALUE : Writing 0x1B key value generates a software POI reset. */ -} RSTGEN_SWPOI_SWPOIKEY_Enum; - -/* ========================================================= SWPOR ========================================================= */ -/* ============================================= RSTGEN SWPOR SWPORKEY [0..7] ============================================== */ -typedef enum { /*!< RSTGEN_SWPOR_SWPORKEY */ - RSTGEN_SWPOR_SWPORKEY_KEYVALUE = 212, /*!< KEYVALUE : Writing 0xD4 key value generates a software POR reset. */ -} RSTGEN_SWPOR_SWPORKEY_Enum; - -/* ======================================================== TPIURST ======================================================== */ -/* ========================================================= INTEN ========================================================= */ -/* ======================================================== INTSTAT ======================================================== */ -/* ======================================================== INTCLR ========================================================= */ -/* ======================================================== INTSET ========================================================= */ -/* ========================================================= STAT ========================================================== */ - - -/* =========================================================================================================================== */ -/* ================ RTC ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CTRLOW ========================================================= */ -/* ========================================================= CTRUP ========================================================= */ -/* =============================================== RTC CTRUP CTERR [31..31] ================================================ */ -typedef enum { /*!< RTC_CTRUP_CTERR */ - RTC_CTRUP_CTERR_NOERR = 0, /*!< NOERR : No read error occurred */ - RTC_CTRUP_CTERR_RDERR = 1, /*!< RDERR : Read error occurred */ -} RTC_CTRUP_CTERR_Enum; - -/* ================================================ RTC CTRUP CEB [28..28] ================================================= */ -typedef enum { /*!< RTC_CTRUP_CEB */ - RTC_CTRUP_CEB_DIS = 0, /*!< DIS : Disable the Century bit from changing */ - RTC_CTRUP_CEB_EN = 1, /*!< EN : Enable the Century bit to change */ -} RTC_CTRUP_CEB_Enum; - -/* ================================================= RTC CTRUP CB [27..27] ================================================= */ -typedef enum { /*!< RTC_CTRUP_CB */ - RTC_CTRUP_CB_2000 = 0, /*!< 2000 : Century is 2000s */ - RTC_CTRUP_CB_1900_2100 = 1, /*!< 1900_2100 : Century is 1900s/2100s */ -} RTC_CTRUP_CB_Enum; - -/* ======================================================== ALMLOW ========================================================= */ -/* ========================================================= ALMUP ========================================================= */ -/* ======================================================== RTCCTL ========================================================= */ -/* =============================================== RTC RTCCTL HR1224 [5..5] ================================================ */ -typedef enum { /*!< RTC_RTCCTL_HR1224 */ - RTC_RTCCTL_HR1224_24HR = 0, /*!< 24HR : Hours in 24 hour mode */ - RTC_RTCCTL_HR1224_12HR = 1, /*!< 12HR : Hours in 12 hour mode */ -} RTC_RTCCTL_HR1224_Enum; - -/* ================================================ RTC RTCCTL RSTOP [4..4] ================================================ */ -typedef enum { /*!< RTC_RTCCTL_RSTOP */ - RTC_RTCCTL_RSTOP_RUN = 0, /*!< RUN : Allow the RTC input clock to run */ - RTC_RTCCTL_RSTOP_STOP = 1, /*!< STOP : Stop the RTC input clock */ -} RTC_RTCCTL_RSTOP_Enum; - -/* ================================================= RTC RTCCTL RPT [1..3] ================================================= */ -typedef enum { /*!< RTC_RTCCTL_RPT */ - RTC_RTCCTL_RPT_DIS = 0, /*!< DIS : Alarm interrupt disabled */ - RTC_RTCCTL_RPT_YEAR = 1, /*!< YEAR : Interrupt every year */ - RTC_RTCCTL_RPT_MONTH = 2, /*!< MONTH : Interrupt every month */ - RTC_RTCCTL_RPT_WEEK = 3, /*!< WEEK : Interrupt every week */ - RTC_RTCCTL_RPT_DAY = 4, /*!< DAY : Interrupt every day */ - RTC_RTCCTL_RPT_HR = 5, /*!< HR : Interrupt every hour */ - RTC_RTCCTL_RPT_MIN = 6, /*!< MIN : Interrupt every minute */ - RTC_RTCCTL_RPT_SEC = 7, /*!< SEC : Interrupt every second/10th/100th */ -} RTC_RTCCTL_RPT_Enum; - -/* ================================================ RTC RTCCTL WRTC [0..0] ================================================= */ -typedef enum { /*!< RTC_RTCCTL_WRTC */ - RTC_RTCCTL_WRTC_DIS = 0, /*!< DIS : Counter writes are disabled */ - RTC_RTCCTL_WRTC_EN = 1, /*!< EN : Counter writes are enabled */ -} RTC_RTCCTL_WRTC_Enum; - -/* ========================================================= INTEN ========================================================= */ -/* ======================================================== INTSTAT ======================================================== */ -/* ======================================================== INTCLR ========================================================= */ -/* ======================================================== INTSET ========================================================= */ - - -/* =========================================================================================================================== */ -/* ================ SCARD ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== SR =========================================================== */ -/* ================================================== SCARD SR FHF [6..6] ================================================== */ -typedef enum { /*!< SCARD_SR_FHF */ - SCARD_SR_FHF_HALFFULL = 1, /*!< HALFFULL : FIFO is half full. */ -} SCARD_SR_FHF_Enum; - -/* ================================================ SCARD SR FT2REND [5..5] ================================================ */ -typedef enum { /*!< SCARD_SR_FT2REND */ - SCARD_SR_FT2REND_CMPL = 1, /*!< CMPL : TX to RX completed. */ - SCARD_SR_FT2REND_NOTCMPL = 0, /*!< NOTCMPL : TX to RX not completed. */ -} SCARD_SR_FT2REND_Enum; - -/* ================================================== SCARD SR PE [4..4] =================================================== */ -typedef enum { /*!< SCARD_SR_PE */ - SCARD_SR_PE_PEERR = 1, /*!< PEERR : Parity error. */ - SCARD_SR_PE_PENONE = 0, /*!< PENONE : No parity error. */ -} SCARD_SR_PE_Enum; - -/* ================================================== SCARD SR OVR [3..3] ================================================== */ -typedef enum { /*!< SCARD_SR_OVR */ - SCARD_SR_OVR_RXOVR = 1, /*!< RXOVR : RX FIFO overflow. */ - SCARD_SR_OVR_RXOVRNONE = 0, /*!< RXOVRNONE : RX FIFO no overflow. */ -} SCARD_SR_OVR_Enum; - -/* ================================================== SCARD SR FER [2..2] ================================================== */ -typedef enum { /*!< SCARD_SR_FER */ - SCARD_SR_FER_FRAMINGERR = 1, /*!< FRAMINGERR : Framing error. */ - SCARD_SR_FER_NOFRAMINGERR = 0, /*!< NOFRAMINGERR : No framing error detected. */ -} SCARD_SR_FER_Enum; - -/* ================================================ SCARD SR TBERBF [1..1] ================================================= */ -typedef enum { /*!< SCARD_SR_TBERBF */ - SCARD_SR_TBERBF_TXFIFOEMPTY = 1, /*!< TXFIFOEMPTY : Transmit: FIFO empty. */ - SCARD_SR_TBERBF_TXFIFONOTEMPTY = 0, /*!< TXFIFONOTEMPTY : Transmit: FIFO not empty. */ -} SCARD_SR_TBERBF_Enum; - -/* ================================================== SCARD SR FNE [0..0] ================================================== */ -typedef enum { /*!< SCARD_SR_FNE */ - SCARD_SR_FNE_NOTEMPTY = 1, /*!< NOTEMPTY : RX FIFO not empty. */ - SCARD_SR_FNE_EMPTY = 0, /*!< EMPTY : RX FIFO empty. */ -} SCARD_SR_FNE_Enum; - -/* ========================================================== IER ========================================================== */ -/* ========================================================== TCR ========================================================== */ -/* ========================================================== UCR ========================================================== */ -/* ========================================================== DR =========================================================== */ -/* ========================================================= BPRL ========================================================== */ -/* ========================================================= BPRH ========================================================== */ -/* ========================================================= UCR1 ========================================================== */ -/* ========================================================== SR1 ========================================================== */ -/* ================================================= SCARD SR1 IDLE [3..3] ================================================= */ -typedef enum { /*!< SCARD_SR1_IDLE */ - SCARD_SR1_IDLE_IDLE = 1, /*!< IDLE : ISO7816 idle. */ - SCARD_SR1_IDLE_ACTIVE = 0, /*!< ACTIVE : ISO7816 active. */ -} SCARD_SR1_IDLE_Enum; - -/* =============================================== SCARD SR1 SYNCEND [2..2] ================================================ */ -typedef enum { /*!< SCARD_SR1_SYNCEND */ - SCARD_SR1_SYNCEND_CMPL = 1, /*!< CMPL : Synchronization complete. */ - SCARD_SR1_SYNCEND_INCMPL = 0, /*!< INCMPL : Incomplete. */ -} SCARD_SR1_SYNCEND_Enum; - -/* ================================================= SCARD SR1 PRL [1..1] ================================================== */ -typedef enum { /*!< SCARD_SR1_PRL */ - SCARD_SR1_PRL_INSREM = 1, /*!< INSREM : Card inserted/removed. */ -} SCARD_SR1_PRL_Enum; - -/* =============================================== SCARD SR1 ECNTOVER [0..0] =============================================== */ -typedef enum { /*!< SCARD_SR1_ECNTOVER */ - SCARD_SR1_ECNTOVER_OVR = 1, /*!< OVR : ETU overflow. */ -} SCARD_SR1_ECNTOVER_Enum; - -/* ========================================================= IER1 ========================================================== */ -/* ========================================================= ECNTL ========================================================= */ -/* ========================================================= ECNTH ========================================================= */ -/* ========================================================== GTR ========================================================== */ -/* ======================================================== RETXCNT ======================================================== */ -/* ====================================================== RETXCNTRMI ======================================================= */ -/* ======================================================== CLKCTRL ======================================================== */ - - -/* =========================================================================================================================== */ -/* ================ SECURITY ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= CTRL ========================================================== */ -/* ============================================= SECURITY CTRL FUNCTION [4..7] ============================================= */ -typedef enum { /*!< SECURITY_CTRL_FUNCTION */ - SECURITY_CTRL_FUNCTION_CRC32 = 0, /*!< CRC32 : Perform CRC32 operation */ - SECURITY_CTRL_FUNCTION_RAND = 1, /*!< RAND : DMA pseudo-random number stream based on CRC value */ - SECURITY_CTRL_FUNCTION_GENADDR = 2, /*!< GENADDR : Generate DMA stream based on address */ -} SECURITY_CTRL_FUNCTION_Enum; - -/* ======================================================== SRCADDR ======================================================== */ -/* ========================================================== LEN ========================================================== */ -/* ======================================================== RESULT ========================================================= */ -/* ======================================================= LOCKCTRL ======================================================== */ -/* ============================================ SECURITY LOCKCTRL SELECT [0..7] ============================================ */ -typedef enum { /*!< SECURITY_LOCKCTRL_SELECT */ - SECURITY_LOCKCTRL_SELECT_CUSTOMER_KEY = 1, /*!< CUSTOMER_KEY : Unlock Customer Key (access to top half of info0) */ - SECURITY_LOCKCTRL_SELECT_NONE = 0, /*!< NONE : Lock Control should be set to NONE when not in use. */ -} SECURITY_LOCKCTRL_SELECT_Enum; - -/* ======================================================= LOCKSTAT ======================================================== */ -/* =========================================== SECURITY LOCKSTAT STATUS [0..31] ============================================ */ -typedef enum { /*!< SECURITY_LOCKSTAT_STATUS */ - SECURITY_LOCKSTAT_STATUS_CUSTOMER_KEY = 1, /*!< CUSTOMER_KEY : Customer Key is unlocked (access is granted to - top half of info0) */ - SECURITY_LOCKSTAT_STATUS_NONE = 0, /*!< NONE : No resources are unlocked */ -} SECURITY_LOCKSTAT_STATUS_Enum; - -/* ========================================================= KEY0 ========================================================== */ -/* ========================================================= KEY1 ========================================================== */ -/* ========================================================= KEY2 ========================================================== */ -/* ========================================================= KEY3 ========================================================== */ - - -/* =========================================================================================================================== */ -/* ================ UART0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== DR =========================================================== */ -/* =============================================== UART0 DR OEDATA [11..11] ================================================ */ -typedef enum { /*!< UART0_DR_OEDATA */ - UART0_DR_OEDATA_NOERR = 0, /*!< NOERR : No error on UART OEDATA, overrun error indicator. */ - UART0_DR_OEDATA_ERR = 1, /*!< ERR : Error on UART OEDATA, overrun error indicator. */ -} UART0_DR_OEDATA_Enum; - -/* =============================================== UART0 DR BEDATA [10..10] ================================================ */ -typedef enum { /*!< UART0_DR_BEDATA */ - UART0_DR_BEDATA_NOERR = 0, /*!< NOERR : No error on UART BEDATA, break error indicator. */ - UART0_DR_BEDATA_ERR = 1, /*!< ERR : Error on UART BEDATA, break error indicator. */ -} UART0_DR_BEDATA_Enum; - -/* ================================================ UART0 DR PEDATA [9..9] ================================================= */ -typedef enum { /*!< UART0_DR_PEDATA */ - UART0_DR_PEDATA_NOERR = 0, /*!< NOERR : No error on UART PEDATA, parity error indicator. */ - UART0_DR_PEDATA_ERR = 1, /*!< ERR : Error on UART PEDATA, parity error indicator. */ -} UART0_DR_PEDATA_Enum; - -/* ================================================ UART0 DR FEDATA [8..8] ================================================= */ -typedef enum { /*!< UART0_DR_FEDATA */ - UART0_DR_FEDATA_NOERR = 0, /*!< NOERR : No error on UART FEDATA, framing error indicator. */ - UART0_DR_FEDATA_ERR = 1, /*!< ERR : Error on UART FEDATA, framing error indicator. */ -} UART0_DR_FEDATA_Enum; - -/* ========================================================== RSR ========================================================== */ -/* ================================================ UART0 RSR OESTAT [3..3] ================================================ */ -typedef enum { /*!< UART0_RSR_OESTAT */ - UART0_RSR_OESTAT_NOERR = 0, /*!< NOERR : No error on UART OESTAT, overrun error indicator. */ - UART0_RSR_OESTAT_ERR = 1, /*!< ERR : Error on UART OESTAT, overrun error indicator. */ -} UART0_RSR_OESTAT_Enum; - -/* ================================================ UART0 RSR BESTAT [2..2] ================================================ */ -typedef enum { /*!< UART0_RSR_BESTAT */ - UART0_RSR_BESTAT_NOERR = 0, /*!< NOERR : No error on UART BESTAT, break error indicator. */ - UART0_RSR_BESTAT_ERR = 1, /*!< ERR : Error on UART BESTAT, break error indicator. */ -} UART0_RSR_BESTAT_Enum; - -/* ================================================ UART0 RSR PESTAT [1..1] ================================================ */ -typedef enum { /*!< UART0_RSR_PESTAT */ - UART0_RSR_PESTAT_NOERR = 0, /*!< NOERR : No error on UART PESTAT, parity error indicator. */ - UART0_RSR_PESTAT_ERR = 1, /*!< ERR : Error on UART PESTAT, parity error indicator. */ -} UART0_RSR_PESTAT_Enum; - -/* ================================================ UART0 RSR FESTAT [0..0] ================================================ */ -typedef enum { /*!< UART0_RSR_FESTAT */ - UART0_RSR_FESTAT_NOERR = 0, /*!< NOERR : No error on UART FESTAT, framing error indicator. */ - UART0_RSR_FESTAT_ERR = 1, /*!< ERR : Error on UART FESTAT, framing error indicator. */ -} UART0_RSR_FESTAT_Enum; - -/* ========================================================== FR =========================================================== */ -/* ================================================= UART0 FR TXFE [7..7] ================================================== */ -typedef enum { /*!< UART0_FR_TXFE */ - UART0_FR_TXFE_XMTFIFO_EMPTY = 1, /*!< XMTFIFO_EMPTY : Transmit fifo is empty. */ -} UART0_FR_TXFE_Enum; - -/* ================================================= UART0 FR RXFF [6..6] ================================================== */ -typedef enum { /*!< UART0_FR_RXFF */ - UART0_FR_RXFF_RCVFIFO_FULL = 1, /*!< RCVFIFO_FULL : Receive fifo is full. */ -} UART0_FR_RXFF_Enum; - -/* ================================================= UART0 FR TXFF [5..5] ================================================== */ -typedef enum { /*!< UART0_FR_TXFF */ - UART0_FR_TXFF_XMTFIFO_FULL = 1, /*!< XMTFIFO_FULL : Transmit fifo is full. */ -} UART0_FR_TXFF_Enum; - -/* ================================================= UART0 FR RXFE [4..4] ================================================== */ -typedef enum { /*!< UART0_FR_RXFE */ - UART0_FR_RXFE_RCVFIFO_EMPTY = 1, /*!< RCVFIFO_EMPTY : Receive fifo is empty. */ -} UART0_FR_RXFE_Enum; - -/* ================================================= UART0 FR BUSY [3..3] ================================================== */ -typedef enum { /*!< UART0_FR_BUSY */ - UART0_FR_BUSY_BUSY = 1, /*!< BUSY : UART busy indicator. */ -} UART0_FR_BUSY_Enum; - -/* ================================================== UART0 FR DCD [2..2] ================================================== */ -typedef enum { /*!< UART0_FR_DCD */ - UART0_FR_DCD_DETECTED = 1, /*!< DETECTED : Data carrier detect detected. */ -} UART0_FR_DCD_Enum; - -/* ================================================== UART0 FR DSR [1..1] ================================================== */ -typedef enum { /*!< UART0_FR_DSR */ - UART0_FR_DSR_READY = 1, /*!< READY : Data set ready. */ -} UART0_FR_DSR_Enum; - -/* ================================================== UART0 FR CTS [0..0] ================================================== */ -typedef enum { /*!< UART0_FR_CTS */ - UART0_FR_CTS_CLEARTOSEND = 1, /*!< CLEARTOSEND : Clear to send is indicated. */ -} UART0_FR_CTS_Enum; - -/* ========================================================= ILPR ========================================================== */ -/* ========================================================= IBRD ========================================================== */ -/* ========================================================= FBRD ========================================================== */ -/* ========================================================= LCRH ========================================================== */ -/* ========================================================== CR =========================================================== */ -/* ================================================ UART0 CR CLKSEL [4..6] ================================================= */ -typedef enum { /*!< UART0_CR_CLKSEL */ - UART0_CR_CLKSEL_NOCLK = 0, /*!< NOCLK : No UART clock. This is the low power default. */ - UART0_CR_CLKSEL_24MHZ = 1, /*!< 24MHZ : 24 MHz clock. */ - UART0_CR_CLKSEL_12MHZ = 2, /*!< 12MHZ : 12 MHz clock. */ - UART0_CR_CLKSEL_6MHZ = 3, /*!< 6MHZ : 6 MHz clock. */ - UART0_CR_CLKSEL_3MHZ = 4, /*!< 3MHZ : 3 MHz clock. */ -} UART0_CR_CLKSEL_Enum; - -/* ========================================================= IFLS ========================================================== */ -/* ========================================================== IER ========================================================== */ -/* ========================================================== IES ========================================================== */ -/* ========================================================== MIS ========================================================== */ -/* ========================================================== IEC ========================================================== */ - - -/* =========================================================================================================================== */ -/* ================ VCOMP ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CFG ========================================================== */ -/* =============================================== VCOMP CFG LVLSEL [16..19] =============================================== */ -typedef enum { /*!< VCOMP_CFG_LVLSEL */ - VCOMP_CFG_LVLSEL_0P58V = 0, /*!< 0P58V : Set Reference input to 0.58 Volts. */ - VCOMP_CFG_LVLSEL_0P77V = 1, /*!< 0P77V : Set Reference input to 0.77 Volts. */ - VCOMP_CFG_LVLSEL_0P97V = 2, /*!< 0P97V : Set Reference input to 0.97 Volts. */ - VCOMP_CFG_LVLSEL_1P16V = 3, /*!< 1P16V : Set Reference input to 1.16 Volts. */ - VCOMP_CFG_LVLSEL_1P35V = 4, /*!< 1P35V : Set Reference input to 1.35 Volts. */ - VCOMP_CFG_LVLSEL_1P55V = 5, /*!< 1P55V : Set Reference input to 1.55 Volts. */ - VCOMP_CFG_LVLSEL_1P74V = 6, /*!< 1P74V : Set Reference input to 1.74 Volts. */ - VCOMP_CFG_LVLSEL_1P93V = 7, /*!< 1P93V : Set Reference input to 1.93 Volts. */ - VCOMP_CFG_LVLSEL_2P13V = 8, /*!< 2P13V : Set Reference input to 2.13 Volts. */ - VCOMP_CFG_LVLSEL_2P32V = 9, /*!< 2P32V : Set Reference input to 2.32 Volts. */ - VCOMP_CFG_LVLSEL_2P51V = 10, /*!< 2P51V : Set Reference input to 2.51 Volts. */ - VCOMP_CFG_LVLSEL_2P71V = 11, /*!< 2P71V : Set Reference input to 2.71 Volts. */ - VCOMP_CFG_LVLSEL_2P90V = 12, /*!< 2P90V : Set Reference input to 2.90 Volts. */ - VCOMP_CFG_LVLSEL_3P09V = 13, /*!< 3P09V : Set Reference input to 3.09 Volts. */ - VCOMP_CFG_LVLSEL_3P29V = 14, /*!< 3P29V : Set Reference input to 3.29 Volts. */ - VCOMP_CFG_LVLSEL_3P48V = 15, /*!< 3P48V : Set Reference input to 3.48 Volts. */ -} VCOMP_CFG_LVLSEL_Enum; - -/* ================================================= VCOMP CFG NSEL [8..9] ================================================= */ -typedef enum { /*!< VCOMP_CFG_NSEL */ - VCOMP_CFG_NSEL_VREFEXT1 = 0, /*!< VREFEXT1 : Use external reference 1 for reference input. */ - VCOMP_CFG_NSEL_VREFEXT2 = 1, /*!< VREFEXT2 : Use external reference 2 for reference input. */ - VCOMP_CFG_NSEL_VREFEXT3 = 2, /*!< VREFEXT3 : Use external reference 3 for reference input. */ - VCOMP_CFG_NSEL_DAC = 3, /*!< DAC : Use DAC output selected by LVLSEL for reference input. */ -} VCOMP_CFG_NSEL_Enum; - -/* ================================================= VCOMP CFG PSEL [0..1] ================================================= */ -typedef enum { /*!< VCOMP_CFG_PSEL */ - VCOMP_CFG_PSEL_VDDADJ = 0, /*!< VDDADJ : Use VDDADJ for the positive input. */ - VCOMP_CFG_PSEL_VTEMP = 1, /*!< VTEMP : Use the temperature sensor output for the positive input. - Note: If this channel is selected for PSEL, the bandap - circuit required for temperature comparisons will automatically - turn on. The bandgap circuit requires 11us to stabalize. */ - VCOMP_CFG_PSEL_VEXT1 = 2, /*!< VEXT1 : Use external voltage 0 for positive input. */ - VCOMP_CFG_PSEL_VEXT2 = 3, /*!< VEXT2 : Use external voltage 1 for positive input. */ -} VCOMP_CFG_PSEL_Enum; - -/* ========================================================= STAT ========================================================== */ -/* =============================================== VCOMP STAT PWDSTAT [1..1] =============================================== */ -typedef enum { /*!< VCOMP_STAT_PWDSTAT */ - VCOMP_STAT_PWDSTAT_POWERED_DOWN = 1, /*!< POWERED_DOWN : The voltage comparator is powered down. */ -} VCOMP_STAT_PWDSTAT_Enum; - -/* =============================================== VCOMP STAT CMPOUT [0..0] ================================================ */ -typedef enum { /*!< VCOMP_STAT_CMPOUT */ - VCOMP_STAT_CMPOUT_VOUT_LOW = 0, /*!< VOUT_LOW : The negative input of the comparator is greater than - the positive input. */ - VCOMP_STAT_CMPOUT_VOUT_HIGH = 1, /*!< VOUT_HIGH : The positive input of the comparator is greater - than the negative input. */ -} VCOMP_STAT_CMPOUT_Enum; - -/* ======================================================== PWDKEY ========================================================= */ -/* ============================================== VCOMP PWDKEY PWDKEY [0..31] ============================================== */ -typedef enum { /*!< VCOMP_PWDKEY_PWDKEY */ - VCOMP_PWDKEY_PWDKEY_Key = 55, /*!< Key : Key */ -} VCOMP_PWDKEY_PWDKEY_Enum; - -/* ========================================================= INTEN ========================================================= */ -/* ======================================================== INTSTAT ======================================================== */ -/* ======================================================== INTCLR ========================================================= */ -/* ======================================================== INTSET ========================================================= */ - - -/* =========================================================================================================================== */ -/* ================ WDT ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== CFG ========================================================== */ -/* ================================================ WDT CFG CLKSEL [24..26] ================================================ */ -typedef enum { /*!< WDT_CFG_CLKSEL */ - WDT_CFG_CLKSEL_OFF = 0, /*!< OFF : Low Power Mode. This setting disables the watch dog timer. */ - WDT_CFG_CLKSEL_128HZ = 1, /*!< 128HZ : 128 Hz LFRC clock. */ - WDT_CFG_CLKSEL_16HZ = 2, /*!< 16HZ : 16 Hz LFRC clock. */ - WDT_CFG_CLKSEL_1HZ = 3, /*!< 1HZ : 1 Hz LFRC clock. */ - WDT_CFG_CLKSEL_1_16HZ = 4, /*!< 1_16HZ : 1/16th Hz LFRC clock. */ -} WDT_CFG_CLKSEL_Enum; - -/* ========================================================= RSTRT ========================================================= */ -/* ================================================ WDT RSTRT RSTRT [0..7] ================================================= */ -typedef enum { /*!< WDT_RSTRT_RSTRT */ - WDT_RSTRT_RSTRT_KEYVALUE = 178, /*!< KEYVALUE : This is the key value to write to WDTRSTRT to restart - the WDT. This is a write only register. */ -} WDT_RSTRT_RSTRT_Enum; - -/* ========================================================= LOCK ========================================================== */ -/* ================================================= WDT LOCK LOCK [0..7] ================================================== */ -typedef enum { /*!< WDT_LOCK_LOCK */ - WDT_LOCK_LOCK_KEYVALUE = 58, /*!< KEYVALUE : This is the key value to write to WDTLOCK to lock - the WDT. */ -} WDT_LOCK_LOCK_Enum; - -/* ========================================================= COUNT ========================================================= */ -/* ========================================================= INTEN ========================================================= */ -/* ======================================================== INTSTAT ======================================================== */ -/* ======================================================== INTCLR ========================================================= */ -/* ======================================================== INTSET ========================================================= */ - -/** @} */ /* End of group EnumValue_peripherals */ - - -#ifdef __cplusplus -} -#endif - -#endif /* APOLLO3C_H */ - - -/** @} */ /* End of group apollo3c */ - -/** @} */ /* End of group Ambiq Micro */ diff --git a/cores/arduino/am_sdk_ap3/CMSIS/AmbiqMicro/Source/startup_apollo3.s b/cores/arduino/am_sdk_ap3/CMSIS/AmbiqMicro/Source/startup_apollo3.s deleted file mode 100644 index 493e711..0000000 --- a/cores/arduino/am_sdk_ap3/CMSIS/AmbiqMicro/Source/startup_apollo3.s +++ /dev/null @@ -1,408 +0,0 @@ -;****************************************************************************** -; -;! @file startup_apollo3.s -;! -;! @brief Definitions for Apollo3 interrupt handlers, the vector table, and the stack. -; -;****************************************************************************** - -;****************************************************************************** -; -; Copyright (c) 2019, Ambiq Micro -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; -; 2. Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; -; 3. Neither the name of the copyright holder nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; Third party software included in this distribution is subject to the -; additional license terms as defined in the /docs/licenses directory. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; -; This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. -; -;****************************************************************************** - -;****************************************************************************** -; -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -;************************************************************************ -Stack EQU 0x00001000 - -;****************************************************************************** -; -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; -;****************************************************************************** -Heap EQU 0x00000000 - -;****************************************************************************** -; -; Allocate space for the stack. -; -;****************************************************************************** - AREA STACK, NOINIT, READWRITE, ALIGN=3 -StackMem - SPACE Stack -__initial_sp - -;****************************************************************************** -; -; Allocate space for the heap. -; -;****************************************************************************** - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -HeapMem - SPACE Heap -__heap_limit - -;****************************************************************************** -; -; Indicate that the code in this file preserves 8-byte alignment of the stack. -; -;****************************************************************************** - PRESERVE8 - -;****************************************************************************** -; -; Place code into the reset code section. -; -;****************************************************************************** - AREA RESET, CODE, READONLY - THUMB - -;****************************************************************************** -; -; The vector table. -; -;****************************************************************************** -; -; Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and -; am_usagefault_isr does not work if am_fault_isr is defined externally. -; Therefore, we'll explicitly use am_fault_isr in the table for those vectors. -; - - EXPORT __Vectors -__Vectors - DCD StackMem + Stack ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; The MPU fault handler - DCD BusFault_Handler ; The bus fault handler - DCD UsageFault_Handler ; The usage fault handler - DCD SecureFault_Handler ; Secure fault handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall handler - DCD DebugMon_Handler ; Debug monitor handler - DCD 0 ; Reserved - DCD PendSV_Handler ; The PendSV handler - DCD SysTick_Handler ; The SysTick handler - - ; - ; Peripheral Interrupts - ; - DCD am_brownout_isr ; 0: Reserved - DCD am_watchdog_isr ; 1: Reserved - DCD am_rtc_isr ; 2: RTC - DCD am_vcomp_isr ; 3: Voltage Comparator - DCD am_ioslave_ios_isr ; 4: I/O Slave general - DCD am_ioslave_acc_isr ; 5: I/O Slave access - DCD am_iomaster0_isr ; 6: I/O Master 0 - DCD am_iomaster1_isr ; 7: I/O Master 1 - DCD am_iomaster2_isr ; 8: I/O Master 2 - DCD am_iomaster3_isr ; 9: I/O Master 3 - DCD am_iomaster4_isr ; 10: I/O Master 4 - DCD am_iomaster5_isr ; 11: I/O Master 5 - DCD am_ble_isr ; 12: BLEIF - DCD am_gpio_isr ; 13: GPIO - DCD am_ctimer_isr ; 14: CTIMER - DCD am_uart_isr ; 15: UART0 - DCD am_uart1_isr ; 16: UART1 - DCD am_scard_isr ; 17: SCARD - DCD am_adc_isr ; 18: ADC - DCD am_pdm0_isr ; 19: PDM - DCD am_mspi0_isr ; 20: MSPI0 - DCD am_software0_isr ; 21: SOFTWARE0 - DCD am_stimer_isr ; 22: SYSTEM TIMER - DCD am_stimer_cmpr0_isr ; 23: SYSTEM TIMER COMPARE0 - DCD am_stimer_cmpr1_isr ; 24: SYSTEM TIMER COMPARE1 - DCD am_stimer_cmpr2_isr ; 25: SYSTEM TIMER COMPARE2 - DCD am_stimer_cmpr3_isr ; 26: SYSTEM TIMER COMPARE3 - DCD am_stimer_cmpr4_isr ; 27: SYSTEM TIMER COMPARE4 - DCD am_stimer_cmpr5_isr ; 28: SYSTEM TIMER COMPARE5 - DCD am_stimer_cmpr6_isr ; 29: SYSTEM TIMER COMPARE6 - DCD am_stimer_cmpr7_isr ; 30: SYSTEM TIMER COMPARE7 - DCD am_clkgen_isr ; 31: CLKGEN - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -;****************************************************************************** -; -; Place code immediately following vector table. -; -;****************************************************************************** -;****************************************************************************** -; -; The Patch table. -; -; The patch table should pad the vector table size to a total of 64 entries -; (16 core + 48 periph) such that code begins at offset 0x100. -; -;****************************************************************************** - EXPORT __Patchable -__Patchable - DCD 0 ; 32 - DCD 0 ; 33 - DCD 0 ; 34 - DCD 0 ; 35 - DCD 0 ; 36 - DCD 0 ; 37 - DCD 0 ; 38 - DCD 0 ; 39 - DCD 0 ; 40 - DCD 0 ; 41 - DCD 0 ; 42 - DCD 0 ; 43 - DCD 0 ; 44 - DCD 0 ; 45 - DCD 0 ; 46 - DCD 0 ; 47 - -;****************************************************************************** -; -; This is the code that gets called when the processor first starts execution -; following a reset event. -; -;****************************************************************************** -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - - ; - ; Enable the FPU. - ; - MOVW R0, #0xED88 - MOVT R0, #0xE000 - LDR R1, [R0] - ORR R1, #0x00F00000 - STR R1, [R0] - DSB - ISB - - ; - ; Branch to main. - ; - LDR R0, =__main - BX R0 - - ENDP - -;****************************************************************************** -; -; Weak Exception Handlers. -; -;****************************************************************************** - -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SecureFault_Handler\ - PROC - EXPORT SecureFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -am_default_isr\ - PROC - EXPORT am_brownout_isr [WEAK] - EXPORT am_watchdog_isr [WEAK] - EXPORT am_rtc_isr [WEAK] - EXPORT am_vcomp_isr [WEAK] - EXPORT am_ioslave_ios_isr [WEAK] - EXPORT am_ioslave_acc_isr [WEAK] - EXPORT am_iomaster0_isr [WEAK] - EXPORT am_iomaster1_isr [WEAK] - EXPORT am_iomaster2_isr [WEAK] - EXPORT am_iomaster3_isr [WEAK] - EXPORT am_iomaster4_isr [WEAK] - EXPORT am_iomaster5_isr [WEAK] - EXPORT am_ble_isr [WEAK] - EXPORT am_gpio_isr [WEAK] - EXPORT am_ctimer_isr [WEAK] - EXPORT am_uart_isr [WEAK] - EXPORT am_uart0_isr [WEAK] - EXPORT am_uart1_isr [WEAK] - EXPORT am_scard_isr [WEAK] - EXPORT am_adc_isr [WEAK] - EXPORT am_pdm0_isr [WEAK] - EXPORT am_mspi0_isr [WEAK] - EXPORT am_software0_isr [WEAK] - EXPORT am_stimer_isr [WEAK] - EXPORT am_stimer_cmpr0_isr [WEAK] - EXPORT am_stimer_cmpr1_isr [WEAK] - EXPORT am_stimer_cmpr2_isr [WEAK] - EXPORT am_stimer_cmpr3_isr [WEAK] - EXPORT am_stimer_cmpr4_isr [WEAK] - EXPORT am_stimer_cmpr5_isr [WEAK] - EXPORT am_stimer_cmpr6_isr [WEAK] - EXPORT am_stimer_cmpr7_isr [WEAK] - EXPORT am_clkgen_isr [WEAK] - -am_brownout_isr -am_watchdog_isr -am_rtc_isr -am_vcomp_isr -am_ioslave_ios_isr -am_ioslave_acc_isr -am_iomaster0_isr -am_iomaster1_isr -am_iomaster2_isr -am_iomaster3_isr -am_iomaster4_isr -am_iomaster5_isr -am_ble_isr -am_gpio_isr -am_ctimer_isr -am_uart_isr -am_uart0_isr -am_uart1_isr -am_scard_isr -am_adc_isr -am_pdm0_isr -am_mspi0_isr -am_software0_isr -am_stimer_isr -am_stimer_cmpr0_isr -am_stimer_cmpr1_isr -am_stimer_cmpr2_isr -am_stimer_cmpr3_isr -am_stimer_cmpr4_isr -am_stimer_cmpr5_isr -am_stimer_cmpr6_isr -am_stimer_cmpr7_isr -am_clkgen_isr - - ; all device interrupts go here unless the weak label is over - ; ridden in the linker hard spin so the debugger will know it - ; was an unhandled interrupt request a come-from-buffer or - ; instruction trace hardware would sure be nice if you get here - B . - - ENDP - -;****************************************************************************** -; -; Align the end of the section. -; -;****************************************************************************** - ALIGN - -;****************************************************************************** -; -; Initialization of the heap and stack. -; -;****************************************************************************** - AREA |.text|, CODE, READONLY - -;****************************************************************************** -; -; User Initial Stack & Heap. -; -;****************************************************************************** - IF :DEF: __MICROLIB - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - ELSE - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap PROC - LDR R0, =HeapMem - LDR R1, =(StackMem + Stack) - LDR R2, =(HeapMem + Heap) - LDR R3, =StackMem - BX LR - - ENDP - - ENDIF - -;****************************************************************************** -; -; Align the end of the section. -; -;****************************************************************************** - ALIGN - -;****************************************************************************** -; -; All Done -; -;****************************************************************************** - END - - diff --git a/cores/arduino/am_sdk_ap3/CMSIS/AmbiqMicro/Source/system_apollo3.c b/cores/arduino/am_sdk_ap3/CMSIS/AmbiqMicro/Source/system_apollo3.c index 70c419b..ab3506d 100644 --- a/cores/arduino/am_sdk_ap3/CMSIS/AmbiqMicro/Source/system_apollo3.c +++ b/cores/arduino/am_sdk_ap3/CMSIS/AmbiqMicro/Source/system_apollo3.c @@ -8,26 +8,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE diff --git a/cores/arduino/am_sdk_ap3/CMSIS/version_cmsis_info.txt b/cores/arduino/am_sdk_ap3/CMSIS/version_cmsis_info.txt new file mode 100644 index 0000000..d78a88c --- /dev/null +++ b/cores/arduino/am_sdk_ap3/CMSIS/version_cmsis_info.txt @@ -0,0 +1,24 @@ + +Last updated: August 15, 2019 + +This file contains origination information about the various +CMSIS header and library files located in this folder. + + +ARM/Include/: +AmbiqSuite SDK file: Pack Origination: +cmsis*.h CMSIS/5.6.0/CMSIS/Core/Include/ +core_cm4.h CMSIS/5.6.0/CMSIS/Core/Include/ +mpu_armv7.h CMSIS/5.6.0/CMSIS/Core/Include/ +arm_math.h CMSIS/5.6.0/CMSIS/Include/ + + +ARM/Lib/ARM/: +AmbiqSuite SDK file: Pack Origination: +arm_cortexM4lf_math.lib CMSIS/5.6.0/CMSIS/DSP/Lib/ARM/ +arm_cortexM4l_math.lib CMSIS/5.6.0/CMSIS/DSP/Lib/ARM/ +libarm_cortexM4lf_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/GCC/ +libarm_cortexM4l_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/GCC/ +iar_cortexM4lf_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/IAR/ +iar_cortexM4l_math.a CMSIS/5.6.0/CMSIS/DSP/Lib/IAR/ + diff --git a/cores/arduino/am_sdk_ap3/devices/am_devices_button.c b/cores/arduino/am_sdk_ap3/devices/am_devices_button.c index b59a324..fdcb22f 100644 --- a/cores/arduino/am_sdk_ap3/devices/am_devices_button.c +++ b/cores/arduino/am_sdk_ap3/devices/am_devices_button.c @@ -8,26 +8,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -40,7 +40,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/devices/am_devices_button.h b/cores/arduino/am_sdk_ap3/devices/am_devices_button.h index 2a152af..8b60282 100644 --- a/cores/arduino/am_sdk_ap3/devices/am_devices_button.h +++ b/cores/arduino/am_sdk_ap3/devices/am_devices_button.h @@ -8,26 +8,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -40,7 +40,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_DEVICES_BUTTON_H diff --git a/cores/arduino/am_sdk_ap3/devices/am_devices_led.c b/cores/arduino/am_sdk_ap3/devices/am_devices_led.c index 0e3b896..2c89e8c 100644 --- a/cores/arduino/am_sdk_ap3/devices/am_devices_led.c +++ b/cores/arduino/am_sdk_ap3/devices/am_devices_led.c @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/devices/am_devices_led.h b/cores/arduino/am_sdk_ap3/devices/am_devices_led.h index f0ced46..79837b9 100644 --- a/cores/arduino/am_sdk_ap3/devices/am_devices_led.h +++ b/cores/arduino/am_sdk_ap3/devices/am_devices_led.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_DEVICES_LED_H diff --git a/cores/arduino/am_sdk_ap3/CMSIS/AmbiqMicro/Include/system_apollo3c.h b/cores/arduino/am_sdk_ap3/mcu/am_sdk_version.h similarity index 80% rename from cores/arduino/am_sdk_ap3/CMSIS/AmbiqMicro/Include/system_apollo3c.h rename to cores/arduino/am_sdk_ap3/mcu/am_sdk_version.h index 321f31d..54a60b6 100644 --- a/cores/arduino/am_sdk_ap3/CMSIS/AmbiqMicro/Include/system_apollo3c.h +++ b/cores/arduino/am_sdk_ap3/mcu/am_sdk_version.h @@ -1,33 +1,35 @@ //***************************************************************************** // -//! @file system_apollo3c.h +// am_sdk_version.h +//! @file +//! +//! @brief Defines SDK version. //! -//! @brief Ambiq Micro Apollo3C MCU specific functions. // //***************************************************************************** //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -40,30 +42,33 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. +// //***************************************************************************** - -#ifndef SYSTEM_APOLLO3C_H -#define SYSTEM_APOLLO3C_H +#ifndef AM_SDK_VERSION_H +#define AM_SDK_VERSION_H #ifdef __cplusplus -extern "C" { +extern "C" +{ #endif -#include - -extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) - //***************************************************************************** // -// External function definitions +// Macros to define HAL SDK version. // //***************************************************************************** -extern void SystemInit (void); -extern void SystemCoreClockUpdate (void); +// +// Define the current HAL version. +// +#ifndef AM_HAL_VERSION_MAJ +#define AM_HAL_VERSION_MAJ 2 +#define AM_HAL_VERSION_MIN 4 +#define AM_HAL_VERSION_REV 2 +#endif // AM_HAL_VERSION_MAJ #ifdef __cplusplus } #endif -#endif // SYSTEM_APOLLO3C_H - +#endif // AM_SDK_VERSION_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/Makefile b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/Makefile index 37a1320..da6d179 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/Makefile +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/Makefile @@ -2,26 +2,26 @@ # # Makefile - Rules for compiling # -# Copyright (c) 2019, Ambiq Micro +# Copyright (c) 2020, Ambiq Micro # All rights reserved. -# +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: -# +# # 1. Redistributions of source code must retain the above copyright notice, # this list of conditions and the following disclaimer. -# +# # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# +# # 3. Neither the name of the copyright holder nor the names of its # contributors may be used to endorse or promote products derived from this # software without specific prior written permission. -# +# # Third party software included in this distribution is subject to the # additional license terms as defined in the /docs/licenses directory. -# +# # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -34,7 +34,7 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # -# This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +# This is part of revision 2.4.2 of the AmbiqSuite Development Package. # #****************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_adc.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_adc.c index 3bd7723..e56c71c 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_adc.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_adc.c @@ -5,34 +5,34 @@ //! //! @brief Functions for interfacing with the Analog to Digital Converter. //! -//! @addtogroup adc2 Analog-to-Digital Converter (ADC) -//! @ingroup apollo2hal +//! @addtogroup adc3 Analog-to-Digital Converter (ADC) +//! @ingroup apollo3hal //! @{ // //***************************************************************************** //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -642,7 +642,7 @@ uint32_t am_hal_adc_control(void *pHandle, // // pArgs must point to an array of 3 floats. To assure that the // array is valid, upon calling the 3rd float (pArgs[2]) must be - // set to the to the value -123.456F. + // set to the value -123.456F. // if ( pArgs != NULL ) { diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_adc.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_adc.h index 8c93517..4b096c7 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_adc.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_adc.h @@ -5,34 +5,34 @@ //! //! @brief Functions for interfacing with the Analog to Digital Converter //! -//! @addtogroup adc2 Analog-to-Digital Converter (ADC) -//! @ingroup apollo2hal +//! @addtogroup adc3 Analog-to-Digital Converter (ADC) +//! @ingroup apollo3hal //! @{ // //***************************************************************************** //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_ADC_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble.c index 5b7b38a..e122b2c 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble.c @@ -12,26 +12,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -44,7 +44,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -138,11 +138,6 @@ am_hal_ble_state_t g_sBLEState[AM_REG_BLEIF_NUM_MODULES]; // Static function prototypes. // //***************************************************************************** -#if 0 -static void am_hal_ble_fifo_write(void *pHandle, uint32_t *pui32Data, uint32_t ui32NumBytes); -static uint32_t am_hal_ble_fifo_fill(void *pHandle); -static bool am_hal_ble_lock_and_check_status(am_hal_ble_state_t *pBle); -#endif static bool am_hal_ble_bus_lock(am_hal_ble_state_t *pBle); static void am_hal_ble_bus_release(am_hal_ble_state_t *pBle); static uint32_t am_hal_ble_fifo_drain(void *pHandle); @@ -219,6 +214,20 @@ static const uint16_t ccitt_table[] = } \ } +#define WHILE_TIMEOUT_MS_BREAK(expr, timeout, error) \ + { \ + uint32_t ui32Timeout = 0; \ + while (expr) \ + { \ + if (ui32Timeout == (timeout * 1000)) \ + { \ + break; \ + } \ + \ + delay_us(1); \ + ui32Timeout++; \ + } \ + } //***************************************************************************** // // Helper function for checking BLE data. @@ -394,7 +403,7 @@ am_hal_ble_initialize(uint32_t ui32Module, void **ppHandle) // Return the status. // return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_initialize() //***************************************************************************** // @@ -436,7 +445,7 @@ am_hal_ble_deinitialize(void *pHandle) // Return the status. // return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_deinitialize() //***************************************************************************** // @@ -543,7 +552,7 @@ am_hal_ble_config(void *pHandle, const am_hal_ble_config_t *psConfig) // Return the status. // return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_config() //***************************************************************************** // @@ -556,18 +565,10 @@ am_hal_ble_power_control(void *pHandle, uint32_t ui32PowerState) uint32_t ui32Module; // - // Enable the BLE buck trim values + // BLE buck is shared by Burst as well + // Enable the BLE buck trim values if in use // - if ( APOLLO3_GE_A1 ) - { - CLKGEN->BLEBUCKTONADJ = - _VAL2FLD(CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN, CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_EN) | - _VAL2FLD(CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM, CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetF) | - _VAL2FLD(CLKGEN_BLEBUCKTONADJ_TONADJUSTEN, CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_EN) | - _VAL2FLD(CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD, CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_94KHz) | - _VAL2FLD(CLKGEN_BLEBUCKTONADJ_TONHIGHTHRESHOLD, 0x10) | - _VAL2FLD(CLKGEN_BLEBUCKTONADJ_TONLOWTHRESHOLD, 0xF); - } + am_hal_pwrctrl_blebuck_trim(); // // Check the handle. @@ -667,7 +668,7 @@ am_hal_ble_power_control(void *pHandle, uint32_t ui32PowerState) // Return the status. // return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_power_control() //***************************************************************************** // @@ -695,8 +696,10 @@ am_hal_ble_boot(void *pHandle) if (pBLE->bUseDefaultPatches) { + // // The B0 silicon patching method is slightly different from A1. B0 silicon // does not require the Copy Patch method introduced for A1 silicon. + // if (APOLLO3_A0 || APOLLO3_A1) { ui32Status = am_hal_ble_default_copy_patch_apply(pHandle); @@ -706,21 +709,27 @@ am_hal_ble_boot(void *pHandle) } } - //apply the BLE trim value + // + // Apply the BLE trim value + // ui32Status = am_hal_ble_default_trim_set_ramcode(pHandle); if (ui32Status != AM_HAL_STATUS_SUCCESS) { return ui32Status; } + // // Apply the NVDS patch. + // ui32Status = am_hal_ble_default_patch_apply(pHandle); if (ui32Status != AM_HAL_STATUS_SUCCESS) { return ui32Status; } + // // Complete the patching step + // ui32Status = am_hal_ble_patch_complete(pHandle); if (ui32Status != AM_HAL_STATUS_SUCCESS) { @@ -736,7 +745,7 @@ am_hal_ble_boot(void *pHandle) { return AM_HAL_STATUS_SUCCESS; } -} +} // am_hal_ble_boot() //***************************************************************************** // @@ -942,7 +951,7 @@ am_hal_ble_patch_apply(void *pHandle, am_hal_ble_patch_t *psPatch) { return AM_HAL_STATUS_SUCCESS; } -} +} // am_hal_ble_patch_apply() uint32_t am_hal_ble_patch_copy_end_apply(void *pHandle) @@ -1025,7 +1034,7 @@ am_hal_ble_patch_copy_end_apply(void *pHandle) return AM_HAL_STATUS_FAIL; } return 0; -} +} // am_hal_ble_patch_copy_end_apply() //***************************************************************************** // @@ -1099,7 +1108,7 @@ am_hal_ble_default_patch_apply(void *pHandle) } return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_default_patch_apply() //***************************************************************************** // @@ -1263,7 +1272,7 @@ am_hal_ble_patch_complete(void *pHandle) // Return the status. // return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_patch_complete() //***************************************************************************** // @@ -1316,7 +1325,7 @@ am_hal_ble_trim_set(void *pHandle, uint32_t ui32BleCoreAddress, uint32_t ui32Tri } return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_trim_set() //***************************************************************************** // @@ -1375,7 +1384,7 @@ am_hal_ble_default_trim_set_ramcode(void *pHandle) } return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_default_trim_set_ramcode() //***************************************************************************** // @@ -1408,7 +1417,7 @@ am_hal_ble_vs_command_build(uint32_t *pui32Command, uint32_t ui32OpCode, // Return the status. // return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_vs_command_build() //***************************************************************************** // @@ -1457,7 +1466,7 @@ am_hal_ble_blocking_hci_write(void *pHandle, uint8_t ui8Type, } return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_blocking_hci_write() //***************************************************************************** // @@ -1546,7 +1555,7 @@ am_hal_ble_blocking_hci_read(void *pHandle, uint32_t *pui32Data, uint32_t *pui32 } return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_blocking_hci_read() //***************************************************************************** // @@ -1591,7 +1600,7 @@ am_hal_ble_nonblocking_hci_write(void *pHandle, uint8_t ui8Type, uint32_t ui32Status = am_hal_ble_nonblocking_transfer(pHandle, &HciWrite); return ui32Status; -} +} // am_hal_ble_nonblocking_hci_write() //***************************************************************************** // @@ -1659,7 +1668,7 @@ am_hal_ble_nonblocking_hci_read(void *pHandle, uint32_t *pui32Data, // If we get here, return fail. // return AM_HAL_STATUS_FAIL; -} +} // am_hal_ble_nonblocking_hci_read() //***************************************************************************** // @@ -1685,7 +1694,7 @@ am_hal_ble_check_status(am_hal_ble_state_t *pBle) } return true; -} +} // am_hal_ble_check_status() //***************************************************************************** // @@ -1701,7 +1710,7 @@ am_hal_ble_check_irq(am_hal_ble_state_t *pBle) } return false; -} +} // am_hal_ble_check_irq() //***************************************************************************** // @@ -1732,7 +1741,7 @@ am_hal_ble_check_status_edge(am_hal_ble_state_t *pBle) } return true; -} +} // am_hal_ble_check_status_edge() //***************************************************************************** // @@ -1858,6 +1867,9 @@ am_hal_ble_blocking_transfer(void *pHandle, am_hal_ble_transfer_t *psTransfer) delay_us(10); } + // + // Disable IOCLK + // BLEIFn(0)->BLEDBG_b.IOCLKON = 0; if (ui32SpiStatus != AM_HAL_STATUS_SUCCESS) @@ -1866,6 +1878,7 @@ am_hal_ble_blocking_transfer(void *pHandle, am_hal_ble_transfer_t *psTransfer) // Restore the interrupt state. // BLEIFn(ui32Module)->INTEN = ui32IntEnable; + am_hal_ble_wakeup_set(pBle, 0); return ui32SpiStatus; } } @@ -1918,12 +1931,6 @@ am_hal_ble_blocking_transfer(void *pHandle, am_hal_ble_transfer_t *psTransfer) // if (psTransfer->ui8Command == AM_HAL_BLE_WRITE) { -#if 0 // 0 for FIFO handling with IOM hal style - while (pBle->ui32TransferIndex < pBle->sCurrentTransfer.ui16Length) - { - am_hal_ble_fifo_fill(pHandle); - } -#else // 0 for FIFO handling with IOM hal style bool bCmdCmp = false; uint32_t numWait = 0; // Adjust the byte count to be sent/received for repeat count @@ -1983,7 +1990,9 @@ am_hal_ble_blocking_transfer(void *pHandle, am_hal_ble_transfer_t *psTransfer) } } } -#endif //0 for FIFO handling with IOM hal style + WHILE_TIMEOUT_MS_BREAK ( BLEIFn(ui32Module)->INTSTAT_b.CMDCMP == 0, 2, + AM_HAL_BLE_HCI_PACKET_INCOMPLETE ); + am_hal_ble_wakeup_set(pBle, 0); } else { @@ -2047,7 +2056,7 @@ am_hal_ble_blocking_transfer(void *pHandle, am_hal_ble_transfer_t *psTransfer) // Return the status. // return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_blocking_transfer() //***************************************************************************** // @@ -2081,7 +2090,7 @@ am_hal_ble_nonblocking_transfer(void *pHandle, am_hal_ble_transfer_t *psTransfer } return ui32Status; -} +} // am_hal_ble_nonblocking_transfer() //***************************************************************************** // @@ -2192,7 +2201,7 @@ nonblocking_write(am_hal_ble_state_t *pBle, am_hal_ble_transfer_t *psTransfer) // AM_CRITICAL_END; return ui32Status; -} +} // nonblocking_write() //***************************************************************************** // @@ -2269,136 +2278,7 @@ nonblocking_read(am_hal_ble_state_t *pBle, am_hal_ble_transfer_t *psTransfer) // AM_CRITICAL_END; return ui32Status; -} - -#if 0 -//***************************************************************************** -// -// Write ui32NumBytes to the TX FIFO. -// -//***************************************************************************** -static void -am_hal_ble_fifo_write(void *pHandle, uint32_t *pui32Data, uint32_t ui32NumBytes) -{ - uint32_t ui32Index; - uint32_t ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; - - for (ui32Index = 0; (ui32Index * 4) < ui32NumBytes; ui32Index++) - { - BLEIFn(ui32Module)->FIFOPUSH = pui32Data[ui32Index]; - } - - // we need to have 10us delay to not overwrite FIFO. - delay_us(10); -} - -//***************************************************************************** -// -// Refill the fifo for transmit. -// -//***************************************************************************** -static uint32_t -am_hal_ble_fifo_fill(void *pHandle) -{ - uint32_t ui32Module; - uint32_t ui32FifoFillSize, ui32Space, ui32BytesLeft; - uint32_t *pSrc; - - // - // Check the handle. - // - if (!AM_HAL_BLE_CHK_HANDLE(pHandle)) - { - return 0; - } - - // - // Handle is good, so get the module number. - // - ui32Module = ((am_hal_ble_state_t *) pHandle)->ui32Module; - - // - // Rename some pointers for convenience. - // - am_hal_ble_state_t *pBle = pHandle; - am_hal_ble_transfer_t *pTransfer = &pBle->sCurrentTransfer; - - // - // Check to see how much space there is in the FIFO, and also how many - // bytes are remaining in the transfer. - // - ui32Space = BLEIFn(ui32Module)->FIFOPTR_b.FIFO0REM; - ui32BytesLeft = (pTransfer->ui16Length - pBle->ui32TransferIndex); - - // - // Calculate how much we can fill the fifo. If our data doesn't all fit - // right now, fill up the fifo as much as we can, up to the closest - // multiple of 4. - // - if (ui32Space == 0) - { - return 0; - } - else if (ui32Space >= ui32BytesLeft) - { - ui32FifoFillSize = ui32BytesLeft; - } - else - { - ui32FifoFillSize = ui32Space & (~0x3); - } - - // - // Calculate the place where we last left off, feed the FIFO starting from - // that location, and update the index to match. - // - pSrc = &pTransfer->pui32Data[pBle->ui32TransferIndex / 4]; - - am_hal_ble_fifo_write(pHandle, pSrc, ui32FifoFillSize); - - pBle->ui32TransferIndex += ui32FifoFillSize; - - // - // Return the number of bytes we wrote. - // - return ui32FifoFillSize; -} - -//***************************************************************************** -// -// Mark the BLE interface busy so it doesn't get used by more than one -// interface. -// -//***************************************************************************** -static bool -am_hal_ble_lock_and_check_status(am_hal_ble_state_t *pBle) -{ - bool bLockObtained = false; - - // - // In one atomic sweep, check to see if the bus is busy, and reserve it if - // it isn't. - // - AM_CRITICAL_BEGIN; - - BLEIFn(0)->BLEDBG_b.IOCLKON = 1; - delay_us(5); - - if ( am_hal_ble_check_status(pBle) && am_hal_ble_bus_lock(pBle) ) - { - bLockObtained = true; - } - - BLEIFn(0)->BLEDBG_b.IOCLKON = 0; - - AM_CRITICAL_END; - - // - // Tell the caller if we successfully locked the bus. - // - return bLockObtained; -} -#endif +} // nonblocking_read() //***************************************************************************** // @@ -2437,7 +2317,7 @@ am_hal_ble_bus_lock(am_hal_ble_state_t *pBle) // Tell the caller if we successfully locked the bus. // return bLockObtained; -} +} // am_hal_ble_bus_lock() //***************************************************************************** // @@ -2519,7 +2399,7 @@ am_hal_ble_fifo_drain(void *pHandle) // Return the number of bytes we wrote. // return ui32ReadSize; -} +} // am_hal_ble_fifo_drain() //***************************************************************************** // @@ -2588,7 +2468,7 @@ am_hal_ble_cmd_write(void *pHandle, am_hal_ble_transfer_t *psTransfer) // Return the status. // return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_cmd_write() //***************************************************************************** // @@ -2610,7 +2490,7 @@ am_hal_ble_fifo_read(void *pHandle, uint32_t *pui32Data, uint32_t ui32NumBytes) #endif } -} +} // am_hal_ble_fifo_read() //***************************************************************************** // @@ -2749,7 +2629,7 @@ am_hal_ble_int_service(void *pHandle, uint32_t ui32Status) // Return the status. // return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_int_service() //***************************************************************************** // @@ -2782,7 +2662,7 @@ am_hal_ble_int_enable(void *pHandle, uint32_t ui32InterruptMask) // Return the status. // return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_int_enable() //***************************************************************************** // @@ -2815,7 +2695,7 @@ am_hal_ble_int_disable(void *pHandle, uint32_t ui32InterruptMask) // Return the status. // return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_int_disable() //***************************************************************************** // @@ -2836,7 +2716,7 @@ am_hal_ble_int_status(void *pHandle, bool bEnabledOnly) { return BLEIFn(ui32Module)->INTSTAT; } -} +} // am_hal_ble_int_status() //***************************************************************************** // @@ -2867,7 +2747,7 @@ am_hal_ble_int_clear(void *pHandle, uint32_t ui32InterruptMask) // Return the status. // return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_int_clear() //***************************************************************************** // @@ -2898,7 +2778,7 @@ am_hal_ble_check_32k_clock(void *pHandle) { return AM_HAL_STATUS_SUCCESS; } -} +} // am_hal_ble_check_32k_clock() //***************************************************************************** // @@ -2952,6 +2832,9 @@ am_hal_ble_plf_reg_read(void *pHandle, uint32_t ui32Address, uint32_t *pui32Valu sWriteCommand.words, AM_HAL_BLE_PLF_REGISTER_READ_LENGTH); + // + // Make sure the IO clock for the STATUS signal is on. + // BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; // @@ -2964,6 +2847,7 @@ am_hal_ble_plf_reg_read(void *pHandle, uint32_t ui32Address, uint32_t *pui32Valu *pui32Value = (((sResponse.words[1] & 0xFF000000) >> 24) | ((sResponse.words[2] & 0x00FFFFFF) << 8)); + // // Re-enable BLE interrupts. // @@ -2971,7 +2855,8 @@ am_hal_ble_plf_reg_read(void *pHandle, uint32_t ui32Address, uint32_t *pui32Valu BLEIFn(ui32Module)->INTEN = ui32IntEnable; return AM_HAL_STATUS_SUCCESS; -} + +} // am_hal_ble_plf_reg_read() //***************************************************************************** // @@ -3025,6 +2910,9 @@ am_hal_ble_plf_reg_write(void *pHandle, uint32_t ui32Address, uint32_t ui32Value sWriteCommand.words, AM_HAL_BLE_PLF_REGISTER_WRITE_LENGTH); + // + // Make sure the IO clock for the STATUS signal is on. + // BLEIFn(ui32Module)->BLEDBG_b.IOCLKON = 1; // @@ -3042,7 +2930,8 @@ am_hal_ble_plf_reg_write(void *pHandle, uint32_t ui32Address, uint32_t ui32Value BLEIFn(ui32Module)->INTEN = ui32IntEnable; return AM_HAL_STATUS_SUCCESS; -} + +} // am_hal_ble_plf_reg_write() //***************************************************************************** // @@ -3067,7 +2956,7 @@ am_hal_ble_load_modex_trim_set(void *pHandle) { return AM_HAL_STATUS_FAIL; } -} +} // am_hal_ble_load_modex_trim_set() //***************************************************************************** // @@ -3099,7 +2988,7 @@ am_hal_ble_read_trimdata_from_info1(void) } return TrimData; -} +} // am_hal_ble_read_trimdata_from_info1() //***************************************************************************** // @@ -3147,7 +3036,7 @@ am_hal_ble_transmitter_modex_set(void *pHandle, uint8_t ui8ModFrqOffset) am_hal_ble_plf_reg_write(pBLE, 0x43000004, RegValueMCGR); return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_transmitter_modex_set() //***************************************************************************** // @@ -3187,7 +3076,7 @@ am_hal_ble_sleep_set(void *pHandle, bool enable) } return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_sleep_set() //***************************************************************************** // @@ -3216,13 +3105,13 @@ am_hal_ble_sleep_get(void *pHandle) } return false; -} +} // am_hal_ble_sleep_get() //***************************************************************************** // // set the tx power of BLE // values. -// ui32TxPower: 0x03->-20dBm 0x04->-10dBm 0x05->-5dBm 0x08->0dBm 0x0F->4dBm +// ui32TxPower: 0x03->-20dBm 0x04->-10dBm 0x05->-5dBm 0x08->0dBm 0x0F->3dBm // //***************************************************************************** uint32_t @@ -3265,7 +3154,7 @@ am_hal_ble_tx_power_set(void *pHandle, uint8_t ui32TxPower) am_hal_ble_plf_reg_write(pBLE, 0x43000004, RegValueMCGR); return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_ble_tx_power_set() //***************************************************************************** // diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble.h index 8f57213..0814402 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble.h @@ -12,26 +12,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -44,7 +44,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch.c index 9520001..e379654 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch.c @@ -12,26 +12,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -44,7 +44,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch.h index eb800f7..89e688b 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch.h @@ -12,26 +12,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -44,7 +44,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch_b0.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch_b0.c index 997049e..69d0ec4 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch_b0.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch_b0.c @@ -12,26 +12,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -44,7 +44,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -119,111 +119,128 @@ const uint32_t am_hal_ble_num_default_patches_b0 = AM_HAL_BLE_NUM_DEFAULT_PATCHE // Fixed Channelmap indication rejected issue // Fixed 800M Spur // Fixed feature issue -// Date: 2019-05-15 +// Fixed disconnect issue //long time large data transfer +// Date: 2019-10-25 //***************************************************************************** - -am_hal_ble_buffer(0x0568) am_ble_performance_patch_data_b0 = + am_hal_ble_buffer(0x0654)am_ble_performance_patch_data_b0 = { .bytes = { - 0x00,0x11,0x64,0x05,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x01,0xc5,0x01, + 0x00,0x11,0x50,0x06,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x01,0xc5,0x01, 0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x01,0x00,0x01,0x06,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x1f,0xb5,0x00,0x24,0x00,0x98,0x22,0x28,0x2a,0xd2,0x01,0x00, - 0x79,0x44,0x09,0x79,0x49,0x18,0x8f,0x44,0x10,0x27,0x27,0x27,0x27,0x27,0x27,0x27, - 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am_ble_performance_patch_b0 = { .ui32Type = 0xBB, - .ui32Length = 0x0568, - .ui32CRC = 0x03da, + .ui32Length = 0x0654, + .ui32CRC = 0x4c38, .pui32Data = am_ble_performance_patch_data_b0.words, }; + + //***************************************************************************** @@ -238,65 +255,63 @@ am_hal_ble_patch_t am_ble_performance_patch_b0 = // Fixed Channelmap indication rejected issue // Fixed 800M Spur // Fixed feature issue -// Date: 2019-05-15 +// Fixed disconnect issue //long time large data transfer +// Date: 2019-10-25 //***************************************************************************** -am_hal_ble_buffer(0x025c) am_ble_buffer_patch_data_b0 = +const am_hal_ble_buffer(0x0230)am_ble_buffer_patch_data_b0 = { - .bytes = + .bytes = { - 0x00,0x22,0x5c,0x02,0x1f,0x00,0x00,0x00,0x84,0x4d,0x06,0x00,0x73,0x55,0x06,0x00, - 0x75,0x5d,0x06,0x00,0x17,0x63,0x06,0x00,0xa9,0x6d,0x06,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x20,0xec,0xf7,0xf9,0xfc,0x00,0x28, - 0x0a,0xd0,0x00,0x20,0x00,0x90,0x03,0x46,0x02,0x46,0x01,0x46,0x24,0x68,0x21,0x20, - 0x35,0x34,0xa0,0x47,0x00,0xbf,0x38,0xbd,0xef,0xf7,0xfb,0xfe,0x0f,0x49,0x00,0x28, - 0x02,0xd0,0x08,0x78,0x01,0x28,0x12,0xd0,0x08,0x78,0x02,0x28,0x0f,0xd0,0x00,0x28, - 0x06,0xd0,0x01,0x28,0x04,0xd0,0x00,0xf0,0x0c,0x6e,0x00,0x20,0x00,0x00,0x00,0x04, - 0x1c,0x6e,0x00,0x20,0x00,0x49,0x08,0x47,0x81,0x33,0x00,0x20,0x23,0x4e,0xca,0x7c, - 0x75,0x68,0xc9,0x6a,0x00,0x2a,0x1d,0xd0,0x7d,0x22,0x12,0x02,0x91,0x42,0x02,0xd3, - 0x8a,0x1a,0x01,0x20,0x00,0xe0,0x52,0x1a,0x00,0x28,0x05,0xd0,0x20,0x46,0x50,0x43, - 0xea,0xf7,0x02,0xfa,0x20,0x1a,0x04,0xe0,0xea,0xf7,0xde,0xf9,0x00,0x19,0x01,0x02, - 0xc2,0x00,0x69,0x18,0x12,0x18,0x89,0x18,0x4a,0x0a,0x53,0x02,0xc9,0x1a,0x71,0x60, - 0x1e,0x21,0x48,0x43,0x80,0x18,0x70,0xbd,0x2c,0x68,0x00,0x20,0x0c,0x6e,0x00,0x20, - 0x00,0x49,0x08,0x47,0xf1,0x33,0x00,0x20,0xc1,0x7c,0xc0,0x6a,0x00,0x29,0x15,0xd0, - 0x7d,0x21,0x09,0x02,0x88,0x42,0x02,0xd3,0x02,0xd5,0x04,0x20,0x60,0x70,0x34,0xe0, - 0x28,0x69,0x06,0xf0,0xb5,0xf8,0x00,0x28,0x02,0xd0,0x02,0x20,0x60,0x70,0x2c,0xe0, - 0x03,0x98,0x04,0xf0,0x1f,0xfa,0x04,0x28,0x07,0xd1,0x68,0x46,0x01,0x79,0x02,0x20, - 0x88,0x43,0x05,0xd0,0x00,0x20,0x00,0x28,0x04,0xd0,0x00,0xbf,0x00,0x20,0x1c,0xe0, - 0x01,0x20,0xf8,0xe7,0xf0,0x88,0x00,0x90, - + 0x00,0x22,0x30,0x02,0x1f,0x00,0x00,0x00,0x84,0x65,0x06,0x00,0x73,0x6d,0x06,0x00, + 0x75,0x75,0x06,0x00,0x17,0x7b,0x06,0x00,0xa9,0x85,0x06,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x20,0xec,0xf7, + 0xf9,0xfc,0x00,0x28,0x0a,0xd0,0x00,0x20,0x00,0x90,0x03,0x46,0x02,0x46,0x01,0x46, + 0x24,0x68,0x21,0x20,0x35,0x34,0xa0,0x47,0x00,0xbf,0x38,0xbd,0xef,0xf7,0xfb,0xfe, + 0x0f,0x49,0x00,0x28,0x02,0xd0,0x08,0x78,0x01,0x28,0x12,0xd0,0x08,0x78,0x02,0x28, + 0x0f,0xd0,0x00,0x28,0x06,0xd0,0x01,0x28,0x04,0xd0,0x00,0xf0,0x0c,0x6e,0x00,0x20, + 0x00,0x00,0x00,0x04,0x1c,0x6e,0x00,0x20,0x00,0x49,0x08,0x47,0x41,0x34,0x00,0x20, + 0x23,0x4e,0xca,0x7c,0x75,0x68,0xc9,0x6a,0x00,0x2a,0x1d,0xd0,0x7d,0x22,0x12,0x02, + 0x91,0x42,0x02,0xd3,0x8a,0x1a,0x01,0x20,0x00,0xe0,0x52,0x1a,0x00,0x28,0x05,0xd0, + 0x20,0x46,0x50,0x43,0xea,0xf7,0x02,0xfa,0x20,0x1a,0x04,0xe0,0xea,0xf7,0xde,0xf9, + 0x00,0x19,0x01,0x02,0xc2,0x00,0x69,0x18,0x12,0x18,0x89,0x18,0x4a,0x0a,0x53,0x02, + 0xc9,0x1a,0x71,0x60,0x1e,0x21,0x48,0x43,0x80,0x18,0x70,0xbd,0x2c,0x68,0x00,0x20, + 0x0c,0x6e,0x00,0x20,0x00,0x49,0x08,0x47,0xb1,0x34,0x00,0x20,0xc1,0x7c,0xc0,0x6a, + 0x00,0x29,0x15,0xd0,0x7d,0x21,0x09,0x02,0x88,0x42,0x02,0xd3,0x02,0xd5,0x04,0x20, + 0x60,0x70,0x34,0xe0,0x28,0x69,0x06,0xf0,0xb5,0xf8,0x00,0x28,0x02,0xd0,0x02,0x20, + 0x60,0x70,0x2c,0xe0,0x03,0x98,0x04,0xf0,0x1f,0xfa,0x04,0x28,0x07,0xd1,0x68,0x46, + 0x01,0x79,0x02,0x20,0x88,0x43,0x05,0xd0,0x00,0x20,0x00,0x28,0x04,0xd0,0x00,0xbf, + 0x00,0x20,0x1c,0xe0,0x01,0x20,0xf8,0xe7,0xf0,0x88,0x00,0x90, + //0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00, AM_HAL_BLE_LOCAL_FEATURE,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - - 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0xff,0xff,0xff,0xff,0x03,0x00,0x00, - 0xff,0x00,0x3c,0x1f,0x00,0x00,0x00,0x00,0x01,0x20,0x00,0x00,0x8d,0x84,0x00,0x00, - 0x02,0x20,0x00,0x00,0xcd,0x7d,0x00,0x00,0x03,0x20,0x00,0x00,0xd1,0x7e,0x00,0x00, - 0x05,0x20,0x00,0x00,0xfd,0x84,0x00,0x00,0xf0,0xb4,0x00,0x23,0x18,0x4c,0x25,0x69, - 0x18,0x49,0x7d,0x22,0x09,0x68,0x12,0x02,0x91,0x42,0x02,0xd3,0x8a,0x1a,0x01,0x23, - 0x00,0xe0,0x52,0x1a,0x06,0x46,0x56,0x43,0xf2,0x13,0x51,0x43,0x71,0x1a,0x1e,0x26, - 0x4e,0x43,0x4f,0x10,0xf6,0x19,0x8f,0x11,0xf6,0x19,0x49,0x12,0x71,0x18,0xce,0x13, - 0x00,0x2b,0x01,0xd0,0x80,0x1a,0x00,0xe0,0x10,0x18,0x42,0x19,0x91,0x08,0x8d,0x00, - 0x52,0x1b,0x00,0x2b,0x04,0xd0,0x43,0x01,0x18,0x1a,0x40,0x18,0x80,0x1b,0x03,0xe0, - 0x43,0x01,0x18,0x1a,0x40,0x18,0x80,0x19,0x22,0x61,0xf0,0xbc,0x70,0x47,0x00,0x00, - 0x00,0x6e,0x00,0x20,0x58,0x68,0x00,0x20,0x10,0xb4,0x00,0x23,0x14,0x21,0x02,0x46, - 0x4a,0x43,0x11,0x49,0x7d,0x24,0x09,0x68,0x24,0x02,0xa1,0x42,0x02,0xd9,0x09,0x1b, - 0x01,0x23,0x00,0xe0,0x61,0x1a,0x48,0x43,0x81,0x00,0x41,0x18,0x88,0x0a,0x0c,0x0c, - 0x00,0x19,0x4c,0x0c,0x00,0x19,0x4c,0x0d,0x00,0x19,0x4c,0x0e,0x00,0x19,0xc9,0x0f, - 0x40,0x18,0xc0,0x08,0x00,0x2b,0x01,0xd0,0x10,0x18,0x01,0xe0,0x10,0x1a,0x40,0x1e, - 0x40,0x1e,0x10,0xbc,0x70,0x47,0x00,0x00,0x58,0x68,0x00,0x20 + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0xff,0xff,0xff, + 0xff,0x03,0x00,0x00,0xff,0x00,0x3c,0x1f,0x00,0x00,0x00,0x00,0x01,0x20,0x00,0x00, + 0x8d,0x84,0x00,0x00,0x02,0x20,0x00,0x00,0xcd,0x7d,0x00,0x00,0x03,0x20,0x00,0x00, + 0xd1,0x7e,0x00,0x00,0x05,0x20,0x00,0x00,0xfd,0x84,0x00,0x00,0xf0,0xb4,0x00,0x23, + 0x18,0x4c,0x25,0x69,0x18,0x49,0x7d,0x22,0x09,0x68,0x12,0x02,0x91,0x42,0x02,0xd3, + 0x8a,0x1a,0x01,0x23,0x00,0xe0,0x52,0x1a,0x06,0x46,0x56,0x43,0xf2,0x13,0x51,0x43, + 0x71,0x1a,0x1e,0x26,0x4e,0x43,0x4f,0x10,0xf6,0x19,0x8f,0x11,0xf6,0x19,0x49,0x12, + 0x71,0x18,0xce,0x13,0x00,0x2b,0x01,0xd0,0x80,0x1a,0x00,0xe0,0x10,0x18,0x42,0x19, + 0x91,0x08,0x8d,0x00,0x52,0x1b,0x00,0x2b,0x04,0xd0,0x43,0x01,0x18,0x1a,0x40,0x18, + 0x80,0x1b,0x03,0xe0,0x43,0x01,0x18,0x1a,0x40,0x18,0x80,0x19,0x22,0x61,0xf0,0xbc, + 0x70,0x47,0x00,0x00,0x00,0x6e,0x00,0x20,0x58,0x68,0x00,0x20,0x10,0xb4,0x00,0x23, + 0x14,0x21,0x02,0x46,0x4a,0x43,0x11,0x49,0x7d,0x24,0x09,0x68,0x24,0x02,0xa1,0x42, + 0x02,0xd9,0x09,0x1b,0x01,0x23,0x00,0xe0,0x61,0x1a,0x48,0x43,0x81,0x00,0x41,0x18, + 0x88,0x0a,0x0c,0x0c,0x00,0x19,0x4c,0x0c,0x00,0x19,0x4c,0x0d,0x00,0x19,0x4c,0x0e, + 0x00,0x19,0xc9,0x0f,0x40,0x18,0xc0,0x08,0x00,0x2b,0x01,0xd0,0x10,0x18,0x01,0xe0, + 0x10,0x1a,0x40,0x1e,0x40,0x1e,0x10,0xbc,0x70,0x47,0x00,0x00,0x58,0x68,0x00,0x20 } }; am_hal_ble_patch_t am_ble_buffer_patch_b0 = { .ui32Type = 0xCC, - .ui32Length = 0x025c, - .ui32CRC = 0x713d, + .ui32Length = 0x0230, + .ui32CRC = 0x320c, .pui32Data = am_ble_buffer_patch_data_b0.words, }; + //***************************************************************************** // // Patch Name: Function PATCH v0.4 for Apollo3 B0 diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch_b0.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch_b0.h index 3e9c7e0..1534f58 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch_b0.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ble_patch_b0.h @@ -12,26 +12,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -44,7 +44,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_burst.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_burst.c index 5e56a0a..f1a5d13 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_burst.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_burst.c @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -92,16 +92,7 @@ am_hal_burst_mode_initialize(am_hal_burst_avail_e *peBurstAvail) // if (PWRCTRL->SUPPLYSRC_b.BLEBUCKEN) { - if ( APOLLO3_GE_A1 ) - { - CLKGEN->BLEBUCKTONADJ = - _VAL2FLD(CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN, CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_EN) | - _VAL2FLD(CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM, CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetF) | - _VAL2FLD(CLKGEN_BLEBUCKTONADJ_TONADJUSTEN, CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_EN) | - _VAL2FLD(CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD, CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_94KHz) | - _VAL2FLD(CLKGEN_BLEBUCKTONADJ_TONHIGHTHRESHOLD, 0x10) | - _VAL2FLD(CLKGEN_BLEBUCKTONADJ_TONLOWTHRESHOLD, 0xF); - } + am_hal_pwrctrl_blebuck_trim(); } // diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_burst.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_burst.h index fc85385..2b61522 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_burst.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_burst.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_BURST_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cachectrl.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cachectrl.c index fe4e2e0..9a42126 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cachectrl.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cachectrl.c @@ -5,7 +5,7 @@ //! //! @brief Functions for interfacing with the CACHE controller. //! -//! @addtogroup clkgen3 Clock Generator (CACHE) +//! @addtogroup cachectrl3 Cache Control (CACHE) //! @ingroup apollo3hal //! @{ // @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cachectrl.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cachectrl.h index 7b085b1..fc39115 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cachectrl.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cachectrl.h @@ -5,7 +5,7 @@ //! //! @brief Functions for accessing and configuring the CACHE controller. //! -//! @addtogroup clkgen3 Clock Generator (CACHE) +//! @addtogroup cachectrl3 Cache Control (CACHE) //! @ingroup apollo3hal //! @{ // @@ -13,26 +13,26 @@ // **************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // // **************************************************************************** #ifndef AM_HAL_CACHECTRL_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_clkgen.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_clkgen.c index eb23d3c..6a9d530 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_clkgen.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_clkgen.c @@ -13,26 +13,26 @@ // **************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // // **************************************************************************** @@ -93,48 +93,40 @@ am_hal_clkgen_control(am_hal_clkgen_control_e eControl, void *pArgs) break; case AM_HAL_CLKGEN_CONTROL_LFRC_START: - CLKGEN->OCTRL &= ~_VAL2FLD(CLKGEN_OCTRL_STOPRC, - CLKGEN_OCTRL_STOPRC_STOP); + CLKGEN->OCTRL_b.STOPRC = CLKGEN_OCTRL_STOPRC_EN; break; case AM_HAL_CLKGEN_CONTROL_XTAL_START: - CLKGEN->OCTRL &= ~_VAL2FLD(CLKGEN_OCTRL_STOPXT, - CLKGEN_OCTRL_STOPXT_STOP); + CLKGEN->OCTRL_b.STOPXT = CLKGEN_OCTRL_STOPXT_EN; break; case AM_HAL_CLKGEN_CONTROL_LFRC_STOP: - CLKGEN->OCTRL |= _VAL2FLD(CLKGEN_OCTRL_STOPRC, - CLKGEN_OCTRL_STOPRC_STOP); + CLKGEN->OCTRL_b.STOPRC = CLKGEN_OCTRL_STOPRC_STOP; break; case AM_HAL_CLKGEN_CONTROL_XTAL_STOP: - // TODO - Fixme. What is Errata #? // Software Workaround to guarantee proper function of HFADJ. if (APOLLO3_B0) { - MCUCTRL->XTALCTRL_b.XTALICOMPTRIM = 1; + MCUCTRL->XTALCTRL_b.XTALICOMPTRIM = 1; } - CLKGEN->OCTRL |= _VAL2FLD(CLKGEN_OCTRL_STOPXT, - CLKGEN_OCTRL_STOPXT_STOP); + CLKGEN->OCTRL_b.STOPXT = CLKGEN_OCTRL_STOPXT_STOP; break; case AM_HAL_CLKGEN_CONTROL_RTC_SEL_LFRC: - CLKGEN->OCTRL |= _VAL2FLD(CLKGEN_OCTRL_OSEL, - CLKGEN_OCTRL_OSEL_RTC_LFRC); + CLKGEN->OCTRL_b.OSEL = CLKGEN_OCTRL_OSEL_RTC_LFRC; break; case AM_HAL_CLKGEN_CONTROL_RTC_SEL_XTAL: - CLKGEN->OCTRL |= _VAL2FLD(CLKGEN_OCTRL_OSEL, - CLKGEN_OCTRL_OSEL_RTC_XT); + CLKGEN->OCTRL_b.OSEL = CLKGEN_OCTRL_OSEL_RTC_XT; break; case AM_HAL_CLKGEN_CONTROL_HFADJ_ENABLE: - // TODO - Fixme. What is Errata #? // Software Workaround to guarantee proper function of HFADJ. if (APOLLO3_B0) { - MCUCTRL->XTALCTRL_b.XTALICOMPTRIM = 3; - am_hal_flash_delay(FLASH_CYCLES_US(1000)); + MCUCTRL->XTALCTRL_b.XTALICOMPTRIM = 3; + am_hal_flash_delay(FLASH_CYCLES_US(1000)); } if ( pArgs == 0 ) { diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_clkgen.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_clkgen.h index 36be415..81bd3ad 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_clkgen.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_clkgen.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_CLKGEN_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cmdq.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cmdq.c index 112b9af..7c74c68 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cmdq.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cmdq.c @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cmdq.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cmdq.h index 2ca1a68..8e815b2 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cmdq.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_cmdq.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -95,6 +95,12 @@ typedef struct bool bErr; } am_hal_cmdq_status_t; + +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // //! @brief Initialize a Command Queue @@ -279,4 +285,8 @@ uint32_t am_hal_cmdq_reset(void *pHandle); //***************************************************************************** uint32_t am_hal_cmdq_post_loop_block(void *pHandle, bool bInt); +#ifdef __cplusplus +} +#endif + #endif // AM_HAL_CMDQ_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ctimer.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ctimer.c index c186dc2..230dce6 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ctimer.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ctimer.c @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -299,6 +299,42 @@ am_hal_triple_read( uint32_t u32TimerAddr, uint32_t ui32Data[]) #error Compiler is unknown, please contact Ambiq support team #endif + + +//***************************************************************************** +// +// ctimer_clr() +// +// For the appropriate ctimer configuration register, set the CLR bit high +// in the appropriate timer segment (A, B, or both). +// +// The CLR bit is required to be set in order to completely initialize +// the timer at config time. The timer clear occurs asynchrnously during the +// low-to-high transition of the CLR bit. +// +// This function only sets the CLR bit. It is assumed that the actual timer +// configuration will occur following the call to this function and will clear +// the CLR bit at that time. +// +//***************************************************************************** +static void +ctimer_clr(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) +{ + // + // Find the address of the correct control register and set the CLR bit + // for the timer segment in that control register. + // + volatile uint32_t *pui32ConfigReg = + (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + + AM_CRITICAL_BEGIN + AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment & + (CTIMER_CTRL0_TMRA0CLR_Msk | + CTIMER_CTRL0_TMRB0CLR_Msk)); + AM_CRITICAL_END + +} // ctimer_clr() + //***************************************************************************** // //! @brief Convenience function for responding to CTimer interrupts. @@ -535,7 +571,8 @@ am_hal_ctimer_int_register(uint32_t ui32Interrupt, //! @return None. // //***************************************************************************** -void am_hal_ctimer_globen(uint32_t ui32ConfigVal) +void +am_hal_ctimer_globen(uint32_t ui32ConfigVal) { uint32_t *pui32ConfigReg; @@ -576,10 +613,18 @@ void am_hal_ctimer_globen(uint32_t ui32ConfigVal) //! //! @note This function is deprecated and will eventually be replaced by //! am_hal_ctimer_config_single(), which performs the same configuration -//! without requiring a structure. -//! Please use am_hal_ctimer_config_single(). +//! without requiring a structure and without assuming both timer halves +//! are being configured. +//! Please use am_hal_ctimer_config_single() for new development. //! //! @return None. +//! +//! +//! @note In order to initialize the given timer into a known state, this +//! function asserts the CLR configuration bit. The CLR bit will be deasserted +//! with the write of the configuration register. The CLR bit is also +//! intentionally deasserted with a call to am_hal_ctimer_start(). +//! // //***************************************************************************** void @@ -590,6 +635,12 @@ am_hal_ctimer_config(uint32_t ui32TimerNumber, uint32_t ui32Seg, ui32ClkSrc; uint32_t *pui32ConfigReg; + // + // Make sure the timer is completely initialized on configuration by + // setting the CLR bit. + // + ctimer_clr(ui32TimerNumber, AM_HAL_CTIMER_BOTH); + // // Start preparing the configuration word for this timer. The configuration // values for Timer A and Timer B provided in the config structure should @@ -605,14 +656,14 @@ am_hal_ctimer_config(uint32_t ui32TimerNumber, ui32ConfigVal |= psConfig->ui32Link ? AM_HAL_CTIMER_LINK : 0; // - // Begin critical section while config registers are read and modified. + // Find the correct register to write. // - AM_CRITICAL_BEGIN + pui32ConfigReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); // - // Find the correct register to write. + // Begin critical section while config registers are read and modified. // - pui32ConfigReg = (uint32_t*)CTIMERADDRn(CTIMER, ui32TimerNumber, CTRL0); + AM_CRITICAL_BEGIN // // Write our configuration value. @@ -666,6 +717,7 @@ am_hal_ctimer_config(uint32_t ui32TimerNumber, //! counter-timer. It can be used to configure either a 16-bit timer (A or B) or a //! 32-bit timer using the BOTH option. //! +//! //! Valid values for ui32TimerSegment are: //! //! AM_HAL_CTIMER_TIMERA @@ -704,6 +756,13 @@ am_hal_ctimer_config(uint32_t ui32TimerNumber, //! AM_HAL_CTIMER_ADC_TRIG //! //! @return None. +//! +//! +//! @note In order to initialize the given timer into a known state, this +//! function asserts the CLR configuration bit. The CLR bit will be deasserted +//! with the write of the configuration register. The CLR bit is also +//! intentionally deasserted with a call to am_hal_ctimer_start(). +//! // //***************************************************************************** void @@ -714,6 +773,12 @@ am_hal_ctimer_config_single(uint32_t ui32TimerNumber, volatile uint32_t *pui32ConfigReg; uint32_t ui32Seg, ui32ClkSrc; + // + // Make sure the timer is completely initialized on configuration by + // setting the CLR bit. + // + ctimer_clr(ui32TimerNumber, ui32TimerSegment); + // // Find the correct register to write based on the timer number. // @@ -734,7 +799,6 @@ am_hal_ctimer_config_single(uint32_t ui32TimerNumber, // If we're working with TIMERB, we need to shift our configuration value // up by 16 bits. // - if ( ui32TimerSegment == AM_HAL_CTIMER_TIMERB ) { ui32ConfigVal = ((ui32ConfigVal & 0xFFFF) << 16); @@ -767,7 +831,6 @@ am_hal_ctimer_config_single(uint32_t ui32TimerNumber, // // Save the clock source for this timer. // - switch ( ui32TimerSegment ) { case AM_HAL_CTIMER_TIMERA: @@ -811,8 +874,14 @@ am_hal_ctimer_config_single(uint32_t ui32TimerNumber, //! AM_HAL_CTIMER_TIMERA //! AM_HAL_CTIMER_TIMERB //! -//! //! @return None. +//! +//! +//! @note In order to initialize the given timer into a known state, this +//! function asserts the CLR configuration bit. The CLR bit will be deasserted +//! with the write of the configuration register. The CLR bit is also +//! intentionally deasserted with a call to am_hal_ctimer_start(). +//! // //***************************************************************************** void @@ -1031,6 +1100,11 @@ am_hal_ctimer_stop(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment) //! AM_HAL_CTIMER_BOTH //! //! @return None. +//! +//! +//! @note Setting the CLR bit is necessary for completing timer initialization +//! including after MCU resets. +//! // //***************************************************************************** void @@ -1239,6 +1313,7 @@ am_hal_ctimer_output_config(uint32_t ui32TimerNumber, { uint32_t ux, ui32Ctx, ui32CtxPadNum; uint32_t ui32CtxOutcfgFnc, ui32CtxOutcfgMsk, ui32CfgShf; + uint32_t ui32OutcfgValue; am_hal_gpio_pincfg_t sPinCfg = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; @@ -1348,23 +1423,31 @@ am_hal_ctimer_output_config(uint32_t ui32TimerNumber, // if ( ui32Ctx < 10 ) { - CTIMER->OUTCFG0 &= ~ui32CtxOutcfgMsk; - CTIMER->OUTCFG0 |= ui32CtxOutcfgFnc; + ui32OutcfgValue = CTIMER->OUTCFG0; + ui32OutcfgValue &= ~ui32CtxOutcfgMsk; + ui32OutcfgValue |= ui32CtxOutcfgFnc; + CTIMER->OUTCFG0 = ui32OutcfgValue; } else if ( ui32Ctx < 20 ) { - CTIMER->OUTCFG1 &= ~ui32CtxOutcfgMsk; - CTIMER->OUTCFG1 |= ui32CtxOutcfgFnc; + ui32OutcfgValue = CTIMER->OUTCFG1; + ui32OutcfgValue &= ~ui32CtxOutcfgMsk; + ui32OutcfgValue |= ui32CtxOutcfgFnc; + CTIMER->OUTCFG1 = ui32OutcfgValue; } else if ( ui32Ctx < 30 ) { - CTIMER->OUTCFG2 &= ~ui32CtxOutcfgMsk; - CTIMER->OUTCFG2 |= ui32CtxOutcfgFnc; + ui32OutcfgValue = CTIMER->OUTCFG2; + ui32OutcfgValue &= ~ui32CtxOutcfgMsk; + ui32OutcfgValue |= ui32CtxOutcfgFnc; + CTIMER->OUTCFG2 = ui32OutcfgValue; } else { - CTIMER->OUTCFG3 &= ~ui32CtxOutcfgMsk; - CTIMER->OUTCFG3 |= ui32CtxOutcfgFnc; + ui32OutcfgValue = CTIMER->OUTCFG3; + ui32OutcfgValue &= ~ui32CtxOutcfgMsk; + ui32OutcfgValue |= ui32CtxOutcfgFnc; + CTIMER->OUTCFG3 = ui32OutcfgValue; } GPIO->CTENCFG &= ~(1 << ui32Ctx); diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ctimer.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ctimer.h index 2f5b4be..a515179 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ctimer.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ctimer.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_CTIMER_H @@ -161,12 +161,9 @@ typedef enum //***************************************************************************** // -//! @name DEPRECATED Interrupt Status Bits -//! -//! @{ +// DEPRECATED Interrupt Status Bits // //***************************************************************************** -//! @bug 31 common examples use AM_HAL_CTIMER_INT_TIMERA0 #define AM_HAL_CTIMER_INT_TIMERA0 AM_HAL_CTIMER_INT_TIMERA0C0 #define AM_HAL_CTIMER_INT_TIMERB0 AM_HAL_CTIMER_INT_TIMERB0C0 #define AM_HAL_CTIMER_INT_TIMERA1 AM_HAL_CTIMER_INT_TIMERA1C0 @@ -175,7 +172,6 @@ typedef enum #define AM_HAL_CTIMER_INT_TIMERB2 AM_HAL_CTIMER_INT_TIMERB2C0 #define AM_HAL_CTIMER_INT_TIMERA3 AM_HAL_CTIMER_INT_TIMERA3C0 #define AM_HAL_CTIMER_INT_TIMERB3 AM_HAL_CTIMER_INT_TIMERB3C0 -//! @} //***************************************************************************** // @@ -211,7 +207,9 @@ typedef enum //***************************************************************************** // -// Timer function macros. +//! Timer function macros. +//! +//! @{ // //***************************************************************************** //! Single Count: Counts one time to the compare value, then the output @@ -234,28 +232,37 @@ typedef enum //! Alternate Pulse: like Repeated Pulse but alternating between two different //! pulse width/spacing settings. #define AM_HAL_CTIMER_FN_PWM_ALTERNATE _VAL2FLD(CTIMER_CTRL0_TMRA0FN, 7) +//! @} //***************************************************************************** // -// Half-timer options. +//! Half-timer options. +//! +//! @{ // //***************************************************************************** #define AM_HAL_CTIMER_INT_ENABLE CTIMER_CTRL0_TMRA0IE0_Msk //#define AM_HAL_CTIMER_PIN_ENABLE CTIMER_CTRL0_TMRA0PE_Msk #define AM_HAL_CTIMER_PIN_INVERT CTIMER_CTRL0_TMRA0POL_Msk #define AM_HAL_CTIMER_CLEAR CTIMER_CTRL0_TMRA0CLR_Msk +//! @} //***************************************************************************** // -// Additional timer options. +//! Additional timer options. +//! +//! @{ // //***************************************************************************** #define AM_HAL_CTIMER_LINK CTIMER_CTRL0_CTLINK0_Msk #define AM_HAL_CTIMER_ADC_TRIG CTIMER_CTRL3_ADCEN_Msk +//! @} //***************************************************************************** // -// Timer selection macros. +//! Timer selection macros. +//! +//! @{ // //***************************************************************************** #define AM_HAL_CTIMER_TIMERA 0x0000FFFF @@ -263,6 +270,43 @@ typedef enum #define AM_HAL_CTIMER_BOTH 0xFFFFFFFF //! @} +//***************************************************************************** +// +//! Timer trigger options for Apollo3 Blue (rev B0 and later) including +//! Apollo3 Blue Plus. +//! +//! Valid only for CTIMER4 and CTIMER5 when CTLINK==1 and TMRA4TRIG==1 +//! +//! @{ +// +//***************************************************************************** +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCAP0 CTIMER_AUX4_TMRB4TRIG_A7OUT +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCAP1 CTIMER_AUX4_TMRB4TRIG_B7OUT +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCAP2 CTIMER_AUX4_TMRB4TRIG_A1OUT +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCAP3 CTIMER_AUX4_TMRB4TRIG_B1OUT +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP0 CTIMER_AUX4_TMRB4TRIG_B3OUT2 +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP1 CTIMER_AUX4_TMRB4TRIG_A3OUT2 +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP2 CTIMER_AUX4_TMRB4TRIG_A1OUT2 +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP3 CTIMER_AUX4_TMRB4TRIG_B1OUT2 +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP4 CTIMER_AUX4_TMRB4TRIG_A6OUT2DUAL +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP5 CTIMER_AUX4_TMRB4TRIG_A7OUT2DUAL +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP6 CTIMER_AUX4_TMRB4TRIG_B5OUT2DUAL +#define AM_HAL_CTIMER_AUX4_TMRB4TRIG_STIMERCMP7 CTIMER_AUX4_TMRB4TRIG_A5OUT2DUAL + +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCAP0 CTIMER_AUX5_TMRB5TRIG_A7OUT +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCAP1 CTIMER_AUX5_TMRB5TRIG_B7OUT +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCAP2 CTIMER_AUX5_TMRB5TRIG_A1OUT +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCAP3 CTIMER_AUX5_TMRB5TRIG_B1OUT +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP0 CTIMER_AUX5_TMRB5TRIG_B3OUT2 +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP1 CTIMER_AUX5_TMRB5TRIG_A3OUT2 +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP2 CTIMER_AUX5_TMRB5TRIG_A1OUT2 +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP3 CTIMER_AUX5_TMRB5TRIG_B1OUT2 +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP4 CTIMER_AUX5_TMRB5TRIG_A6OUT2DUAL +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP5 CTIMER_AUX5_TMRB5TRIG_A7OUT2DUAL +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP6 CTIMER_AUX5_TMRB5TRIG_B5OUT2DUAL +#define AM_HAL_CTIMER_AUX5_TMRB5TRIG_STIMERCMP7 CTIMER_AUX5_TMRB5TRIG_A5OUT2DUAL +//! @} + //***************************************************************************** // //! @name All-In-One Configuration @@ -384,7 +428,6 @@ typedef struct uint32_t OUTCFG3; } am_hal_ctimer_aio_connect_t; - //! @} //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_debug.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_debug.c index b609af9..03e310a 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_debug.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_debug.c @@ -17,26 +17,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -49,7 +49,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_debug.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_debug.h index 2e66aeb..853c1f0 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_debug.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_debug.h @@ -17,26 +17,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -49,7 +49,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_DEBUG_H @@ -60,6 +60,44 @@ extern "C" { #endif + +//***************************************************************************** +// +// Determine DBG_FILENAME +// +//***************************************************************************** +// +// By spec and convention, the standard __FILE__ compiler macro includes a full +// path (absolute or relative) to the file being compiled. This makes recreating +// binaries virtually impossible unless rebuilt on the same or identically +// configured system. +// +// To be able to build consistent binaries on different systems, we want to make +// sure the full pathname is not included in the binary. Only IAR EWARM provides +// an easy mechanism to provide only the filename without the path. For other +// platforms, we will simply use a generic pathname. +// +#if defined (__IAR_SYSTEMS_ICC__) +// +// With EWARM the --no_path_in_file_macros option reduces __FILE__ to only the +// module name. Therefore this define assumes the option is being used. +// +#define DBG_FILENAME __FILE__ +#elif defined(__KEIL__) +// +// Keil provides __MODULE__ which is simply the module name portion of __FILE__. +// +#define DBG_FILENAME __MODULE__ +#elif defined(__ARMCC_VERSION) +#define DBG_FILENAME __MODULE__ +#else +// +// With GCC, we're out of luck. +// +#define DBG_FILENAME "debug_filename.ext" +//#define DBG_FILENAME __FILE__ +#endif + //***************************************************************************** // // Debug assert macros. @@ -68,10 +106,10 @@ extern "C" #ifndef AM_HAL_DEBUG_NO_ASSERT #define am_hal_debug_assert_msg(bCondition, pcMessage) \ - if ( !(bCondition)) am_hal_debug_error(__FILE__, __LINE__, pcMessage) + if ( !(bCondition)) am_hal_debug_error(DBG_FILENAME, __LINE__, pcMessage) #define am_hal_debug_assert(bCondition) \ - if ( !(bCondition)) am_hal_debug_error(__FILE__, __LINE__, 0) + if ( !(bCondition)) am_hal_debug_error(DBG_FILENAME, __LINE__, 0) #else diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_flash.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_flash.c index 8c48a8d..759d4d5 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_flash.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_flash.c @@ -24,26 +24,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -56,7 +56,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -112,6 +112,10 @@ const uint32_t ui32SramMaxAddr = (AM_HAL_FLASH_SRAM_LARGEST_VALID_ADDR + 1); //! Detailed Description above for more details. //! //! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32ProgramKey is invalid. +//! 2 ui32FlashInst is invalid. +//! 3 Flash controller hardware timeout. // //***************************************************************************** int @@ -147,6 +151,11 @@ am_hal_flash_mass_erase(uint32_t ui32ProgramKey, uint32_t ui32FlashInst) //! Detailed Description above for more details. //! //! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32ProgramKey is invalid. +//! 2 ui32FlashInst is invalid. +//! 3 ui32PageNum is invalid. +//! 4 Flash controller hardware timeout. // //***************************************************************************** int @@ -176,6 +185,14 @@ am_hal_flash_page_erase(uint32_t ui32ProgramKey, uint32_t ui32FlashInst, //! Detailed Description above for more details. //! //! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32ProgramKey is invalid. +//! 2 pui32Dst is invalid. +//! 3 Flash addressing range would be exceeded. That is, (pui32Dst + +//! (ui32NumWords * 4)) is greater than the last valid address. +//! 4 pui32Src is invalid. +//! 5 Unused - will never be returned. +//! 6 Flash controller hardware timeout. // //***************************************************************************** int @@ -251,6 +268,8 @@ am_hal_flash_program_main(uint32_t ui32ProgramKey, uint32_t *pui32Src, //! care of not re-clearing bits if they are already programmed as 0 //! //! @return 0 for success, non-zero for failure. +//! +//! Note: See am_hal_flash_program_main() for further details on return codes. // //***************************************************************************** int @@ -289,6 +308,16 @@ am_hal_flash_clear_bits(uint32_t ui32ProgramKey, uint32_t *pui32Addr, //! Detailed Description above for more details. //! //! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32InfoKey is invalid. +//! 2 ui32InfoInst is invalid. +//! 3 ui32Offset is invalid. +//! 4 INFO addressing range would be exceeded. That is, (ui32Offset + +//! ui32NumWords) is greater than the last valid address. +//! 5 pui32Src is invalid. +//! 6 pui32Src is invalid. +//! 7 Hardware error. +//! 8 Flash controller hardware timeout. // //***************************************************************************** int @@ -362,6 +391,11 @@ am_hal_flash_program_info(uint32_t ui32InfoKey, uint32_t ui32InfoInst, //! Detailed Description above for more details. //! //! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32InfoKey is invalid. +//! 2 ui32Inst is invalid. +//! 3 Hardware error. +//! 4 Flash controller hardware timeout. // //***************************************************************************** int @@ -386,6 +420,14 @@ am_hal_flash_erase_info(uint32_t ui32InfoKey, //! Detailed Description above for more details. //! //! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32InfoKey is invalid. +//! 2 ui32Inst is invalid. +//! 3 Hardware error. +//! 4 Flash controller hardware timeout. +//! 11 Internal error. +//! 12 Internal error. +//! 13 Flash controller hardware timeout. // //***************************************************************************** int @@ -410,6 +452,21 @@ am_hal_flash_erase_main_plus_info(uint32_t ui32InfoKey, //! Detailed Description above for more details. //! //! @return 0 for success, non-zero for failure. +//! Failing return code indicates: +//! 1 ui32InfoKey is invalid, instance 0. +//! 2 Internal error, instance 0. +//! 3 Hardware error, instance 0. +//! 4 Flash controller hardware timeout, instance 0. +//! 11 Internal error. +//! 12 Internal error. +//! 13 Flash controller hardware timeout. +//! 21 ui32InfoKey is invalid, instance 1. +//! 22 Internal error, instance 1. +//! 23 Hardware error, instance 1. +//! 24 Flash controller hardware timeout, instance 1. +//! 31 Internal error, instance 1. +//! 32 Internal error, instance 1. +//! 33 Flash controller hardware timeout, instance 1. // //***************************************************************************** int @@ -441,6 +498,18 @@ am_hal_flash_erase_main_plus_info_both_instances(uint32_t ui32InfoKey) //! Detailed Description above for more details. //! //! @return Does not return if successful. Returns failure code otherwise. +//! Failing return code indicates: +//! 0x00000001 ui32RecoveryKey is invalid. +//! 0x00000002 Customer key lock not set. +//! 0x00001001 Internal error. +//! 0x00001002 Internal error. +//! 0x00001003 Info erase, instance 0 - hardware error. +//! 0x00001004 Info erase, instance 0 - flash controller hardware timeout. +//! 0xi000ppee Error erasing page in instance, pp=page number, ee=error code. +//! i=2|3, instance 0. +//! i=4|5, instance 1. +//! ee=1|2|3 Internal or hardware error. +//! ee=4 Flash controller hardware timeout. // //***************************************************************************** void @@ -467,8 +536,8 @@ am_hal_flash_recovery(uint32_t ui32RecoveryKey) //! overhead encountered with executing the function itself (such as the //! check for burst mode). //! - Use of the FLASH_CYCLES_US() or FLASH_CYCLES_US_NOCACHE() macros for the -//! ui32Iteractions parameter will result in approximate microsecond timing. -//! - The parameter ui32Iteractions==0 is allowed but is still incurs a delay. +//! ui32Iterations parameter will result in approximate microsecond timing. +//! - The parameter ui32Iterations==0 is allowed but is still incurs a delay. //! //! Example: //! - MCU operating at 48MHz -> 20.83 ns / cycle @@ -662,6 +731,8 @@ customer_info_signature_erased(void) //! hardware. //! //! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. // //***************************************************************************** static int @@ -699,6 +770,10 @@ customer_info_signature_set(uint32_t ui32InfoKey) ui32Valid, // source data 0, // offset 4); // number of words + + // + // See am_hal_flash_program_info() for further details on return codes. + // return iRC | ((iRC) ? (1 << 16) : 0); } // customer_info_signature_set() @@ -740,6 +815,8 @@ am_hal_flash_customer_info_signature_check(void) //! Detailed Description above for more details. //! //! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. // //***************************************************************************** bool @@ -766,6 +843,8 @@ am_hal_flash_info_signature_set(uint32_t ui32InfoKey) //! Detailed Description above for more details. //! //! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. // //***************************************************************************** int32_t @@ -861,6 +940,8 @@ am_hal_flash_info_erase_disable_check(void) //! Detailed Description above for more details. //! //! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. // //***************************************************************************** int32_t @@ -963,6 +1044,8 @@ am_hal_flash_info_program_disable_get(void) //! Detailed Description above for more details. //! //! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. // //***************************************************************************** int32_t @@ -1048,6 +1131,8 @@ am_hal_flash_wipe_flash_enable_check(void) //! Detailed Description above for more details. //! //! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. // //***************************************************************************** int32_t @@ -1133,6 +1218,8 @@ am_hal_flash_wipe_sram_enable_check(void) //! Detailed Description above for more details. //! //! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. // //***************************************************************************** int32_t @@ -1218,6 +1305,8 @@ am_hal_flash_swo_disable_check(void) //! Detailed Description above for more details. //! //! @return Zero for success. Non-Zero for errors. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. // //***************************************************************************** int32_t @@ -1372,6 +1461,8 @@ generate_chunk_mask(uint32_t *pui32StartAddress, uint32_t *pui32StopAddress) //! 0x400000 if the protection bits were already programmed (mask the return //! value with 0x3FFFFF to ignore this case and treat as success). //! Otherwise, non-zero for failure. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. // //***************************************************************************** int32_t @@ -1542,6 +1633,8 @@ am_hal_flash_copy_protect_check(uint32_t *pui32StartAddress, //! 0x400000 if the protection bits were already programmed (mask the return //! value with 0x3FFFFF to ignore this case and treat as success). //! Otherwise, non-zero for failure. +//! +//! Note: See am_hal_flash_program_info() for further details on return codes. // //***************************************************************************** int32_t diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_flash.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_flash.h index 74e9ed4..7e28f0d 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_flash.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_flash.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_FLASH_H @@ -91,6 +91,20 @@ extern "C" #define AM_HAL_FLASH_INSTANCE_PAGES ( AM_HAL_FLASH_INSTANCE_SIZE / AM_HAL_FLASH_PAGE_SIZE ) #define AM_HAL_FLASH_TOTAL_SIZE ( AM_HAL_FLASH_INSTANCE_SIZE * AM_HAL_FLASH_NUM_INSTANCES ) #define AM_HAL_FLASH_LARGEST_VALID_ADDR ( AM_HAL_FLASH_ADDR + AM_HAL_FLASH_TOTAL_SIZE - 1 ) +#define AM_HAL_FLASH_APPL_ADDR 0xC000 + +// +// Macros to determine whether a given address is a valid internal +// flash or SRAM address. +// +#define ISADDRSRAM(x) ((x >= AM_HAL_FLASH_SRAM_ADDR) && \ + (x <= (AM_HAL_FLASH_SRAM_LARGEST_VALID_ADDR & ~0x3))) +#if AM_HAL_FLASH_ADDR == 0x0 +#define ISADDRFLASH(x) (x <= (AM_HAL_FLASH_LARGEST_VALID_ADDR & ~0x3)) +#else +#define ISADDRFLASH(x) ((x >= AM_HAL_FLASH_ADDR) && \ + (x <= (AM_HAL_FLASH_LARGEST_VALID_ADDR & ~0x3))) +#endif // // Macros to describe the flash ROW layout. @@ -98,7 +112,7 @@ extern "C" #define AM_HAL_FLASH_ROW_WIDTH_BYTES (512) // -// Convert an absolute flash address to a instance +// Convert an absolute flash address to an instance // #define AM_HAL_FLASH_ADDR2INST(addr) ( ( addr >> 19 ) & (AM_HAL_FLASH_NUM_INSTANCES - 1) ) diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_global.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_global.c index 208d986..ca894ca 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_global.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_global.c @@ -14,26 +14,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -46,7 +46,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_global.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_global.h index dfb07cf..c9ad4c0 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_global.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_global.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_GLOBAL_H @@ -58,28 +58,28 @@ extern "C" //***************************************************************************** // -// Macro definitions +// Include the SDK global version information. // //***************************************************************************** -// Utility for compile time assertions -// Will cause divide by 0 error at build time -#define _AM_ASSERT_CONCAT_(a, b) a##b -#define _AM_ASSERT_CONCAT(a, b) _AM_ASSERT_CONCAT_(a, b) -#define am_ct_assert(e) enum { _AM_ASSERT_CONCAT(assert_line_, __LINE__) = 1/(!!(e)) } +#include "../../am_sdk_version.h" //***************************************************************************** // -// Macros to define HAL SDK version. +// Device definitions // //***************************************************************************** -#ifndef AM_HAL_VERSION_MAJ +#define AM_HAL_DEVICE_NAME "Apollo3 Blue" + +//***************************************************************************** // -// Set current HAL version to 2.2.0 +// Macro definitions // -#define AM_HAL_VERSION_MAJ 2 -#define AM_HAL_VERSION_MIN 2 -#define AM_HAL_VERSION_REV 0 -#endif // AM_HAL_VERSION_MAJ +//***************************************************************************** +// Utility for compile time assertions +// Will cause divide by 0 error at build time +#define _AM_ASSERT_CONCAT_(a, b) a##b +#define _AM_ASSERT_CONCAT(a, b) _AM_ASSERT_CONCAT_(a, b) +#define am_ct_assert(e) enum { _AM_ASSERT_CONCAT(assert_line_, __LINE__) = 1/(!!(e)) } //***************************************************************************** // diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_gpio.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_gpio.c index 4fb8648..9417c11 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_gpio.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_gpio.c @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -336,11 +336,12 @@ g_ui8NCEtable[AM_HAL_GPIO_MAX_PADS][4] = // //***************************************************************************** static am_hal_gpio_handler_t gpio_ppfnHandlers[AM_HAL_GPIO_MAX_PADS]; +static void *gpio_pHandlerCtxt[AM_HAL_GPIO_MAX_PADS]; //***************************************************************************** // // Helper functions -// num_bits64() - Determine how many bits are set in a 64-bit value. +// popcount() - Determine how many bits are set in the given bitmasks. // pincfg_equ() - compare 2 am_hal_gpio_pincfg_t structures for equality. // //***************************************************************************** @@ -361,17 +362,16 @@ pincfg_equ(void *cfg1, void *cfg2) } // pincfg_equ() static uint32_t -num_bits64(uint64_t ui64bitmask) +popcount(uint64_t ui64bitmask) { - uint32_t ux = 0; + uint32_t uCnt = 0; while ( ui64bitmask ) { - ux += ui64bitmask & 1; + uCnt += ui64bitmask & 1; ui64bitmask >>= 1; } - return ux; -} // num_bits64() - + return uCnt; +} // popcount() //***************************************************************************** // @@ -687,7 +687,7 @@ am_hal_gpio_fast_pinconfig(uint64_t ui64PinMask, #ifndef AM_HAL_DISABLE_API_VALIDATION if ( (ui64PinMask & ~(((uint64_t)1 << AM_HAL_GPIO_MAX_PADS) - 1)) || - (num_bits64(ui64PinMask) > 8) || + (popcount(ui64PinMask) > 8) || (bfGpioCfg.eGPOutcfg == AM_HAL_GPIO_PIN_OUTCFG_TRISTATE) ) { return AM_HAL_STATUS_INVALID_ARG; @@ -1078,6 +1078,52 @@ am_hal_gpio_interrupt_register(uint32_t ui32GPIONumber, } // am_hal_gpio_interrupt_register() +//***************************************************************************** +// +//! @brief Advanced GPIO interrupt service routine registration. +//! +//! @param ui32GPIONumber - GPIO number (0-49) to be registered. +//! +//! @param pfnHandler - Function pointer to the callback. +//! +//! @param pCtxt - context for the callback. +//! +//! @return Status. +//! Fails if pfnHandler is NULL or ui32GPIONumber > 49. +// +//***************************************************************************** +uint32_t +am_hal_gpio_interrupt_register_adv(uint32_t ui32GPIONumber, + am_hal_gpio_handler_adv_t pfnHandler, void *pCtxt) +{ +#ifndef AM_HAL_DISABLE_API_VALIDATION + // + // Check parameters + // + if ( ui32GPIONumber >= AM_HAL_GPIO_MAX_PADS ) + { + return AM_HAL_STATUS_OUT_OF_RANGE; + } + + if ( pfnHandler == NULL ) + { + return AM_HAL_STATUS_INVALID_ARG; + } +#endif // AM_HAL_DISABLE_API_VALIDATION + + // + // Store the handler function pointer. + // + gpio_ppfnHandlers[ui32GPIONumber] = (am_hal_gpio_handler_t)((uint32_t)pfnHandler & ~0x1); + gpio_pHandlerCtxt[ui32GPIONumber] = pCtxt; + + // + // Return the status. + // + return AM_HAL_STATUS_SUCCESS; + +} // am_hal_gpio_interrupt_register_adv() + //***************************************************************************** // // GPIO interrupt service routine. @@ -1150,7 +1196,15 @@ am_hal_gpio_interrupt_service(uint64_t ui64Status) // // If we found an interrupt handler routine, call it now. // - pfnHandler(); + if ((uint32_t)pfnHandler & 0x1) + { + pfnHandler(); + } + else + { + am_hal_gpio_handler_adv_t padvHandler = (am_hal_gpio_handler_adv_t)((uint32_t)pfnHandler | 0x1); + padvHandler(gpio_pHandlerCtxt[ui32Cnt + ui32FFS]); + } } else { diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_gpio.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_gpio.h index ff68aba..cd7b0ce 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_gpio.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_gpio.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -66,11 +66,127 @@ extern "C" // Maximum number of GPIOs on this device // #define AM_HAL_GPIO_MAX_PADS (50) +#define AM_HAL_GPIO_NUMWORDS ((AM_HAL_GPIO_MAX_PADS + 31) / 32) // -// Macro to assist with defining a GPIO bit given a GPIO number. +//! Macros to assist with defining a GPIO mask given a GPIO number. +//! +//! IMPORTANT: AM_HAL_GPIO_BIT(n) is DEPRECATED and is provided only for +//! backward compatibility. It is replaced with AM_HAL_GPIO_MASKBIT(). // -#define AM_HAL_GPIO_BIT(n) (((uint64_t) 0x1) << n) +#define AM_HAL_GPIO_BIT(n) (((uint64_t) 0x1) << n) /* DEPRECATED, PLEASE USE AM_HAL_GPIO_MASKBIT() */ + +//! +//! The following macros ensure forward compatibility with future SDK releases. +//! They should be used, in lieu of AM_HAL_GPIO_BIT(), when creating bitmasks +//! for GPIO interrupts. +//! AM_HAL_GPIO_MASKCREATE() +//! AM_HAL_GPIO_MASKBIT() +//! + +#define AM_HAL_GPIO_MASKCREATE(sMaskNm) uint64_t p##sMaskNm=0 +//! AM_HAL_GPIO_MASKCREATE() should be used before AM_HAL_GPIO_MASKBIT() to +//! ensure forward compatibility. In future releases it will allocate and +//! initialize a bitmask structure used in the various GPIO interrupt functions. +//! + +// Implented as an inline function below. +//#define AM_HAL_GPIO_MASKBIT(psMaskNm, n) (psMaskNm |= (((uint64_t) 0x1) << n)) +#define AM_HAL_GPIO_MASKBIT(psMaskNm, n) psMaskNm |= (((uint64_t) 0x1) << n) +//! AM_HAL_GPIO_MASKBIT(psMaskNm, n) +//! Support macros for use with AM_HAL_GPIO_MASKBIT(). +//! AM_HAL_GPIO_MASKCREATE() +//! AM_HAL_GPIO_MASKCLR() +//! +//! To set a single bit based on a pin number in an existing bitmask structure. +//! AM_HAL_GPIO_MASKBIT(pGpioIntMask, n) +//! where n is the desired GPIO bit number. +//! Note - this usage is analogous to the deprecated AM_HAL_GPIO_BIT(n). +//! + +#define AM_HAL_GPIO_MASKCLR(psMaskNm) +//! AM_HAL_GPIO_MASKCLR() +//! Clear an existing GpioIntMask bitmask structure. +//! Note that AM_HAL_GPIO_MASKCREATE() clears the bitmask struct on creation. +//! IMPORTANT - The AM_HAL_GPIO_MASKCLR() macro does not operate on any hardware +//! or register. It is used for initializing/clearing the memory allocated for +//! the bitmask structure. +//! +//! // Usage example for any Apollo device: +//! // Create a GPIO interrupt bitmask structure named GpioIntMask, initialize +//! // that structure, and create a ptr to that structure named pGpioIntMask. +//! // Then use that structure to pass a bitmask to the interrupt function. +//! AM_HAL_GPIO_MASKCREATE(GpioIntMask); +//! am_hal_gpio_interrupt_clear(AM_HAL_GPIO_MASKBIT(pGpioIntMask)); +//! + +//***************************************************************************** +//! +//! Structure for defining bitmasks used in the interrupt functions. +//! +//***************************************************************************** +typedef struct // Future use - not currently used for Apollo3. +{ + union + { + volatile uint32_t Msk[AM_HAL_GPIO_NUMWORDS]; + + struct + { + volatile uint32_t b0: 1; + volatile uint32_t b1: 1; + volatile uint32_t b2: 1; + volatile uint32_t b3: 1; + volatile uint32_t b4: 1; + volatile uint32_t b5: 1; + volatile uint32_t b6: 1; + volatile uint32_t b7: 1; + volatile uint32_t b8: 1; + volatile uint32_t b9: 1; + volatile uint32_t b10: 1; + volatile uint32_t b11: 1; + volatile uint32_t b12: 1; + volatile uint32_t b13: 1; + volatile uint32_t b14: 1; + volatile uint32_t b15: 1; + volatile uint32_t b16: 1; + volatile uint32_t b17: 1; + volatile uint32_t b18: 1; + volatile uint32_t b19: 1; + volatile uint32_t b20: 1; + volatile uint32_t b21: 1; + volatile uint32_t b22: 1; + volatile uint32_t b23: 1; + volatile uint32_t b24: 1; + volatile uint32_t b25: 1; + volatile uint32_t b26: 1; + volatile uint32_t b27: 1; + volatile uint32_t b28: 1; + volatile uint32_t b29: 1; + volatile uint32_t b30: 1; + volatile uint32_t b31: 1; + volatile uint32_t b32: 1; + volatile uint32_t b33: 1; + volatile uint32_t b34: 1; + volatile uint32_t b35: 1; + volatile uint32_t b36: 1; + volatile uint32_t b37: 1; + volatile uint32_t b38: 1; + volatile uint32_t b39: 1; + volatile uint32_t b40: 1; + volatile uint32_t b41: 1; + volatile uint32_t b42: 1; + volatile uint32_t b43: 1; + volatile uint32_t b44: 1; + volatile uint32_t b45: 1; + volatile uint32_t b46: 1; + volatile uint32_t b47: 1; + volatile uint32_t b48: 1; + volatile uint32_t b49: 1; + volatile uint32_t brsvd: 14; // Pad out to the next full word + } Msk_b; + } U; +} am_hal_gpio_mask_t; //***************************************************************************** //! @@ -338,6 +454,7 @@ extern const am_hal_gpio_pincfg_t g_AM_HAL_GPIO_OUTPUT_WITH_READ; // //***************************************************************************** typedef void (*am_hal_gpio_handler_t)(void); +typedef void (*am_hal_gpio_handler_adv_t)(void *); //***************************************************************************** // @@ -549,6 +666,23 @@ extern uint32_t am_hal_gpio_interrupt_status_get(bool bEnabledOnly, extern uint32_t am_hal_gpio_interrupt_register(uint32_t ui32GPIONumber, am_hal_gpio_handler_t pfnHandler); +//***************************************************************************** +// +//! @brief Advanced GPIO interrupt service routine registration. +//! +//! @param ui32GPIONumber - GPIO number (0-49) to be registered. +//! +//! @param pfnHandler - Function pointer to the callback. +//! +//! @param pCtxt - context for the callback. +//! +//! @return Status. +//! Fails if pfnHandler is NULL or ui32GPIONumber > 49. +// +//***************************************************************************** +extern uint32_t am_hal_gpio_interrupt_register_adv(uint32_t ui32GPIONumber, + am_hal_gpio_handler_adv_t pfnHandler, void *pCtxt); + //***************************************************************************** // // GPIO interrupt service routine. @@ -690,6 +824,11 @@ extern uint32_t am_hal_gpio_interrupt_service(uint64_t ui64Status); } +//***************************************************************************** +//! +//! @brief Fast GPIO helper macros. +//! +//***************************************************************************** // // Define Fast GPIO enable and disable. // diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_interrupt.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_interrupt.c index 7edfb74..d9808ab 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_interrupt.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_interrupt.c @@ -15,26 +15,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -47,7 +47,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_interrupt.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_interrupt.h index a2d91f3..ffe5122 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_interrupt.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_interrupt.h @@ -15,26 +15,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -47,7 +47,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_INTERRUPT_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_iom.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_iom.c index a9dbe38..92eebf8 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_iom.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_iom.c @@ -5,7 +5,7 @@ //! //! @brief Functions for interfacing with IO Master serial (SPI/I2C) modules. //! -//! @addtogroup IOM3 +//! @addtogroup iom3 IO Master (SPI/I2C) //! @ingroup apollo3hal //! @{ // @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -245,6 +245,10 @@ typedef struct uint32_t ui32NextHPIdx; uint32_t ui32LastHPIdxProcessed; am_hal_iom_dma_entry_t *pHPTransactions; + // Max pending transactions based on NB Buffer size + uint32_t ui32MaxPending; + // Number of back to back transactions with no callbacks + uint32_t ui32NumUnSolicited; #else uint32_t ui32NextIdx; am_hal_iom_txn_cmdlist_t *pTransactions; @@ -802,6 +806,7 @@ am_hal_iom_CQInit(void *pHandle, uint32_t ui32Length, pIOMState->pCmdQHdl = NULL; pIOMState->ui32MaxTransactions = 0; + pIOMState->ui32NumUnSolicited = 0; cqCfg.pCmdQBuf = pTCB; cqCfg.cmdQSize = ui32Length / 2; @@ -965,6 +970,11 @@ am_hal_iom_CQDisable(void *pHandle) return am_hal_cmdq_disable(pIOMState->pCmdQHdl); } // am_hal_iom_CQDisable() +static void iom_dummy_callback(void *pCallbackCtxt, uint32_t status) +{ + // Dummy - Do nothing +} + static void iom_seq_loopback(void *pCallbackCtxt, uint32_t status) { // Reset the state to allow serving callbacks for next set @@ -2264,6 +2274,15 @@ am_hal_iom_configure(void *pHandle, am_hal_iom_config_t *psConfig) pIOMState->pNBTxnBuf = psConfig->pNBTxnBuf; pIOMState->ui32NBTxnBufLength = psConfig->ui32NBTxnBufLength; +#if (AM_HAL_IOM_CQ == 1) + // Worst case minimum CQ entries that can be accomodated in provided buffer + // Need to account for the wrap + pIOMState->ui32MaxPending = ((pIOMState->ui32NBTxnBufLength - 8) * 4 / AM_HAL_IOM_CQ_ENTRY_SIZE); + if (pIOMState->ui32MaxPending > AM_HAL_IOM_MAX_PENDING_TRANSACTIONS) + { + pIOMState->ui32MaxPending = AM_HAL_IOM_MAX_PENDING_TRANSACTIONS; + } +#endif // Disable the DCX for (uint8_t i = 0; i <= AM_HAL_IOM_MAX_CS_SPI; i++) { @@ -2669,6 +2688,7 @@ am_hal_iom_nonblocking_transfer(void *pHandle, #if (AM_HAL_IOM_CQ == 1) + am_hal_iom_callback_t pfnCallback1 = pfnCallback; if (!pIOMState->pCmdQHdl) { return AM_HAL_STATUS_INVALID_OPERATION; @@ -2683,10 +2703,16 @@ am_hal_iom_nonblocking_transfer(void *pHandle, // Paused operations not allowed in block mode return AM_HAL_STATUS_INVALID_OPERATION; } + if ( !pfnCallback1 && !pIOMState->block && (pIOMState->eSeq == AM_HAL_IOM_SEQ_NONE) && + (pIOMState->ui32NumUnSolicited >= (pIOMState->ui32MaxPending / 2)) ) + { + // Need to schedule a dummy callback, to ensure ui32NumPendTransactions get updated in ISR + pfnCallback1 = iom_dummy_callback; + } // // DMA defaults to using the Command Queue // - ui32Status = am_hal_iom_CQAddTransaction(pHandle, psTransaction, pfnCallback, pCallbackCtxt); + ui32Status = am_hal_iom_CQAddTransaction(pHandle, psTransaction, pfnCallback1, pCallbackCtxt); if (ui32Status == AM_HAL_STATUS_SUCCESS) { @@ -2703,7 +2729,7 @@ am_hal_iom_nonblocking_transfer(void *pHandle, // // Register for interrupt only if there is a callback // - ui32Status = am_hal_cmdq_post_block(pIOMState->pCmdQHdl, pfnCallback); + ui32Status = am_hal_cmdq_post_block(pIOMState->pCmdQHdl, pfnCallback1); if (ui32Status == AM_HAL_STATUS_SUCCESS) { ui32NumPend = pIOMState->ui32NumPendTransactions++; @@ -2711,6 +2737,19 @@ am_hal_iom_nonblocking_transfer(void *pHandle, if (pfnCallback) { pIOMState->bAutonomous = false; + pIOMState->ui32NumUnSolicited = 0; + } + else + { + if (pfnCallback1) + { + // This implies we have already scheduled a dummy callback + pIOMState->ui32NumUnSolicited = 0; + } + else + { + pIOMState->ui32NumUnSolicited++; + } } if (0 == ui32NumPend) { @@ -2787,281 +2826,6 @@ am_hal_iom_nonblocking_transfer(void *pHandle, } // am_hal_iom_nonblocking_transfer() -//***************************************************************************** -// -//! @brief Perform a simple full-duplex transaction to the SPI interface. -//! -//! This function performs SPI full-duplex operation to a selected SPI device. -//! -//! @note The actual SPI and I2C interfaces operate in BYTES, not 32-bit words. -//! This means that you will need to byte-pack the \e pui32TxData array with the -//! data you intend to send over the interface. One easy way to do this is to -//! declare the array as a 32-bit integer array, but use an 8-bit pointer to -//! put your actual data into the array. If there are not enough bytes in your -//! desired message to completely fill the last 32-bit word, you may pad that -//! last word with bytes of any value. The IOM hardware will only read the -//! first \e ui32NumBytes in the \e pui32TxData array. -//! -//! @return returns AM_HAL_IOM_SUCCESS on successful execution. -// -//***************************************************************************** -uint32_t -am_hal_iom_spi_blocking_fullduplex(void *pHandle, - am_hal_iom_transfer_t *psTransaction) -{ - uint32_t ui32Cmd, ui32Offset, ui32OffsetCnt, ui32Dir, ui32Cont; - uint32_t ui32FifoRem, ui32FifoSiz; - uint32_t ui32Bytes; - uint32_t ui32RxBytes; - uint32_t ui32IntConfig; - uint32_t *pui32TxBuffer; - uint32_t *pui32RxBuffer; - am_hal_iom_state_t *pIOMState = (am_hal_iom_state_t*)pHandle; - uint32_t ui32Module; - uint32_t ui32Status = AM_HAL_STATUS_SUCCESS; - bool bCmdCmp = false; - uint32_t numWait = 0; - -#ifndef AM_HAL_DISABLE_API_VALIDATION - if ( !AM_HAL_IOM_CHK_HANDLE(pHandle) ) - { - return AM_HAL_STATUS_INVALID_HANDLE; - } - - if ( !psTransaction ) - { - return AM_HAL_STATUS_INVALID_ARG; - } - - if ( psTransaction->eDirection != AM_HAL_IOM_FULLDUPLEX ) - { - return AM_HAL_STATUS_INVALID_OPERATION; - } - - // - // Validate parameters - // - ui32Status = validate_transaction(pIOMState, psTransaction, true); - - if ( ui32Status != AM_HAL_STATUS_SUCCESS ) - { - return ui32Status; - } -#endif // AM_HAL_DISABLE_API_VALIDATION - - ui32Module = pIOMState->ui32Module; - ui32Offset = psTransaction->ui32Instr; - ui32OffsetCnt = psTransaction->ui32InstrLen; - ui32Bytes = psTransaction->ui32NumBytes; - ui32Dir = psTransaction->eDirection; - ui32Cont = psTransaction->bContinue ? 1 : 0; - pui32RxBuffer = psTransaction->pui32RxBuffer; - pui32TxBuffer = psTransaction->pui32TxBuffer; - - // - // Make sure any previous non-blocking transfers have completed. - // - ui32Status = am_hal_flash_delay_status_check(pIOMState->waitTimeout, - (uint32_t)&pIOMState->ui32NumPendTransactions, - 0xFFFFFFFF, - 0, - true); - if ( ui32Status != AM_HAL_STATUS_SUCCESS ) - { - return ui32Status; - } - - // - // Make sure any previous blocking transfer has been completed. - // This check is required to make sure previous transaction has cleared if the blocking call - // finished with a timeout - // - ui32Status = am_hal_flash_delay_status_check(pIOMState->waitTimeout, - (uint32_t)&IOMn(ui32Module)->STATUS, - (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk), - IOM0_STATUS_IDLEST_Msk, - true); - - if ( ui32Status != AM_HAL_STATUS_SUCCESS ) - { - return ui32Status; - } - - // - // Disable interrupts so that we don't get any undesired interrupts. - // - ui32IntConfig = IOMn(ui32Module)->INTEN; - - // - // Disable IOM interrupts as we'll be polling - // - IOMn(ui32Module)->INTEN = 0; - - // - // Clear interrupts - // - IOMn(ui32Module)->INTCLR = AM_HAL_IOM_INT_ALL; - - // - // Set the dev addr (either 7 or 10 bit as configured in MI2CCFG). - // - IOMn(ui32Module)->DEVCFG = psTransaction->uPeerInfo.ui32I2CDevAddr; - // CMDRPT register has been repurposed for DCX - // Set the DCX - IOMn(ui32Module)->DCX = pIOMState->dcx[psTransaction->uPeerInfo.ui32SpiChipSelect]; - - // - // Build the CMD value - // - - ui32Cmd = pIOMState->eInterfaceMode == AM_HAL_IOM_SPI_MODE ? - psTransaction->uPeerInfo.ui32SpiChipSelect : 0; - ui32Cmd = build_cmd(ui32Cmd, ui32Dir, ui32Cont, ui32Offset, ui32OffsetCnt, ui32Bytes); - - // - // Set the OFFSETHI register. - // - IOMn(ui32Module)->OFFSETHI = (uint16_t)(ui32Offset >> 8); - - // - // Set FULLDUPLEX mode - // - IOMn(ui32Module)->MSPICFG |= _VAL2FLD(IOM0_MSPICFG_FULLDUP, 1); - - // - // Start the transfer - // - IOMn(ui32Module)->CMD = ui32Cmd; - - ui32Bytes = psTransaction->ui32NumBytes; - ui32RxBytes = ui32Bytes; - - // - // Start a loop to catch the Rx data. - // - // - // Keep looping until we're out of bytes to send or command complete (error). - // - while (ui32Bytes || ui32RxBytes) - { - // - // Limit the wait to reasonable limit - instead of blocking forever - // - numWait = 0; - ui32FifoRem = IOMn(ui32Module)->FIFOPTR_b.FIFO0REM; - ui32FifoSiz = IOMn(ui32Module)->FIFOPTR_b.FIFO1SIZ; - - while ((ui32FifoRem < 4) && - (ui32FifoSiz < 4)) - { - if (numWait++ < AM_HAL_IOM_MAX_BLOCKING_WAIT) - { - if (bCmdCmp && (ui32RxBytes > ui32FifoSiz)) - { - // - // No more data expected. Get out of the loop - // - break; - } - am_hal_flash_delay( FLASH_CYCLES_US(1) ); - } - else - { - // - // We've waited long enough - get out! - // - break; - } - bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; - ui32FifoRem = IOMn(ui32Module)->FIFOPTR_b.FIFO0REM; - ui32FifoSiz = IOMn(ui32Module)->FIFOPTR_b.FIFO1SIZ; - } - if (bCmdCmp || ((ui32FifoRem < 4) && (ui32FifoSiz < 4))) - { - // - // Something went wrong - bail out - // - break; - } - - while ((ui32FifoRem >= 4) && ui32Bytes) - { - IOMn(ui32Module)->FIFOPUSH = *pui32TxBuffer++; - ui32FifoRem -= 4; - if (ui32Bytes >= 4) - { - ui32Bytes -= 4; - } - else - { - ui32Bytes = 0; - } - } - while ((ui32FifoSiz >= 4) && ui32RxBytes) - { - // - // Safe to read the FIFO, read 4 bytes - // - *pui32RxBuffer++ = IOMn(ui32Module)->FIFOPOP; -#if MANUAL_POP - IOMn(ui32Module)->FIFOPOP = 0x11111111; -#endif - ui32FifoSiz -= 4; - if (ui32RxBytes >= 4) - { - ui32RxBytes -= 4; - } - else - { - ui32RxBytes = 0; - } - } - } - - // - // Make sure transfer is completed. - // - ui32Status = am_hal_flash_delay_status_check(AM_HAL_IOM_MAX_BLOCKING_WAIT, - (uint32_t)&IOMn(ui32Module)->STATUS, - (IOM0_STATUS_IDLEST_Msk | IOM0_STATUS_CMDACT_Msk), - IOM0_STATUS_IDLEST_Msk, - true); - - if ( ui32Status != AM_HAL_STATUS_SUCCESS ) - { - return ui32Status; - } - - ui32Status = internal_iom_get_int_err(ui32Module, 0); - - if (ui32Status == AM_HAL_STATUS_SUCCESS) - { - if (ui32Bytes) - { - // Indicates transaction did not finish for some reason - ui32Status = AM_HAL_STATUS_FAIL; - } - } - else - { - // Do Error recovery - // Reset Submodule & FIFO - internal_iom_reset_on_error(pIOMState, IOMn(ui32Module)->INTSTAT); - } - - // - // Clear interrupts - // Re-enable IOM interrupts. - // - IOMn(ui32Module)->INTCLR = AM_HAL_IOM_INT_ALL; - IOMn(ui32Module)->INTEN = ui32IntConfig; - - // - // Return the status. - // - return ui32Status; - -} //***************************************************************************** // @@ -3125,16 +2889,6 @@ uint32_t am_hal_iom_control(void *pHandle, am_hal_iom_request_e eReq, void *pArg status = AM_HAL_STATUS_INVALID_ARG; } break; - case AM_HAL_IOM_REQ_SPI_FULLDUPLEX: - if (pArgs) - { - IOMn(ui32Module)->MSPICFG_b.FULLDUP = *((uint32_t *)pArgs); - } - else - { - status = AM_HAL_STATUS_INVALID_ARG; - } - break; case AM_HAL_IOM_REQ_SPI_RDTHRESH: if (pArgs) { @@ -3222,6 +2976,7 @@ uint32_t am_hal_iom_control(void *pHandle, am_hal_iom_request_e eReq, void *pArg pIOMState->ui32LastIdxProcessed = 0; pIOMState->ui32NumSeqTransactions = 0; pIOMState->ui32NumPendTransactions = 0; + pIOMState->ui32NumUnSolicited = 0; pIOMState->eSeq = eSeq; pIOMState->bAutonomous = true; } @@ -3450,6 +3205,7 @@ uint32_t am_hal_iom_control(void *pHandle, am_hal_iom_request_e eReq, void *pArg #if (AM_HAL_IOM_CQ == 1) am_hal_iom_cq_raw_t *pCqRaw = (am_hal_iom_cq_raw_t *)pArgs; am_hal_cmdq_entry_t *pCQBlock; + am_hal_iom_callback_t pfnCallback1; uint32_t ui32Critical = 0; uint32_t index; @@ -3491,10 +3247,17 @@ uint32_t am_hal_iom_control(void *pHandle, am_hal_iom_request_e eReq, void *pArg pCQBlock->address = (uint32_t)&IOMn(pIOMState->ui32Module)->CQSETCLEAR; pCQBlock->value = pCqRaw->ui32StatusSetClr; + pfnCallback1 = pCqRaw->pfnCallback; + if ( !pfnCallback1 && !pIOMState->block && (pIOMState->eSeq == AM_HAL_IOM_SEQ_NONE) && + (pIOMState->ui32NumUnSolicited >= (pIOMState->ui32MaxPending / 2)) ) + { + // Need to schedule a dummy callback, to ensure ui32NumPendTransactions get updated in ISR + pfnCallback1 = iom_dummy_callback; + } // // Store the callback function pointer. // - pIOMState->pfnCallback[index & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1)] = pCqRaw->pfnCallback; + pIOMState->pfnCallback[index & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1)] = pfnCallback1; pIOMState->pCallbackCtxt[index & (AM_HAL_IOM_MAX_PENDING_TRANSACTIONS - 1)] = pCqRaw->pCallbackCtxt; // @@ -3508,7 +3271,7 @@ uint32_t am_hal_iom_control(void *pHandle, am_hal_iom_request_e eReq, void *pArg // // Register for interrupt only if there is a callback // - status = am_hal_cmdq_post_block(pIOMState->pCmdQHdl, pCqRaw->pfnCallback); + status = am_hal_cmdq_post_block(pIOMState->pCmdQHdl, pfnCallback1); if (status == AM_HAL_STATUS_SUCCESS) { @@ -3517,6 +3280,19 @@ uint32_t am_hal_iom_control(void *pHandle, am_hal_iom_request_e eReq, void *pArg if (pCqRaw->pfnCallback) { pIOMState->bAutonomous = false; + pIOMState->ui32NumUnSolicited = 0; + } + else + { + if (pfnCallback1) + { + // This implies we have already scheduled a dummy callback + pIOMState->ui32NumUnSolicited = 0; + } + else + { + pIOMState->ui32NumUnSolicited++; + } } if (0 == ui32NumPend) { diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_iom.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_iom.h index 8098810..8f6fbcb 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_iom.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_iom.h @@ -5,7 +5,7 @@ //! @brief Functions for accessing and configuring the IO Master module //! //! @addtogroup hal Hardware Abstraction Layer (HAL) -//! @addtogroup iom IO Master (SPI/I2C) +//! @addtogroup iom3 IO Master (SPI/I2C) //! @ingroup hal //! @{ @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -55,9 +55,6 @@ #include "am_hal_status.h" #include "am_hal_sysctrl.h" -#ifdef __cplusplus // Patch -extern "C" { -#endif // End patch //***************************************************************************** // @@ -136,7 +133,7 @@ typedef enum #define AM_HAL_IOM_FIFO_SIZE_MAX 32 #define AM_HAL_IOM_MAX_OFFSETSIZE 3 #define AM_HAL_IOM_MAX_TXNSIZE_SPI 4095 -#define AM_HAL_IOM_MAX_TXNSIZE_I2C 255 +#define AM_HAL_IOM_MAX_TXNSIZE_I2C 4095 #define AM_HAL_IOM_MAX_CS_SPI 3 //***************************************************************************** @@ -163,7 +160,6 @@ typedef enum { AM_HAL_IOM_TX, AM_HAL_IOM_RX, - AM_HAL_IOM_FULLDUPLEX, // Not supported currently - TODO } am_hal_iom_dir_e; // @@ -400,8 +396,6 @@ typedef enum // Pass uint32_t as pArgs AM_HAL_IOM_REQ_SPI_LSB, // Pass uint32_t as pArgs - AM_HAL_IOM_REQ_SPI_FULLDUPLEX, - // Pass uint32_t as pArgs AM_HAL_IOM_REQ_SPI_RDTHRESH, // Pass uint32_t as pArgs AM_HAL_IOM_REQ_SPI_WRTHRESH, @@ -510,6 +504,11 @@ union \ // #define AM_HAL_IOM_INT_ERR (AM_HAL_IOM_INT_SWERR | AM_HAL_IOM_INT_I2CARBERR | AM_HAL_IOM_INT_INTERR | AM_HAL_IOM_INT_NAK) +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // //! @brief IOM initialization function @@ -828,15 +827,14 @@ uint32_t am_hal_iom_highprio_transfer(void *pHandle, void *pCallbackCtxt); +#ifdef __cplusplus +} +#endif + //***************************************************************************** // // End Doxygen group. //! @} // //***************************************************************************** - -#ifdef __cplusplus // Patch -} -#endif // End patch - #endif // AM_HAL_IOM_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ios.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ios.c index 359a3db..a369598 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ios.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ios.c @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ios.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ios.h index fb62f0d..9020ec3 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ios.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_ios.h @@ -5,34 +5,34 @@ //! //! @brief Functions for interfacing with the IO Slave module //! -//! @addtogroup ios2 IO Slave (SPI/I2C) -//! @ingroup apollo2hal +//! @addtogroup ios3 IO Slave (SPI/I2C) +//! @ingroup apollo3hal //! @{ // //***************************************************************************** //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_IOS_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_itm.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_itm.c index 07cc99b..a9726cf 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_itm.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_itm.c @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_itm.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_itm.h index 7605df0..9bb6c00 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_itm.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_itm.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mcuctrl.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mcuctrl.c index ea17a59..801f266 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mcuctrl.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mcuctrl.c @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mcuctrl.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mcuctrl.h index cf6817c..c27ceb9 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mcuctrl.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mcuctrl.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_MCUCTRL_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mspi.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mspi.c index f250ae2..2247091 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mspi.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mspi.c @@ -5,7 +5,7 @@ //! //! @brief Functions for interfacing with the MSPI. //! -//! @addtogroup mcuctrl3 Multi-bit SPI (MSPI) +//! @addtogroup mspi3 Multi-bit SPI (MSPI) //! @ingroup apollo3hal //! @{ // @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -78,6 +78,24 @@ // Max time to wait when attempting to pause the command queue #define AM_HAL_MSPI_MAX_PAUSE_DELAY (100*1000) // 100ms +// +// MSPI interface mode and chip enable selection. +// This is an internal extension to am_hal_mspi_device_e +// +typedef enum +{ + AM_HAL_MSPI_FLASH_DUAL_CE0_1_1_2 = AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL + 1, + AM_HAL_MSPI_FLASH_DUAL_CE1_1_1_2, + AM_HAL_MSPI_FLASH_DUAL_CE0_1_2_2, + AM_HAL_MSPI_FLASH_DUAL_CE1_1_2_2, + AM_HAL_MSPI_FLASH_QUAD_CE0_1_1_4, + AM_HAL_MSPI_FLASH_QUAD_CE1_1_1_4, + AM_HAL_MSPI_FLASH_QUAD_CE0_1_4_4, + AM_HAL_MSPI_FLASH_QUAD_CE1_1_4_4, + AM_HAL_MSPI_FLASH_SERIAL_CE0_3WIRE, + AM_HAL_MSPI_FLASH_SERIAL_CE1_3WIRE, +} mspi_device_e; + // // Command Queue entry structure for DMA transfer. // @@ -257,6 +275,10 @@ typedef struct uint32_t ui32NextHPIdx; uint32_t ui32LastHPIdxProcessed; am_hal_mspi_dma_entry_t *pHPTransactions; + // Max pending transactions based on NB Buffer size + uint32_t ui32MaxPending; + // Number of back to back transactions with no callbacks + uint32_t ui32NumUnSolicited; #else uint32_t ui32MaxTransactions; uint32_t ui32NextIdx; @@ -989,57 +1011,280 @@ mspi_add_hp_transaction(void *pHandle, //***************************************************************************** // -//! @brief Configure the internal PADs. +//! @brief Determine the virtual device configuration //! //! @param handle - handle for the interface. //! @param eMSPIDevice - external device configuration for MSPI -//! This function configures the internal pads based on the external device -//! configuration. //! +//! @return virtual device value. +// +// +//***************************************************************************** +// +// MSPI interface mode and chip enable selection. +// This is an internal extension to am_hal_mspi_device_e +// +static uint32_t +mspi_virtual_device(mspi_device_info_t *pMSPIDeviceInfo, uint32_t *pVirtDevice) +{ + // + // Check that the Device Config is in the proper range. + // + if (pMSPIDeviceInfo->eDeviceConfig > AM_HAL_MSPI_FLASH_MAX) + { + return AM_HAL_STATUS_INVALID_ARG; + } + + switch(pMSPIDeviceInfo->eXipMixedMode) + { + case AM_HAL_MSPI_XIPMIXED_NORMAL: + { + // if Serial CE0 or CE1, check for separate I/O. + if ( (AM_HAL_MSPI_FLASH_SERIAL_CE0 == pMSPIDeviceInfo->eDeviceConfig) || + (AM_HAL_MSPI_FLASH_SERIAL_CE1 == pMSPIDeviceInfo->eDeviceConfig) ) + { + // if serial mode, but not separate I/O , then calculate 3WIRE mode value. + if (!pMSPIDeviceInfo->bSeparateIO) + { + *pVirtDevice = (uint32_t)pMSPIDeviceInfo->eDeviceConfig + + AM_HAL_MSPI_FLASH_SERIAL_CE0_3WIRE - + AM_HAL_MSPI_FLASH_SERIAL_CE0; + return AM_HAL_STATUS_SUCCESS; + } + else + { + // Otherwise return the original eDeviceConfig. + *pVirtDevice = pMSPIDeviceInfo->eDeviceConfig; + return AM_HAL_STATUS_SUCCESS; + } + } + else + { + // Otherwise return the original eDeviceConfig. + *pVirtDevice = pMSPIDeviceInfo->eDeviceConfig; + return AM_HAL_STATUS_SUCCESS; + } + } + break; + + case AM_HAL_MSPI_XIPMIXED_D2: + if ( (AM_HAL_MSPI_FLASH_SERIAL_CE0 == pMSPIDeviceInfo->eDeviceConfig) || + (AM_HAL_MSPI_FLASH_SERIAL_CE1 == pMSPIDeviceInfo->eDeviceConfig) ) + { + *pVirtDevice = (uint32_t)pMSPIDeviceInfo->eDeviceConfig + + AM_HAL_MSPI_FLASH_DUAL_CE0_1_1_2 - + AM_HAL_MSPI_FLASH_SERIAL_CE0; + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + case AM_HAL_MSPI_XIPMIXED_AD2: + if ( (AM_HAL_MSPI_FLASH_SERIAL_CE0 == pMSPIDeviceInfo->eDeviceConfig) || + (AM_HAL_MSPI_FLASH_SERIAL_CE1 == pMSPIDeviceInfo->eDeviceConfig) ) + { + *pVirtDevice = (uint32_t)pMSPIDeviceInfo->eDeviceConfig + + AM_HAL_MSPI_FLASH_DUAL_CE0_1_2_2 - + AM_HAL_MSPI_FLASH_SERIAL_CE0; + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + case AM_HAL_MSPI_XIPMIXED_D4: + if ( (AM_HAL_MSPI_FLASH_SERIAL_CE0 == pMSPIDeviceInfo->eDeviceConfig) || + (AM_HAL_MSPI_FLASH_SERIAL_CE1 == pMSPIDeviceInfo->eDeviceConfig) ) + { + *pVirtDevice = (uint32_t)pMSPIDeviceInfo->eDeviceConfig + + AM_HAL_MSPI_FLASH_QUAD_CE0_1_1_4 - + AM_HAL_MSPI_FLASH_SERIAL_CE0; + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + case AM_HAL_MSPI_XIPMIXED_AD4: + if ( (AM_HAL_MSPI_FLASH_SERIAL_CE0 == pMSPIDeviceInfo->eDeviceConfig) || + (AM_HAL_MSPI_FLASH_SERIAL_CE1 == pMSPIDeviceInfo->eDeviceConfig) ) + { + *pVirtDevice = (uint32_t)pMSPIDeviceInfo->eDeviceConfig + + AM_HAL_MSPI_FLASH_QUAD_CE0_1_4_4 - + AM_HAL_MSPI_FLASH_SERIAL_CE0; + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + break; + + default: + return AM_HAL_STATUS_INVALID_ARG; + } +} + + //***************************************************************************** +// +//! @brief Configure the device config, seperate I/O, mixed mode, and internal +//! PADs based on the virtual device configuration passed in. +//! +//! @param handle - handle for the interface. +//! @param eMSPIDevice - external device configuration for MSPI //! //! @return HAL status of the operation. // // //***************************************************************************** static uint32_t -mspi_pad_configure(void *pHandle, - am_hal_mspi_device_e eMSPIDevice) +mspi_device_configure(void *pHandle, uint32_t ui32MSPIDevice) { am_hal_mspi_state_t *pMSPIState = (am_hal_mspi_state_t *)pHandle; uint32_t ui32Module = pMSPIState->ui32Module; - // MSPI PADOUTEN: - // Bit 0 - 7 : DS0 - DS7 - // Bit 8 : CLK - switch ( eMSPIDevice ) + switch ( ui32MSPIDevice ) { case AM_HAL_MSPI_FLASH_SERIAL_CE0: - case AM_HAL_MSPI_FLASH_DUAL_CE0: - MSPIn(ui32Module)->PADCFG = 0; - MSPIn(ui32Module)->PADOUTEN = 0x103; + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 1; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x103; break; case AM_HAL_MSPI_FLASH_SERIAL_CE1: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 1; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x130; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_DUAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x103; + break; case AM_HAL_MSPI_FLASH_DUAL_CE1: - MSPIn(ui32Module)->PADCFG = 0; - MSPIn(ui32Module)->PADOUTEN = 0x130; + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_DUAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x130; break; case AM_HAL_MSPI_FLASH_QUAD_CE0: - MSPIn(ui32Module)->PADCFG = 0; - MSPIn(ui32Module)->PADOUTEN = 0x10F; + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_QUAD0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x10F; break; case AM_HAL_MSPI_FLASH_QUAD_CE1: - MSPIn(ui32Module)->PADCFG = 0; - MSPIn(ui32Module)->PADOUTEN = 0x1F0; + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_QUAD1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x1F0; break; case AM_HAL_MSPI_FLASH_OCTAL_CE0: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_OCTAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x1FF; + break; case AM_HAL_MSPI_FLASH_OCTAL_CE1: - case AM_HAL_MSPI_FLASH_QUADPAIRED: - MSPIn(ui32Module)->PADCFG = 0; - MSPIn(ui32Module)->PADOUTEN = 0x1FF; + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_OCTAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x1FF; break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: - MSPIn(ui32Module)->PADCFG = 0; - MSPIn(ui32Module)->PADOUTEN = 0x133; + return AM_HAL_STATUS_INVALID_ARG; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0_1_1_2: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 1; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x103; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1_1_1_2: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 1; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x130; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0_1_2_2: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 3; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x103; + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1_1_2_2: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 3; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x130; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0_1_1_4: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 5; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x10F; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1_1_1_4: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 5; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x1F0; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0_1_4_4: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 7; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x10F; + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1_1_4_4: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 7; + MSPIn(ui32Module)->PADCFG = 0; + MSPIn(ui32Module)->PADOUTEN = 0x1F0; + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE0_3WIRE: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL0; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + // Enable both D0 and D1 - as D1 might be getting used for DCX + MSPIn(ui32Module)->PADOUTEN = 0x103; + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1_3WIRE: + MSPIn(ui32Module)->CFG_b.DEVCFG = MSPI_CFG_DEVCFG_SERIAL1; + MSPIn(ui32Module)->CFG_b.SEPIO = 0; + MSPIn(ui32Module)->FLASH_b.XIPMIXED = 0; + MSPIn(ui32Module)->PADCFG = 0; + // Enable both D0 and D1 - as D1 might be getting used for DCX + MSPIn(ui32Module)->PADOUTEN = 0x130; + break; + default: break; } @@ -1049,6 +1294,11 @@ mspi_pad_configure(void *pHandle, return AM_HAL_STATUS_SUCCESS; } +static void mspi_dummy_callback(void *pCallbackCtxt, uint32_t status) +{ + // Dummy - Do nothing +} + static void mspi_seq_loopback(void *pCallbackCtxt, uint32_t status) { // Reset the state to allow serving callbacks for next set @@ -1242,18 +1492,6 @@ am_hal_mspi_device_configure(void *pHandle, #endif // AM_HAL_DISABLE_API_VALIDATION ui32Module = pMSPIState->ui32Module; - // - // Set the external flash device configuration. - // - ui32Config = _VAL2FLD(MSPI_CFG_DEVCFG, pConfig->eDeviceConfig); - - // - // If separate MOSI/MISO, then configure. - // - if ( pConfig->bSeparateIO ) - { - ui32Config |= _VAL2FLD(MSPI_CFG_SEPIO, 1); - } // // Set the clock polarity and phase based on SPI mode. @@ -1322,7 +1560,7 @@ am_hal_mspi_device_configure(void *pHandle, // // Set the APBCLK for continuous operation. // - MSPIn(ui32Module)->MSPICFG_b.APBCLK = 0; + MSPIn(ui32Module)->MSPICFG_b.APBCLK = 1; // // Reset the register storage for next write. @@ -1373,11 +1611,6 @@ am_hal_mspi_device_configure(void *pHandle, // ui32Config |= _VAL2FLD(MSPI_FLASH_WRITEINSTR, pConfig->ui8WriteInstr); - // - // Set the XIPMIXED mode - // - ui32Config |= _VAL2FLD(MSPI_FLASH_XIPMIXED, pConfig->eXipMixedMode); - // // Set the configuration in the MSPI peripheral. // @@ -1393,7 +1626,15 @@ am_hal_mspi_device_configure(void *pHandle, // set the DMATHRESH MSPIn(ui32Module)->DMATHRESH = AM_HAL_MSPI_DEFAULT_BURST_COUNT >> 2; + // Worst case minimum CQ entries that can be accomodated in provided buffer + // Need to account for the wrap + g_MSPIState[ui32Module].ui32MaxPending = ((pConfig->ui32TCBSize - 8) * 4 / AM_HAL_MSPI_CQ_ENTRY_SIZE); + if (g_MSPIState[ui32Module].ui32MaxPending > AM_HAL_MSPI_MAX_CQ_ENTRIES) + { + g_MSPIState[ui32Module].ui32MaxPending = AM_HAL_MSPI_MAX_CQ_ENTRIES; + } } + // // Reset the register storage for next write. // @@ -1411,10 +1652,34 @@ am_hal_mspi_device_configure(void *pHandle, // MSPIn(ui32Module)->MSPICFG_b.IOMSEL = 7; - // - // Configure the MSPI PADs. - // - mspi_pad_configure(pHandle, pConfig->eDeviceConfig); + { + mspi_device_info_t MSPIDeviceInfo; + uint32_t ui32DeviceConfig; + uint32_t ui32Status; + + // + // Determine the virtual device configuration. + // + MSPIDeviceInfo.eDeviceConfig = pConfig->eDeviceConfig; + MSPIDeviceInfo.eXipMixedMode = pConfig->eXipMixedMode; + MSPIDeviceInfo.bSeparateIO = pConfig->bSeparateIO; + ui32Status = mspi_virtual_device(&MSPIDeviceInfo, &ui32DeviceConfig); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + + // + // Configure the MSPI for a specific device configuration. + // This function sets the following registers/fields: + // CFG.DEVCFG + // CFG.SEPIO + // FLASH.XIPMIXED + // PADCFG + // PADOUTEN + // + mspi_device_configure(pHandle, ui32DeviceConfig); + } // // Set the default endianess for the FIFO. @@ -1477,6 +1742,7 @@ am_hal_mspi_enable(void *pHandle) pMSPIState->eSeq = AM_HAL_MSPI_SEQ_NONE; pMSPIState->ui32NumTransactions = 0; pMSPIState->bAutonomous = true; + pMSPIState->ui32NumUnSolicited = 0; #else // Use the buffer for software queuing for DMA @@ -1622,17 +1888,45 @@ uint32_t am_hal_mspi_control(void *pHandle, MSPIn(ui32Module)->FLASH_b.XIPEN = 1; break; - case AM_HAL_MSPI_REQ_XIP_MIXED_MODE: + case AM_HAL_MSPI_REQ_DEVICE_CONFIG: #ifndef AM_HAL_DISABLE_API_VALIDATION if (!pConfig) { - return AM_HAL_STATUS_INVALID_ARG; + return AM_HAL_STATUS_INVALID_ARG; + } + if (pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_IN_USE; } #endif // AM_HAL_DISABLE_API_VALIDATION - // - // Set XIPMIXED Mode - // - MSPIn(ui32Module)->FLASH_b.XIPMIXED = *((uint32_t *)pConfig); + { + uint32_t ui32DeviceConfig; + uint32_t ui32Status; + + // + // Determine the virtual device configuration. + // + ui32Status = mspi_virtual_device((mspi_device_info_t *)pConfig, &ui32DeviceConfig); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + + // + // Configure the MSPI for a specific device configuration. + // This function sets the following registers/fields: + // CFG.DEVCFG + // CFG.SEPIO + // FLASH.XIPMIXED + // PADCFG + // PADOUTEN + // + ui32Status = mspi_device_configure(pHandle, ui32DeviceConfig); + if (AM_HAL_STATUS_SUCCESS != ui32Status) + { + return ui32Status; + } + } break; case AM_HAL_MSPI_REQ_PAUSE: @@ -1699,6 +1993,7 @@ uint32_t am_hal_mspi_control(void *pHandle, pMSPIState->ui32NumCQEntries = 0; pMSPIState->eSeq = eSeq; pMSPIState->bAutonomous = true; + pMSPIState->ui32NumUnSolicited = 0; } break; } @@ -1923,6 +2218,7 @@ uint32_t am_hal_mspi_control(void *pHandle, uint32_t ui32Critical = 0; uint32_t ui32NumPend; uint32_t index; + am_hal_mspi_callback_t pfnCallback1; #ifndef AM_HAL_DISABLE_API_VALIDATION if (!pCqRaw) { @@ -1961,10 +2257,18 @@ uint32_t am_hal_mspi_control(void *pHandle, pCQBlock++; pCQBlock->address = (uint32_t)&MSPIn(ui32Module)->CQSETCLEAR; pCQBlock->value = pCqRaw->ui32StatusSetClr; + + pfnCallback1 = pCqRaw->pfnCallback; + if ( !pfnCallback1 && !pMSPIState->block && (pMSPIState->eSeq == AM_HAL_MSPI_SEQ_NONE) && + (pMSPIState->ui32NumUnSolicited >= (pMSPIState->ui32MaxPending / 2)) ) + { + // Need to schedule a dummy callback, to ensure ui32NumCQEntries get updated in ISR + pfnCallback1 = mspi_dummy_callback; + } // // Store the callback function pointer. // - pMSPIState->pfnCallback[index & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1)] = pCqRaw->pfnCallback; + pMSPIState->pfnCallback[index & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1)] = pfnCallback1; pMSPIState->pCallbackCtxt[index & (AM_HAL_MSPI_MAX_CQ_ENTRIES - 1)] = pCqRaw->pCallbackCtxt; // @@ -1979,7 +2283,7 @@ uint32_t am_hal_mspi_control(void *pHandle, // Post the transaction to the CQ. // Register for interrupt only if there is a callback // - ui32Status = am_hal_cmdq_post_block(pMSPIState->CQ.pCmdQHdl, pCqRaw->pfnCallback); + ui32Status = am_hal_cmdq_post_block(pMSPIState->CQ.pCmdQHdl, pfnCallback1); if (AM_HAL_STATUS_SUCCESS != ui32Status) { // @@ -1996,6 +2300,19 @@ uint32_t am_hal_mspi_control(void *pHandle, if (pCqRaw->pfnCallback) { pMSPIState->bAutonomous = false; + pMSPIState->ui32NumUnSolicited = 0; + } + else + { + if (pfnCallback1) + { + // This implies we have already scheduled a dummy callback + pMSPIState->ui32NumUnSolicited = 0; + } + else + { + pMSPIState->ui32NumUnSolicited++; + } } // // End the critical section. @@ -2081,7 +2398,13 @@ uint32_t am_hal_mspi_blocking_transfer(void *pHandle, { return AM_HAL_STATUS_INVALID_HANDLE; } - + // + // Check that the interface is enabled. + // + if (!pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } #endif // AM_HAL_DISABLE_API_VALIDATION ui32Module = pMSPIState->ui32Module; @@ -2246,6 +2569,13 @@ uint32_t am_hal_mspi_nonblocking_transfer(void *pHandle, { return AM_HAL_STATUS_INVALID_OPERATION; } + // + // Check that the interface is enabled. + // + if (!pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } #if MSPI_USE_CQ #if 0 // We should be able to queue up the CQ even if high priority transaction is in progress @@ -2263,10 +2593,17 @@ uint32_t am_hal_mspi_nonblocking_transfer(void *pHandle, #endif // AM_HAL_DISABLE_API_VALIDATION #if MSPI_USE_CQ + am_hal_mspi_callback_t pfnCallback1 = pfnCallback; + if ( !pfnCallback1 && !pMSPIState->block && (pMSPIState->eSeq == AM_HAL_MSPI_SEQ_NONE) && + (pMSPIState->ui32NumUnSolicited >= (pMSPIState->ui32MaxPending / 2)) ) + { + // Need to schedule a dummy callback, to ensure ui32NumCQEntries get updated in ISR + pfnCallback1 = mspi_dummy_callback; + } // // DMA defaults to using the Command Queue // - ui32Status = mspi_cq_add_transaction(pHandle, pTransfer, eMode, pfnCallback, pCallbackCtxt); + ui32Status = mspi_cq_add_transaction(pHandle, pTransfer, eMode, pfnCallback1, pCallbackCtxt); if (AM_HAL_STATUS_SUCCESS != ui32Status) { @@ -2285,7 +2622,7 @@ uint32_t am_hal_mspi_nonblocking_transfer(void *pHandle, // // Post the transaction to the CQ. // - ui32Status = am_hal_cmdq_post_block(pMSPIState->CQ.pCmdQHdl, pfnCallback); + ui32Status = am_hal_cmdq_post_block(pMSPIState->CQ.pCmdQHdl, pfnCallback1); if (AM_HAL_STATUS_SUCCESS != ui32Status) { @@ -2303,6 +2640,19 @@ uint32_t am_hal_mspi_nonblocking_transfer(void *pHandle, if (pfnCallback) { pMSPIState->bAutonomous = false; + pMSPIState->ui32NumUnSolicited = 0; + } + else + { + if (pfnCallback1) + { + // This implies we have already scheduled a dummy callback + pMSPIState->ui32NumUnSolicited = 0; + } + else + { + pMSPIState->ui32NumUnSolicited++; + } } // // End the critical section. @@ -2942,6 +3292,13 @@ uint32_t am_hal_mspi_power_control(void *pHandle, case AM_HAL_SYSCTRL_NORMALSLEEP: case AM_HAL_SYSCTRL_DEEPSLEEP: + // Make sure MPSI is not active currently + if (pMSPIState->prefix.s.bEnable && + ((MSPIn(pMSPIState->ui32Module)->DMASTAT_b.DMATIP) || + pMSPIState->ui32NumHPPendingEntries)) + { + return AM_HAL_STATUS_IN_USE; + } if (bRetainState) { // @@ -2968,6 +3325,23 @@ uint32_t am_hal_mspi_power_control(void *pHandle, pMSPIState->registerState.bValid = true; } + // + // Disable all the interrupts. + // + am_hal_mspi_interrupt_disable(pHandle, MSPI_INTEN_SCRERR_Msk | + MSPI_INTEN_CQERR_Msk | + MSPI_INTEN_CQPAUSED_Msk | + MSPI_INTEN_CQUPD_Msk | + MSPI_INTEN_CQCMP_Msk | + MSPI_INTEN_DERR_Msk | + MSPI_INTEN_DCMP_Msk | + MSPI_INTEN_RXF_Msk | + MSPI_INTEN_RXO_Msk | + MSPI_INTEN_RXU_Msk | + MSPI_INTEN_TXO_Msk | + MSPI_INTEN_TXE_Msk | + MSPI_INTEN_CMDCMP_Msk); + // // Disable power control. // @@ -3020,6 +3394,13 @@ uint32_t am_hal_mspi_highprio_transfer(void *pHandle, { return AM_HAL_STATUS_INVALID_ARG; } + // + // Check that the interface is enabled. + // + if (!pMSPIState->prefix.s.bEnable) + { + return AM_HAL_STATUS_INVALID_OPERATION; + } #endif // AM_HAL_DISABLE_API_VALIDATION #if MSPI_USE_CQ diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mspi.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mspi.h index d6d8159..c9d8290 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mspi.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_mspi.h @@ -5,7 +5,7 @@ //! //! @brief Functions for accessing and configuring the MSPI. //! -//! @addtogroup mspi3 MSPI (Multi-bit SPI) +//! @addtogroup mspi3 Multi-bit SPI (MSPI) //! @ingroup apollo3hal //! @{ // @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_MSPI_H @@ -183,16 +183,17 @@ extern "C" // typedef enum { - AM_HAL_MSPI_FLASH_SERIAL_CE0 = 0x01, - AM_HAL_MSPI_FLASH_SERIAL_CE1 = 0x02, - AM_HAL_MSPI_FLASH_DUAL_CE0 = 0x05, - AM_HAL_MSPI_FLASH_DUAL_CE1 = 0x06, - AM_HAL_MSPI_FLASH_QUAD_CE0 = 0x09, - AM_HAL_MSPI_FLASH_QUAD_CE1 = 0x0A, - AM_HAL_MSPI_FLASH_OCTAL_CE0 = 0x0D, - AM_HAL_MSPI_FLASH_OCTAL_CE1 = 0x0E, - AM_HAL_MSPI_FLASH_QUADPAIRED = 0x0F, - AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL = 0x03 + AM_HAL_MSPI_FLASH_SERIAL_CE0, + AM_HAL_MSPI_FLASH_SERIAL_CE1, + AM_HAL_MSPI_FLASH_DUAL_CE0, + AM_HAL_MSPI_FLASH_DUAL_CE1, + AM_HAL_MSPI_FLASH_QUAD_CE0, + AM_HAL_MSPI_FLASH_QUAD_CE1, + AM_HAL_MSPI_FLASH_OCTAL_CE0, + AM_HAL_MSPI_FLASH_OCTAL_CE1, + AM_HAL_MSPI_FLASH_QUADPAIRED, + AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL, + AM_HAL_MSPI_FLASH_MAX = AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL } am_hal_mspi_device_e; // @@ -273,8 +274,8 @@ extern "C" AM_HAL_MSPI_REQ_XIP_DIS, // pConfig N/A AM_HAL_MSPI_REQ_XIP_EN, - // Pass uint32_t as pConfig - AM_HAL_MSPI_REQ_XIP_MIXED_MODE, + // Pass mspi_device_info_t as pConfig + AM_HAL_MSPI_REQ_DEVICE_CONFIG, // Pause the CQ gracefully AM_HAL_MSPI_REQ_PAUSE, // Unpause the CQ @@ -387,6 +388,21 @@ extern "C" } am_hal_mspi_dev_config_t; + // + // MSPI configuration record for determining virtual device configuration. + // + typedef struct + { + //! External Flash Device configuration + am_hal_mspi_device_e eDeviceConfig; + + //! XIPMIXED configure + am_hal_mspi_xipmixed_mode_e eXipMixedMode; + + //! Separate MOSI/MISO + bool bSeparateIO; + + } mspi_device_info_t; // // MSPI Capabilities structure // diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pdm.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pdm.c index b407af5..ade3c63 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pdm.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pdm.c @@ -12,26 +12,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -44,7 +44,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -146,6 +146,13 @@ am_hal_pdm_state_t; //***************************************************************************** am_hal_pdm_state_t g_am_hal_pdm_states[AM_REG_PDM_NUM_MODULES]; +//***************************************************************************** +// +// Static function definitions. +// +//***************************************************************************** +static uint32_t find_dma_threshold(uint32_t ui32TotalCount); + //***************************************************************************** // // Initialization function. @@ -239,8 +246,8 @@ am_hal_pdm_power_control(void *pHandle, uint32_t ui32Module = pState->ui32Module; am_hal_pwrctrl_periph_e ePDMPowerModule = ((am_hal_pwrctrl_periph_e) - (AM_HAL_PWRCTRL_PERIPH_PDM + - ui32Module)); + (AM_HAL_PWRCTRL_PERIPH_PDM + + ui32Module)); // // Check the handle. // @@ -400,40 +407,63 @@ am_hal_pdm_disable(void *pHandle) //***************************************************************************** // -// Starts a DMA transaction from the PDM directly to SRAM +// Given the total number of bytes in a DMA transaction, find a reasonable +// threshold setting. // //***************************************************************************** -uint32_t -am_hal_pdm_dma_start(void *pHandle, am_hal_pdm_transfer_t *pDmaCfg) +static uint32_t +find_dma_threshold(uint32_t ui32TotalCount) { - am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; - uint32_t ui32Module = pState->ui32Module; - AM_HAL_PDM_HANDLE_CHECK(pHandle); - // - // Calculate a FIFO threshold that will work. The PDM DMA hardware can only - // perform transactions where the total count is an integer multiple of the - // threshold value. We will loop here to try to find a threshold value and - // an integer multiple (ui32NumReloads) that will fit the total count the - // user asked for. + // Start with a threshold value of 24, and search downward for values that + // fit our criteria. // - uint32_t ui32Threshold = 0; - uint32_t ui32NumReloads = 1; + uint32_t ui32Threshold; + uint32_t ui32Minimum = AM_HAL_PDM_DMA_THRESHOLD_MIN; - for (ui32NumReloads = 1; ui32NumReloads < pDmaCfg->ui32TotalCount; ui32NumReloads++) + for ( ui32Threshold = 24; ui32Threshold >= ui32Minimum; ui32Threshold -= 4 ) { // - // Check to make sure the total count is evenly divisible into chunks - // that are smaller than the maximum threshold size. + // With our loop parameters, we've already guaranteed that the + // threshold will be no higher than 24, and that it will be divisible + // by 4. The only remaining requirement is that ui32TotalCount must + // also be divisible by the threshold. // - if (((pDmaCfg->ui32TotalCount % ui32NumReloads) == 0) && - ((pDmaCfg->ui32TotalCount / ui32NumReloads) <= 0x1F)) + if ((ui32TotalCount % ui32Threshold) == 0) { - ui32Threshold = pDmaCfg->ui32TotalCount / ui32NumReloads; break; } } + // + // If we found an appropriate value, we'll return it here. Otherwise, we + // will return zero. + // + if (ui32Threshold < ui32Minimum) + { + ui32Threshold = 0; + } + + return ui32Threshold; +} + +//***************************************************************************** +// +// Starts a DMA transaction from the PDM directly to SRAM +// +//***************************************************************************** +uint32_t +am_hal_pdm_dma_start(void *pHandle, am_hal_pdm_transfer_t *pDmaCfg) +{ + am_hal_pdm_state_t *pState = (am_hal_pdm_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + AM_HAL_PDM_HANDLE_CHECK(pHandle); + + // + // Find an appropriate threshold size for this transfer. + // + uint32_t ui32Threshold = find_dma_threshold(pDmaCfg->ui32TotalCount); + // // If we didn't find a threshold that will work, throw an error. // @@ -463,16 +493,6 @@ am_hal_pdm_dma_start(void *pHandle, am_hal_pdm_transfer_t *pDmaCfg) // PDMn(ui32Module)->DMACFG_b.DMAEN = PDM_DMACFG_DMAEN_EN; -// // -// // Reset the voice module. -// // -// PDMn(ui32Module)->VCFG_b.RSTB = PDM_VCFG_RSTB_RESET; -// -// delay_us(100); -// -// PDMn(ui32Module)->VCFG_b.RSTB = PDM_VCFG_RSTB_NORM; -// PDMn(ui32Module)->VCFG_b.PDMCLKEN = 1; - return AM_HAL_STATUS_SUCCESS; } diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pdm.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pdm.h index 95cfedd..302e73f 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pdm.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pdm.h @@ -12,26 +12,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -44,7 +44,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -64,6 +64,18 @@ extern "C" #define AM_REG_PDM_NUM_MODULES 1 #define PDMn(n) ((PDM_Type*)(PDM_BASE + (n * (PDM_BASE - PDM_BASE)))) +//***************************************************************************** +// +// DMA threshold minimum. +// +// The PDM DMA works best if its threshold value is set to a multiple of 4 +// between 16 and 24, but it will technically allow threshold settings between +// 4 and 24. This macro sets the minimum threshold value that the HAL layer +// will allow. +// +//***************************************************************************** +#define AM_HAL_PDM_DMA_THRESHOLD_MIN 16 + //***************************************************************************** // // PDM-specific error conditions. @@ -200,7 +212,6 @@ am_hal_pdm_chset_e; #define AM_HAL_PDM_INT_OVF PDM_INTSTAT_OVF_Msk #define AM_HAL_PDM_INT_THR PDM_INTSTAT_THR_Msk - //***************************************************************************** // // Configuration structure for the PDM @@ -262,7 +273,6 @@ typedef struct } am_hal_pdm_transfer_t; - // Init/De-init. extern uint32_t am_hal_pdm_initialize(uint32_t ui32Module, void **ppHandle); extern uint32_t am_hal_pdm_deinitialize(void *pHandle); @@ -305,4 +315,3 @@ extern uint32_t am_hal_pdm_interrupt_status_get(void *pHandle, uint32_t *pui32St //! @} // //***************************************************************************** - diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pin.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pin.h index 0577824..fdc4b2b 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pin.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pin.h @@ -12,26 +12,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -44,7 +44,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -90,7 +90,7 @@ #define AM_HAL_PIN_4_SLINT (1) #define AM_HAL_PIN_4_NCE4 (2) #define AM_HAL_PIN_4_GPIO (3) -#define AM_HAL_PIN_4_UART1RX (5) +#define AM_HAL_PIN_4_UART1RX (5) #define AM_HAL_PIN_4_CTIM17 (6) #define AM_HAL_PIN_4_MSPI2 (7) diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pwrctrl.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pwrctrl.c index e7e7ad4..7640a79 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pwrctrl.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pwrctrl.c @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.4.1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pwrctrl.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pwrctrl.h index d1e3936..9ba0a42 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pwrctrl.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pwrctrl.h @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.4.1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pwrctrl_internal.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pwrctrl_internal.h index 165c9a4..7107b4d 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pwrctrl_internal.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_pwrctrl_internal.h @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.4.1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_queue.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_queue.c index 3eee7fb..a66bac5 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_queue.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_queue.c @@ -5,7 +5,7 @@ //! //! @brief Functions for implementing a queue system. //! -//! @addtogroup Miscellaneous3 Software Features (MISC) +//! @addtogroup queue3 (QUEUE) //! @ingroup apollo3hal //! @{ // @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_queue.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_queue.h index 1aa958b..5a768f4 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_queue.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_queue.h @@ -5,7 +5,7 @@ //! //! @brief Functions for implementing a queue system. //! -//! @addtogroup Miscellaneous3 Software Features (MISC) +//! @addtogroup queue3 (QUEUE) //! @ingroup apollo3hal //! @{ // @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_QUEUE_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_reset.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_reset.c index cbf24dd..af71dd6 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_reset.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_reset.c @@ -5,34 +5,34 @@ //! //! @brief Hardware abstraction layer for the Reset Generator module. //! -//! @addtogroup rstgen2 Reset Generator (RSTGEN) -//! @ingroup apollo2hal +//! @addtogroup rstgen3 Reset Generator (RSTGEN) +//! @ingroup apollo3hal //! @{ // //***************************************************************************** //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_reset.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_reset.h index e1cdad2..ab50b63 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_reset.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_reset.h @@ -5,34 +5,34 @@ //! //! @brief Hardware abstraction layer for the Reset Generator module. //! -//! @addtogroup wdt2 Watchdog Timer (RSTGEN) -//! @ingroup apollo2hal +//! @addtogroup rstgen3 Reset Generator (RSTGEN) +//! @ingroup apollo3hal //! @{ // //***************************************************************************** //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_RSTGEN_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_rtc.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_rtc.c index 308af7b..e363788 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_rtc.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_rtc.c @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_rtc.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_rtc.h index 2ca7e44..890dd67 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_rtc.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_rtc.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_RTC_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_scard.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_scard.c index 6896ec2..97082f2 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_scard.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_scard.c @@ -5,7 +5,7 @@ //! //! @brief Functions for interfacing with the SCARD. //! -//! @addtogroup SCARD +//! @addtogroup scard3 //! @ingroup apollo3hal //! @{ // @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_scard.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_scard.h index 6594036..da8d87a 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_scard.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_scard.h @@ -5,7 +5,7 @@ //! //! @brief Functions for accessing and configuring the SCARD. //! -//! @addtogroup SCARD +//! @addtogroup scard3 //! @ingroup apollo3hal //! @{ // @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_SCARD_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_secure_ota.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_secure_ota.c index 6d9f2a5..553b385 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_secure_ota.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_secure_ota.c @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #include diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_secure_ota.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_secure_ota.h index 95f5ac2..8f64dd8 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_secure_ota.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_secure_ota.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_security.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_security.c index e0e7f44..91510ba 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_security.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_security.c @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,22 +45,50 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #include #include #include "am_mcu_apollo.h" -// Local defines +//***************************************************************************** +// Local defines. +//***************************************************************************** +// +// ENABLE_EXTMEM_CRC +// By default, the CRC engine can only operate on data located in internal +// memory (i.e. flash or SRAM). This define enables am_hal_crc() to support +// external memories, but requires a small amount of global SRAM allocated for +// that purpose. If it is not desired to support this feature, set to 0. +// +#define ENABLE_EXTMEM_CRC 1 + +// // Maximum iterations for hardware CRC to finish +// #define MAX_CRC_WAIT 100000 #define AM_HAL_SECURITY_LOCKSTAT_CUSTOMER 0x1 #define AM_HAL_SECURITY_LOCKSTAT_RECOVERY 0x40000000 -// Global declaration -// These are declared as ptr variables to avoid an issue with GCC reading from location 0x0. +//***************************************************************************** +// +// Globals +// +//***************************************************************************** +#if ENABLE_EXTMEM_CRC +// +// Set up a small global buffer that can be used am_hal_crc32() when +// computing CRCs on external memory. +// +#define CRC_XFERBUF_SZ (512) // Reserve 512 bytes for the buffer +static uint32_t g_CRC_buffer[CRC_XFERBUF_SZ / 4]; +#endif // ENABLE_EXTMEM_CRC + +// +// Assign ptr variables to avoid an issue with GCC reading from location 0x0. +// const volatile uint32_t *g_pFlash0 = (uint32_t*)(AM_HAL_SBL_ADDRESS + 0); const volatile uint32_t *g_pFlash4 = (uint32_t*)(AM_HAL_SBL_ADDRESS + 4); @@ -226,7 +254,7 @@ uint32_t am_hal_security_get_info(am_hal_security_info_t *pSecInfo) return AM_HAL_STATUS_FAIL; } return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_security_get_info() //***************************************************************************** // @@ -264,7 +292,7 @@ uint32_t am_hal_security_set_key(am_hal_security_locktype_t lockType, am_hal_sec SECURITY->KEY3 = pKey->keys.key3; return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_security_set_key() //***************************************************************************** // @@ -301,62 +329,169 @@ uint32_t am_hal_security_get_lock_status(am_hal_security_locktype_t lockType, bo } *pbUnlockStatus = SECURITY->LOCKSTAT & unlockMask; return AM_HAL_STATUS_SUCCESS; -} +} // am_hal_security_get_lock_status() //***************************************************************************** // //! @brief Compute CRC32 for a specified payload //! -//! @param startAddr - The start address of the payload -//! @param sizeBytes - The length of payload in bytes -//! @param pCrc - Pointer to return computed CRC +//! @param ui32StartAddr - The start address of the payload. +//! @param ui32SizeBytes - The length of payload in bytes. +//! @param pui32Crc - Pointer to variable to return the computed CRC. //! -//! This will use the hardware engine to compute CRC32 on an arbitrary data payload +//! This function uses the hardware engine to compute CRC32 on an arbitrary data +//! payload. The payload can reside in any contiguous memory including external +//! memory. //! //! @return Returns AM_HAL_STATUS_SUCCESS on success // //***************************************************************************** -uint32_t am_hal_crc32(uint32_t startAddr, uint32_t sizeBytes, uint32_t *pCrc) +uint32_t +am_hal_crc32(uint32_t ui32StartAddr, uint32_t ui32SizeBytes, uint32_t *pui32Crc) { - uint32_t status; + uint32_t status, ui32CRC32; + bool bInternal; #ifndef AM_HAL_DISABLE_API_VALIDATION - if (pCrc == NULL) + if (pui32Crc == NULL) { return AM_HAL_STATUS_INVALID_ARG; } + // // Make sure size is multiple of 4 bytes - if (sizeBytes & 0x3) + // + if (ui32SizeBytes & 0x3) { return AM_HAL_STATUS_INVALID_ARG; } - // TODO - check the address #endif // AM_HAL_DISABLE_API_VALIDATION + status = AM_HAL_STATUS_OUT_OF_RANGE; // Default status + + // + // Determine whether the startaddr is in internal flash or SRAM. + // + bInternal = ISADDRFLASH(ui32StartAddr) || ISADDRSRAM(ui32StartAddr); + + if ( bInternal ) + { + // + // Program the CRC engine to compute the crc + // + ui32CRC32 = 0xFFFFFFFF; + SECURITY->RESULT = ui32CRC32; + SECURITY->SRCADDR = ui32StartAddr; + SECURITY->LEN = ui32SizeBytes; + SECURITY->CTRL_b.FUNCTION = SECURITY_CTRL_FUNCTION_CRC32; + + // + // Start the CRC + // + SECURITY->CTRL_b.ENABLE = 1; + + // + // Wait for CRC to finish + // + status = am_hal_flash_delay_status_change(MAX_CRC_WAIT, + (uint32_t)&SECURITY->CTRL, SECURITY_CTRL_ENABLE_Msk, 0); + + if (status == AM_HAL_STATUS_SUCCESS) + { + *pui32Crc = SECURITY->RESULT; + } + + return status; + } + +#if ENABLE_EXTMEM_CRC + uint32_t ui32XferSize, ui32cnt; + uint32_t *pui32Buf, *pui32Data; + + // + // If we're here, the source data resides in non-internal memory (that is, + // not flash or SRAM). // - // Program the CRC engine to compute the crc + // Begin the loop for computing the CRC of the external memory. The data + // will first be copied to the SRAM buffer. // - SECURITY->RESULT = 0xFFFFFFFF; - SECURITY->SRCADDR = startAddr; - SECURITY->LEN_b.LEN = (sizeBytes >> SECURITY_LEN_LEN_Pos); + // Program the parts of the CRC engine that will not need to change + // inside the loop: SRCADDR, FUNCTION, initial seed in RESULT. + // While inside the loop, only the LEN will need to be provided. + // + SECURITY->SRCADDR = (uint32_t)&g_CRC_buffer[0]; SECURITY->CTRL_b.FUNCTION = SECURITY_CTRL_FUNCTION_CRC32; - // Start the CRC - SECURITY->CTRL_b.ENABLE = 1; // - // Wait for CRC to finish + // During the loop the RESULT register must not be rewritten, even if the + // value written on each pass is identical. Rewriting it appears to reset + // a state machine such that an incorrect CRC value is computed. // - status = am_hal_flash_delay_status_change(MAX_CRC_WAIT, - (uint32_t)&SECURITY->CTRL, SECURITY_CTRL_ENABLE_Msk, 0); + ui32CRC32 = 0xFFFFFFFF; + SECURITY->RESULT = ui32CRC32; - if (status == AM_HAL_STATUS_SUCCESS) + pui32Data = (uint32_t*)ui32StartAddr; + while ( ui32SizeBytes ) { - *pCrc = SECURITY->RESULT; + // + // First copy a chunk of payload data to SRAM where the CRC engine + // can operate on it. + // + ui32XferSize = (ui32SizeBytes >= CRC_XFERBUF_SZ) ? + CRC_XFERBUF_SZ : ui32SizeBytes; + ui32SizeBytes -= ui32XferSize; + ui32cnt = ui32XferSize / 4; + pui32Buf = &g_CRC_buffer[0]; + while ( ui32cnt-- ) + { + *pui32Buf++ = *pui32Data++; + } + + // + // Program the CRC engine's LEN parameter. + // All other parameters were preprogrammed: SRCADDR, FUNCTION, RESULT. + // + SECURITY->LEN = ui32XferSize; + + // + // Start the CRC + // + SECURITY->CTRL_b.ENABLE = 1; + + // + // Wait for CRC to finish + // + status = am_hal_flash_delay_status_change(MAX_CRC_WAIT, + (uint32_t)&SECURITY->CTRL, SECURITY_CTRL_ENABLE_Msk, 0); + + if ( (status == AM_HAL_STATUS_SUCCESS) && !SECURITY->CTRL_b.CRCERROR ) + { + ui32CRC32 = SECURITY->RESULT; + } + else if ( SECURITY->CTRL_b.CRCERROR ) + { + return AM_HAL_STATUS_HW_ERR; + } + else + { + // + // Error from status_change function. + // Return the CRC value we do have, but return an error. + // + //return status; + break; + } } + // + // Return result to caller + // + *pui32Crc = ui32CRC32; +#endif // ENABLE_EXTMEM_CRC + return status; -} + +} // am_hal_crc32() //***************************************************************************** // @@ -434,4 +569,4 @@ uint32_t am_hal_bootloader_exit(uint32_t *pImage) } return status; -} +} // am_hal_bootloader_exit() diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_security.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_security.h index ac393af..42e064f 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_security.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_security.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -96,6 +96,11 @@ typedef union } keys; } am_hal_security_128bkey_t; +#ifdef __cplusplus +extern "C" +{ +#endif + //***************************************************************************** // //! @brief Get Device Security Info @@ -172,4 +177,8 @@ uint32_t am_hal_crc32(uint32_t startAddr, uint32_t sizeBytes, uint32_t *pCrc); //***************************************************************************** uint32_t am_hal_bootloader_exit(uint32_t *pImage); +#ifdef __cplusplus +} +#endif + #endif // AM_HAL_SECURITY_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_status.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_status.h index f32d3b3..8007a9d 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_status.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_status.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_STATUS_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_stimer.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_stimer.c index de81036..06658b6 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_stimer.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_stimer.c @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_stimer.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_stimer.h index b43bdba..c1fa730 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_stimer.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_stimer.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_STIMER_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_sysctrl.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_sysctrl.c index db66080..1b99aea 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_sysctrl.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_sysctrl.c @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_sysctrl.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_sysctrl.h index 4485ad2..ffa9adc 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_sysctrl.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_sysctrl.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_SYSCTRL_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_systick.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_systick.c index 4193a88..87afce7 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_systick.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_systick.c @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_systick.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_systick.h index b8d51e3..0b6cc53 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_systick.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_systick.h @@ -5,34 +5,34 @@ //! //! @brief Functions for accessing and configuring the SYSTICK. //! -//! @addtogroup systick2 System Timer (SYSTICK) -//! @ingroup apollo2hal +//! @addtogroup systick3 System Timer (SYSTICK) +//! @ingroup apollo3hal //! @{ // //***************************************************************************** //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_SYSTICK_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_tpiu.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_tpiu.c index 1bf16b6..39ab647 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_tpiu.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_tpiu.c @@ -15,26 +15,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -47,7 +47,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_tpiu.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_tpiu.h index 7ed1a1c..1ca0f47 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_tpiu.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_tpiu.h @@ -13,26 +13,26 @@ //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_TPIU_H diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_uart.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_uart.c index c9bb9c0..973434e 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_uart.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_uart.c @@ -5,34 +5,34 @@ //! //! @brief Functions for interfacing with the UART. //! -//! @addtogroup uart2 UART -//! @ingroup apollo2hal +//! @addtogroup uart3 UART +//! @ingroup apollo3hal //! @{ // //***************************************************************************** //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -1091,7 +1091,7 @@ am_hal_uart_tx_flush(void *pHandle) // //***************************************************************************** uint32_t -am_hal_uart_flags_get(void *pHandle, uint32_t *ui32Flags) +am_hal_uart_flags_get(void *pHandle, uint32_t *pui32Flags) { am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; uint32_t ui32Module = pState->ui32Module; @@ -1099,12 +1099,25 @@ am_hal_uart_flags_get(void *pHandle, uint32_t *ui32Flags) // // Check to make sure this is a valid handle. // - if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + if ( !AM_HAL_UART_CHK_HANDLE(pHandle) ) { return AM_HAL_STATUS_INVALID_HANDLE; } - return UARTn(ui32Module)->FR; + if ( pui32Flags ) + { + // + // Set the flags value, then return success. + // + *pui32Flags = UARTn(ui32Module)->FR; + + return AM_HAL_STATUS_SUCCESS; + } + else + { + return AM_HAL_STATUS_INVALID_ARG; + } + } // am_hal_uart_flags_get() //***************************************************************************** @@ -1195,13 +1208,49 @@ tx_queue_update(void *pHandle) return ui32ErrorStatus; } // tx_queue_update() +//***************************************************************************** +// +// UART FIFO Read. +// +//***************************************************************************** +uint32_t +am_hal_uart_fifo_read(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead) +{ + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + return uart_fifo_read(pHandle, pui8Data, ui32NumBytes, pui32NumBytesRead); +} + +//***************************************************************************** +// +// UART FIFO Write. +// +//***************************************************************************** +uint32_t +am_hal_uart_fifo_write(void *pHandle, uint8_t *pui8Data, uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten) +{ + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + return uart_fifo_write(pHandle, pui8Data, ui32NumBytes, + pui32NumBytesWritten); +} + //***************************************************************************** // // Interrupt service // //***************************************************************************** uint32_t -am_hal_uart_interrupt_service(void *pHandle, uint32_t ui32Status, uint32_t *pui32UartTxIdle) +am_hal_uart_interrupt_service(void *pHandle, uint32_t ui32Status, + uint32_t *pui32UartTxIdle) { am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; uint32_t ui32Module = pState->ui32Module; @@ -1354,3 +1403,24 @@ am_hal_uart_interrupt_status_get(void *pHandle, uint32_t *pui32Status, bool bEna return AM_HAL_STATUS_SUCCESS; } // am_hal_uart_interrupt_status_get() + +//***************************************************************************** +// +// Return the set of enabled interrupts. +// +//***************************************************************************** +uint32_t +am_hal_uart_interrupt_enable_get(void *pHandle, uint32_t *pui32IntMask) +{ + am_hal_uart_state_t *pState = (am_hal_uart_state_t *) pHandle; + uint32_t ui32Module = pState->ui32Module; + + if (!AM_HAL_UART_CHK_HANDLE(pHandle)) + { + return AM_HAL_STATUS_INVALID_HANDLE; + } + + *pui32IntMask = UARTn(ui32Module)->IER; + + return AM_HAL_STATUS_SUCCESS; +} // am_hal_uart_interrupt_enable_get() diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_uart.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_uart.h index 02d5692..6e515f5 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_uart.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_uart.h @@ -5,34 +5,34 @@ //! //! @brief Functions for accessing and configuring the UART. //! -//! @addtogroup uart2 UART -//! @ingroup apollo2hal +//! @addtogroup uart3 UART +//! @ingroup apollo3hal //! @{ // //***************************************************************************** //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_UART_H @@ -330,7 +330,6 @@ extern uint32_t am_hal_uart_configure(void *pHandle, extern uint32_t am_hal_uart_transfer(void *pHandle, const am_hal_uart_transfer_t *pTransfer); - //***************************************************************************** // //! @brief Wait for the UART TX to become idle @@ -358,7 +357,7 @@ extern uint32_t am_hal_uart_tx_flush(void *pHandle); //! @brief Read the UART flags. //! //! @param pHandle is the handle for the UART to operate on. -//! @param ui32Flags is the destination pointer for the UART flags. +//! @param pui32Flags is the destination pointer for the UART flags. //! //! The UART hardware provides some information about the state of the physical //! interface at all times. This function provides a way to read that data @@ -382,7 +381,56 @@ extern uint32_t am_hal_uart_tx_flush(void *pHandle); //! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. // //***************************************************************************** -extern uint32_t am_hal_uart_flags_get(void *pHandle, uint32_t *ui32Flags); +extern uint32_t am_hal_uart_flags_get(void *pHandle, uint32_t *pui32Flags); + +//***************************************************************************** +// +//! @brief Read the UART FIFO directly. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param pui8Data is a pointer where the UART data should be written. +//! @param ui32NumBytes is the number of bytes to transfer. +//! @param pui32NumBytesRead is the nubmer of bytes actually transferred. +//! +//! This function reads the UART FIFO directly, and writes the resulting bytes +//! to pui8Data. Since the UART FIFO hardware has no direct size indicator, the +//! caller can only specify the maximum number of bytes they can handle. This +//! function will try to read as many bytes as possible. At the end of the +//! transfer, the number of bytes actually transferred will be written to the +//! pui32NumBytesRead parameter. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART error. +// +//***************************************************************************** +extern uint32_t am_hal_uart_fifo_read(void *pHandle, + uint8_t *pui8Data, + uint32_t ui32NumBytes, + uint32_t *pui32NumBytesRead); + +//***************************************************************************** +// +//! @brief Write the UART FIFO directly. +//! +//! @param pHandle is the handle for the UART to operate on. +//! @param pui8Data is a pointer where the UART data should be written. +//! @param ui32NumBytes is the number of bytes to transfer. +//! @param pui32NumBytesWritten is the nubmer of bytes actually transferred. +//! +//! This function reads from pui8Data, and writes the requested number of bytes +//! directly to the UART FIFO. Since the UART FIFO hardware has no register to +//! tell us how much free space it has, the caller can only specify the number +//! of bytes they would like to send. This function will try to write as many +//! bytes as possible up to the requested number. At the end of the transfer, +//! the number of bytes actually transferred will be written to the +//! pui32NumBytesWritten parameter. +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART error. +// +//***************************************************************************** +extern uint32_t am_hal_uart_fifo_write(void *pHandle, + uint8_t *pui8Data, + uint32_t ui32NumBytes, + uint32_t *pui32NumBytesWritten); //***************************************************************************** // @@ -606,7 +654,6 @@ extern uint32_t am_hal_uart_interrupt_clear(void *pHandle, //! @endcode //! //! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. - // //***************************************************************************** extern uint32_t am_hal_uart_interrupt_status_get(void *pHandle, @@ -622,6 +669,42 @@ typedef enum } am_hal_uart_errors_t; +//***************************************************************************** +// +//! @brief Check to see which interrupts are enabled. +//! +//! @param pHandle is the handle for the UART to operate on. +//! +//! @param pui32IntMask is the current set of interrupt enable bits (all bits +//! OR'ed together) +//! +//! This function checks the UART Interrupt Enable Register to see which UART +//! interrupts are currently enabled. The result will be an interrupt mask with +//! one bit set for each of the currently enabled UART interrupts. +//! +//! The full set of UART interrupt bits is given by the list below: +//! +//! @code +//! +//! AM_HAL_UART_INT_OVER_RUN +//! AM_HAL_UART_INT_BREAK_ERR +//! AM_HAL_UART_INT_PARITY_ERR +//! AM_HAL_UART_INT_FRAME_ERR +//! AM_HAL_UART_INT_RX_TMOUT +//! AM_HAL_UART_INT_TX +//! AM_HAL_UART_INT_RX +//! AM_HAL_UART_INT_DSRM +//! AM_HAL_UART_INT_DCDM +//! AM_HAL_UART_INT_CTSM +//! AM_HAL_UART_INT_TXCMP +//! +//! @endcode +//! +//! @return AM_HAL_STATUS_SUCCESS or applicable UART errors. +// +//***************************************************************************** +extern uint32_t am_hal_uart_interrupt_enable_get(void *pHandle, uint32_t *pui32IntMask); + #ifdef __cplusplus } #endif diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_wdt.c b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_wdt.c index 6d9a24b..0294014 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_wdt.c +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_wdt.c @@ -5,34 +5,34 @@ //! //! @brief Hardware abstraction layer for the Watchdog Timer module. //! -//! @addtogroup wdt2 Watchdog Timer (WDT) -//! @ingroup apollo2hal +//! @addtogroup wdt3 Watchdog Timer (WDT) +//! @ingroup apollo3hal //! @{ // //***************************************************************************** //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** @@ -336,9 +336,6 @@ am_hal_wdt_int_disable(void) //! //! This function reads the current value of watch dog timer counter register. //! -//! WARNING caller is responsible for masking interrutps before calling this -//! function. -//! //! @return None // //***************************************************************************** @@ -348,6 +345,11 @@ am_hal_wdt_counter_get(void) uint32_t ui32Values[3] = {0}; uint32_t ui32Value; + // + // Start a critical section. + // + uint32_t ui32InterruptState = am_hal_interrupt_master_disable(); + // // First, go read the value from the counter register 3 times // back to back in assembly language. @@ -398,6 +400,11 @@ am_hal_wdt_counter_get(void) "Bad CDT read"); } + // + // End the critical section. + // + am_hal_interrupt_master_set(ui32InterruptState); + return ui32Value; } // am_hal_wdt_counter_get() diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_wdt.h b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_wdt.h index eb122e0..3f4c87a 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_wdt.h +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/am_hal_wdt.h @@ -5,34 +5,34 @@ //! //! @brief Hardware abstraction layer for the Watchdog Timer module. //! -//! @addtogroup wdt2 Watchdog Timer (WDT) -//! @ingroup apollo2hal +//! @addtogroup wdt3 Watchdog Timer (WDT) +//! @ingroup apollo3hal //! @{ // //***************************************************************************** //***************************************************************************** // -// Copyright (c) 2019, Ambiq Micro +// Copyright (c) 2020, Ambiq Micro // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its // contributors may be used to endorse or promote products derived from this // software without specific prior written permission. -// +// // Third party software included in this distribution is subject to the // additional license terms as defined in the /docs/licenses directory. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -45,7 +45,7 @@ // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +// This is part of revision 2.4.2 of the AmbiqSuite Development Package. // //***************************************************************************** #ifndef AM_HAL_WDT_H @@ -134,7 +134,6 @@ typedef struct } am_hal_wdt_config_t; - //***************************************************************************** // //! @brief Restarts the watchdog timer ("Pets" the dog) @@ -152,7 +151,7 @@ am_hal_wdt_config_t; WDT->RSTRT = WDT_RSTRT_RSTRT_KEYVALUE; \ (void)(WDT->RSTRT); \ } \ - while(0) + while (0) #ifdef __cplusplus extern "C" @@ -167,6 +166,7 @@ extern void am_hal_wdt_init(const am_hal_wdt_config_t *psConfig); extern void am_hal_wdt_start(void); extern void am_hal_wdt_halt(void); extern void am_hal_wdt_lock_and_start(void); +extern uint32_t am_hal_wdt_counter_get(void); extern void am_hal_wdt_int_enable(void); extern uint32_t am_hal_wdt_int_enable_get(void); extern void am_hal_wdt_int_disable(void); diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/gcc/Makefile b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/gcc/Makefile index 135b859..f0a051e 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/gcc/Makefile +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/gcc/Makefile @@ -2,26 +2,26 @@ # # Makefile - Rules for building the libraries, examples and docs. # -# Copyright (c) 2019, Ambiq Micro +# Copyright (c) 2020, Ambiq Micro # All rights reserved. -# +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: -# +# # 1. Redistributions of source code must retain the above copyright notice, # this list of conditions and the following disclaimer. -# +# # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# +# # 3. Neither the name of the copyright holder nor the names of its # contributors may be used to endorse or promote products derived from this # software without specific prior written permission. -# +# # Third party software included in this distribution is subject to the # additional license terms as defined in the /docs/licenses directory. -# +# # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -34,7 +34,7 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # -# This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +# This is part of revision 2.4.2 of the AmbiqSuite Development Package. # #****************************************************************************** TARGET := libam_hal @@ -79,11 +79,12 @@ all clean: else DEFINES = -DAM_ASSERT_INVALID_THRESHOLD=0 -DEFINES+= -DAM_PART_APOLLO3 DEFINES+= -DAM_DEBUG_ASSERT +DEFINES+= -DAM_PART_APOLLO3 +DEFINES+= -Dgcc -INCLUDES = -I../../../../mcu/apollo3 -INCLUDES+= -I../../../../CMSIS/AmbiqMicro/Include +INCLUDES = -I../../../../CMSIS/AmbiqMicro/Include +INCLUDES+= -I../../../../mcu/apollo3 INCLUDES+= -I../../../../CMSIS/ARM/Include VPATH = .. diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/gcc/bin/libam_hal.a b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/gcc/bin/libam_hal.a index b844b30..cc20904 100644 Binary files a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/gcc/bin/libam_hal.a and b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/gcc/bin/libam_hal.a differ diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/iar/Makefile b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/iar/Makefile index ddff39c..a7a897b 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/iar/Makefile +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/iar/Makefile @@ -2,26 +2,26 @@ # # Makefile - Rules for building the libraries, examples and docs. # -# Copyright (c) 2019, Ambiq Micro +# Copyright (c) 2020, Ambiq Micro # All rights reserved. -# +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: -# +# # 1. Redistributions of source code must retain the above copyright notice, # this list of conditions and the following disclaimer. -# +# # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# +# # 3. Neither the name of the copyright holder nor the names of its # contributors may be used to endorse or promote products derived from this # software without specific prior written permission. -# +# # Third party software included in this distribution is subject to the # additional license terms as defined in the /docs/licenses directory. -# +# # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -34,7 +34,7 @@ # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # -# This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package. +# This is part of revision 2.4.2 of the AmbiqSuite Development Package. # #****************************************************************************** TARGET := libam_hal diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/iar/bin/libam_hal.a b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/iar/bin/libam_hal.a index e3b44d4..c95c477 100644 Binary files a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/iar/bin/libam_hal.a and b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/iar/bin/libam_hal.a differ diff --git a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/iar/libam_hal.ewp b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/iar/libam_hal.ewp index e85961b..9d2709f 100644 --- a/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/iar/libam_hal.ewp +++ b/cores/arduino/am_sdk_ap3/mcu/apollo3/hal/iar/libam_hal.ewp @@ -209,8 +209,8 @@ CCDefines iar AM_ASSERT_INVALID_THRESHOLD=0 - AM_PART_APOLLO3 AM_DEBUG_ASSERT + AM_PART_APOLLO3