diff --git a/boards.txt b/boards.txt index 746810ba..f626cbb9 100644 --- a/boards.txt +++ b/boards.txt @@ -314,3 +314,39 @@ edge2.menu.loader.sparkfun_svl.build.ldscript={build.variant.path}/linker_script ############################################################### +amap3micromod.name=SparkFun Artemis MicroMod +amap3micromod.build.variant=artemis_micromod +amap3micromod.build.board=AM_AP3_SFE_ARTEMIS_MICROMOD +amap3micromod.upload.maximum_size=960000 +amap3micromod.upload.sbl_baud=115200 +amap3micromod.build.arch=APOLLO3 +amap3micromod.build.mcu=cortex-m4 +amap3micromod.build.f_cpu=48000000L +amap3micromod.build.core=arduino +amap3micromod.build.includes="-I{build.variant.path}/config" "-I{build.variant.path}/bsp" +amap3micromod.build.extra_flags=-DPART_apollo3 -DAM_PACKAGE_BGA -DAM_PART_APOLLO3 +amap3micromod.build.ldscript={build.variant.path}/linker_scripts/gcc/artemis_sbl_svl_app.ld +amap3micromod.build.preferred_export_format=bin +amap3micromod.build.defs= +amap3micromod.build.libs= +amap3micromod.menu.svl_baud.921600=921600 +amap3micromod.menu.svl_baud.460800=460800 +amap3micromod.menu.svl_baud.230400=230400 +amap3micromod.menu.svl_baud.115200=115200 +amap3micromod.menu.svl_baud.57600=57600 +amap3micromod.menu.loader.sparkfun_svl=SparkFun Variable Loader (Recommended) +amap3micromod.menu.loader.ambiq_sbl=Ambiq Secure Bootloader (Advanced) + +amap3micromod.menu.svl_baud.57600.upload.svl_baud=57600 +amap3micromod.menu.svl_baud.115200.upload.svl_baud=115200 +amap3micromod.menu.svl_baud.230400.upload.svl_baud=230400 +amap3micromod.menu.svl_baud.460800.upload.svl_baud=460800 +amap3micromod.menu.svl_baud.921600.upload.svl_baud=921600 + +amap3micromod.menu.loader.ambiq_sbl.upload.tool=ambiq_bin2board +amap3micromod.menu.loader.ambiq_sbl.build.ldscript={build.variant.path}/linker_scripts/gcc/ambiq_sbl_app.ld + +amap3micromod.menu.loader.sparkfun_svl.upload.tool=artemis_svl +amap3micromod.menu.loader.sparkfun_svl.build.ldscript={build.variant.path}/linker_scripts/gcc/artemis_sbl_svl_app.ld + +############################################################### diff --git a/variants/artemis_micromod/bsp/README.md b/variants/artemis_micromod/bsp/README.md new file mode 100644 index 00000000..001fd130 --- /dev/null +++ b/variants/artemis_micromod/bsp/README.md @@ -0,0 +1,15 @@ +# Variant BSP +The Board Support Package (BSP) is a feature of the AmbiqSuite SDK that allows you to: +- define names and default configurations for pins +- write globally-accessible routines for common functions + +These features are potentially useful when: +- designing an Apollo3-based board for a custom purpose where pin functions will be mainly static +- using AmbiqSuite examples within Arduino + +For an example of a BSP see the AmbiqSuite release 2.1.0 SDK under 'SDK/boards/Apollo3_EVB/bsp' + +To include BSP files (i.e. am_bsp.h, am_bsp.c, am_bsp_pins.h, am_bsp_pins.c, as well as +bsp_pins.src and pinconfig.py) add " -I{build.variant.path}/bsp" to the board definition in +boards.txt as part of the board.build.includes parameter. + diff --git a/variants/artemis_micromod/bsp/am_bsp.c b/variants/artemis_micromod/bsp/am_bsp.c new file mode 100644 index 00000000..ff97924b --- /dev/null +++ b/variants/artemis_micromod/bsp/am_bsp.c @@ -0,0 +1,1062 @@ +//***************************************************************************** +// +// am_bsp.c +//! @file +//! +//! @brief Top level functions for performing board initialization. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_eb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v2.0.0 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include "am_bsp.h" +#include "am_util.h" + +//***************************************************************************** +// +// Power tracking structures for IOM and UART +// +//***************************************************************************** +am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// LEDs +// +//***************************************************************************** +#ifdef AM_BSP_NUM_LEDS +am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS] = +{ + {AM_BSP_GPIO_LED0, AM_DEVICES_LED_ON_HIGH | AM_DEVICES_LED_POL_DIRECT_DRIVE_M}, +}; +#endif + +#ifdef AM_BSP_NUM_BUTTONS +//***************************************************************************** +// +// Buttons. +// +//***************************************************************************** +am_devices_button_t am_bsp_psButtons[AM_BSP_NUM_BUTTONS] = +{ + AM_DEVICES_BUTTON(AM_BSP_GPIO_BUTTON0, AM_DEVICES_BUTTON_NORMAL_HIGH) +}; +#endif + +//***************************************************************************** +// +// Print interface tracking variable. +// +//***************************************************************************** +static uint32_t g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + +//***************************************************************************** +// +// Default UART configuration settings. +// +//***************************************************************************** +static void *g_sCOMUART; + +static const am_hal_uart_config_t g_sBspUartConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = 0, + .ui32TxBufferSize = 0, + .pui8RxBuffer = 0, + .ui32RxBufferSize = 0, +}; + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Default UART configuration settings if using buffers. +// +//***************************************************************************** +#define AM_BSP_UART_BUFFER_SIZE 1024 +static uint8_t pui8UartTxBuffer[AM_BSP_UART_BUFFER_SIZE]; +static uint8_t pui8UartRxBuffer[AM_BSP_UART_BUFFER_SIZE]; + +static am_hal_uart_config_t g_sBspUartBufferedConfig = +{ + // + // Standard UART settings: 115200-8-N-1 + // + .ui32BaudRate = 115200, + .ui32DataBits = AM_HAL_UART_DATA_BITS_8, + .ui32Parity = AM_HAL_UART_PARITY_NONE, + .ui32StopBits = AM_HAL_UART_ONE_STOP_BIT, + .ui32FlowControl = AM_HAL_UART_FLOW_CTRL_NONE, + + // + // Set TX and RX FIFOs to interrupt at half-full. + // + .ui32FifoLevels = (AM_HAL_UART_TX_FIFO_1_2 | + AM_HAL_UART_RX_FIFO_1_2), + + // + // The default interface will just use polling instead of buffers. + // + .pui8TxBuffer = pui8UartTxBuffer, + .ui32TxBufferSize = sizeof(pui8UartTxBuffer), + .pui8RxBuffer = pui8UartRxBuffer, + .ui32RxBufferSize = sizeof(pui8UartRxBuffer), +}; +#endif // AM_BSP_DISABLE_BUFFERED_UART + +//***************************************************************************** +// +//! @brief Prepare the MCU for low power operation. +//! +//! This function enables several power-saving features of the MCU, and +//! disables some of the less-frequently used peripherals. It also sets the +//! system clock to 24 MHz. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_low_power_init(void) +{ + // + // Initialize for low power in the power control block + // + am_hal_pwrctrl_low_power_init(); + + // + // Disable the RTC. + // + am_hal_rtc_osc_disable(); + + // + // Stop the XTAL. + // + am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_XTAL_STOP, 0); + + // + // Make sure SWO/ITM/TPIU is disabled. + // SBL may not get it completely shut down. + // + am_bsp_itm_printf_disable(); + +#ifdef AM_BSP_NUM_LEDS + // + // Initialize the LEDs. + // On the apollo3_evb, when the GPIO outputs are disabled (the default at + // power up), the FET gates are floating and partially illuminating the LEDs. + // + uint32_t ux, ui32GPIONumber; + for (ux = 0; ux < AM_BSP_NUM_LEDS; ux++) + { + ui32GPIONumber = am_bsp_psLEDs[ux].ui32GPIONumber; + + // + // Configure the pin as a push-pull GPIO output + // (aka AM_DEVICES_LED_POL_DIRECT_DRIVE_M). + // + am_hal_gpio_pinconfig(ui32GPIONumber, g_AM_HAL_GPIO_OUTPUT); + + // + // Turn off the LED. + // + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE); + am_hal_gpio_state_write(ui32GPIONumber, AM_HAL_GPIO_OUTPUT_CLEAR); + } +#endif // AM_BSP_NUM_LEDS + +} // am_bsp_low_power_init() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function enables TPIU registers for debug printf messages and enables +//! ITM GPIO pin to SWO mode. This function should be called after reset and +//! after waking up from deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_enable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { +#ifdef AM_BSP_GPIO_ITM_SWO + am_bsp_itm_printf_enable(); +#endif + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_enable(); + } +#ifndef AM_BSP_DISABLE_BUFFERED_UART + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_BUFFERED_UART0) + { + am_bsp_buffered_uart_printf_enable(); + } +#endif // AM_BSP_DISABLE_BUFFERED_UART +} // am_bsp_debug_printf_enable() + +//***************************************************************************** +// +//! @brief Enable the TPIU and ITM for debug printf messages. +//! +//! This function disables TPIU registers for debug printf messages and +//! enables ITM GPIO pin to GPIO mode and prepares the MCU to go to deep sleep. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_debug_printf_disable(void) +{ + if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_SWO) + { + am_bsp_itm_printf_disable(); + } + else if (g_ui32PrintInterface == AM_BSP_PRINT_INFC_UART0) + { + am_bsp_uart_printf_disable(); + } +} // am_bsp_debug_printf_disable() + +//***************************************************************************** +// +// @brief Enable printing over ITM. +// +//***************************************************************************** +void +#ifdef AM_BSP_GPIO_ITM_SWO +am_bsp_itm_printf_enable(void) +#else +am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg) +#endif +{ + am_hal_tpiu_config_t TPIUcfg; + + // + // Set the global print interface. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_SWO; + + // + // Enable the ITM interface and the SWO pin. + // + am_hal_itm_enable(); + + // + // Enable the ITM and TPIU + // Set the BAUD clock for 1M + // + TPIUcfg.ui32SetItmBaud = AM_HAL_TPIU_BAUD_2M; + am_hal_tpiu_enable(&TPIUcfg); + #ifdef AM_BSP_GPIO_ITM_SWO + am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_BSP_GPIO_ITM_SWO); + #else + am_hal_gpio_pinconfig(ui32Pin, sPincfg); + #endif + + // + // Attach the ITM to the STDIO driver. + // + am_util_stdio_printf_init(am_hal_itm_print); +} // am_bsp_itm_printf_enable() + +//***************************************************************************** +// +//! @brief ITM-based string print function. +//! +//! This function is used for printing a string via the ITM. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_itm_string_print(char *pcString) +{ + am_hal_itm_print(pcString); +} + +//***************************************************************************** +// +// @brief Disable printing over ITM. +// +//***************************************************************************** +void +am_bsp_itm_printf_disable(void) +{ + // + // Disable the ITM/TPIU + // + am_hal_itm_disable(); + + // + // Detach the ITM interface from the STDIO driver. + // + am_util_stdio_printf_init(0); + + // // + // // Disconnect the SWO pin + // // + // am_hal_gpio_pinconfig(AM_BSP_GPIO_ITM_SWO, g_AM_HAL_GPIO_DISABLE); +} // am_bsp_itm_printf_disable() + +//***************************************************************************** +// +//! @brief Set up the IOM pins based on mode and module. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_BSP_GPIO_IOM0_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_BSP_GPIO_IOM0_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_BSP_GPIO_IOM0_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_BSP_GPIO_IOM0_CS); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_BSP_GPIO_IOM1_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_BSP_GPIO_IOM1_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_BSP_GPIO_IOM1_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_BSP_GPIO_IOM1_CS); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_BSP_GPIO_IOM2_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_BSP_GPIO_IOM2_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_BSP_GPIO_IOM2_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_BSP_GPIO_IOM2_CS); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_BSP_GPIO_IOM3_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_BSP_GPIO_IOM3_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_BSP_GPIO_IOM3_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_BSP_GPIO_IOM3_CS); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_BSP_GPIO_IOM4_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_BSP_GPIO_IOM4_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_BSP_GPIO_IOM4_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_BSP_GPIO_IOM4_CS); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_BSP_GPIO_IOM5_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_BSP_GPIO_IOM5_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_BSP_GPIO_IOM5_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_BSP_GPIO_IOM5_CS); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_BSP_GPIO_IOM0_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_BSP_GPIO_IOM0_SDA); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_BSP_GPIO_IOM1_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_BSP_GPIO_IOM1_SDA); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_BSP_GPIO_IOM2_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_BSP_GPIO_IOM2_SDA); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_BSP_GPIO_IOM3_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_BSP_GPIO_IOM3_SDA); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_BSP_GPIO_IOM4_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_BSP_GPIO_IOM4_SDA); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_BSP_GPIO_IOM5_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_BSP_GPIO_IOM5_SDA); + break; + + default: + break; + } +} // am_bsp_iom_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOM pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOM_NUM_MODULES ) + { + // + // FPGA supports only IOM0 and 1. + // + return; + } + + ui32Combined = ((ui32Module << 2) | eIOMMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_SPI_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_CS, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM0_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((1 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM1_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((2 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM2_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((3 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM3_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((4 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM4_SDA, g_AM_HAL_GPIO_DISABLE); + break; + + case ((5 << 2) | AM_HAL_IOM_I2C_MODE): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOM5_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_iom_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_BSP_GPIO_MSPI_CE0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_BSP_GPIO_MSPI_CE1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_BSP_GPIO_MSPI_D0); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_BSP_GPIO_MSPI_D1); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_BSP_GPIO_MSPI_D2); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_BSP_GPIO_MSPI_D3); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_BSP_GPIO_MSPI_D4); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_BSP_GPIO_MSPI_D5); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_BSP_GPIO_MSPI_D6); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_BSP_GPIO_MSPI_D7); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_BSP_GPIO_MSPI_SCK); + break; + } +} // am_bsp_mspi_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the MSPI pins based on the external flash device type. +//! +//! This function configures up to 10-pins for MSPI serial, dual, quad, +//! dual-quad, and octal operation. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice) +{ + switch ( eMSPIDevice ) + { + case AM_HAL_MSPI_FLASH_SERIAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_SERIAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_DUAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUAD_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE0: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_OCTAL_CE1: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + case AM_HAL_MSPI_FLASH_QUADPAIRED: + case AM_HAL_MSPI_FLASH_QUADPAIRED_SERIAL: + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_CE1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D0, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D1, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D2, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D3, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D4, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D5, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D6, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_D7, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_MSPI_SCK, g_AM_HAL_GPIO_DISABLE); + break; + } +} // am_bsp_mspi_pins_disable() + +//***************************************************************************** +// +//! @brief Set up the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_BSP_GPIO_IOS_SCK); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_BSP_GPIO_IOS_MISO); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_BSP_GPIO_IOS_MOSI); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_BSP_GPIO_IOS_CE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_BSP_GPIO_IOS_SCL); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_BSP_GPIO_IOS_SDA); + break; + default: + break; + } +} // am_bsp_ios_pins_enable() + +//***************************************************************************** +// +//! @brief Disable the IOS pins based on mode and module. +//! +//! @return None. +// +//***************************************************************************** +void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode) +{ + uint32_t ui32Combined; + + // + // Validate parameters + // + if ( ui32Module >= AM_REG_IOSLAVE_NUM_MODULES ) + { + return; + } + + ui32Combined = ((ui32Module << 2) | ui32IOSMode); + + switch ( ui32Combined ) + { + case ((0 << 2) | AM_HAL_IOS_USE_SPI): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCK, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MISO, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_MOSI, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_CE, g_AM_HAL_GPIO_DISABLE); + break; + + case ((0 << 2) | AM_HAL_IOS_USE_I2C): + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SCL, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_IOS_SDA, g_AM_HAL_GPIO_DISABLE); + break; + default: + break; + } +} // am_bsp_ios_pins_disable() + +//***************************************************************************** +// +//! @brief UART-based string print function. +//! +//! This function is used for printing a string via the UART, which for some +//! MCU devices may be multi-module. +//! +//! @return None. +// +//***************************************************************************** +void +am_bsp_uart_string_print(char *pcString) +{ + uint32_t ui32StrLen = 0; + uint32_t ui32BytesWritten = 0; + + // + // Measure the length of the string. + // + while (pcString[ui32StrLen] != 0) + { + ui32StrLen++; + } + + // + // Print the string via the UART. + // + const am_hal_uart_transfer_t sUartWrite = + { + .ui32Direction = AM_HAL_UART_WRITE, + .pui8Data = (uint8_t *) pcString, + .ui32NumBytes = ui32StrLen, + .ui32TimeoutMs = AM_HAL_UART_WAIT_FOREVER, + .pui32BytesTransferred = &ui32BytesWritten, + }; + + am_hal_uart_transfer(g_sCOMUART, &sUartWrite); + + if (ui32BytesWritten != ui32StrLen) + { + // + // Couldn't send the whole string!! + // + while(1); + } +} // am_bsp_uart_string_print() + +//***************************************************************************** +// +// Pass-through function to let applications access the COM UART. +// +//***************************************************************************** +uint32_t +am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer) +{ + return am_hal_uart_transfer(g_sCOMUART, psTransfer); +} // am_bsp_com_uart_transfer() + +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Initialize and configure the UART with a custom configuration +// +//***************************************************************************** +void +am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, p_config); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); +} // am_bsp_uart_printf_enable() + +//***************************************************************************** +// +// Disable the UART +// +//***************************************************************************** +void +am_bsp_uart_printf_disable(void) +{ + // + // Make sure the UART has finished sending everything it's going to send. + // + am_hal_uart_tx_flush(g_sCOMUART); + + // + // Detach the UART from the stdio driver. + // + am_util_stdio_printf_init(0); + + // + // Power down the UART, and surrender the handle. + // + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_DEEPSLEEP, false); + am_hal_uart_deinitialize(g_sCOMUART); + + // + // Disable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_HAL_GPIO_DISABLE); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_HAL_GPIO_DISABLE); + +} // am_bsp_uart_printf_disable() + +#ifndef AM_BSP_DISABLE_BUFFERED_UART +//***************************************************************************** +// +// Initialize and configure the UART +// +//***************************************************************************** +void +am_bsp_buffered_uart_printf_enable(void) +{ + // + // Save the information that we're using the UART for printing. + // + g_ui32PrintInterface = AM_BSP_PRINT_INFC_UART0; + + // + // Initialize, power up, and configure the communication UART. Use the + // custom configuration if it was provided. Otherwise, just use the default + // configuration. + // + am_hal_uart_initialize(AM_BSP_UART_PRINT_INST, &g_sCOMUART); + am_hal_uart_power_control(g_sCOMUART, AM_HAL_SYSCTRL_WAKE, false); + am_hal_uart_configure(g_sCOMUART, &g_sBspUartBufferedConfig); + + // + // Enable the UART pins. + // + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_TX, g_AM_BSP_GPIO_COM_UART_TX); + am_hal_gpio_pinconfig(AM_BSP_GPIO_COM_UART_RX, g_AM_BSP_GPIO_COM_UART_RX); + + // + // Register the BSP print function to the STDIO driver. + // + am_util_stdio_printf_init(am_bsp_uart_string_print); + + // + // Enable the interrupts for the UART. + // + NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + AM_BSP_UART_PRINT_INST)); +} // am_bsp_buffered_uart_printf_enable() + +//***************************************************************************** +// +// Interrupt routine for the buffered UART interface. +// +//***************************************************************************** +void +am_bsp_buffered_uart_service(void) +{ + uint32_t ui32Status, ui32Idle; + am_hal_uart_interrupt_status_get(g_sCOMUART, &ui32Status, true); + am_hal_uart_interrupt_clear(g_sCOMUART, ui32Status); + am_hal_uart_interrupt_service(g_sCOMUART, ui32Status, &ui32Idle); +} // am_bsp_buffered_uart_service() +#endif // AM_BSP_DISABLE_BUFFERED_UART + + + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/variants/artemis_micromod/bsp/am_bsp.h b/variants/artemis_micromod/bsp/am_bsp.h new file mode 100644 index 00000000..d3015b0f --- /dev/null +++ b/variants/artemis_micromod/bsp/am_bsp.h @@ -0,0 +1,217 @@ +//***************************************************************************** +// +// am_bsp.h +//! @file +//! +//! @brief Functions to aid with configuring the GPIOs. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +#ifndef AM_BSP_H +#define AM_BSP_H + +#include +#include +#include "am_mcu_apollo.h" +#include "am_bsp_pins.h" + +// +// Make individual includes to not require full port before usage. +//#include "am_devices.h" +// +#include "am_devices_led.h" +#include "am_devices_button.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Begin User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Primary I2C. +// +//***************************************************************************** +#define AM_BSP_PRIM_I2C_IOM 4 +#define AM_BSP_PRIM_I2C_SDA_PIN AM_BSP_GPIO_SDA +#define AM_BSP_PRIM_I2C_SCL_PIN AM_BSP_GPIO_SCL +#define g_AM_BSP_PRIM_I2C_SDA g_AM_BSP_GPIO_SDA +#define g_AM_BSP_PRIM_I2C_SCL g_AM_BSP_GPIO_SCL + +//***************************************************************************** +// +// Primary SPI Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_SPI_IOM 3 +#define AM_BSP_PRIM_SPI_CLK_PIN AM_BSP_GPIO_SPI_SCK +#define AM_BSP_PRIM_SPI_SDO_PIN AM_BSP_GPIO_SPI_SDO +#define AM_BSP_PRIM_SPI_SDI_PIN AM_BSP_GPIO_SPI_SDI +#define g_AM_BSP_PRIM_SPI_CLK g_AM_BSP_GPIO_SPI_SCK +#define g_AM_BSP_PRIM_SPI_SDO g_AM_BSP_GPIO_SPI_SDO +#define g_AM_BSP_PRIM_SPI_SDI g_AM_BSP_GPIO_SPI_SDI + +//***************************************************************************** +// +// Primary UART Pins +// +//***************************************************************************** +#define AM_BSP_PRIM_UART_TX_PIN AM_BSP_GPIO_COM_UART_TX +#define AM_BSP_PRIM_UART_RX_PIN AM_BSP_GPIO_COM_UART_RX +#define g_AM_BSP_PRIM_UART_TX g_AM_BSP_GPIO_COM_UART_TX +#define g_AM_BSP_PRIM_UART_RX g_AM_BSP_GPIO_COM_UART_RX + +//***************************************************************************** +// +// LED definitions. +// +//***************************************************************************** +#define AM_BSP_NUM_LEDS 1 +extern am_devices_led_t am_bsp_psLEDs[AM_BSP_NUM_LEDS]; + +// LED Device Array Indices +#define AM_BSP_LED0 0 +#define AM_BSP_LED_BLUE AM_BSP_LED0 + +// Corresponding GPIO Numbers +#define AM_BSP_GPIO_LED0 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED19 AM_BSP_GPIO_LED_BLUE +#define AM_BSP_GPIO_LED_STAT AM_BSP_GPIO_LED_BLUE + +//***************************************************************************** +// +// PWM_LED peripheral assignments. +// +//***************************************************************************** +// +// The Artemis MM PB LED0 is pad 19 +// +#define AM_BSP_PIN_PWM_LED AM_BSP_GPIO_LED0 +#define AM_BSP_PWM_LED_TIMER 1 +#define AM_BSP_PWM_LED_TIMER_SEG AM_HAL_CTIMER_TIMERB +#define AM_BSP_PWM_LED_TIMER_INT AM_HAL_CTIMER_INT_TIMERB1C0 + +//***************************************************************************** +// +// UART definitions. +// +//***************************************************************************** +// +// Apollo3 has two UART instances. +// AM_BSP_UART_PRINT_INST should correspond to COM_UART. +// +#define AM_BSP_UART_IOS_INST 0 +#define AM_BSP_UART_PRINT_INST 0 +#define AM_BSP_UART_BOOTLOADER_INST 0 + +//***************************************************************************** +// +// Aliases for MicroMod connector pins. +// +//***************************************************************************** +#define AM_BSP_GPIO_CAM_MCLK AM_BSP_GPIO_AUD_OUT +#define AM_BSP_GPIO_CAM_PCLK AM_BSP_GPIO_AUD_IN + +#define AM_BSP_GPIO_BUS0 AM_BSP_GPIO_G0 +#define AM_BSP_GPIO_BUS1 AM_BSP_GPIO_G1 +#define AM_BSP_GPIO_BUS2 AM_BSP_GPIO_G2 +#define AM_BSP_GPIO_BUS3 AM_BSP_GPIO_G3 +#define AM_BSP_GPIO_BUS4 AM_BSP_GPIO_G4 +#define AM_BSP_GPIO_BUS5 AM_BSP_GPIO_G5 +#define AM_BSP_GPIO_BUS6 AM_BSP_GPIO_G6 +#define AM_BSP_GPIO_BUS7 AM_BSP_GPIO_G7 + +#define AM_BSP_GPIO_ADC_DM AM_BSP_GPIO_G9 +#define AM_BSP_GPIO_ADC_DP AM_BSP_GPIO_G10 + +#define AM_BSP_GPIO_CAM_HSYNC AM_BSP_GPIO_G9 +#define AM_BSP_GPIO_CAM_VSYNC AM_BSP_GPIO_G10 +#define AM_BSP_GPIO_CAM_TRIG AM_BSP_GPIO_D1 + +//***************************************************************************** +// +// End User Modifiable Area +// +//***************************************************************************** + +//***************************************************************************** +// +// Print interface type +// +//***************************************************************************** +#define AM_BSP_PRINT_INFC_NONE 0 +#define AM_BSP_PRINT_INFC_SWO 1 +#define AM_BSP_PRINT_INFC_UART0 2 +#define AM_BSP_PRINT_INFC_BUFFERED_UART0 3 + + +//***************************************************************************** +// +//! Structure containing UART configuration information while it is powered down. +// +//***************************************************************************** +typedef struct +{ + bool bSaved; + uint32_t ui32TxPinNum; + uint32_t ui32TxPinCfg; +} +am_bsp_uart_pwrsave_t; + +//***************************************************************************** +// +// External data definitions. +// +//***************************************************************************** +extern am_bsp_uart_pwrsave_t am_bsp_uart_pwrsave[AM_REG_UART_NUM_MODULES]; + +//***************************************************************************** +// +// External function definitions. +// +//***************************************************************************** +extern void am_bsp_low_power_init(void); +extern void am_bsp_iom_pins_enable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_iom_pins_disable(uint32_t ui32Module, am_hal_iom_mode_e eIOMMode); +extern void am_bsp_mspi_pins_enable(am_hal_mspi_device_e eMSPIDevice); +extern void am_bsp_mspi_pins_disable(am_hal_mspi_device_e eMSPIDevice); + +extern void am_bsp_ios_pins_enable(uint32_t ui32Module, uint32_t ui32IOSMode); // SparkFun Edge does not expose IO Slave Clock signal, so hiding these functions +extern void am_bsp_ios_pins_disable(uint32_t ui32Module, uint32_t ui32IOSMode); + +extern void am_bsp_debug_printf_enable(void); +extern void am_bsp_debug_printf_disable(void); + +#ifdef AM_BSP_GPIO_ITM_SWO +extern void am_bsp_itm_printf_enable(void); +#else +extern void am_bsp_itm_printf_enable(uint32_t ui32Pin, am_hal_gpio_pincfg_t sPincfg); +#endif +extern void am_bsp_itm_string_print(char *pcString); +extern void am_bsp_itm_printf_disable(void); + +extern void am_bsp_uart_string_print(char *pcString); +extern void am_bsp_uart_printf_enable(void); +extern void am_bsp_uart_printf_enable_custom(const am_hal_uart_config_t* p_config); +extern void am_bsp_uart_printf_disable(void); + +extern void am_bsp_buffered_uart_printf_enable(void); +extern void am_bsp_buffered_uart_service(void); + +extern uint32_t am_bsp_com_uart_transfer(const am_hal_uart_transfer_t *psTransfer); + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_H diff --git a/variants/artemis_micromod/bsp/am_bsp_pins.c b/variants/artemis_micromod/bsp/am_bsp_pins.c new file mode 100644 index 00000000..1cfdb8d3 --- /dev/null +++ b/variants/artemis_micromod/bsp/am_bsp_pins.c @@ -0,0 +1,1379 @@ +//***************************************************************************** +// +// am_bsp_pins.c +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_evb_bsp BSP for the Apollo3 Engineering Board +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include "am_bsp.h" + +//***************************************************************************** +// +// AUD_MCLK pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_AUD_MCLK = +{ + .uFuncSel = AM_HAL_PIN_18_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE +}; + +//***************************************************************************** +// +// AUD_OUT pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_AUD_OUT = +{ + .uFuncSel = AM_HAL_PIN_18_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE +}; + +//***************************************************************************** +// +// AUD_IN pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_AUD_IN = +{ + .uFuncSel = AM_HAL_PIN_11_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// AUD_LRCLK pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_AUD_LRCLK = +{ + .uFuncSel = AM_HAL_PIN_36_GPIO +}; + +//***************************************************************************** +// +// AUD_BCLK pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_AUD_BCLK = +{ + .uFuncSel = AM_HAL_PIN_37_GPIO +}; + +//***************************************************************************** +// +// SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// I2C_INT pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_I2C_INT = +{ + .uFuncSel = AM_HAL_PIN_2_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// SCL1 pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SCL1 = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// SDA1 pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDA1 = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// BATT_VIN pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BATT_VIN = +{ + .uFuncSel = AM_HAL_PIN_31_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// SDIO_CLK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDIO_CLK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// SDIO_CMD pin: I/O Master 0 SPI SDO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDIO_CMD = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// SDIO_DATA0 pin: I/O Master 0 SPI SDI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDIO_DATA0 = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// SDIO_DATA1 pin: QSPI data1 signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDIO_DATA1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1 +}; + +//***************************************************************************** +// +// SDIO_DATA2 pin: QSPI data2 signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDIO_DATA2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2 +}; + +//***************************************************************************** +// +// SDIO_DATA3 pin: QSPI data3 signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDIO_DATA3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13 +}; + +//***************************************************************************** +// +// SPI_SDI pin: I/O Master 3 SPI SDI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_SDI = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// SPI_SDO pin: I/O Master 3 SPI SDO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_SDO = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// SPI_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// SPI_CS pin: SPI CS signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_CS = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// SPI_SDI1 pin: I/O Master 0 SPI SDI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_SDI1 = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// SPI_SDO1 pin: I/O Master 0 SPI SDO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_SDO1 = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// SPI_SCK1 pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_SCK1 = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// SPI_CS1 pin: SPI1 CS signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_CS1 = +{ + .uFuncSel = AM_HAL_PIN_23_NCE23, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// A0 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_A0 = +{ + .uFuncSel = AM_HAL_PIN_32_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// A1 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_A1 = +{ + .uFuncSel = AM_HAL_PIN_35_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// PWM0 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_PWM0 = +{ + .uFuncSel = AM_HAL_PIN_44_CTIM20, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE +}; + +//***************************************************************************** +// +// PWM1 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_PWM1 = +{ + .uFuncSel = AM_HAL_PIN_45_CTIM22, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE +}; + +//***************************************************************************** +// +// D0 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_D0 = +{ + .uFuncSel = AM_HAL_PIN_0_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE +}; + +//***************************************************************************** +// +// D1 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_D1 = +{ + .uFuncSel = AM_HAL_PIN_1_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE +}; + +//***************************************************************************** +// +// TX1 pin: This pin is the UART1 transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_TX1 = +{ + .uFuncSel = AM_HAL_PIN_12_UART1TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// RX1 pin: This pin is the UART1 receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_RX1 = +{ + .uFuncSel = AM_HAL_PIN_25_UART1RX +}; + +//***************************************************************************** +// +// RTS1 pin: This pin is the UART1 rts pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_RTS1 = +{ + .uFuncSel = AM_HAL_PIN_10_UART1RTS +}; + +//***************************************************************************** +// +// CTS1 pin: This pin is the UART1 cts pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CTS1 = +{ + .uFuncSel = AM_HAL_PIN_17_UART1CTS +}; + +//***************************************************************************** +// +// G0 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G0 = +{ + .uFuncSel = AM_HAL_PIN_16_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// G1 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G1 = +{ + .uFuncSel = AM_HAL_PIN_33_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// G2 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G2 = +{ + .uFuncSel = AM_HAL_PIN_34_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// G3 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G3 = +{ + .uFuncSel = AM_HAL_PIN_27_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// G4 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G4 = +{ + .uFuncSel = AM_HAL_PIN_28_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// G5 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G5 = +{ + .uFuncSel = AM_HAL_PIN_29_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// G6 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G6 = +{ + .uFuncSel = AM_HAL_PIN_14_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// G7 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G7 = +{ + .uFuncSel = AM_HAL_PIN_15_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// G9 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G9 = +{ + .uFuncSel = AM_HAL_PIN_12_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// G10 pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G10 = +{ + .uFuncSel = AM_HAL_PIN_13_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA = +{ + .uFuncSel = AM_HAL_PIN_36_PDMDATA +}; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK = +{ + .uFuncSel = AM_HAL_PIN_37_PDMCLK +}; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labeled STAT. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE = +{ + .uFuncSel = AM_HAL_PIN_19_GPIO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX = +{ + .uFuncSel = AM_HAL_PIN_48_UART0TX, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_2MA +}; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX = +{ + .uFuncSel = AM_HAL_PIN_49_UART0RX +}; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS = +{ + .uFuncSel = AM_HAL_PIN_11_NCE11, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3 = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 0, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO = +{ + .uFuncSel = AM_HAL_PIN_6_M0MISO, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI = +{ + .uFuncSel = AM_HAL_PIN_7_M0MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL = +{ + .uFuncSel = AM_HAL_PIN_5_M0SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA = +{ + .uFuncSel = AM_HAL_PIN_6_M0SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 0 +}; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS = +{ + .uFuncSel = AM_HAL_PIN_14_NCE14, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 1, + .uNCE = 2, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO = +{ + .uFuncSel = AM_HAL_PIN_9_M1MISO, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI = +{ + .uFuncSel = AM_HAL_PIN_10_M1MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL = +{ + .uFuncSel = AM_HAL_PIN_8_M1SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA = +{ + .uFuncSel = AM_HAL_PIN_9_M1SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 1 +}; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS = +{ + .uFuncSel = AM_HAL_PIN_15_NCE15, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 2, + .uNCE = 3, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO = +{ + .uFuncSel = AM_HAL_PIN_25_M2MISO, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI = +{ + .uFuncSel = AM_HAL_PIN_28_M2MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL = +{ + .uFuncSel = AM_HAL_PIN_27_M2SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA = +{ + .uFuncSel = AM_HAL_PIN_25_M2SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 2 +}; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS = +{ + .uFuncSel = AM_HAL_PIN_12_NCE12, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 3, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO = +{ + .uFuncSel = AM_HAL_PIN_43_M3MISO, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI = +{ + .uFuncSel = AM_HAL_PIN_38_M3MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL = +{ + .uFuncSel = AM_HAL_PIN_42_M3SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA = +{ + .uFuncSel = AM_HAL_PIN_43_M3SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 3 +}; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS = +{ + .uFuncSel = AM_HAL_PIN_13_NCE13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 4, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO = +{ + .uFuncSel = AM_HAL_PIN_40_M4MISO, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI = +{ + .uFuncSel = AM_HAL_PIN_44_M4MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL = +{ + .uFuncSel = AM_HAL_PIN_39_M4SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA = +{ + .uFuncSel = AM_HAL_PIN_40_M4SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 4 +}; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS = +{ + .uFuncSel = AM_HAL_PIN_16_NCE16, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 5, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO = +{ + .uFuncSel = AM_HAL_PIN_49_M5MISO, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI = +{ + .uFuncSel = AM_HAL_PIN_47_M5MOSI, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCK, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL = +{ + .uFuncSel = AM_HAL_PIN_48_M5SCL, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA = +{ + .uFuncSel = AM_HAL_PIN_49_M5SDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN, + .uIOMnum = 5 +}; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0 = +{ + .uFuncSel = AM_HAL_PIN_19_NCE19, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1 = +{ + .uFuncSel = AM_HAL_PIN_41_NCE41, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_NONE, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6, + .uNCE = 1, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0 = +{ + .uFuncSel = AM_HAL_PIN_22_MSPI0, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1 = +{ + .uFuncSel = AM_HAL_PIN_26_MSPI1, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2 = +{ + .uFuncSel = AM_HAL_PIN_4_MSPI2, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3 = +{ + .uFuncSel = AM_HAL_PIN_23_MSPI13, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4 = +{ + .uFuncSel = AM_HAL_PIN_0_MSPI4, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5 = +{ + .uFuncSel = AM_HAL_PIN_1_MSPI5, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6 = +{ + .uFuncSel = AM_HAL_PIN_2_MSPI6, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7 = +{ + .uFuncSel = AM_HAL_PIN_3_MSPI7, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_8MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK = +{ + .uFuncSel = AM_HAL_PIN_24_MSPI8, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA, + .eIntDir = AM_HAL_GPIO_PIN_INTDIR_LO2HI, + .uIOMnum = 6 +}; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE = +{ + .uFuncSel = AM_HAL_PIN_3_SLnCE, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE, + .uNCE = 0, + .eCEpol = AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW +}; + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO = +{ + .uFuncSel = AM_HAL_PIN_2_SLMISO, + .eDriveStrength = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA +}; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI = +{ + .uFuncSel = AM_HAL_PIN_1_SLMOSI, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCK, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL = +{ + .uFuncSel = AM_HAL_PIN_0_SLSCL, + .eGPInput = AM_HAL_GPIO_PIN_INPUT_ENABLE +}; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA = +{ + .uFuncSel = AM_HAL_PIN_1_SLSDAWIR3, + .ePullup = AM_HAL_GPIO_PIN_PULLUP_1_5K, + .eGPOutcfg = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN +}; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK = +{ + .uFuncSel = AM_HAL_PIN_20_SWDCK +}; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO = +{ + .uFuncSel = AM_HAL_PIN_21_SWDIO +}; + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/variants/artemis_micromod/bsp/am_bsp_pins.h b/variants/artemis_micromod/bsp/am_bsp_pins.h new file mode 100644 index 00000000..13d6e1cd --- /dev/null +++ b/variants/artemis_micromod/bsp/am_bsp_pins.h @@ -0,0 +1,937 @@ +//***************************************************************************** +// +// am_bsp_pins.h +//! @file +//! +//! @brief BSP pin configuration definitions. +//! +//! @addtogroup BSP Board Support Package (BSP) +//! @addtogroup apollo3_bsp BSP for the Apollo3 EVB. +//! @ingroup BSP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2019, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.2.0-hotfix-2.2.1 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#ifndef AM_BSP_PINS_H +#define AM_BSP_PINS_H + +#include +#include +#include "am_mcu_apollo.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// AUD_MCLK pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_AUD_MCLK 18 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_AUD_MCLK; + +//***************************************************************************** +// +// AUD_OUT pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_AUD_OUT 18 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_AUD_OUT; + +//***************************************************************************** +// +// AUD_IN pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_AUD_IN 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_AUD_IN; + +//***************************************************************************** +// +// AUD_LRCLK pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_AUD_LRCLK 36 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_AUD_LRCLK; + +//***************************************************************************** +// +// AUD_BCLK pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_AUD_BCLK 37 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_AUD_BCLK; + +//***************************************************************************** +// +// SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SCL; + +//***************************************************************************** +// +// SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDA; + +//***************************************************************************** +// +// I2C_INT pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_I2C_INT 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_I2C_INT; + +//***************************************************************************** +// +// SCL1 pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SCL1 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SCL1; + +//***************************************************************************** +// +// SDA1 pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SDA1 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDA1; + +//***************************************************************************** +// +// BATT_VIN pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_BATT_VIN 31 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_BATT_VIN; + +//***************************************************************************** +// +// SDIO_CLK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SDIO_CLK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDIO_CLK; + +//***************************************************************************** +// +// SDIO_CMD pin: I/O Master 0 SPI SDO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SDIO_CMD 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDIO_CMD; + +//***************************************************************************** +// +// SDIO_DATA0 pin: I/O Master 0 SPI SDI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SDIO_DATA0 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDIO_DATA0; + +//***************************************************************************** +// +// SDIO_DATA1 pin: QSPI data1 signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SDIO_DATA1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDIO_DATA1; + +//***************************************************************************** +// +// SDIO_DATA2 pin: QSPI data2 signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SDIO_DATA2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDIO_DATA2; + +//***************************************************************************** +// +// SDIO_DATA3 pin: QSPI data3 signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SDIO_DATA3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SDIO_DATA3; + +//***************************************************************************** +// +// SPI_SDI pin: I/O Master 3 SPI SDI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SPI_SDI 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_SDI; + +//***************************************************************************** +// +// SPI_SDO pin: I/O Master 3 SPI SDO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SPI_SDO 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_SDO; + +//***************************************************************************** +// +// SPI_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SPI_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_SCK; + +//***************************************************************************** +// +// SPI_CS pin: SPI CS signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SPI_CS 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_CS; +#define AM_BSP_SPI_CS_CHNL 0 + +//***************************************************************************** +// +// SPI_SDI1 pin: I/O Master 0 SPI SDI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SPI_SDI1 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_SDI1; + +//***************************************************************************** +// +// SPI_SDO1 pin: I/O Master 0 SPI SDO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SPI_SDO1 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_SDO1; + +//***************************************************************************** +// +// SPI_SCK1 pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SPI_SCK1 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_SCK1; + +//***************************************************************************** +// +// SPI_CS1 pin: SPI1 CS signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_SPI_CS1 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SPI_CS1; +#define AM_BSP_SPI_CS1_CHNL 0 + +//***************************************************************************** +// +// A0 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_A0 32 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_A0; + +//***************************************************************************** +// +// A1 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_A1 35 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_A1; + +//***************************************************************************** +// +// PWM0 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_PWM0 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_PWM0; + +//***************************************************************************** +// +// PWM1 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_PWM1 45 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_PWM1; + +//***************************************************************************** +// +// D0 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_D0 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_D0; + +//***************************************************************************** +// +// D1 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_D1 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_D1; + +//***************************************************************************** +// +// TX1 pin: This pin is the UART1 transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_TX1 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_TX1; + +//***************************************************************************** +// +// RX1 pin: This pin is the UART1 receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_RX1 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_RX1; + +//***************************************************************************** +// +// RTS1 pin: This pin is the UART1 rts pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_RTS1 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_RTS1; + +//***************************************************************************** +// +// CTS1 pin: This pin is the UART1 cts pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_CTS1 17 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_CTS1; + +//***************************************************************************** +// +// G0 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_G0 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G0; + +//***************************************************************************** +// +// G1 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_G1 33 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G1; + +//***************************************************************************** +// +// G2 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_G2 34 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G2; + +//***************************************************************************** +// +// G3 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_G3 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G3; + +//***************************************************************************** +// +// G4 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_G4 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G4; + +//***************************************************************************** +// +// G5 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_G5 29 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G5; + +//***************************************************************************** +// +// G6 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_G6 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G6; + +//***************************************************************************** +// +// G7 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_G7 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G7; + +//***************************************************************************** +// +// G9 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_G9 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G9; + +//***************************************************************************** +// +// G10 pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_G10 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_G10; + +//***************************************************************************** +// +// MIC_DATA pin: Data line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_DATA 36 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_DATA; + +//***************************************************************************** +// +// MIC_CLK pin: Clock line for PDM microphones. +// +//***************************************************************************** +#define AM_BSP_GPIO_MIC_CLK 37 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MIC_CLK; + +//***************************************************************************** +// +// LED_BLUE pin: The BLUE LED labeled STAT. +// +//***************************************************************************** +#define AM_BSP_GPIO_LED_BLUE 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_LED_BLUE; + +//***************************************************************************** +// +// COM_UART_TX pin: This pin is the COM_UART transmit pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_TX 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_TX; + +//***************************************************************************** +// +// COM_UART_RX pin: This pin is the COM_UART receive pin. +// +//***************************************************************************** +#define AM_BSP_GPIO_COM_UART_RX 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_COM_UART_RX; + +//***************************************************************************** +// +// IOM0_CS pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS 11 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS; +#define AM_BSP_IOM0_CS_CHNL 0 + +//***************************************************************************** +// +// IOM0_CS3 pin: I/O Master 0 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_CS3 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_CS3; +#define AM_BSP_IOM0_CS3_CHNL 3 + +//***************************************************************************** +// +// IOM0_MISO pin: I/O Master 0 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MISO 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MISO; + +//***************************************************************************** +// +// IOM0_MOSI pin: I/O Master 0 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_MOSI 7 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_MOSI; + +//***************************************************************************** +// +// IOM0_SCK pin: I/O Master 0 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCK 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCK; + +//***************************************************************************** +// +// IOM0_SCL pin: I/O Master 0 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SCL 5 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SCL; + +//***************************************************************************** +// +// IOM0_SDA pin: I/O Master 0 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM0_SDA 6 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM0_SDA; + +//***************************************************************************** +// +// IOM1_CS pin: I/O Master 1 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_CS 14 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_CS; +#define AM_BSP_IOM1_CS_CHNL 2 + +//***************************************************************************** +// +// IOM1_MISO pin: I/O Master 1 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MISO 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MISO; + +//***************************************************************************** +// +// IOM1_MOSI pin: I/O Master 1 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_MOSI 10 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_MOSI; + +//***************************************************************************** +// +// IOM1_SCK pin: I/O Master 1 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCK 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCK; + +//***************************************************************************** +// +// IOM1_SCL pin: I/O Master 1 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SCL 8 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SCL; + +//***************************************************************************** +// +// IOM1_SDA pin: I/O Master 1 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM1_SDA 9 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM1_SDA; + +//***************************************************************************** +// +// IOM2_CS pin: I/O Master 2 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_CS 15 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_CS; +#define AM_BSP_IOM2_CS_CHNL 3 + +//***************************************************************************** +// +// IOM2_MISO pin: I/O Master 2 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MISO 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MISO; + +//***************************************************************************** +// +// IOM2_MOSI pin: I/O Master 2 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_MOSI 28 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_MOSI; + +//***************************************************************************** +// +// IOM2_SCK pin: I/O Master 2 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCK 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCK; + +//***************************************************************************** +// +// IOM2_SCL pin: I/O Master 2 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SCL 27 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SCL; + +//***************************************************************************** +// +// IOM2_SDA pin: I/O Master 2 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM2_SDA 25 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM2_SDA; + +//***************************************************************************** +// +// IOM3_CS pin: I/O Master 3 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_CS 12 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_CS; +#define AM_BSP_IOM3_CS_CHNL 0 + +//***************************************************************************** +// +// IOM3_MISO pin: I/O Master 3 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MISO 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MISO; + +//***************************************************************************** +// +// IOM3_MOSI pin: I/O Master 3 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_MOSI 38 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_MOSI; + +//***************************************************************************** +// +// IOM3_SCK pin: I/O Master 3 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCK 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCK; + +//***************************************************************************** +// +// IOM3_SCL pin: I/O Master 3 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SCL 42 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SCL; + +//***************************************************************************** +// +// IOM3_SDA pin: I/O Master 3 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM3_SDA 43 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM3_SDA; + +//***************************************************************************** +// +// IOM4_CS pin: I/O Master 4 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_CS 13 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_CS; +#define AM_BSP_IOM4_CS_CHNL 1 + +//***************************************************************************** +// +// IOM4_MISO pin: I/O Master 4 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MISO 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MISO; + +//***************************************************************************** +// +// IOM4_MOSI pin: I/O Master 4 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_MOSI 44 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_MOSI; + +//***************************************************************************** +// +// IOM4_SCK pin: I/O Master 4 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCK 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCK; + +//***************************************************************************** +// +// IOM4_SCL pin: I/O Master 4 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SCL 39 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SCL; + +//***************************************************************************** +// +// IOM4_SDA pin: I/O Master 4 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM4_SDA 40 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM4_SDA; + +//***************************************************************************** +// +// IOM5_CS pin: I/O Master 5 chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_CS 16 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_CS; +#define AM_BSP_IOM5_CS_CHNL 0 + +//***************************************************************************** +// +// IOM5_MISO pin: I/O Master 5 SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MISO 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MISO; + +//***************************************************************************** +// +// IOM5_MOSI pin: I/O Master 5 SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_MOSI 47 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_MOSI; + +//***************************************************************************** +// +// IOM5_SCK pin: I/O Master 5 SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCK 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCK; + +//***************************************************************************** +// +// IOM5_SCL pin: I/O Master 5 I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SCL 48 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SCL; + +//***************************************************************************** +// +// IOM5_SDA pin: I/O Master 5 I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOM5_SDA 49 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOM5_SDA; + +//***************************************************************************** +// +// MSPI_CE0 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE0 19 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE0; +#define AM_BSP_MSPI_CE0_CHNL 0 + +//***************************************************************************** +// +// MSPI_CE1 pin: MSPI chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_CE1 41 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_CE1; +#define AM_BSP_MSPI_CE1_CHNL 1 + +//***************************************************************************** +// +// MSPI_D0 pin: MSPI data 0. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D0 22 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D0; + +//***************************************************************************** +// +// MSPI_D1 pin: MSPI data 1. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D1 26 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D1; + +//***************************************************************************** +// +// MSPI_D2 pin: MSPI data 2. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D2 4 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D2; + +//***************************************************************************** +// +// MSPI_D3 pin: MSPI data 3. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D3 23 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D3; + +//***************************************************************************** +// +// MSPI_D4 pin: MSPI data 4. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D4 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D4; + +//***************************************************************************** +// +// MSPI_D5 pin: MSPI data 5. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D5 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D5; + +//***************************************************************************** +// +// MSPI_D6 pin: MSPI data 6. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D6 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D6; + +//***************************************************************************** +// +// MSPI_D7 pin: MSPI data 7. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_D7 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_D7; + +//***************************************************************************** +// +// MSPI_SCK pin: MSPI clock. +// +//***************************************************************************** +#define AM_BSP_GPIO_MSPI_SCK 24 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_MSPI_SCK; + +//***************************************************************************** +// +// IOS_CE pin: I/O Slave chip select. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_CE 3 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_CE; +#define AM_BSP_IOS_CE_CHNL 0 + +//***************************************************************************** +// +// IOS_MISO pin: I/O Slave SPI MISO signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MISO 2 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MISO; + +//***************************************************************************** +// +// IOS_MOSI pin: I/O Slave SPI MOSI signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_MOSI 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_MOSI; + +//***************************************************************************** +// +// IOS_SCK pin: I/O Slave SPI SCK signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCK 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCK; + +//***************************************************************************** +// +// IOS_SCL pin: I/O Slave I2C clock signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SCL 0 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SCL; + +//***************************************************************************** +// +// IOS_SDA pin: I/O Slave I2C data signal. +// +//***************************************************************************** +#define AM_BSP_GPIO_IOS_SDA 1 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_IOS_SDA; + +//***************************************************************************** +// +// SWDCK pin: Cortex Serial Wire DCK. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDCK 20 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDCK; + +//***************************************************************************** +// +// SWDIO pin: Cortex Serial Wire DIO. +// +//***************************************************************************** +#define AM_BSP_GPIO_SWDIO 21 +extern const am_hal_gpio_pincfg_t g_AM_BSP_GPIO_SWDIO; + + +#ifdef __cplusplus +} +#endif + +#endif // AM_BSP_PINS_H + +//***************************************************************************** +// +// End Doxygen group. +//! @} +// +//***************************************************************************** diff --git a/variants/artemis_micromod/config/variant.cpp b/variants/artemis_micromod/config/variant.cpp new file mode 100644 index 00000000..71025c8a --- /dev/null +++ b/variants/artemis_micromod/config/variant.cpp @@ -0,0 +1,87 @@ +/* +Copyright (c) 2019 SparkFun Electronics + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. +*/ + +#include "variant.h" + +const ap3_gpio_pad_t ap3_variant_pinmap[AP3_VARIANT_NUM_PINS] = { + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + AP3_GPIO_PAD_UNUSED, //Pad not broken out of the Apollo3 on the Artemis + 31, + 32, + 33, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + AP3_GPIO_PAD_UNUSED, //Pad not broken out of the Apollo3 on the Artemis + 47, + 48, + 49, +}; + +// Uart Definitions +//Serial(instance, RX, TX, RTS, CTS) +Uart Serial(0, 49, 48); // Declares a Uart object called Serial using instance 0 of Apollo3 UART peripherals with RX on variant pin 49 and TX on pin 48 (note, you specify *pins* not Apollo3 pads. This uses the variant's pin map to determine the Apollo3 pad) + +Uart Serial1(1, 25, 12, 10, 17); //Enable flow control by default + +// Mapping of analog pins to digital pins of variant +extern const ap3_gpio_pin_t ap3_analog_A32 = 32; +extern const ap3_gpio_pin_t ap3_analog_A35 = 35; +extern const ap3_gpio_pin_t ap3_analog_A31 = 31; diff --git a/variants/artemis_micromod/config/variant.h b/variants/artemis_micromod/config/variant.h new file mode 100644 index 00000000..42ba9887 --- /dev/null +++ b/variants/artemis_micromod/config/variant.h @@ -0,0 +1,107 @@ +/* +Copyright (c) 2019 SparkFun Electronics + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. +*/ +#ifndef _AP3_VARIANT_H_ +#define _AP3_VARIANT_H_ + +#include "Arduino.h" + +#define AP3_VARIANT_NUM_PINS (50) + +// Pin map declaration +extern const ap3_gpio_pad_t ap3_variant_pinmap[AP3_VARIANT_NUM_PINS]; + +// Uart declarations +class Uart; // Forward declaration of Uart +extern Uart Serial; +extern Uart Serial1; + +// Wire defines +#define WIRE_INTERFACES_COUNT 2 + +#define AP3_Wire_IOM 4 // Secify that Wire uses IOMaster instance 4 +#define AP3_Wire1_IOM 1 + +// SPI Defines +#define SPI_INTERFACES_COUNT 2 + +#define AP3_SPI_IOM 3 // Specify that SPI uses IOMaster 3 +#define AP3_SPI_DUP ap3_spi_full_duplex // Specify that SPI is full-duplex (as opposed to ap3_spi_tx_only or ap3_spi_rx_only) + +#define AP3_SPI1_IOM 0 +#define AP3_SPI1_DUP ap3_spi_full_duplex + +// Mapping of analog pins to digital pins of variant +// (this method - aliasing the name of a constant variable - is compatible with the usage of 'AX' names in 'arm_math.h') +#define A0 ap3_analog_A32 +#define A1 ap3_analog_A35 +#define BATTVIN3 ap3_analog_A31 + +// Promise the existence of analog pin names +extern const ap3_gpio_pin_t ap3_analog_A32; +extern const ap3_gpio_pin_t ap3_analog_A35; +extern const ap3_gpio_pin_t ap3_analog_A31; + +#define LED_BUILTIN 19 + +#define POWER_CONTROL 3 + +// Pins with dedicated silk +#define PWM0 44 +#define PWM1 45 + +#define D0 0 +#define D1 1 + +#define MOSI1 7 +#define MISO1 6 //Duplicate route to pad 22 as well. +#define SCK1 5 +#define CS1 23 + +#define SDA1 9 +#define SCL1 8 +#define I2CINT 2 + +#define MOSI 38 +#define MISO 43 +#define SCK 42 +#define CS 41 + +#define PDM_DATA 36 +#define PDM_CLOCK 37 + +#define ADC_DIFF_NEG 12 +#define ADC_DIFF_POS 13 + +#define G0 16 +#define G1 33 +#define G2 34 +#define G3 27 +#define G4 28 +#define G5 29 +#define G6 14 +#define G7 15 +#define G8 3 +#define G9 ADC_DIFF_NEG +#define G10 ADC_DIFF_POS +#define G11 11 + +#endif // _AP3_VARIANT_H_ diff --git a/variants/artemis_micromod/linker_scripts/gcc/ambiq_sbl_app.ld b/variants/artemis_micromod/linker_scripts/gcc/ambiq_sbl_app.ld new file mode 100644 index 00000000..262ef3ae --- /dev/null +++ b/variants/artemis_micromod/linker_scripts/gcc/ambiq_sbl_app.ld @@ -0,0 +1,78 @@ +/****************************************************************************** + * + * blank_slate.ld - Linker script for applications using startup_gnu.c + * + *****************************************************************************/ +ENTRY(Reset_Handler) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x0000C000, LENGTH = 960K + SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 384K +} + +SECTIONS +{ + .text : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) + KEEP(*(.patch)) + *(.text) + *(.text*) + + . = ALIGN(4); + __init_array_start = .; + KEEP(*(.init_array)) /* C++ constructors */ + KEEP(*(.ctors)) /* and vtable init */ + __init_array_end = .; + + *(.rodata) + *(.rodata*) + . = ALIGN(4); + _etext = .; + } > FLASH + + /* User stack section initialized by startup code. */ + .stack (NOLOAD): + { + . = ALIGN(8); + *(.stack) + *(.stack*) + . = ALIGN(8); + } > SRAM + + .data : + { + . = ALIGN(4); + _sdata = .; + *(.data) + *(.data*) + . = ALIGN(4); + _edata = .; + } > SRAM AT>FLASH + + /* used by startup to initialize data */ + _init_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _sbss = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } > SRAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + __HeapLimit = .; + } > SRAM + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/variants/artemis_micromod/linker_scripts/gcc/artemis_sbl_svl_app.ld b/variants/artemis_micromod/linker_scripts/gcc/artemis_sbl_svl_app.ld new file mode 100644 index 00000000..6b024b9b --- /dev/null +++ b/variants/artemis_micromod/linker_scripts/gcc/artemis_sbl_svl_app.ld @@ -0,0 +1,80 @@ +/****************************************************************************** + * + * blank_slate.ld - Linker script for applications using startup_gnu.c + * + *****************************************************************************/ +ENTRY(Reset_Handler) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00010000, LENGTH = 960K /*Modified from 0xC000 to work with SparkFun ABL*/ + SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 384K +} + +SECTIONS +{ + .text : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) + KEEP(*(.patch)) + *(.text) + *(.text*) + + . = ALIGN(4); + __init_array_start = .; + KEEP(*(.init_array)) /* C++ constructors */ + KEEP(*(.ctors)) /* and vtable init */ + __init_array_end = .; + + *(.rodata) + *(.rodata*) + . = ALIGN(4); + _etext = .; + } > FLASH + + /* User stack section initialized by startup code. */ + .stack (NOLOAD): + { + . = ALIGN(8); + *(.stack) + *(.stack*) + . = ALIGN(8); + } > SRAM + + .data : + { + . = ALIGN(4); + _sdata = .; + *(.data) + *(.data*) + . = ALIGN(4); + _edata = .; + } > SRAM AT>FLASH + + /* used by startup to initialize data */ + _init_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _sbss = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } > SRAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + __HeapLimit = .; + } > SRAM + + /* TODO: Collision Checking (at link time) */ + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/variants/artemis_micromod/startup/startup_gcc.c b/variants/artemis_micromod/startup/startup_gcc.c new file mode 100644 index 00000000..8aa5b706 --- /dev/null +++ b/variants/artemis_micromod/startup/startup_gcc.c @@ -0,0 +1,392 @@ +//***************************************************************************** +// +//! @file startup_gcc.c +//! +//! @brief Definitions for interrupt handlers, the vector table, and the stack. +// +//***************************************************************************** + +//***************************************************************************** +// +// Copyright (c) 2018, Ambiq Micro +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// Third party software included in this distribution is subject to the +// additional license terms as defined in the /docs/licenses directory. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision v1.2.12-1330-gad755f6e5 of the AmbiqSuite Development Package. +// +//***************************************************************************** + +#include +#include "am_mcu_apollo.h" // Defines AM_CMSIS_REGS + +//***************************************************************************** +// +// Forward declaration of interrupt handlers. +// +//***************************************************************************** +extern void Reset_Handler(void) __attribute ((naked)); +#if AM_CMSIS_REGS +extern void NMI_Handler(void) __attribute ((weak)); +extern void HardFault_Handler(void) __attribute ((weak)); +extern void MemManage_Handler(void) __attribute ((weak, alias ("HardFault_Handler"))); +extern void BusFault_Handler(void) __attribute ((weak, alias ("HardFault_Handler"))); +extern void UsageFault_Handler(void) __attribute ((weak, alias ("HardFault_Handler"))); +extern void SecureFault_Handler(void) __attribute ((weak)); +extern void SVC_Handler(void) __attribute ((weak, alias ("am_default_isr"))); +extern void DebugMon_Handler(void) __attribute ((weak, alias ("am_default_isr"))); +extern void PendSV_Handler(void) __attribute ((weak, alias ("am_default_isr"))); +extern void SysTick_Handler(void) __attribute ((weak, alias ("am_default_isr"))); +#else // AM_CMSIS_REGS +extern void am_nmi_isr(void) __attribute ((weak)); +extern void am_fault_isr(void) __attribute ((weak)); +extern void am_mpufault_isr(void) __attribute ((weak, alias ("am_fault_isr"))); +extern void am_busfault_isr(void) __attribute ((weak, alias ("am_fault_isr"))); +extern void am_usagefault_isr(void) __attribute ((weak, alias ("am_fault_isr"))); +extern void am_svcall_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_debugmon_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_pendsv_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_systick_isr(void) __attribute ((weak, alias ("am_default_isr"))); +#endif // AM_CMSIS_REGS + +extern void am_brownout_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_watchdog_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_rtc_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_vcomp_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_ioslave_ios_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_ioslave_acc_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_iomaster0_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_iomaster1_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_iomaster2_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_iomaster3_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_iomaster4_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_iomaster5_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_ble_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_gpio_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_ctimer_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_uart_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_uart1_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_scard_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_adc_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_pdm_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_mspi_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr0_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr1_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr2_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr3_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr4_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr5_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr6_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_stimer_cmpr7_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_clkgen_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_software0_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_software1_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_software2_isr(void) __attribute ((weak, alias ("am_default_isr"))); +extern void am_software3_isr(void) __attribute ((weak, alias ("am_default_isr"))); + +extern void am_default_isr(void) __attribute ((weak)); + +//***************************************************************************** +// +// The entry point for the application. +// +//***************************************************************************** +extern int main(void); + +//***************************************************************************** +// +// Reserve space for the system stack. +// +//***************************************************************************** +__attribute__ ((section(".stack"))) +static uint32_t g_pui32Stack[20*1024]; + +//***************************************************************************** +// +// The vector table. Note that the proper constructs must be placed on this to +// ensure that it ends up at physical address 0x0000.0000. +// +// Note: Aliasing and weakly exporting am_mpufault_isr, am_busfault_isr, and +// am_usagefault_isr does not work if am_fault_isr is defined externally. +// Therefore, we'll explicitly use am_fault_isr in the table for those vectors. +// +//***************************************************************************** +__attribute__ ((section(".isr_vector"))) +void (* const g_am_pfnVectors[])(void) = +{ + (void (*)(void))((uint32_t)g_pui32Stack + sizeof(g_pui32Stack)), + // The initial stack pointer +#if AM_CMSIS_REGS + Reset_Handler, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + HardFault_Handler, // The MemManage_Handler + HardFault_Handler, // The BusFault_Handler + HardFault_Handler, // The UsageFault_Handler + SecureFault_Handler, // The SecureFault_Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + DebugMon_Handler, // Debug monitor handler + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler +#else // AM_CMSIS_REGS + am_reset_isr, // The reset handler + am_nmi_isr, // The NMI handler + am_fault_isr, // The hard fault handler + am_fault_isr, // The MPU fault handler + am_fault_isr, // The bus fault handler + am_fault_isr, // The usage fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + am_svcall_isr, // SVCall handle + am_debugmon_isr, // Debug monitor handler + 0, // Reserved + am_pendsv_isr, // The PendSV handler + am_systick_isr, // The SysTick handler +#endif // AM_CMSIS_REGS + + // + // Peripheral Interrupts + // + am_brownout_isr, // 0: Brownout (rstgen) + am_watchdog_isr, // 1: Watchdog + am_rtc_isr, // 2: RTC + am_vcomp_isr, // 3: Voltage Comparator + am_ioslave_ios_isr, // 4: I/O Slave general + am_ioslave_acc_isr, // 5: I/O Slave access + am_iomaster0_isr, // 6: I/O Master 0 + am_iomaster1_isr, // 7: I/O Master 1 + am_iomaster2_isr, // 8: I/O Master 2 + am_iomaster3_isr, // 9: I/O Master 3 + am_iomaster4_isr, // 10: I/O Master 4 + am_iomaster5_isr, // 11: I/O Master 5 + am_ble_isr, // 12: BLEIF + am_gpio_isr, // 13: GPIO + am_ctimer_isr, // 14: CTIMER + am_uart_isr, // 15: UART0 + am_uart1_isr, // 16: UART1 + am_scard_isr, // 17: SCARD + am_adc_isr, // 18: ADC + am_pdm_isr, // 19: PDM + am_mspi_isr, // 20: MSPI + am_default_isr, // 21: reserved + am_stimer_isr, // 22: SYSTEM TIMER + am_stimer_cmpr0_isr, // 23: SYSTEM TIMER COMPARE0 + am_stimer_cmpr1_isr, // 24: SYSTEM TIMER COMPARE1 + am_stimer_cmpr2_isr, // 25: SYSTEM TIMER COMPARE2 + am_stimer_cmpr3_isr, // 26: SYSTEM TIMER COMPARE3 + am_stimer_cmpr4_isr, // 27: SYSTEM TIMER COMPARE4 + am_stimer_cmpr5_isr, // 28: SYSTEM TIMER COMPARE5 + am_stimer_cmpr6_isr, // 29: SYSTEM TIMER COMPARE6 + am_stimer_cmpr7_isr, // 30: SYSTEM TIMER COMPARE7 + am_clkgen_isr, // 31: CLKGEN + am_software0_isr, // 32: SOFTWARE0 + am_software1_isr, // 33: SOFTWARE1 + am_software2_isr, // 34: SOFTWARE2 + am_software3_isr // 35: SOFTWARE3 +}; + +//****************************************************************************** +// +// Place code immediately following vector table. +// +//****************************************************************************** +//****************************************************************************** +// +// The Patch table. +// +//****************************************************************************** +__attribute__ ((section(".patch"))) +uint32_t const __Patchable[] = +{ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +//***************************************************************************** +// +// The following are constructs created by the linker, indicating where the +// the "data" and "bss" segments reside in memory. The initializers for the +// "data" segment resides immediately following the "text" segment. +// +//***************************************************************************** +extern uint32_t _etext; +extern uint32_t _sdata; +extern uint32_t _edata; +extern uint32_t _sbss; +extern uint32_t _ebss; + +//***************************************************************************** +// +// This is the code that gets called when the processor first starts execution +// following a reset event. Only the absolutely necessary set is performed, +// after which the application supplied entry() routine is called. +// +//***************************************************************************** +#if defined(__GNUC_STDC_INLINE__) +void +Reset_Handler(void) +{ + // + // Set the vector table pointer. + // + __asm(" ldr r0, =0xE000ED08\n" + " ldr r1, =g_am_pfnVectors\n" + " str r1, [r0]"); + + // + // Set the stack pointer. + // + __asm(" ldr sp, [r1]"); +#ifndef NOFPU + // + // Enable the FPU. + // + __asm("ldr r0, =0xE000ED88\n" + "ldr r1,[r0]\n" + "orr r1,#(0xF << 20)\n" + "str r1,[r0]\n" + "dsb\n" + "isb\n"); +#endif + // + // Copy the data segment initializers from flash to SRAM. + // + __asm(" ldr r0, =_init_data\n" + " ldr r1, =_sdata\n" + " ldr r2, =_edata\n" + "copy_loop:\n" + " ldr r3, [r0], #4\n" + " str r3, [r1], #4\n" + " cmp r1, r2\n" + " blt copy_loop\n"); + // + // Zero fill the bss segment. + // + __asm(" ldr r0, =_sbss\n" + " ldr r1, =_ebss\n" + " mov r2, #0\n" + "zero_loop:\n" + " cmp r0, r1\n" + " it lt\n" + " strlt r2, [r0], #4\n" + " blt zero_loop"); + + // + // Call the application's entry point. + // + main(); + + // + // If main returns then execute a break point instruction + // + __asm(" bkpt "); +} +#else +#error GNU STDC inline not supported. +#endif + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a NMI. This +// simply enters an infinite loop, preserving the system state for examination +// by a debugger. +// +//***************************************************************************** +void +#if AM_CMSIS_REGS +NMI_Handler(void) +#else // AM_CMSIS_REGS +am_nmi_isr(void) +#endif // AM_CMSIS_REGS +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives a fault +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +void +#if AM_CMSIS_REGS +HardFault_Handler(void) +#else // AM_CMSIS_REGS +am_fault_isr(void) +#endif // AM_CMSIS_REGS +{ + // + // Go into an infinite loop. + // + while(1) + { + } +} + +//***************************************************************************** +// +// This is the code that gets called when the processor receives an unexpected +// interrupt. This simply enters an infinite loop, preserving the system state +// for examination by a debugger. +// +//***************************************************************************** +void +am_default_isr(void) +{ + // + // Go into an infinite loop. + // + while(1) + { + } +}