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Merge pull request #1338 from fpistm/UpdateF4
Update STM32F4 HAL and CMSIS drivers
2 parents 236ad05 + 01ad3ee commit 5ad0fe8

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172 files changed

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‎CI/utils/patch/HAL/F4/0001-F4-Fix-HAL_RCC_USART3-definition-for-STM32F412Cx.patch

Lines changed: 0 additions & 104 deletions
This file was deleted.

‎CI/utils/patch/HAL/F4/0001-F4-Fix-IS_ADC_CHANNEL.patch

Lines changed: 0 additions & 55 deletions
This file was deleted.

‎libraries/SrcWrapper/src/HAL/stm32yyxx_hal_fmpsmbus_ex.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
#ifdef STM32F4xx
2+
#include "stm32f4xx_hal_fmpsmbus_ex.c"
3+
#endif

‎system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2282,7 +2282,7 @@ typedef struct
22822282
/******************************************************************************/
22832283
/******************* Bits definition for FLASH_ACR register *****************/
22842284
#define FLASH_ACR_LATENCY_Pos (0U)
2285-
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
2285+
#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
22862286
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
22872287
#define FLASH_ACR_LATENCY_0WS 0x00000000U
22882288
#define FLASH_ACR_LATENCY_1WS 0x00000001U
@@ -2293,6 +2293,7 @@ typedef struct
22932293
#define FLASH_ACR_LATENCY_6WS 0x00000006U
22942294
#define FLASH_ACR_LATENCY_7WS 0x00000007U
22952295

2296+
22962297
#define FLASH_ACR_PRFTEN_Pos (8U)
22972298
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
22982299
#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
@@ -2538,7 +2539,7 @@ typedef struct
25382539
#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
25392540
#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
25402541
#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
2541-
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS
2542+
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
25422543
#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
25432544
#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
25442545
#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
@@ -2569,7 +2570,7 @@ typedef struct
25692570
#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
25702571
#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
25712572
#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
2572-
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk
2573+
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
25732574
#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
25742575
#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
25752576
#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1

‎system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2282,7 +2282,7 @@ typedef struct
22822282
/******************************************************************************/
22832283
/******************* Bits definition for FLASH_ACR register *****************/
22842284
#define FLASH_ACR_LATENCY_Pos (0U)
2285-
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
2285+
#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
22862286
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
22872287
#define FLASH_ACR_LATENCY_0WS 0x00000000U
22882288
#define FLASH_ACR_LATENCY_1WS 0x00000001U
@@ -2293,6 +2293,7 @@ typedef struct
22932293
#define FLASH_ACR_LATENCY_6WS 0x00000006U
22942294
#define FLASH_ACR_LATENCY_7WS 0x00000007U
22952295

2296+
22962297
#define FLASH_ACR_PRFTEN_Pos (8U)
22972298
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
22982299
#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
@@ -2538,7 +2539,7 @@ typedef struct
25382539
#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
25392540
#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
25402541
#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
2541-
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS
2542+
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
25422543
#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
25432544
#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
25442545
#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
@@ -2569,7 +2570,7 @@ typedef struct
25692570
#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
25702571
#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
25712572
#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
2572-
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk
2573+
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
25732574
#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
25742575
#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
25752576
#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1

‎system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6374,7 +6374,7 @@ typedef struct
63746374
/******************************************************************************/
63756375
/******************* Bits definition for FLASH_ACR register *****************/
63766376
#define FLASH_ACR_LATENCY_Pos (0U)
6377-
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
6377+
#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
63786378
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
63796379
#define FLASH_ACR_LATENCY_0WS 0x00000000U
63806380
#define FLASH_ACR_LATENCY_1WS 0x00000001U
@@ -6385,6 +6385,7 @@ typedef struct
63856385
#define FLASH_ACR_LATENCY_6WS 0x00000006U
63866386
#define FLASH_ACR_LATENCY_7WS 0x00000007U
63876387

6388+
63886389
#define FLASH_ACR_PRFTEN_Pos (8U)
63896390
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
63906391
#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
@@ -7822,7 +7823,7 @@ typedef struct
78227823
#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
78237824
#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
78247825
#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
7825-
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS
7826+
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
78267827
#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
78277828
#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
78287829
#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
@@ -7853,7 +7854,7 @@ typedef struct
78537854
#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
78547855
#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
78557856
#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
7856-
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk
7857+
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
78577858
#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
78587859
#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
78597860
#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1

‎system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6674,7 +6674,7 @@ typedef struct
66746674
/******************************************************************************/
66756675
/******************* Bits definition for FLASH_ACR register *****************/
66766676
#define FLASH_ACR_LATENCY_Pos (0U)
6677-
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
6677+
#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
66786678
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
66796679
#define FLASH_ACR_LATENCY_0WS 0x00000000U
66806680
#define FLASH_ACR_LATENCY_1WS 0x00000001U
@@ -6685,6 +6685,7 @@ typedef struct
66856685
#define FLASH_ACR_LATENCY_6WS 0x00000006U
66866686
#define FLASH_ACR_LATENCY_7WS 0x00000007U
66876687

6688+
66886689
#define FLASH_ACR_PRFTEN_Pos (8U)
66896690
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
66906691
#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
@@ -8122,7 +8123,7 @@ typedef struct
81228123
#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
81238124
#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
81248125
#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
8125-
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS
8126+
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
81268127
#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
81278128
#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
81288129
#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
@@ -8153,7 +8154,7 @@ typedef struct
81538154
#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
81548155
#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
81558156
#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
8156-
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk
8157+
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
81578158
#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
81588159
#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
81598160
#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1

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