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Merge pull request #1341 from fpistm/updateL5
 Update STM32L5 HAL and CMSIS drivers
2 parents 01a1aa3 + dbc5416 commit fbb7951

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‎cores/arduino/stm32/LL/stm32yyxx_ll.h

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@@ -28,6 +28,7 @@
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#include "stm32yyxx_ll_hrtim.h"
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#include "stm32yyxx_ll_hsem.h"
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#include "stm32yyxx_ll_i2c.h"
31+
#include "stm32yyxx_ll_icache.h"
3132
#include "stm32yyxx_ll_ipcc.h"
3233
#include "stm32yyxx_ll_iwdg.h"
3334
#include "stm32yyxx_ll_lptim.h"

‎cores/arduino/stm32/LL/stm32yyxx_ll_icache.h

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@@ -0,0 +1,12 @@
1+
#ifndef _STM32YYXX_LL_ICACHE_H_
2+
#define _STM32YYXX_LL_ICACHE_H_
3+
/* LL raised several warnings, ignore them */
4+
#pragma GCC diagnostic push
5+
#pragma GCC diagnostic ignored "-Wunused-parameter"
6+
#pragma GCC diagnostic ignored "-Wstrict-aliasing"
7+
8+
#ifdef STM32L5xx
9+
#include "stm32l5xx_ll_icache.h"
10+
#endif
11+
#pragma GCC diagnostic pop
12+
#endif /* _STM32YYXX_LL_ICACHE_H_ */

‎libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c

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@@ -1,3 +1,6 @@
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#ifdef STM32L0xx
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#include "stm32l0xx_hal_smbus_ex.c"
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#endif
4+
#ifdef STM32L5xx
5+
#include "stm32l5xx_hal_smbus_ex.c"
6+
#endif

‎libraries/SrcWrapper/src/LL/stm32yyxx_ll_icache.c

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@@ -0,0 +1,3 @@
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#ifdef STM32L5xx
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#include "stm32l5xx_ll_icache.c"
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#endif

‎system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l552xx.h

Lines changed: 19 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -164,8 +164,8 @@ typedef enum
164164
HASH_IRQn = 96, /*!< HASH global interrupt */
165165
LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */
166166
SPI3_IRQn = 99, /*!< SPI3 global interrupt */
167-
I2C4_EV_IRQn = 100, /*!< I2C4 Event interrupt */
168-
I2C4_ER_IRQn = 101, /*!< I2C4 Error interrupt */
167+
I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */
168+
I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */
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DFSDM1_FLT0_IRQn = 102, /*!< DFSDM1 Filter 0 global interrupt */
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DFSDM1_FLT1_IRQn = 103, /*!< DFSDM1 Filter 1 global interrupt */
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DFSDM1_FLT2_IRQn = 104, /*!< DFSDM1 Filter 2 global interrupt */
@@ -1022,7 +1022,9 @@ typedef struct
10221022
__IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */
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__IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
10241024
__IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
1025-
uint32_t RESERVED1[47];/*!< Reserved, Address offset: 0x54 -- 0xFC */
1025+
uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */
1026+
__IO uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x50 */
1027+
uint32_t RESERVED2[43];/*!< Reserved, Address offset: 0x54 -- 0xFC */
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__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
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__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
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__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
@@ -13974,9 +13976,20 @@ typedef struct
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#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk
1397513977

1397613978
/******************** Bits definition for TAMP_COUNTR register ***************/
13977-
#define TAMP_COUNTR_Pos (16U)
13978-
#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
13979-
#define TAMP_COUNTR TAMP_COUNTR_Msk
13979+
#define TAMP_COUNTR_Pos (16U)
13980+
#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
13981+
#define TAMP_COUNTR TAMP_COUNTR_Msk
13982+
13983+
/******************** Bits definition for TAMP_CFGR register *****************/
13984+
#define TAMP_CFGR_TMONEN_Pos (1U)
13985+
#define TAMP_CFGR_TMONEN_Msk (0x1UL << TAMP_CFGR_TMONEN_Pos) /*!< 0x00000002 */
13986+
#define TAMP_CFGR_TMONEN TAMP_CFGR_TMONEN_Msk
13987+
#define TAMP_CFGR_VMONEN_Pos (2U)
13988+
#define TAMP_CFGR_VMONEN_Msk (0x1UL << TAMP_CFGR_VMONEN_Pos) /*!< 0x00000004 */
13989+
#define TAMP_CFGR_VMONEN TAMP_CFGR_VMONEN_Msk
13990+
#define TAMP_CFGR_WUTMONEN_Pos (3U)
13991+
#define TAMP_CFGR_WUTMONEN_Msk (0x1UL << TAMP_CFGR_WUTMONEN_Pos) /*!< 0x00000008 */
13992+
#define TAMP_CFGR_WUTMONEN TAMP_CFGR_WUTMONEN_Msk
1398013993

1398113994
/******************** Bits definition for TAMP_BKP0R register ***************/
1398213995
#define TAMP_BKP0R_Pos (0U)

‎system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l562xx.h

Lines changed: 19 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -166,8 +166,8 @@ typedef enum
166166
PKA_IRQn = 97, /*!< PKA global interrupt */
167167
LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */
168168
SPI3_IRQn = 99, /*!< SPI3 global interrupt */
169-
I2C4_EV_IRQn = 100, /*!< I2C4 Event interrupt */
170-
I2C4_ER_IRQn = 101, /*!< I2C4 Error interrupt */
169+
I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */
170+
I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */
171171
DFSDM1_FLT0_IRQn = 102, /*!< DFSDM1 Filter 0 global interrupt */
172172
DFSDM1_FLT1_IRQn = 103, /*!< DFSDM1 Filter 1 global interrupt */
173173
DFSDM1_FLT2_IRQn = 104, /*!< DFSDM1 Filter 2 global interrupt */
@@ -1096,7 +1096,9 @@ typedef struct
10961096
__IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */
10971097
__IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
10981098
__IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
1099-
uint32_t RESERVED1[47];/*!< Reserved, Address offset: 0x54 -- 0xFC */
1099+
uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */
1100+
__IO uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x50 */
1101+
uint32_t RESERVED2[43];/*!< Reserved, Address offset: 0x54 -- 0xFC */
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__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
11011103
__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
11021104
__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
@@ -14713,9 +14715,20 @@ typedef struct
1471314715
#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk
1471414716

1471514717
/******************** Bits definition for TAMP_COUNTR register ***************/
14716-
#define TAMP_COUNTR_Pos (16U)
14717-
#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
14718-
#define TAMP_COUNTR TAMP_COUNTR_Msk
14718+
#define TAMP_COUNTR_Pos (16U)
14719+
#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
14720+
#define TAMP_COUNTR TAMP_COUNTR_Msk
14721+
14722+
/******************** Bits definition for TAMP_CFGR register *****************/
14723+
#define TAMP_CFGR_TMONEN_Pos (1U)
14724+
#define TAMP_CFGR_TMONEN_Msk (0x1UL << TAMP_CFGR_TMONEN_Pos) /*!< 0x00000002 */
14725+
#define TAMP_CFGR_TMONEN TAMP_CFGR_TMONEN_Msk
14726+
#define TAMP_CFGR_VMONEN_Pos (2U)
14727+
#define TAMP_CFGR_VMONEN_Msk (0x1UL << TAMP_CFGR_VMONEN_Pos) /*!< 0x00000004 */
14728+
#define TAMP_CFGR_VMONEN TAMP_CFGR_VMONEN_Msk
14729+
#define TAMP_CFGR_WUTMONEN_Pos (3U)
14730+
#define TAMP_CFGR_WUTMONEN_Msk (0x1UL << TAMP_CFGR_WUTMONEN_Pos) /*!< 0x00000008 */
14731+
#define TAMP_CFGR_WUTMONEN TAMP_CFGR_WUTMONEN_Msk
1471914732

1472014733
/******************** Bits definition for TAMP_BKP0R register ***************/
1472114734
#define TAMP_BKP0R_Pos (0U)

‎system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l5xx.h

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@@ -79,7 +79,7 @@
7979
*/
8080
#define __STM32L5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
8181
#define __STM32L5_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
82-
#define __STM32L5_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
82+
#define __STM32L5_CMSIS_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
8383
#define __STM32L5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
8484
#define __STM32L5_CMSIS_VERSION ((__STM32L5_CMSIS_VERSION_MAIN << 24U)\
8585
|(__STM32L5_CMSIS_VERSION_SUB1 << 16U)\

‎system/Drivers/CMSIS/Device/ST/STM32L5xx/README.md

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@@ -31,7 +31,8 @@ CMSIS Device L5 | CMSIS Core | Was delivered in the full MCU package
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--------------- | ---------- | -------------------------------------
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Tag v1.0.0 | Tag v5.4.0_cm33 | Tag v1.1.0
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Tag v1.0.2 | Tag v5.4.0_cm33 | Tag v1.2.0
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Tag v1.0.3 | Tag v5.6.0_cm33 | Tag v1.3.0 (and following, if any, till next tag)
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Tag v1.0.3 | Tag v5.6.0_cm33 | Tag v1.3.0
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Tag v1.0.4 | Tag v5.6.0_cm33 | Tag v1.4.0 (and following, if any, till next tag)
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3637
The full **STM32CubeL5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeL5).
3738

‎system/Drivers/CMSIS/Device/ST/STM32L5xx/Release_Notes.html

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span.underline{text-decoration: underline;}
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div.column{display: inline-block; vertical-align: top; width: 50%;}
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</style>
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<link rel="stylesheet" href="_htmresc/mini-st.css" />
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<link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
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<!--[if lt IE 9]>
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<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
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<![endif]-->
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<link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
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</head>
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<body>
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<div class="row">
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<div class="col-sm-12 col-lg-4">
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<div class="card fluid">
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<div class="sectione dark">
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<center>
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<h1 id="release-notes-for-stm32l5xx-cmsis"><small>Release Notes for</small> <strong>STM32L5xx CMSIS</strong></h1>
24+
<h1 id="release-notes-for">Release Notes for</h1>
25+
<h1 id="stm32l5xx-cmsis"><mark>STM32L5xx CMSIS</mark></h1>
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<p>Copyright © 2019 STMicroelectronics<br />
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</p>
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<a href="https://www.st.com" class="logo"><img src="./_htmresc/st_logo.png" alt="ST logo" /></a>
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<a href="https://www.st.com" class="logo"><img src="./_htmresc/st_logo_2020.png" alt="ST logo" /></a>
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</center>
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</div>
31-
</div>
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<h1 id="license">License</h1>
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<p>This software component is licensed by ST under Apache-2.0 license, the "License"; You may not use this component except in compliance with the License. You may obtain a copy of the License at:</p>
3432
<p><a href="https://opensource.org/licenses/Apache-2.0">Apache License v2.0</a></p>
@@ -48,11 +46,44 @@ <h1 id="purpose">Purpose</h1>
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<div class="col-sm-12 col-lg-8">
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<h1 id="update-history">Update History</h1>
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<div class="collapse">
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<input type="checkbox" id="collapse-section4" checked aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.0.3 / 26-June-2020</strong></label>
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<input type="checkbox" id="collapse-section5" checked aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.0.4 / 10-February-2021</strong></label>
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<div>
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<h2 id="main-changes">Main Changes</h2>
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<p><strong>Fourth release</strong></p>
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<p><strong>Maintenance release</strong></p>
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<h2 id="contents">Contents</h2>
54+
<p>Maintenance release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
55+
<ul>
56+
<li>stm32l552xx.h and stm32l562xx.h updates
57+
<ul>
58+
<li>Add TAMP_CFGR configuration register and definitions for TMONEN, VMONEN and WUTMONEN monitoring functions</li>
59+
<li>Fix I2C4_EV_IRQn and I2C4_ER_IRQn order in IRQn_Type</li>
60+
</ul></li>
61+
</ul>
62+
<h2 id="notes">Notes</h2>
63+
<p>Reminder:</p>
64+
<ul>
65+
<li>When TrustZone is enabled in the system (Flash option bit TZEN=1)
66+
<ul>
67+
<li>template device partition_stm32l552xx.h or partition_stm32l562xx.h file must be copied and optionally updated in user application secure project to configure the system (SAU, interrupts, core).</li>
68+
<li>default Security Attribute Unit (SAU) configuration in the partition_stm32l552xx.h and partition_stm32l562xx.h:
69+
<ul>
70+
<li>SAU region 0: 0x0C03E000-0x0C03FFFF (Secure, Non-Secure Callable)</li>
71+
<li>SAU region 1: 0x08040000-0x0807FFFF (Non-Secure FLASH Bank2 (256 Kbytes))</li>
72+
<li>SAU region 2: 0x20018000-0x2003FFFF (Non-Secure RAM (2nd half SRAM1 + SRAM2 (160 Kbytes)))</li>
73+
<li>SAU region 3: 0x40000000-0x4FFFFFFF (Non-Secure Peripheral mapped memory)</li>
74+
<li>SAU region 4: 0x60000000-0x9FFFFFFF (Non-Secure external memories)</li>
75+
<li>SAU region 5: 0x0BF90000-0x0BFA8FFF (Non-Secure System memory)</li>
76+
</ul></li>
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</ul></li>
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</ul>
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</div>
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</div>
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<div class="collapse">
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<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.0.3 / 26-June-2020</strong></label>
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<div>
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<h2 id="main-changes-1">Main Changes</h2>
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<p><strong>Fourth release</strong></p>
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<h2 id="contents-1">Contents</h2>
5687
<p>Fourth release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
5788
<ul>
5889
<li>stm32l552xx.h and stm32l562xx.h updates
@@ -68,7 +99,7 @@ <h2 id="contents">Contents</h2>
6899
<li>Add README.md and License.md files for GitHub publication</li>
69100
<li>Misspelled words corrections in driver descriptions</li>
70101
</ul>
71-
<h2 id="notes">Notes</h2>
102+
<h2 id="notes-1">Notes</h2>
72103
<p>Reminder:</p>
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<ul>
74105
<li>When TrustZone is enabled in the system (Flash option bit TZEN=1)
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<div class="collapse">
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<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.0.2 / 12-February-2020</strong></label>
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<div>
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<h2 id="main-changes-1">Main Changes</h2>
124+
<h2 id="main-changes-2">Main Changes</h2>
94125
<p><strong>Third release</strong></p>
95-
<h2 id="contents-1">Contents</h2>
126+
<h2 id="contents-2">Contents</h2>
96127
<p>Third official release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
97128
<ul>
98129
<li>stm32l552xx.h and stm32l562xx.h updates
@@ -102,7 +133,7 @@ <h2 id="contents-1">Contents</h2>
102133
<li>Align DBGMCU_APB2FZR register and bits definitions with RM0438</li>
103134
</ul></li>
104135
</ul>
105-
<h2 id="notes-1">Notes</h2>
136+
<h2 id="notes-2">Notes</h2>
106137
<p>Reminder:</p>
107138
<ul>
108139
<li>When TrustZone is enabled in the system (Flash option bit TZEN=1)
@@ -124,17 +155,17 @@ <h2 id="notes-1">Notes</h2>
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<div class="collapse">
125156
<input type="checkbox" id="collapse-section2" unchecked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.0.1 / 22-January-2020</strong></label>
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<div>
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<h2 id="main-changes-2">Main Changes</h2>
158+
<h2 id="main-changes-3">Main Changes</h2>
128159
<p><strong>Second release</strong></p>
129-
<h2 id="contents-2">Contents</h2>
160+
<h2 id="contents-3">Contents</h2>
130161
<p>Second official release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
131162
<ul>
132163
<li>Templates system_stm32l5xx.c, system_stm32l5xx_s.c and system_stm32l5xx_ns.c
133164
<ul>
134165
<li>Add vector table relocation capability with conditional USER_VECT_TAB_ADDRESS</li>
135166
</ul></li>
136167
</ul>
137-
<h2 id="notes-2">Notes</h2>
168+
<h2 id="notes-3">Notes</h2>
138169
<p>Reminder:</p>
139170
<ul>
140171
<li>When TrustZone is enabled in the system (Flash option bit TZEN=1)
@@ -156,9 +187,9 @@ <h2 id="notes-2">Notes</h2>
156187
<div class="collapse">
157188
<input type="checkbox" id="collapse-section1" unchecked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 13-December-2019</strong></label>
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<div>
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<h2 id="main-changes-3">Main Changes</h2>
190+
<h2 id="main-changes-4">Main Changes</h2>
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<p><strong>First release</strong></p>
161-
<h2 id="contents-3">Contents</h2>
192+
<h2 id="contents-4">Contents</h2>
162193
<p>First official release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
163194
<ul>
164195
<li>Templates
@@ -176,7 +207,7 @@ <h2 id="contents-3">Contents</h2>
176207
<li>Linker files for 256 and 512 Kbytes Flash device configurations</li>
177208
</ul></li>
178209
</ul>
179-
<h2 id="notes-3">Notes</h2>
210+
<h2 id="notes-4">Notes</h2>
180211
<p>When TrustZone is enabled in the system (Flash option bit TZEN=1), template device partition_stm32l552xx.h or partition_stm32l562xx.h file must be copied and optionally updated in user application secure project to configure the system (SAU, interrupts, core)</p>
181212
</div>
182213
</div>

‎system/Drivers/CMSIS/Device/ST/STM32L5xx/_htmresc/Add button.svg

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