diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h index cc84ebf468..309ac09c5c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h @@ -4880,7 +4880,6 @@ typedef struct #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ - /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface */ @@ -5718,8 +5717,6 @@ typedef struct ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM15)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ @@ -5921,15 +5918,15 @@ typedef struct #define ADC1_2_IRQn ADC1_IRQn #define USBWakeUp_IRQn CEC_IRQn #define OTG_FS_WKUP_IRQn CEC_IRQn -#define TIM9_IRQn TIM1_BRK_TIM15_IRQn -#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn #define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn -#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn +#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn +#define TIM9_IRQn TIM1_BRK_TIM15_IRQn #define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn #define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn +#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn +#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn #define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn #define TIM10_IRQn TIM1_UP_TIM16_IRQn -#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn #define TIM6_IRQn TIM6_DAC_IRQn @@ -5937,15 +5934,15 @@ typedef struct #define ADC1_2_IRQHandler ADC1_IRQHandler #define USBWakeUp_IRQHandler CEC_IRQHandler #define OTG_FS_WKUP_IRQHandler CEC_IRQHandler -#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler -#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler -#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler +#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler +#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler #define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler #define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler +#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler +#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler #define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler #define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler -#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler #define TIM6_IRQHandler TIM6_DAC_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h index 006e5e7abf..31b8fe328c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h @@ -5394,7 +5394,6 @@ typedef struct #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ - /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface */ @@ -6283,8 +6282,6 @@ typedef struct ((INSTANCE) == TIM12) || \ ((INSTANCE) == TIM15)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ @@ -6522,17 +6519,17 @@ typedef struct /* Aliases for __IRQn */ #define ADC1_2_IRQn ADC1_IRQn -#define USBWakeUp_IRQn CEC_IRQn #define OTG_FS_WKUP_IRQn CEC_IRQn +#define USBWakeUp_IRQn CEC_IRQn #define TIM8_BRK_IRQn TIM12_IRQn #define TIM8_BRK_TIM12_IRQn TIM12_IRQn -#define TIM8_UP_TIM13_IRQn TIM13_IRQn #define TIM8_UP_IRQn TIM13_IRQn -#define TIM8_TRG_COM_IRQn TIM14_IRQn +#define TIM8_UP_TIM13_IRQn TIM13_IRQn #define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn +#define TIM8_TRG_COM_IRQn TIM14_IRQn #define TIM9_IRQn TIM1_BRK_TIM15_IRQn -#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn #define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn +#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn #define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn #define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn @@ -6544,17 +6541,17 @@ typedef struct /* Aliases for __IRQHandler */ #define ADC1_2_IRQHandler ADC1_IRQHandler -#define USBWakeUp_IRQHandler CEC_IRQHandler #define OTG_FS_WKUP_IRQHandler CEC_IRQHandler +#define USBWakeUp_IRQHandler CEC_IRQHandler #define TIM8_BRK_IRQHandler TIM12_IRQHandler #define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler -#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler #define TIM8_UP_IRQHandler TIM13_IRQHandler -#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler +#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler #define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler +#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler #define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler -#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler #define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler +#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler #define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler #define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101x6.h b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101x6.h index 9ddcc7d332..2f54e2ee15 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101x6.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101x6.h @@ -4412,12 +4412,10 @@ typedef struct #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ -/****************** Bit definition for SPI_I2SCFGR register *****************/ #define SPI_I2SCFGR_I2SMOD_Pos (11U) #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ - /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface */ @@ -5170,8 +5168,6 @@ typedef struct (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3)) diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xb.h b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xb.h index 086e781169..834eeec4a3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xb.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xb.h @@ -4474,12 +4474,10 @@ typedef struct #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ -/****************** Bit definition for SPI_I2SCFGR register *****************/ #define SPI_I2SCFGR_I2SMOD_Pos (11U) #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ - /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface */ @@ -5279,8 +5277,6 @@ typedef struct ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xe.h b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xe.h index 55fee49c44..a1ac234dcf 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xe.h @@ -514,6 +514,7 @@ typedef struct __IO uint32_t RXCRCR; __IO uint32_t TXCRCR; __IO uint32_t I2SCFGR; + __IO uint32_t I2SPR; } SPI_TypeDef; /** @@ -5283,6 +5284,10 @@ typedef struct /* Serial Peripheral Interface */ /* */ /******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie) + */ +#define SPI_I2S_SUPPORT /*!< I2S support */ #define SPI_CRC_ERROR_WORKAROUND_FEATURE /******************* Bit definition for SPI_CR1 register ********************/ @@ -5401,10 +5406,52 @@ typedef struct #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ /****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN_Pos (0U) +#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ +#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!< Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN_Pos (1U) +#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ +#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!< DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ +#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ + +#define SPI_I2SCFGR_CKPOL_Pos (3U) +#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ +#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!< steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD_Pos (4U) +#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ +#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!< I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ +#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ + +#define SPI_I2SCFGR_PCMSYNC_Pos (7U) +#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ +#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!< PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG_Pos (8U) +#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ +#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!< I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ +#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ + +#define SPI_I2SCFGR_I2SE_Pos (10U) +#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ +#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!< I2S Enable */ #define SPI_I2SCFGR_I2SMOD_Pos (11U) #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ - +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV_Pos (0U) +#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ +#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!< I2S Linear prescaler */ +#define SPI_I2SPR_ODD_Pos (8U) +#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ +#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!< Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE_Pos (9U) +#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ +#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!< Master Clock Output Enable */ /******************************************************************************/ /* */ @@ -6153,6 +6200,10 @@ typedef struct /******************************* SMBUS Instances ******************************/ #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE +/******************************** I2S Instances *******************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3)) + /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) @@ -6253,8 +6304,6 @@ typedef struct ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xg.h b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xg.h index ff2170f1c6..d992cfb629 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xg.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xg.h @@ -526,6 +526,7 @@ typedef struct __IO uint32_t RXCRCR; __IO uint32_t TXCRCR; __IO uint32_t I2SCFGR; + __IO uint32_t I2SPR; } SPI_TypeDef; /** @@ -5358,6 +5359,10 @@ typedef struct /* Serial Peripheral Interface */ /* */ /******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie) + */ +#define SPI_I2S_SUPPORT /*!< I2S support */ /******************* Bit definition for SPI_CR1 register ********************/ #define SPI_CR1_CPHA_Pos (0U) @@ -5475,10 +5480,52 @@ typedef struct #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ /****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN_Pos (0U) +#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ +#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!< Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN_Pos (1U) +#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ +#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!< DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ +#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ + +#define SPI_I2SCFGR_CKPOL_Pos (3U) +#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ +#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!< steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD_Pos (4U) +#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ +#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!< I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ +#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ + +#define SPI_I2SCFGR_PCMSYNC_Pos (7U) +#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ +#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!< PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG_Pos (8U) +#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ +#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!< I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ +#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ + +#define SPI_I2SCFGR_I2SE_Pos (10U) +#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ +#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!< I2S Enable */ #define SPI_I2SCFGR_I2SMOD_Pos (11U) #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ - +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV_Pos (0U) +#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ +#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!< I2S Linear prescaler */ +#define SPI_I2SPR_ODD_Pos (8U) +#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ +#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!< Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE_Pos (9U) +#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ +#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!< Master Clock Output Enable */ /******************************************************************************/ /* */ @@ -6286,6 +6333,10 @@ typedef struct /******************************* SMBUS Instances ******************************/ #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE +/******************************** I2S Instances *******************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3)) + /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) @@ -6407,8 +6458,6 @@ typedef struct ((INSTANCE) == TIM9) || \ ((INSTANCE) == TIM12)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -6602,18 +6651,18 @@ typedef struct #define TIM1_UP_TIM16_IRQn TIM10_IRQn #define TIM1_UP_IRQn TIM10_IRQn #define TIM1_UP_TIM10_IRQn TIM10_IRQn +#define TIM1_TRG_COM_IRQn TIM11_IRQn #define TIM1_TRG_COM_TIM17_IRQn TIM11_IRQn #define TIM1_TRG_COM_TIM11_IRQn TIM11_IRQn -#define TIM1_TRG_COM_IRQn TIM11_IRQn -#define TIM8_BRK_TIM12_IRQn TIM12_IRQn #define TIM8_BRK_IRQn TIM12_IRQn +#define TIM8_BRK_TIM12_IRQn TIM12_IRQn #define TIM8_UP_TIM13_IRQn TIM13_IRQn #define TIM8_UP_IRQn TIM13_IRQn #define TIM8_TRG_COM_IRQn TIM14_IRQn #define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn #define TIM6_DAC_IRQn TIM6_IRQn -#define TIM1_BRK_IRQn TIM9_IRQn #define TIM1_BRK_TIM15_IRQn TIM9_IRQn +#define TIM1_BRK_IRQn TIM9_IRQn #define TIM1_BRK_TIM9_IRQn TIM9_IRQn @@ -6623,18 +6672,18 @@ typedef struct #define TIM1_UP_TIM16_IRQHandler TIM10_IRQHandler #define TIM1_UP_IRQHandler TIM10_IRQHandler #define TIM1_UP_TIM10_IRQHandler TIM10_IRQHandler +#define TIM1_TRG_COM_IRQHandler TIM11_IRQHandler #define TIM1_TRG_COM_TIM17_IRQHandler TIM11_IRQHandler #define TIM1_TRG_COM_TIM11_IRQHandler TIM11_IRQHandler -#define TIM1_TRG_COM_IRQHandler TIM11_IRQHandler -#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler #define TIM8_BRK_IRQHandler TIM12_IRQHandler +#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler #define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler #define TIM8_UP_IRQHandler TIM13_IRQHandler #define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler #define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler #define TIM6_DAC_IRQHandler TIM6_IRQHandler -#define TIM1_BRK_IRQHandler TIM9_IRQHandler #define TIM1_BRK_TIM15_IRQHandler TIM9_IRQHandler +#define TIM1_BRK_IRQHandler TIM9_IRQHandler #define TIM1_BRK_TIM9_IRQHandler TIM9_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102x6.h b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102x6.h index 6fca114f52..57a59f9054 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102x6.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102x6.h @@ -5531,12 +5531,10 @@ typedef struct #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ -/****************** Bit definition for SPI_I2SCFGR register *****************/ #define SPI_I2SCFGR_I2SMOD_Pos (11U) #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ - /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface */ @@ -6289,8 +6287,6 @@ typedef struct (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3)) diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102xb.h b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102xb.h index 362221b600..59b83ab467 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102xb.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102xb.h @@ -5585,12 +5585,10 @@ typedef struct #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ -/****************** Bit definition for SPI_I2SCFGR register *****************/ #define SPI_I2SCFGR_I2SMOD_Pos (11U) #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ - /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface */ @@ -6389,8 +6387,6 @@ typedef struct ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -6532,20 +6528,20 @@ typedef struct #define ADC1_2_IRQn ADC1_IRQn #define CEC_IRQn USBWakeUp_IRQn #define OTG_FS_WKUP_IRQn USBWakeUp_IRQn -#define CAN1_TX_IRQn USB_HP_IRQn #define USB_HP_CAN1_TX_IRQn USB_HP_IRQn -#define USB_LP_CAN1_RX0_IRQn USB_LP_IRQn +#define CAN1_TX_IRQn USB_HP_IRQn #define CAN1_RX0_IRQn USB_LP_IRQn +#define USB_LP_CAN1_RX0_IRQn USB_LP_IRQn /* Aliases for __IRQHandler */ #define ADC1_2_IRQHandler ADC1_IRQHandler #define CEC_IRQHandler USBWakeUp_IRQHandler #define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler -#define CAN1_TX_IRQHandler USB_HP_IRQHandler #define USB_HP_CAN1_TX_IRQHandler USB_HP_IRQHandler -#define USB_LP_CAN1_RX0_IRQHandler USB_LP_IRQHandler +#define CAN1_TX_IRQHandler USB_HP_IRQHandler #define CAN1_RX0_IRQHandler USB_LP_IRQHandler +#define USB_LP_CAN1_RX0_IRQHandler USB_LP_IRQHandler /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103x6.h b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103x6.h index a98c9ae319..9e6ca9a4de 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103x6.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103x6.h @@ -9128,12 +9128,10 @@ typedef struct #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ -/****************** Bit definition for SPI_I2SCFGR register *****************/ #define SPI_I2SCFGR_I2SMOD_Pos (11U) #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ - /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface */ @@ -9912,8 +9910,6 @@ typedef struct ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ @@ -10051,40 +10047,40 @@ typedef struct /* Aliases for __IRQn */ #define ADC1_IRQn ADC1_2_IRQn -#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn +#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn #define TIM9_IRQn TIM1_BRK_IRQn -#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn #define TIM11_IRQn TIM1_TRG_COM_IRQn +#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn -#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn #define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn +#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn #define TIM10_IRQn TIM1_UP_IRQn #define OTG_FS_WKUP_IRQn USBWakeUp_IRQn #define CEC_IRQn USBWakeUp_IRQn -#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn #define USB_HP_IRQn USB_HP_CAN1_TX_IRQn -#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn +#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn #define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn +#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_2_IRQHandler -#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler +#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler #define TIM9_IRQHandler TIM1_BRK_IRQHandler -#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler #define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler +#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler -#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler #define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler +#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler #define TIM10_IRQHandler TIM1_UP_IRQHandler #define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler #define CEC_IRQHandler USBWakeUp_IRQHandler -#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler #define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler -#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler +#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler #define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler +#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h index b9a6be95a2..c174f47488 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h @@ -9190,12 +9190,10 @@ typedef struct #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ -/****************** Bit definition for SPI_I2SCFGR register *****************/ #define SPI_I2SCFGR_I2SMOD_Pos (11U) #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ - /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface */ @@ -10021,8 +10019,6 @@ typedef struct ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ @@ -10182,40 +10178,40 @@ typedef struct /* Aliases for __IRQn */ #define ADC1_IRQn ADC1_2_IRQn -#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn -#define TIM9_IRQn TIM1_BRK_IRQn #define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn -#define TIM11_IRQn TIM1_TRG_COM_IRQn -#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn +#define TIM9_IRQn TIM1_BRK_IRQn +#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn +#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn +#define TIM11_IRQn TIM1_TRG_COM_IRQn #define TIM10_IRQn TIM1_UP_IRQn -#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn #define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn +#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn #define OTG_FS_WKUP_IRQn USBWakeUp_IRQn #define CEC_IRQn USBWakeUp_IRQn #define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn #define USB_HP_IRQn USB_HP_CAN1_TX_IRQn -#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn #define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn +#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_2_IRQHandler -#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler -#define TIM9_IRQHandler TIM1_BRK_IRQHandler #define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler -#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler -#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler +#define TIM9_IRQHandler TIM1_BRK_IRQHandler +#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler +#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler +#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler #define TIM10_IRQHandler TIM1_UP_IRQHandler -#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler #define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler +#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler #define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler #define CEC_IRQHandler USBWakeUp_IRQHandler #define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler #define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler -#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler #define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler +#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h index 4fe654a153..b0b6b48a8e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h @@ -10583,7 +10583,6 @@ typedef struct #define SPI_I2SCFGR_I2SMOD_Pos (11U) #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ - /****************** Bit definition for SPI_I2SPR register *******************/ #define SPI_I2SPR_I2SDIV_Pos (0U) #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ @@ -11484,8 +11483,6 @@ typedef struct ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8) || \ @@ -11693,20 +11690,20 @@ typedef struct /* Aliases for __IRQn */ #define ADC1_IRQn ADC1_2_IRQn #define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn -#define TIM9_IRQn TIM1_BRK_IRQn #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn +#define TIM9_IRQn TIM1_BRK_IRQn #define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn -#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn #define TIM11_IRQn TIM1_TRG_COM_IRQn +#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn -#define TIM10_IRQn TIM1_UP_IRQn -#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn +#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn +#define TIM10_IRQn TIM1_UP_IRQn #define TIM6_DAC_IRQn TIM6_IRQn -#define TIM12_IRQn TIM8_BRK_IRQn #define TIM8_BRK_TIM12_IRQn TIM8_BRK_IRQn -#define TIM8_TRG_COM_TIM14_IRQn TIM8_TRG_COM_IRQn +#define TIM12_IRQn TIM8_BRK_IRQn #define TIM14_IRQn TIM8_TRG_COM_IRQn +#define TIM8_TRG_COM_TIM14_IRQn TIM8_TRG_COM_IRQn #define TIM8_UP_TIM13_IRQn TIM8_UP_IRQn #define TIM13_IRQn TIM8_UP_IRQn #define CEC_IRQn USBWakeUp_IRQn @@ -11720,20 +11717,20 @@ typedef struct /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_2_IRQHandler #define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler -#define TIM9_IRQHandler TIM1_BRK_IRQHandler #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler +#define TIM9_IRQHandler TIM1_BRK_IRQHandler #define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler -#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler #define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler +#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler -#define TIM10_IRQHandler TIM1_UP_IRQHandler -#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler #define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler +#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler +#define TIM10_IRQHandler TIM1_UP_IRQHandler #define TIM6_DAC_IRQHandler TIM6_IRQHandler -#define TIM12_IRQHandler TIM8_BRK_IRQHandler #define TIM8_BRK_TIM12_IRQHandler TIM8_BRK_IRQHandler -#define TIM8_TRG_COM_TIM14_IRQHandler TIM8_TRG_COM_IRQHandler +#define TIM12_IRQHandler TIM8_BRK_IRQHandler #define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler +#define TIM8_TRG_COM_TIM14_IRQHandler TIM8_TRG_COM_IRQHandler #define TIM8_UP_TIM13_IRQHandler TIM8_UP_IRQHandler #define TIM13_IRQHandler TIM8_UP_IRQHandler #define CEC_IRQHandler USBWakeUp_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xg.h b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xg.h index aa50d62f40..ff797c170d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xg.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xg.h @@ -10652,7 +10652,6 @@ typedef struct #define SPI_I2SCFGR_I2SMOD_Pos (11U) #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ - /****************** Bit definition for SPI_I2SPR register *******************/ #define SPI_I2SPR_I2SDIV_Pos (0U) #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ @@ -11642,8 +11641,6 @@ typedef struct ((INSTANCE) == TIM9) || \ ((INSTANCE) == TIM12)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8) || \ @@ -11878,11 +11875,11 @@ typedef struct #define ADC1_IRQn ADC1_2_IRQn #define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn #define TIM9_IRQn TIM1_BRK_TIM9_IRQn -#define TIM1_BRK_TIM15_IRQn TIM1_BRK_TIM9_IRQn #define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn +#define TIM1_BRK_TIM15_IRQn TIM1_BRK_TIM9_IRQn +#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_TIM11_IRQn #define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn #define TIM11_IRQn TIM1_TRG_COM_TIM11_IRQn -#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_TIM11_IRQn #define TIM10_IRQn TIM1_UP_TIM10_IRQn #define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn #define TIM1_UP_TIM16_IRQn TIM1_UP_TIM10_IRQn @@ -11891,25 +11888,25 @@ typedef struct #define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn #define TIM14_IRQn TIM8_TRG_COM_TIM14_IRQn #define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn -#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn #define TIM13_IRQn TIM8_UP_TIM13_IRQn +#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn #define CEC_IRQn USBWakeUp_IRQn #define OTG_FS_WKUP_IRQn USBWakeUp_IRQn #define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn #define USB_HP_IRQn USB_HP_CAN1_TX_IRQn -#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn #define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn +#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_2_IRQHandler #define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler #define TIM9_IRQHandler TIM1_BRK_TIM9_IRQHandler -#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_TIM9_IRQHandler #define TIM1_BRK_IRQHandler TIM1_BRK_TIM9_IRQHandler +#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_TIM9_IRQHandler +#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler #define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler #define TIM11_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler -#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler #define TIM10_IRQHandler TIM1_UP_TIM10_IRQHandler #define TIM1_UP_IRQHandler TIM1_UP_TIM10_IRQHandler #define TIM1_UP_TIM16_IRQHandler TIM1_UP_TIM10_IRQHandler @@ -11918,14 +11915,14 @@ typedef struct #define TIM8_BRK_IRQHandler TIM8_BRK_TIM12_IRQHandler #define TIM14_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler #define TIM8_TRG_COM_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler -#define TIM8_UP_IRQHandler TIM8_UP_TIM13_IRQHandler #define TIM13_IRQHandler TIM8_UP_TIM13_IRQHandler +#define TIM8_UP_IRQHandler TIM8_UP_TIM13_IRQHandler #define CEC_IRQHandler USBWakeUp_IRQHandler #define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler #define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler #define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler -#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler #define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler +#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f105xc.h b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f105xc.h index a051a0639f..b90c1072b2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f105xc.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f105xc.h @@ -1250,6 +1250,11 @@ typedef struct /* Reset and Clock Control */ /* */ /******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie) + */ +#define RCC_PLL2_SUPPORT /*!< Support PLL2 */ +#define RCC_PLLI2S_SUPPORT /******************** Bit definition for RCC_CR register ********************/ #define RCC_CR_HSION_Pos (0U) @@ -1283,11 +1288,6 @@ typedef struct #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ -/* - * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie) - */ -#define RCC_PLL2_SUPPORT /*!< Support PLL2 */ - #define RCC_CR_PLL2ON_Pos (26U) #define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */ #define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */ @@ -1295,11 +1295,6 @@ typedef struct #define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */ #define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ -/* - * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie) - */ -#define RCC_PLLI2S_SUPPORT /*!< Support PLL3 (PLLI2S)*/ - #define RCC_CR_PLL3ON_Pos (28U) #define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */ #define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */ @@ -11914,7 +11909,6 @@ typedef struct #define SPI_I2SCFGR_I2SMOD_Pos (11U) #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ - /****************** Bit definition for SPI_I2SPR register *******************/ #define SPI_I2SPR_I2SDIV_Pos (0U) #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ @@ -14092,8 +14086,6 @@ typedef struct ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ @@ -14289,15 +14281,15 @@ typedef struct #define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn #define USBWakeUp_IRQn OTG_FS_WKUP_IRQn #define CEC_IRQn OTG_FS_WKUP_IRQn -#define TIM9_IRQn TIM1_BRK_IRQn #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn #define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn -#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn +#define TIM9_IRQn TIM1_BRK_IRQn #define TIM11_IRQn TIM1_TRG_COM_IRQn #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn -#define TIM10_IRQn TIM1_UP_IRQn +#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn #define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn +#define TIM10_IRQn TIM1_UP_IRQn #define TIM6_DAC_IRQn TIM6_IRQn @@ -14310,15 +14302,15 @@ typedef struct #define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler #define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler #define CEC_IRQHandler OTG_FS_WKUP_IRQHandler -#define TIM9_IRQHandler TIM1_BRK_IRQHandler #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler #define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler -#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler +#define TIM9_IRQHandler TIM1_BRK_IRQHandler #define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler -#define TIM10_IRQHandler TIM1_UP_IRQHandler +#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler #define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler #define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler +#define TIM10_IRQHandler TIM1_UP_IRQHandler #define TIM6_DAC_IRQHandler TIM6_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h index 3b35fca2ff..55e7fe0278 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h @@ -1330,6 +1330,11 @@ typedef struct /* Reset and Clock Control */ /* */ /******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie) + */ +#define RCC_PLL2_SUPPORT /*!< Support PLL2 */ +#define RCC_PLLI2S_SUPPORT /******************** Bit definition for RCC_CR register ********************/ #define RCC_CR_HSION_Pos (0U) @@ -1363,11 +1368,6 @@ typedef struct #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ -/* - * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie) - */ -#define RCC_PLL2_SUPPORT /*!< Support PLL2 */ - #define RCC_CR_PLL2ON_Pos (26U) #define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */ #define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */ @@ -1375,11 +1375,6 @@ typedef struct #define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */ #define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ -/* - * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie) - */ -#define RCC_PLLI2S_SUPPORT /*!< Support PLL3 (PLLI2S)*/ - #define RCC_CR_PLL3ON_Pos (28U) #define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */ #define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */ @@ -12006,7 +12001,6 @@ typedef struct #define SPI_I2SCFGR_I2SMOD_Pos (11U) #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ - /****************** Bit definition for SPI_I2SPR register *******************/ #define SPI_I2SPR_I2SDIV_Pos (0U) #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ @@ -15003,8 +14997,6 @@ typedef struct ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ @@ -15195,42 +15187,42 @@ typedef struct /* Aliases for __IRQn */ #define ADC1_IRQn ADC1_2_IRQn -#define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn #define USB_LP_IRQn CAN1_RX0_IRQn -#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn +#define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn #define USB_HP_IRQn CAN1_TX_IRQn +#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn #define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn #define USBWakeUp_IRQn OTG_FS_WKUP_IRQn #define CEC_IRQn OTG_FS_WKUP_IRQn +#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn #define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn #define TIM9_IRQn TIM1_BRK_IRQn -#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn +#define TIM11_IRQn TIM1_TRG_COM_IRQn #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn -#define TIM11_IRQn TIM1_TRG_COM_IRQn -#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn #define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn +#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn #define TIM10_IRQn TIM1_UP_IRQn #define TIM6_DAC_IRQn TIM6_IRQn /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_2_IRQHandler -#define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler #define USB_LP_IRQHandler CAN1_RX0_IRQHandler -#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler +#define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler #define USB_HP_IRQHandler CAN1_TX_IRQHandler +#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler #define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler #define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler #define CEC_IRQHandler OTG_FS_WKUP_IRQHandler +#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler #define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler #define TIM9_IRQHandler TIM1_BRK_IRQHandler -#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler +#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler -#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler -#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler #define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler +#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler #define TIM10_IRQHandler TIM1_UP_IRQHandler #define TIM6_DAC_IRQHandler TIM6_IRQHandler diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h index cff2dc1419..65881d3fa7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h @@ -90,11 +90,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V4.3.1 + * @brief CMSIS Device version number V4.3.2 */ #define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ #define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F1_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F1_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/License.md b/system/Drivers/CMSIS/Device/ST/STM32F1xx/License.md new file mode 100644 index 0000000000..72fbf79ee2 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/License.md @@ -0,0 +1,83 @@ +Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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You are solely responsible for determining the appropriateness of using or redistributing the Work and assume any risks associated with Your exercise of permissions under this License. + +8. Limitation of Liability. + +In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages. + +9. Accepting Warranty or Additional Liability. + +While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. + +END OF TERMS AND CONDITIONS + +APPENDIX: + + Copyright [2019] [STMicroelectronics] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/README.md b/system/Drivers/CMSIS/Device/ST/STM32F1xx/README.md new file mode 100644 index 0000000000..294bcb85f9 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/README.md @@ -0,0 +1,41 @@ +# STM32CubeF1 CMSIS Device MCU Component + +## Overview + +**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost. + +**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series. + * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product + * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio + * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series + * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ... + * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series + +Two models of publication are proposed for the STM32Cube embedded software : + * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series) + * The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions. + +## Description + +This **cmsis_device_f1** MCU component repo is one element of the STM32CubeF1 MCU embedded software package, providing the **cmsis device** part. + +## Release note + +Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis_device_f1/blob/master/Release_Notes.html). + +## Compatibility information + +In this table, you can find the successive versions of this CMSIS Device component, in-line with the corresponding versions of the full MCU package: + +CMSIS Device F1 | CMSIS Core | Was delivered in the full MCU package +--------------- | ---------- | ------------------------------------- +Tag v4.3.1 | Tag v5.4.0_cm3 | Tag v1.8.0 +Tag v4.3.1 | Tag v5.4.0_cm3 | Tag v1.8.1 +Tag v4.3.2 | Tag v5.4.0_cm3 | Tag v1.8.2 + +The full **STM32CubeF1** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF1). + +## Troubleshooting +If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_f1/issues/new). + +For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Release_Notes.html index 97683266e1..38ec2ab342 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Release_Notes.html @@ -1,852 +1,401 @@ - - - - - - - - - - - - - - - - - - - - -Release Notes for STM32L1xx CMSIS - - - - - - -
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Release -Notes for STM32F10x CMSIS

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Copyright 2016 STMicroelectronics

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Update History

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V4.3.1 / 26-June-2019

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Main -Changes

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  • Fix MISRA C 2012 Compilation errors: update to use "UL" postfix for bits mask definitions(_Msk) and memory/peripheral base addresses
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  • Fix wrong initialization value for "SystemCoreClock" in System_stm32f1xx.c file
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    • - -
  • Update gcc linker file template to be aligned with AC6 linker file template
  • stm32f1xx.h
    • Align ErrorStatus typedef to common error handling
  • TIM:
    • -
      -
    • Update IS_TIM_SLAVE_INSTANCE() macro to add reference to TIM9 instance
      -
      • -
    -
  • SDMMC:
    • -
      -
    • Remove SDIO_TypeDef() structure, SDIO_BASE define and SDIO Bits definitions : feature not available on all devices
      -except STM32F103xE and       STM32F103xG
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  • USB:
    • -
      -
    • Add new PCD/HCD macros:
      • -
        -
      •  IS_PCD_ALL_INSTANCE()
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      • IS_HCD_ALL_INSTANCE()
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      -
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  • SPI:
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    • Add new SPI_CRC_ERROR_WORKAROUND_FEATURE define to enable SPI CRC workaround feature for STM32F101xE/STM32F103xE devices
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V4.3.0 / 09-October-2018

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Main -Changes

  • Add missing IS_TIM_SYNCHRO_INSTANCE macro definition to check TIM SYNCHRO feature instance support.

V4.2.0 / 31-March-2017

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Main -Changes

  • Use _Pos and _Mask macros for all Bit Definitions
  • Remove Core-CM3 bit definitions from CMSIS devices drivers: duplicated with bit definitions in core_cm3.h.
  • General updates in header files to support LL drivers
    • Remove TIM SMCR OCCS and TIM CCER CC4NP bit definitions
    • Add new USART defines: USART_CR1_OVER8 and USART_CR3_ONEBIT
    • Add I2C_DR_DR bit definition
    • Add new I2C macros: IS_SMBUS_ALL_INSTANCE
    • Add new LL I2S defines: SPI_I2S_SUPPORT and I2S2_I2S3_CLOCK_FEATURE
    • Rename DAC instance to DAC1
    • Rename PWR_CR_PLS_XXX to PWR_CR_PLS_LEVX
    • Add RCC LL defines
      • RCC_HSE_MIN
      • RCC_HSE_MAX
      • RCC_MAX_FREQUENCY
      • RCC_PLL_SUPPORT
      • RCC_PLLI2S_SUPPORT
    • Add new TIM macros to check TIM feature instance support:
      • IS_TIM_COUNTER_MODE_SELECT_INSTANCE()
      • IS_TIM_ADVANCED_INSTANCE
      • IS_TIM_ETR_INSTANCE
      • IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
      • IS_TIM_32B_COUNTER_INSTANCE
      • IS_TIM_BREAK_INSTANCE()
      • IS_TIM_CCXN_INSTANCE()
      • IS_TIM_REPETITION_COUNTER_INSTANCE()
      • IS_TIM_COMMUTATION_EVENT_INSTANCE()

V4.1.0 / 29-April-2016

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Main -Changes

  • Add _Pos and _Msk defines to be used with _VAL2FLD(field, value) and _FLD2VAL(field, value). 
    • The previous naming are kept for backward compatibility.
  • RCC: Add define RCC_CFGR_MCOSEL for compatibility across all STM32 series.
  • ADC: Add define ADC_MULTIMODE_SUPPORT for devices supporting the ADC multimode feature.
  • ADC: Add define ADC_SR_EOS and ADC_SR_JEOS for compatibility accross all STM32 series.
  • stm32f1xx.h: -Replace __STM32F1xx_CMSIS_DEVICE_VERSION_MAIN by -__STM32F1_CMSIS_VERSION_MAIN for MISRA compliancy on define length name.
  • Add APBPrescTable constant to list APB prescalers values.
  • Add FLASHSIZE_BASE for the FLASH Size register base address.
  • Add UID_BASE for the unique device ID register base address.

V4.0.2 / 18-December-2015

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Main -Changes

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  • FLASH: Add FLASH_OBR_DATA0 and FLASH_OBR_DATA1 for FLASH_OBR register.
  • WWDG: Align bit name across all STM32 families.
    • WWDG_CR_T0 renmaed to WWDG_CR_T_0.
    • WWDG_CFR_W0 renamed to WWDG_CFR_W_0.
    • WWDG_CFR_WDGTB0 renamed to WWDG_CFR_WDGTB_0.
    • WWDG_CFR_WDGTB1 renamed to WWDG_CFR_WDGTB_1.
    • Aliases are created for backward compatibilities.
  • Interrupt: Add HardFault_IRQn with value -13.
  • EXTI:: Align bit name across all STM32 families.
    • EXTI_IMR_MR0 renamed to EXTI_IMR_IM0.
    • EXTI_EMR_MR0 renamed to EXTI_EMR_EM0.
    • EXTI_RTSR_TR0 renamed to EXTI_RTSR_RT0.
    • EXTI_FTSR_TR0 renamed to EXTI_FTSR_FT0.
    • EXTI_SWIER_SWIER0 renamed to EXTI_SWIER_SWI0.
    • EXTI_PR_PR0 renamed to EXTI_PR_PIF0.
    • Aliases are created for backward compatibilities.
  • USB OTG: Remove USB_OTG_GCCFG_NOVBUSSENS from USB_OTG_GCCFG as this feature is not present in F1 devices.
  • USB_OTG: Remove USB_OTG_GCCFG_I2CPADEN from USB_OTG_GCCFG as this feature is not present in F1 devices.
  • ADC: Add the notion of common instance for compatibility with other STM32 families.

V4.0.1 / 31-July-2015

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Main -Changes

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  • Remove __IO or __I on constant table declaration (AHBPrescTable in system_stm32f1xx.c) due to issue with mbed C++ code. The table content was filled with random value at initialization phase.
  • uint8_t alignment done on CMSIS CRC registers structure.
  • Removing -definition of FLASH_WRP1_WRP1, FLASH_WRP1_nWRP1, FLASH_WRP2_WRP2, -FLASH_WRP2_nWRP2, FLASH_WRP3_WRP3 and FLASH_WRP3_nWRP3 for product -STM32F101x6, STM32F102x6 and STM32F103x6. Those defines are not -applicable to those products.

V4.0.0 / 16-December-2014

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  • Update -based on STM32Cube specification
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  • This version has to be used only with STM32CubeF1 based development

V3.6.3 / 10-April-2014

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Main -Changes

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  • Update startup files for EWARM toolchain to cope with compiler enhancement of the V7.10 version.
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V3.6.2 / 28-February-2013

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Main -Changes

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  • stm32f10x.h
    • Change #define FLASH_ACR_LATENCY ((uint8_t)0x03) by #define FLASH_ACR_LATENCY ((uint8_t)0x07)
    • Remove ',' from #define  DMA_CCR7_PSIZE  ,  ((uint16_t)0x0300)
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V3.6.1 / 09-March-2012

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Main -Changes

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  • All source files: license disclaimer text update and add link to the License file on ST Internet.

V3.6.0 / 27-January-2012

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Main -Changes

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  • Update directory structure to be compliant with CMSIS V2.1
  • All source files: update disclaimer to add reference to the new license agreement
  • stm32f10x.h
    • Add define for Cortex-M3 revision __CM3_REV
    • Allow -modification of some constants by the application code, definition of -these constants is now bracketed by              #if !defined. The concerned constant are HSE_VALUE, HSI_VALUE and HSE_STARTUP_TIMEOUT
    • Add missing bits definition for DAC CR register
    • Add missing bits definition for FSMC BTR1, BTR2, BTR3, BWTR1, BWTR2, BWTR3 and BWTR4 registers
    • Definition for Flash keys moved from stm32f10x_flash.c to stm32f10x.h
  • Add startup file for TASKING toolchain
  • V3.5.0 (based CMSIS V1.3) vs. V3.6.0 (based on CMSIS V2.1) compatibility update
    • Due to the directory structure difference between CMSIS V1.3 and V2.1, when migrating a project based on STM32F10x drivers V3.5.0 to V3.6.0 you need to perform the following update:
      • In -the compiler preprocessor, remove CortexM3 CMSIS include path. CortexM3 -CMSIS files are included by default in your development toolchain
      • Remove core_cm3.c file (if it is used). Almost of CortexM3 CMSIS function are provided as intrinsic by the compiler
      • In the compiler preprocessor, update path of STM32F10x CMSIS include files from  Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x to Libraries\CMSIS\Device\ST\STM32F10x\Include
      • In the project settings, update path of startup_stm32f10x_xx.s file from Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\”Compiler” to Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\”Compiler”
where, "Compiler" refer to arm, gcc_ride7, iar, TASKING or TrueSTUDIO
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V3.5.0 / 11-March-2011

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Main -Changes

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  • stm32f10x.h -and startup_stm32f10x_hd_vl.s files: remove the FSMC interrupt -definition for STM32F10x High-density Value line devices.
    -
  • system_stm32f10x.c file provided within the CMSIS folder.
    -
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3.4.0 -- 10/15/2010

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  1. General
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  • Add support -for STM32F10x High-density Value line devices.
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  1. STM32F10x CMSIS Device Peripheral Access Layer
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  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    -
    • Update to support High-density Value line devices
      • Add new define STM32F10X_HD_VL
      • RCC, AFIO, FSMC bits definition updated
    • - - All -STM32 devices definitions are commented by default. User has to select the -appropriate device before starting else an error will be signaled on compile -time.
    • Add new IRQs definitions inside the IRQn_Type enumeration for STM23 High-density Value line devices.
    • "bool" type removed.
      -
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    -
    • "system_stm32f10x.c" moved to to "STM32F10x_StdPeriph_Template" directory. This file is also moved to each example directory under "STM32F10x_StdPeriph_Examples".
      -
    • SystemInit_ExtMemCtl() function: update to support High-density Value line devices.
    • Add "VECT_TAB_SRAM" inside "system_stm32f10x.c" -to select if the user want to place the Vector Table in internal SRAM. -An additional define is also to specify the Vector Table offset "VECT_TAB_OFFSET".
      -
  • STM32F10x CMSIS startup files:startup_stm32f10x_xx.s
    • Add three -startup files for STM32 High-density Value line devices: - startup_stm32f10x_hd_vl.s
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3.3.0 -- 04/16/2010

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  1. General
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  • Add support -for STM32F10x XL-density devices.
  • Add startup files for TrueSTUDIO toolchain
  1. STM32F10x CMSIS Device Peripheral Access Layer
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  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    -
    • Update to support XL-density devices
      • Add new define STM32F10X_XL
      • Add new IRQs for TIM9..14
      • Update FLASH_TypeDef structure
      • Add new IP instances TIM9..14
      • RCC, AFIO, DBGMCU bits definition updated
    • Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices (remove comma "," at the end of enum list)
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    -
    • SystemInit_ExtMemCtl() function: update to support XL-density devices
    • SystemInit() function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions. 
      -
  • STM32F10x CMSIS startup files:
    • add three -startup files for STM32 XL-density devices: - startup_stm32f10x_xl.s
    • startup_stm32f10x_md_vl.s for RIDE7: add USART3 IRQ Handler (was missing in previous version)
    • Add startup files for TrueSTUDIO toolchain
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3.2.0 -- 03/01/2010

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  1. General
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  • STM32F10x CMSIS files updated to CMSIS V1.30 release
  • Directory structure updated to be aligned with CMSIS V1.30
    -
  • Add support -for STM32 Low-density Value line (STM32F100x4/6) and -Medium-density Value line (STM32F100x8/B) devices. 
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  1. CMSIS Core Peripheral Access Layer
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  1. STM32F10x CMSIS Device Peripheral Access Layer
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  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h
    -
    • Update -the stm32f10x.h file to support new Value line devices features: CEC -peripheral, new General purpose timers TIM15, TIM16 and TIM17.
    • Peripherals Bits definitions updated to be in line with Value line devices available features.
      -
    • HSE_Value, -HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE, -HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy -purposes.
      -
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c
    -
    • SystemFrequency variable name changed to SystemCoreClock
      -
    • Default - SystemCoreClock is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.
      -
    • All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.
      -
    • Additional function void SystemCoreClockUpdate (void) is provided.
      -
  • STM32F10x CMSIS Startup files: startup_stm32f10x_xx.s
    • Add new -startup files for STM32 Low-density Value line devices: - startup_stm32f10x_ld_vl.s
    • Add new startup -files for STM32 Medium-density Value line devices: - startup_stm32f10x_md_vl.s
    • SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.
      -To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file
      -
    • GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.
      -
- - -

License

-

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless -required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See -the License for the specific language governing permissions and -limitations under the License. -
-
-

For -complete documentation on STM32 Microcontrollers -visit www.st.com/STM32

-
-

-
-
-

 

-
\ No newline at end of file + + + + + + + Release Notes for STM32F1xx CMSIS + + + + + +
+
+
+
+
+

Release Notes for STM32F1xx CMSIS

+

Copyright © 2016 STMicroelectronics
+

+ +
+
+
+

License

+This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at: +
+https://opensource.org/licenses/BSD-3-Clause +
+
+
+

Update History

+
+ +
+

Main Changes

+
    +
  • Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS
    • +
  • SystemInit(): update to don’t reset RCC registers to its reset values.
    • +
  • TIM: +
      +
    • Remove unused IS_TIM_SYNCHRO_INSTANCE() assert macro
      • +
    • +
  • I2S: +
      +
    • Add missing I2SCFG and I2SPR bits difinitions for STM32F101xE and STM32F101xG
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Fix MISRA C 2012 Compilation errors: update to use “UL” postfix for bits mask definitions(_Msk) and memory/peripheral base addresses
    • +
  • Fix wrong initialization value for “SystemCoreClock” in System_stm32f1xx.c file
    • +
  • Update gcc linker file template to be aligned with AC6 linker file template
    • +
  • stm32f1xx.h +
      +
    • Align ErrorStatus typedef to common error handling
      • +
    • +
  • TIM: +
      +
    • Update IS_TIM_SLAVE_INSTANCE() macro to add reference to TIM9 instance
      • +
    • +
  • SDMMC: +
      +
    • Remove SDIO_TypeDef() structure, SDIO_BASE define and SDIO Bits definitions : feature not available on all devices except STM32F103xE and STM32F103xG
      • +
    • +
  • USB: +
      +
    • Add new PCD/HCD macros: +
        +
      • IS_PCD_ALL_INSTANCE()
        • +
      • IS_HCD_ALL_INSTANCE()
        • +
      • +
    • +
  • SPI: +
      +
    • Add new SPI_CRC_ERROR_WORKAROUND_FEATURE define to enable SPI CRC workaround feature for STM32F101xE/STM32F103xE devices
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add missing IS_TIM_SYNCHRO_INSTANCE macro definition to check TIM SYNCHRO feature instance support.
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Use _Pos and _Mask macros for all Bit Definitions
    • +
  • Remove Core-CM3 bit definitions from CMSIS devices drivers: duplicated with bit definitions in core_cm3.h.
    • +
  • General updates in header files to support LL drivers +
      +
    • Remove TIM SMCR OCCS and TIM CCER CC4NP bit definitions
      • +
    • Add new USART defines: USART_CR1_OVER8 and USART_CR3_ONEBIT
      • +
    • Add I2C_DR_DR bit definition
      • +
    • Add new I2C macros: IS_SMBUS_ALL_INSTANCE
      • +
    • Add new LL I2S defines: SPI_I2S_SUPPORT and I2S2_I2S3_CLOCK_FEATURE
      • +
    • Rename DAC instance to DAC1
      • +
    • Rename PWR_CR_PLS_XXX to PWR_CR_PLS_LEVX
      • +
    • Add RCC LL defines +
        +
      • RCC_HSE_MIN
        • +
      • RCC_HSE_MAX
        • +
      • RCC_MAX_FREQUENCY
        • +
      • RCC_PLL_SUPPORT
        • +
      • RCC_PLLI2S_SUPPORT
        • +
      • +
    • Add new TIM macros to check TIM feature instance support: +
        +
      • IS_TIM_COUNTER_MODE_SELECT_INSTANCE()
        • +
      • IS_TIM_ADVANCED_INSTANCE
        • +
      • IS_TIM_ETR_INSTANCE
        • +
      • IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
        • +
      • IS_TIM_32B_COUNTER_INSTANCE
        • +
      • IS_TIM_BREAK_INSTANCE()
        • +
      • IS_TIM_CCXN_INSTANCE()
        • +
      • IS_TIM_REPETITION_COUNTER_INSTANCE()
        • +
      • IS_TIM_COMMUTATION_EVENT_INSTANCE()
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add _Pos and _Msk defines to be used with _VAL2FLD(field, value) and _FLD2VAL(field, value). +
      +
    • The previous naming are kept for backward compatibility.
      • +
    • +
  • RCC: Add define RCC_CFGR_MCOSEL for compatibility across all STM32 series.
    • +
  • ADC: Add define ADC_MULTIMODE_SUPPORT for devices supporting the ADC multimode feature.
    • +
  • ADC: Add define ADC_SR_EOS and ADC_SR_JEOS for compatibility accross all STM32 series.
    • +
  • stm32f1xx.h: Replace __STM32F1xx_CMSIS_DEVICE_VERSION_MAIN by __STM32F1_CMSIS_VERSION_MAIN for MISRA compliancy on define length name.
    • +
  • Add APBPrescTable constant to list APB prescalers values.
    • +
  • Add FLASHSIZE_BASE for the FLASH Size register base address.
    • +
  • Add UID_BASE for the unique device ID register base address.
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • FLASH: Add FLASH_OBR_DATA0 and FLASH_OBR_DATA1 for FLASH_OBR register.
    • +
  • WWDG: Align bit name across all STM32 families. +
      +
    • WWDG_CR_T0 renmaed to WWDG_CR_T_0.
      • +
    • WWDG_CFR_W0 renamed to WWDG_CFR_W_0.
      • +
    • WWDG_CFR_WDGTB0 renamed to WWDG_CFR_WDGTB_0.
      • +
    • WWDG_CFR_WDGTB1 renamed to WWDG_CFR_WDGTB_1.
      • +
    • +
  • Interrupt: Add HardFault_IRQn with value -13.
    • +
  • EXTI:: Align bit name across all STM32 families. +
      +
    • EXTI_IMR_MR0 renamed to EXTI_IMR_IM0.
      • +
    • EXTI_EMR_MR0 renamed to EXTI_EMR_EM0.
      • +
    • EXTI_RTSR_TR0 renamed to EXTI_RTSR_RT0.
      • +
    • EXTI_FTSR_TR0 renamed to EXTI_FTSR_FT0.
      • +
    • EXTI_SWIER_SWIER0 renamed to EXTI_SWIER_SWI0.
      • +
    • EXTI_PR_PR0 renamed to EXTI_PR_PIF0.
      • +
    • Aliases are created for backward compatibilities.
      • +
    • +
  • USB OTG: Remove USB_OTG_GCCFG_NOVBUSSENS from USB_OTG_GCCFG as this feature is not present in F1 devices.
    • +
  • USB_OTG: Remove USB_OTG_GCCFG_I2CPADEN from USB_OTG_GCCFG as this feature is not present in F1 devices.
    • +
  • ADC: Add the notion of common instance for compatibility with other STM32 families.
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Remove __IO or __I on constant table declaration (AHBPrescTable in system_stm32f1xx.c) due to issue with mbed C++ code. The table content was filled with random value at initialization phase.
    • +
  • uint8_t alignment done on CMSIS CRC registers structure.
    • +
  • Removing definition of FLASH_WRP1_WRP1, FLASH_WRP1_nWRP1, FLASH_WRP2_WRP2, FLASH_WRP2_nWRP2, FLASH_WRP3_WRP3 and FLASH_WRP3_nWRP3 for product STM32F101x6, STM32F102x6 and STM32F103x6. Those defines are not applicable to those products.
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Update based on STM32Cube specification
    • +
  • This version has to be used only with STM32CubeF1 based development
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Update startup files for EWARM toolchain to cope with compiler enhancement of the V7.10 version.
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • stm32f10x.h +
      +
    • Change #define FLASH_ACR_LATENCY ((uint8_t)0x03) by #define FLASH_ACR_LATENCY ((uint8_t)0x07)
      • +
    • Remove ‘,’ from #define DMA_CCR7_PSIZE , ((uint16_t)0x0300)
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • All source files: license disclaimer text update and add link to the License file on ST Internet.
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Update directory structure to be compliant with CMSIS V2.1
    • +
  • All source files: update disclaimer to add reference to the new license agreement
    • +
  • stm32f10x.h +
      +
    • Add define for Cortex-M3 revision __CM3_REV
      • +
    • Allow modification of some constants by the application code, definition of these constants is now bracketed by #if !defined. The concerned constant are HSE_VALUE, HSI_VALUE and HSE_STARTUP_TIMEOUT
      • +
    • Add missing bits definition for DAC CR register
      • +
    • Add missing bits definition for FSMC BTR1, _BTR2__, BTR3, BWTR1, BWTR2, BWTR3 and BWTR4 registers
      • +
    • Definition for Flash keys moved from stm32f10x_flash.c to stm32f10x.h
      • +
    • +
  • V3.5.0 (based CMSIS V1.3) vs. V3.6.0 (based on CMSIS V2.1) compatibility update +
      +
    • Due to the directory structure difference between CMSIS V1.3 and V2.1, when migrating a project based on STM32F10x drivers V3.5.0 to V3.6.0 you need to perform the following update: +
        +
      • Rename ADC1_COMP_IRQn to ADC1_IRQn
        • +
      • In the compiler preprocessor, remove CortexM3 CMSIS include path. CortexM3 CMSIS files are included by default in your development toolchain
        • +
      • Remove core_cm3.c file (if it is used). Almost of CortexM3 CMSIS_ function are provided as intrinsic by the compiler
        • +
      • In the compiler preprocessor, update path of _STM32F10x CMSIS include files from Libraries332F10x to Libraries32F10x
        • +
      • In the project settings, update path of startup_stm32f10x_xx.s file from Libraries332F10x”Compiler” to Libraries32F10x”Compiler” where, “Compiler” refer to arm, gcc_ride7, iar, TASKING or TrueSTUDIO
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • stm32f10x.h and startup_stm32f10x_hd_vl.s files: remove the FSMC interrupt definition for STM32F10x High-density Value line devices.
    • +
  • system_stm32f10x.c file provided within the CMSIS folder.
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General +
      +
    • Add support for STM32F10x High-density Value line devices.
      • +
    • +
  • STM32F10x CMSIS Device Peripheral Access Layer +
      +
    • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h +
        +
      • Update to support High-density Value line devices +
          +
        • Add new define STM32F10X_HD_VL
          • +
        • RCC, AFIO, FSMC bits definition updated
          • +
        • +
      • All STM32 devices definitions are commented by default. User has to select the appropriate device before starting else an error will be signaled on compile time.
        • +
      • Add new IRQs definitions inside the IRQn_Type enumeration for STM23 High-density Value line devices.
        • +
      • “bool” type removed.
        • +
      • +
    • +
  • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c +
      +
    • “system_stm32f10x.c” moved to to “STM32F10x_StdPeriph_Template” directory. This file is also moved to each example directory under “STM32F10x_StdPeriph_Examples”.
      • +
    • SystemInit_ExtMemCtl() function: update to support High-density Value line devices.
      • +
    • Add “VECT_TAB_SRAM” inside “system_stm32f10x.c” to select if the user want to place the Vector Table in internal SRAM. An additional define is also to specify the Vector Table offset “VECT_TAB_OFFSET”.
      • +
    • +
  • STM32F10x CMSIS startup files:startup_stm32f10x_xx.s +
      +
    • Add three startup files for STM32 High-density Value line devices: startup_stm32f10x_hd_vl.s
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General +
      +
    • Add support for STM32F10x XL-density devices.
      • +
    • Add startup files for TrueSTUDIO toolchain
      • +
    • +
  • STM32F10x CMSIS Device Peripheral Access Layer +
      +
    • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h +
        +
      • Update to support XL-density devices +
          +
        • Add new define STM32F10X_XL
          • +
        • Add new IRQs for TIM9..14
          • +
        • Update FLASH_TypeDef structure
          • +
        • Add new IP instances TIM9..14
          • +
        • RCC, AFIO, DBGMCU bits definition updated
          • +
        • +
      • Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices (remove comma “,” at the end of enum list)
        • +
      • +
    • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f0xx.c +
        +
      • SystemInit_ExtMemCtl() function: update to support XL-density devices
        • +
      • SystemInit() function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions.
        • +
      • +
    • STM32F10x CMSIS startup files: +
        +
      • add three startup files for STM32 XL-density devices: startup_stm32f10x_xl.s
        • +
      • startup_stm32f10x_md_vl.s for RIDE7: add USART3 IRQ Handler (was missing in previous version)
        • +
      • Add startup files for TrueSTUDIO toolchain
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General +
      +
    • STM32F10x CMSIS files updated to CMSIS V1.30 release
      • +
    • Directory structure updated to be aligned with CMSIS V1.30
      • +
    • Add support for STM32 Low-density Value line (STM32F100x4/6) and Medium-density Value line (STM32F100x8/B) devices.
      • +
    • +
  • CMSIS Core Peripheral Access Layer
    • +
  • STM32F10x CMSIS Device Peripheral Access Layer +
      +
    • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: stm32f10x.h +
        +
      • Update the stm32f10x.h file to support new Value line devices features: CEC peripheral, new General purpose timers TIM15, TIM16 and TIM17.
        • +
      • Peripherals Bits definitions updated to be in line with Value line devices available features.
        • +
      • HSE_Value, HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE, HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy purposes.
        • +
      • +
    • STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: system_stm32f10x.h and system_stm32f10x.c +
        +
      • SystemFrequency variable name changed to SystemCoreClock
        • +
      • Default SystemCoreClock is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.
        • +
      • All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.
        • +
      • Additional function void SystemCoreClockUpdate (void) is provided.
        • +
      • +
    • STM32F10x CMSIS Startup files: startup_stm32f10x_xx.s +
        +
      • Add new startup files for STM32 Low-density Value line devices: startup_stm32f10x_ld_vl.s
        • +
      • Add new startup files for STM32 Medium-density Value line devices: startup_stm32f10x_md_vl.s
        • +
      • SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file
        • +
      • +
    • +
  • GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.
    • +
+
+
+
+
+ + + diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c index 9a42ab15b5..0f6224233d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c @@ -89,12 +89,31 @@ /* #define DATA_IN_ExtSRAM */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ /** * @} @@ -156,57 +175,16 @@ const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; */ void SystemInit (void) { - /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ - /* Set HSION bit */ - RCC->CR |= 0x00000001U; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#if !defined(STM32F105xC) && !defined(STM32F107xC) - RCC->CFGR &= 0xF8FF0000U; -#else - RCC->CFGR &= 0xF0FF0000U; -#endif /* STM32F105xC */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= 0xFEF6FFFFU; - - /* Reset HSEBYP bit */ - RCC->CR &= 0xFFFBFFFFU; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= 0xFF80FFFFU; - -#if defined(STM32F105xC) || defined(STM32F107xC) - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= 0xEBFFFFFFU; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000U; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000U; -#elif defined(STM32F100xB) || defined(STM32F100xE) - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000U; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000U; -#else - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000U; -#endif /* STM32F105xC */ - #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #ifdef DATA_IN_ExtSRAM SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM */ #endif -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#endif /* USER_VECT_TAB_ADDRESS */ } /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/_htmresc/mini-st.css b/system/Drivers/CMSIS/Device/ST/STM32F1xx/_htmresc/mini-st.css new file mode 100644 index 0000000000..3caf11c32e --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32F1xx/_htmresc/mini-st.css @@ -0,0 +1,1700 @@ +@charset "UTF-8"; +/* + Flavor name: Default (mini-default) + Author: Angelos Chalaris (chalarangelo@gmail.com) + Maintainers: Angelos Chalaris + mini.css version: v3.0.0-alpha.3 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #111; + --secondary-fore-color: #444; + --back-color: #f8f8f8; + --secondary-back-color: #f0f0f0; + --blockquote-color: #f57c00; + --pre-color: #1565c0; + --border-color: #aaa; + --secondary-border-color: #ddd; + --heading-ratio: 1.19; + --universal-margin: 0.5rem; + --universal-padding: 0.125rem; + --universal-border-radius: 0.125rem; + --a-link-color: #0277bd; + --a-visited-color: #01579b; } + +html { + font-size: 14px; } + +a, b, del, em, i, ins, q, span, strong, u { + font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif; + line-height: 1.4; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + background: var(--back-color); } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.2; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 500; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); ); + background: var(--mark-back-color); + font-weight: 600; + padding: 0.1em 0.5em 0.2em 0.5em; + color: var(--mark-fore-color); } + +h3 { + font-size: calc(1rem * var(--heading-ratio)); + padding-left: calc(2 * var(--universal-margin)); + /* background: var(--border-color); */ + } + +h4 { + font-size: 1rem;); + padding-left: calc(4 * var(--universal-margin)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(6 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0625rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0625rem solid var(--secondary-border-color); + border-left: 0.375rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 3rem; + font-weight: 700; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0625rem solid var(--secondary-border-color); + border-left: 0.25rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #f8f8f8; + --card-fore-color: #111; + --card-border-color: #ddd; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0625rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0625rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { +/* --card-back-color: #ffca28; */ + --card-back-color: #e5b8b7; + --card-border-color: #e8b825; } + +.card.error { + --card-back-color: #b71c1c; + --card-fore-color: #f8f8f8; + --card-border-color: #a71a1a; } + +.card > .sectione.dark { + --card-back-color: #e0e0e0; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #f0f0f0; + --form-fore-color: #111; + --form-border-color: #ddd; + --input-back-color: #f8f8f8; + --input-fore-color: #111; + --input-border-color: #ddd; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0625rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0625rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 700; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0625rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0625rem + var(--universal-padding) / 2); + left: calc(0.0625rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0625rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0625rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0625rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0625rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #f8f8f8; + --header-hover-back-color: #f0f0f0; + --header-fore-color: #444; + --header-border-color: #ddd; + --nav-back-color: #f8f8f8; + --nav-hover-back-color: #f0f0f0; + --nav-fore-color: #444; + --nav-border-color: #ddd; + --nav-link-color: #0277bd; + --footer-fore-color: #444; + --footer-back-color: #f8f8f8; + --footer-border-color: #ddd; + --footer-link-color: #0277bd; + --drawer-back-color: #f8f8f8; + --drawer-hover-back-color: #f0f0f0; + --drawer-border-color: #ddd; + --drawer-close-color: #444; } + +header { + height: 3.1875rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0625rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0625rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0625rem; + content: ''; + height: 100%; + border: 0.0625rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0625rem; + content: ''; + height: 100%; + border: 0.0625rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0625rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0625rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #aaa; + --table-border-separator-color: #666; + --table-head-back-color: #e6e6e6; + --table-head-fore-color: #111; + --table-body-back-color: #f8f8f8; + --table-body-fore-color: #111; + --table-body-alt-back-color: #eee; } + +table { + border-collapse: separate; + border-spacing: 0; + : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); } + table caption { + font-size: 1.25 * rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; + text-align: left;} + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0625rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0625rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0625rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 850px; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: 1 0 0; + margin-left: calc( 4 * var(--universal-margin)); + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: 100%; + border: 0; + border-bottom: 0.0625rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0625rem solid var(--table-border-color); + border-right: 0.0625rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0625rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0625rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0625rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #fafafa; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(2 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +:root { + --table-body-alt-back-color: #eee; } + +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #0277bd; + --mark-fore-color: #fafafa; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.5; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #444; + --modal-close-hover-color: #f0f0f0; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #e8e8e8; + --collapse-label-fore-color: #212121; + --collapse-label-hover-back-color: #f0f0f0; + --collapse-selected-label-back-color: #ececec; + --collapse-border-color: #ddd; + --collapse-content-back-color: #fafafa; + --collapse-selected-label-border-color: #0277bd; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.5rem; + cursor: pointer; + transition: background 0.3s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0625rem solid var(--collapse-border-color); + padding: calc(1.5 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-bottom-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0625rem solid var(--collapse-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 850px; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.secondary { + --mark-back-color: #d32f2f; } + +mark.tertiary { + --mark-back-color: #308732; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progess module CSS variable definitions */ +:root { + --progress-back-color: #ddd; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect 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+span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-rss { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-search { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-settings { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' 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fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-cart { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0625rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-default.css.map */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F1xx/_htmresc/st_logo.png b/system/Drivers/CMSIS/Device/ST/STM32F1xx/_htmresc/st_logo.png new file mode 100644 index 0000000000..8b80057fd3 Binary files /dev/null and b/system/Drivers/CMSIS/Device/ST/STM32F1xx/_htmresc/st_logo.png differ diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 2724992797..4facf12e62 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -1,7 +1,7 @@ # STM32YYxx CMSIS version: * STM32F0: 2.3.4 - * STM32F1: 4.3.1 + * STM32F1: 4.3.2 * STM32F2: 2.2.3 * STM32F3: 2.3.4 * STM32F4: 2.6.5 diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index df5cd522e6..fbda58823f 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -38,7 +38,6 @@ #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - /** * @} */ @@ -236,12 +235,12 @@ #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) -#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH) -#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH) +#if defined(STM32G4) || defined(STM32H7) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -306,8 +305,22 @@ #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + #endif /* STM32L4 */ +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + #if defined(STM32H7) #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 @@ -365,6 +378,9 @@ #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + #endif /* STM32H7 */ /** @@ -460,7 +476,9 @@ #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 -#endif +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ /** * @} @@ -564,7 +582,14 @@ #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 -#endif + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 @@ -622,6 +647,10 @@ #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL #endif /* STM32G4 */ #if defined(STM32H7) @@ -735,6 +764,66 @@ #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 #endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the events that can be selected to configure the + * set/reset crossbar of a timer output + */ +#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) +#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) +#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) +#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) +#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) +#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) +#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) +#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) +#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) + +#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) +#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) +#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) +#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) +#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) +#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) +#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) +#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) +#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) + +/** @brief Constants defining the event filtering applied to external events + * by a timer + */ +#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ /** * @} */ @@ -874,7 +963,7 @@ #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -965,6 +1054,16 @@ #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT + +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL +#endif /* STM32H7 */ + /** * @} */ @@ -1358,6 +1457,30 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ @@ -1380,6 +1503,13 @@ #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + /** * @} */ @@ -1409,16 +1539,18 @@ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */ +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ #if defined(STM32F4) #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT @@ -1437,6 +1569,13 @@ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown @@ -1509,14 +1648,14 @@ #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA -#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ /** * @} */ @@ -3112,9 +3251,8 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3242,7 +3380,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3350,9 +3488,9 @@ #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND /* alias CMSIS for compatibilities */ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler @@ -3365,7 +3503,7 @@ #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif -#if defined(STM32H7) +#if defined(STM32H7) || defined(STM32L5) #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback @@ -3606,12 +3744,12 @@ * @{ */ #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) -#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT -#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA -#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart -#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT -#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA -#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop #endif /** * @} @@ -3620,9 +3758,9 @@ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32L4) +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE -#endif +#endif /* STM32L4 || STM32F4 || STM32F7 */ /** * @} */ diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32f1xx_hal_can_ex_legacy.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32f1xx_hal_can_ex_legacy.h index fdee6a7df5..ce6c6ee2a2 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32f1xx_hal_can_ex_legacy.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32f1xx_hal_can_ex_legacy.h @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h index 6d791de1d8..3777caeacc 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_can.h @@ -295,11 +295,11 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to #define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ #define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ #define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to transmit error */ #define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */ #define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to transmit error */ #define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ #define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ #define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h index c287eb3a92..155c017e9d 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h @@ -28,9 +28,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx.h" -#if defined(USE_HAL_LEGACY) #include "Legacy/stm32_hal_legacy.h" -#endif #include /* Exported types ------------------------------------------------------------*/ @@ -108,7 +106,14 @@ typedef enum }while (0U) #endif /* USE_RTOS */ -#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif +#ifndef __packed +#define __packed __attribute__((packed)) +#endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ @@ -119,7 +124,14 @@ typedef enum /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) +#endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ @@ -131,7 +143,7 @@ typedef enum #define __ALIGN_END #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN -#if defined (__CC_ARM) /* ARM Compiler */ +#if defined (__CC_ARM) /* ARM Compiler V5*/ #define __ALIGN_BEGIN __align(4) #elif defined (__ICCARM__) /* IAR Compiler */ #define __ALIGN_BEGIN @@ -143,9 +155,9 @@ typedef enum /** * @brief __RAM_FUNC definition */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. Using the 'Options for File' dialog you can simply change the 'Code / Const' @@ -175,9 +187,9 @@ typedef enum /** * @brief __NOINLINE definition */ -#if defined ( __CC_ARM ) || defined ( __GNUC__ ) -/* ARM & GNUCompiler - ---------------- +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- */ #define __NOINLINE __attribute__ ( (noinline) ) diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_hcd.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_hcd.h index 87471adb29..50c4019184 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_hcd.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_hcd.h @@ -33,7 +33,7 @@ extern "C" { * @{ */ -/** @addtogroup HCD +/** @addtogroup HCD HCD * @{ */ @@ -262,9 +262,6 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); /** * @} */ -/** - * @} - */ /* Peripheral State functions ************************************************/ /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions @@ -293,20 +290,11 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); * @} */ /* Private functions prototypes ----------------------------------------------*/ -/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes - * @{ - */ -/** + /** * @} */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup HCD_Private_Functions HCD Private Functions - * @{ - */ - -/** + /** * @} */ #endif /* defined (USB_OTG_FS) */ diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2s.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2s.h index 8e18ba90ea..2313768331 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2s.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2s.h @@ -174,6 +174,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) #define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */ #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */ /** * @} */ @@ -380,6 +381,15 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to tmpreg_udr = ((__HANDLE__)->Instance->SR);\ UNUSED(tmpreg_udr); \ }while(0U) +/** @brief Flush the I2S DR Register. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\ + __IO uint32_t tmpreg_dr = 0x00U;\ + tmpreg_dr = ((__HANDLE__)->Instance->DR);\ + UNUSED(tmpreg_dr); \ + }while(0U) /** * @} */ @@ -462,7 +472,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); */ /** @brief Check whether the specified SPI flag is set or not. - * @param __SR__ copy of I2S SR regsiter. + * @param __SR__ copy of I2S SR register. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg I2S_FLAG_RXNE: Receive buffer not empty flag @@ -477,7 +487,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. - * @param __CR2__ copy of I2S CR2 regsiter. + * @param __CR2__ copy of I2S CR2 register. * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h index a73e1e2eec..00fd23d841 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h @@ -32,7 +32,7 @@ extern "C" { * @{ */ -/** @addtogroup IWDG +/** @defgroup IWDG IWDG * @{ */ @@ -62,9 +62,9 @@ typedef struct IWDG_TypeDef *Instance; /*!< Register base address */ IWDG_InitTypeDef Init; /*!< IWDG required parameters */ - } IWDG_HandleTypeDef; + /** * @} */ @@ -77,22 +77,24 @@ typedef struct /** @defgroup IWDG_Prescaler IWDG Prescaler * @{ */ -#define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */ -#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ -#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ -#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ -#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ -#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ -#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ +#define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */ +#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ +#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ +#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ +#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ +#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ +#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ + /** * @} */ + + /** * @} */ - /* Exported macros -----------------------------------------------------------*/ /** @defgroup IWDG_Exported_Macros IWDG Exported Macros * @{ @@ -107,7 +109,7 @@ typedef struct /** * @brief Reload IWDG counter with value defined in the reload register - * (write access to IWDG_PR & IWDG_RLR registers disabled). + * (write access to IWDG_PR and IWDG_RLR registers disabled). * @param __HANDLE__ IWDG handle * @retval None */ @@ -200,6 +202,8 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); */ #define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) + + /** * @} */ diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_nand.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_nand.h index 2bb1b737d6..b0c2370830 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_nand.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_nand.h @@ -90,10 +90,10 @@ typedef struct typedef struct { uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes - for 8 bits adressing or words for 16 bits addressing */ + for 8 bits addressing or words for 16 bits addressing */ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes - for 8 bits adressing or words for 16 bits addressing */ + for 8 bits addressing or words for 16 bits addressing */ uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ @@ -131,9 +131,9 @@ typedef struct NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */ - void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */ - void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */ + void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ + void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ + void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ #endif } NAND_HandleTypeDef; @@ -146,7 +146,7 @@ typedef enum HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */ HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */ HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */ -}HAL_NAND_CallbackIDTypeDef; +} HAL_NAND_CallbackIDTypeDef; /** * @brief HAL NAND Callback pointer definition @@ -161,8 +161,8 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /** @defgroup NAND_Exported_Macros NAND Exported Macros - * @{ - */ + * @{ + */ /** @brief Reset NAND handle state * @param __HANDLE__ specifies the NAND handle. @@ -192,7 +192,8 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); +HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, + FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); @@ -215,15 +216,23 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); /* IO operation functions ****************************************************/ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); - -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); @@ -231,7 +240,8 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressT #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) /* NAND callback registering/unregistering */ -HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, + pNAND_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); #endif @@ -272,34 +282,34 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); /** @defgroup NAND_Private_Constants NAND Private Constants * @{ */ -#define NAND_DEVICE1 ((uint32_t)0x70000000U) -#define NAND_DEVICE2 ((uint32_t)0x80000000U) -#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U) +#define NAND_DEVICE1 0x70000000UL +#define NAND_DEVICE2 0x80000000UL +#define NAND_WRITE_TIMEOUT 0x01000000UL -#define CMD_AREA ((uint32_t)(1UL<<16U)) /* A16 = CLE high */ -#define ADDR_AREA ((uint32_t)(1UL<<17U)) /* A17 = ALE high */ +#define CMD_AREA (1UL<<16U) /* A16 = CLE high */ +#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ -#define NAND_CMD_AREA_A ((uint8_t)0x00U) -#define NAND_CMD_AREA_B ((uint8_t)0x01U) -#define NAND_CMD_AREA_C ((uint8_t)0x50U) -#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U) +#define NAND_CMD_AREA_A ((uint8_t)0x00) +#define NAND_CMD_AREA_B ((uint8_t)0x01) +#define NAND_CMD_AREA_C ((uint8_t)0x50) +#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) -#define NAND_CMD_WRITE0 ((uint8_t)0x80U) -#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U) -#define NAND_CMD_ERASE0 ((uint8_t)0x60U) -#define NAND_CMD_ERASE1 ((uint8_t)0xD0U) -#define NAND_CMD_READID ((uint8_t)0x90U) -#define NAND_CMD_STATUS ((uint8_t)0x70U) -#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU) -#define NAND_CMD_RESET ((uint8_t)0xFFU) +#define NAND_CMD_WRITE0 ((uint8_t)0x80) +#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) +#define NAND_CMD_ERASE0 ((uint8_t)0x60) +#define NAND_CMD_ERASE1 ((uint8_t)0xD0) +#define NAND_CMD_READID ((uint8_t)0x90) +#define NAND_CMD_STATUS ((uint8_t)0x70) +#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) +#define NAND_CMD_RESET ((uint8_t)0xFF) /* NAND memory status */ -#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U) -#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U) -#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U) -#define NAND_BUSY ((uint32_t)0x00000000U) -#define NAND_ERROR ((uint32_t)0x00000001U) -#define NAND_READY ((uint32_t)0x00000040U) +#define NAND_VALID_ADDRESS 0x00000100UL +#define NAND_INVALID_ADDRESS 0x00000200UL +#define NAND_TIMEOUT_ERROR 0x00000400UL +#define NAND_BUSY 0x00000000UL +#define NAND_ERROR 0x00000001UL +#define NAND_READY 0x00000040UL /** * @} */ @@ -316,7 +326,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); * @retval NAND Raw address value */ #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ - (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) + (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) /** * @brief NAND memory Column address computation. diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_nor.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_nor.h index 5b0e296982..399c128fe2 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_nor.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_nor.h @@ -121,9 +121,11 @@ typedef struct __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ + uint32_t CommandSet; /*!< NOR algorithm command set and control */ + #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp Init callback */ - void (* MspDeInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp DeInit callback */ + void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */ + void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */ #endif } NOR_HandleTypeDef; @@ -135,7 +137,7 @@ typedef enum { HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */ HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */ -}HAL_NOR_CallbackIDTypeDef; +} HAL_NOR_CallbackIDTypeDef; /** * @brief HAL NOR Callback pointer definition @@ -178,7 +180,8 @@ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, + FSMC_NORSRAM_TimingTypeDef *ExtTiming); HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); @@ -197,8 +200,10 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); +HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize); +HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize); HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); @@ -206,7 +211,8 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) /* NOR callback registering/unregistering */ -HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, + pNOR_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId); #endif /** @@ -246,29 +252,29 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @{ */ /* NOR device IDs addresses */ -#define MC_ADDRESS ((uint16_t)0x0000U) -#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U) -#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU) -#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU) +#define MC_ADDRESS ((uint16_t)0x0000) +#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) +#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) +#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) /* NOR CFI IDs addresses */ -#define CFI1_ADDRESS ((uint16_t)0x61U) -#define CFI2_ADDRESS ((uint16_t)0x62U) -#define CFI3_ADDRESS ((uint16_t)0x63U) -#define CFI4_ADDRESS ((uint16_t)0x64U) +#define CFI1_ADDRESS ((uint16_t)0x61) +#define CFI2_ADDRESS ((uint16_t)0x62) +#define CFI3_ADDRESS ((uint16_t)0x63) +#define CFI4_ADDRESS ((uint16_t)0x64) /* NOR operation wait timeout */ -#define NOR_TMEOUT ((uint16_t)0xFFFFU) +#define NOR_TMEOUT ((uint16_t)0xFFFF) /* NOR memory data width */ -#define NOR_MEMORY_8B ((uint8_t)0x0U) -#define NOR_MEMORY_16B ((uint8_t)0x1U) +#define NOR_MEMORY_8B ((uint8_t)0x0) +#define NOR_MEMORY_16B ((uint8_t)0x1) /* NOR memory device read/write start address */ -#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U) -#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U) -#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U) -#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U) +#define NOR_MEMORY_ADRESS1 (0x60000000U) +#define NOR_MEMORY_ADRESS2 (0x64000000U) +#define NOR_MEMORY_ADRESS3 (0x68000000U) +#define NOR_MEMORY_ADRESS4 (0x6C000000U) /** * @} */ @@ -285,7 +291,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @retval NOR shifted address value */ #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ - ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ + ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pccard.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pccard.h index ab3f81079a..e35816f053 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pccard.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pccard.h @@ -80,9 +80,9 @@ typedef struct HAL_LockTypeDef Lock; /*!< PCCARD Lock */ #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp Init callback */ - void (* MspDeInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp DeInit callback */ - void (* ItCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD IT callback */ + void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */ + void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */ + void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */ #endif } PCCARD_HandleTypeDef; @@ -95,7 +95,7 @@ typedef enum HAL_PCCARD_MSP_INIT_CB_ID = 0x00U, /*!< PCCARD MspInit Callback ID */ HAL_PCCARD_MSP_DEINIT_CB_ID = 0x01U, /*!< PCCARD MspDeInit Callback ID */ HAL_PCCARD_IT_CB_ID = 0x02U /*!< PCCARD IT Callback ID */ -}HAL_PCCARD_CallbackIDTypeDef; +} HAL_PCCARD_CallbackIDTypeDef; /** * @brief HAL PCCARD Callback pointer definition @@ -137,7 +137,8 @@ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard); * @{ */ /* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming); +HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, + FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming); HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard); @@ -150,8 +151,10 @@ void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard); */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus); -HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus); -HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus); +HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, + uint8_t *pStatus); +HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, + uint8_t *pStatus); HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus); HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard); @@ -159,8 +162,10 @@ void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard); #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) /* PCCARD callback registering/unregistering */ -HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId); +HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, + pPCCARD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, + HAL_PCCARD_CallbackIDTypeDef CallbackId); #endif /** * @} diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h index ed1ead5675..822ca9b3b2 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h @@ -330,11 +330,11 @@ typedef struct */ #define RCC_PERIPHCLK_RTC 0x00000001U #define RCC_PERIPHCLK_ADC 0x00000002U -#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ - || defined(STM32F107xC) +#if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE)\ + || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) #define RCC_PERIPHCLK_I2S2 0x00000004U #define RCC_PERIPHCLK_I2S3 0x00000008U -#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_smartcard.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_smartcard.h index 0f5587d641..78b0a22b38 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_smartcard.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_smartcard.h @@ -708,7 +708,7 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc); #define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25U)/(4U*(__BAUD__))) #define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100U) -#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U + 50U) / 100U) +#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) ((((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100U)) * 16U) + 50U) / 100U) /* SMARTCARD BRR = mantissa + overflow + fraction = (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */ #define SMARTCARD_BRR(__PCLK__, __BAUD__) (((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4U) + \ diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h index 04914e6908..271bd3afde 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h @@ -487,7 +487,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) /** @brief Check whether the specified SPI flag is set or not. - * @param __SR__ copy of SPI SR regsiter. + * @param __SR__ copy of SPI SR register. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag @@ -498,10 +498,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_FLAG_BSY: Busy flag * @retval SET or RESET. */ -#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) +#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. - * @param __CR2__ copy of SPI CR2 regsiter. + * @param __CR2__ copy of SPI CR2 register. * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable @@ -509,15 +510,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_IT_ERR: Error interrupt enable * @retval SET or RESET. */ -#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. * This parameter can be a value of @ref SPI_Mode * @retval None */ -#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ - ((__MODE__) == SPI_MODE_MASTER)) +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) /** @brief Checks if SPI Direction Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Direction Mode. @@ -554,25 +556,25 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_Clock_Polarity * @retval None */ -#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ - ((__CPOL__) == SPI_POLARITY_HIGH)) +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) /** @brief Checks if SPI Clock Phase parameter is in allowed range. * @param __CPHA__ specifies the SPI Clock Phase. * This parameter can be a value of @ref SPI_Clock_Phase * @retval None */ -#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ - ((__CPHA__) == SPI_PHASE_2EDGE)) +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) /** @brief Checks if SPI Slave Select parameter is in allowed range. * @param __NSS__ specifies the SPI Slave Select management parameter. * This parameter can be a value of @ref SPI_Slave_Select_management * @retval None */ -#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ - ((__NSS__) == SPI_NSS_HARD_INPUT) || \ - ((__NSS__) == SPI_NSS_HARD_OUTPUT)) +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. * @param __PRESCALER__ specifies the SPI Baudrate prescaler. @@ -593,8 +595,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_MSB_LSB_transmission * @retval None */ -#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ - ((__BIT__) == SPI_FIRSTBIT_LSB)) +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) /** @brief Checks if SPI TI mode parameter is disabled. * @param __MODE__ SPI_TIMODE_DISABLE. Device not support Ti Mode. @@ -616,7 +618,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 * @retval None */ -#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ + ((__POLYNOMIAL__) <= 0xFFFFU) && \ + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h index 3bf0d5aa78..ef86a4bd4b 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sram.h @@ -77,10 +77,10 @@ typedef struct DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp Init callback */ - void (* MspDeInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp DeInit callback */ - void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Complete callback */ - void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Error callback */ + void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ + void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ + void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ #endif } SRAM_HandleTypeDef; @@ -94,7 +94,7 @@ typedef enum HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ -}HAL_SRAM_CallbackIDTypeDef; +} HAL_SRAM_CallbackIDTypeDef; /** * @brief HAL SRAM Callback pointer definition @@ -110,8 +110,8 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); /* Exported macro ------------------------------------------------------------*/ /** @defgroup SRAM_Exported_Macros SRAM Exported Macros - * @{ - */ + * @{ + */ /** @brief Reset SRAM handle state * @param __HANDLE__ SRAM handle @@ -137,11 +137,12 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); */ /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ + * @{ + */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, + FSMC_NORSRAM_TimingTypeDef *ExtTiming); HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); @@ -151,27 +152,37 @@ void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); */ /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions - * @{ - */ + * @{ + */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) /* SRAM callback registering/unregistering */ -HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); -HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_DmaCallbackTypeDef pCallback); #endif /** @@ -179,8 +190,8 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR */ /** @addtogroup SRAM_Exported_Functions_Group3 Control functions - * @{ - */ + * @{ + */ /* SRAM Control functions ****************************************************/ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); @@ -191,8 +202,8 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); */ /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions - * @{ - */ + * @{ + */ /* SRAM State functions ******************************************************/ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h index 8722e09fb8..632976a60a 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h @@ -167,7 +167,7 @@ typedef struct This parameter can be a value of @ref TIM_Encoder_Mode */ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC1Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ @@ -179,7 +179,7 @@ typedef struct This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC2Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ @@ -294,6 +294,26 @@ typedef enum HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ } HAL_TIM_StateTypeDef; +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + /** * @brief HAL Active channel structures definition */ @@ -315,13 +335,16 @@ typedef struct __TIM_HandleTypeDef typedef struct #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ @@ -360,34 +383,34 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ - ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ - ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ - ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ - ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - - ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ - ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ - ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ - ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ - ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ - ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ - ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ - ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ } HAL_TIM_CallbackIDTypeDef; /** @@ -593,6 +616,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ @@ -984,25 +1016,45 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @retval None */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->Base_MspInitCallback = NULL; \ - (__HANDLE__)->Base_MspDeInitCallback = NULL; \ - (__HANDLE__)->IC_MspInitCallback = NULL; \ - (__HANDLE__)->IC_MspDeInitCallback = NULL; \ - (__HANDLE__)->OC_MspInitCallback = NULL; \ - (__HANDLE__)->OC_MspDeInitCallback = NULL; \ - (__HANDLE__)->PWM_MspInitCallback = NULL; \ - (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ } while(0) #else -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** @@ -1547,6 +1599,9 @@ mode. #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ ((__STATE__) == TIM_OCNIDLESTATE_RESET)) +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) @@ -1698,15 +1753,15 @@ mode. #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) -#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ @@ -1717,6 +1772,8 @@ mode. ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) @@ -1742,11 +1799,49 @@ mode. ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP))) :\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P))) +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + (__HANDLE__)->ChannelState[3]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) + /** * @} */ @@ -1918,9 +2013,15 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, + uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, + uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -1966,6 +2067,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** * @} */ @@ -1985,7 +2091,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h index ad81f67f8b..1979d73153 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h @@ -223,6 +223,7 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); */ /* Extended Peripheral State functions ***************************************/ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h index 4c41e5a72c..97ebeaff92 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h @@ -537,7 +537,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) -/** @brief Checks whether the specified UART interrupt has occurred or not. +/** @brief Checks whether the specified UART interrupt source is enabled or not. * @param __HANDLE__ specifies the UART Handle. * UART Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). @@ -806,7 +806,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); #define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_))) #define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) -#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U) +#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U) /* UART BRR = mantissa + overflow + fraction = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ #define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ @@ -815,7 +815,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); #define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_))) #define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) -#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U) +#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U) /* UART BRR = mantissa + overflow + fraction = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ #define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_usart.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_usart.h index 9d5d2e9bb9..40a231f5f0 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_usart.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_usart.h @@ -607,7 +607,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); #define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U) -#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U) +#define USART_DIVFRAQ(_PCLK_, _BAUD_) ((((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U) /* UART BRR = mantissa + overflow + fraction = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF0) << 1) + (UART DIVFRAQ & 0x0FU) */ diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_wwdg.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_wwdg.h index 8e977736c0..d9916cf4ed 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_wwdg.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_wwdg.h @@ -37,6 +37,7 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ + /** @defgroup WWDG_Exported_Types WWDG Exported Types * @{ */ @@ -55,7 +56,7 @@ typedef struct uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ - uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not. + uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not. This parameter can be a value of @ref WWDG_EWI_Mode */ } WWDG_InitTypeDef; @@ -67,16 +68,17 @@ typedef struct typedef struct __WWDG_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ { - WWDG_TypeDef *Instance; /*!< Register base address */ + WWDG_TypeDef *Instance; /*!< Register base address */ + + WWDG_InitTypeDef Init; /*!< WWDG required parameters */ - WWDG_InitTypeDef Init; /*!< WWDG required parameters */ #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) - void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ + void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ - void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ -#endif + void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ } WWDG_HandleTypeDef; #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) @@ -85,16 +87,16 @@ typedef struct */ typedef enum { - HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */ - HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */ -}HAL_WWDG_CallbackIDTypeDef; + HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */ + HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */ +} HAL_WWDG_CallbackIDTypeDef; /** * @brief HAL WWDG Callback pointer definition */ -typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer to a WWDG common callback functions */ +typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */ -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} */ @@ -125,10 +127,10 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t /** @defgroup WWDG_Prescaler WWDG Prescaler * @{ */ -#define WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */ -#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ -#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ -#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */ +#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */ /** * @} */ @@ -136,7 +138,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t /** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode * @{ */ -#define WWDG_EWI_DISABLE 0x00000000U /*!< EWI Disable */ +#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */ #define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */ /** * @} @@ -151,9 +153,9 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t /** @defgroup WWDG_Private_Macros WWDG Private Macros * @{ */ -#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ - ((__PRESCALER__) == WWDG_PRESCALER_2) || \ - ((__PRESCALER__) == WWDG_PRESCALER_4) || \ +#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ + ((__PRESCALER__) == WWDG_PRESCALER_2) || \ + ((__PRESCALER__) == WWDG_PRESCALER_4) || \ ((__PRESCALER__) == WWDG_PRESCALER_8)) #define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W)) @@ -174,14 +176,14 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t */ /** - * @brief Enables the WWDG peripheral. - * @param __HANDLE__: WWDG handle + * @brief Enable the WWDG peripheral. + * @param __HANDLE__ WWDG handle * @retval None */ -#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) +#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) /** - * @brief Enables the WWDG early wakeup interrupt. + * @brief Enable the WWDG early wakeup interrupt. * @param __HANDLE__: WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: @@ -192,23 +194,23 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t #define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__)) /** - * @brief Checks whether the selected WWDG interrupt has occurred or not. + * @brief Check whether the selected WWDG interrupt has occurred or not. * @param __HANDLE__ WWDG handle * @param __INTERRUPT__ specifies the it to check. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT * @retval The new state of WWDG_FLAG (SET or RESET). */ -#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__)) +#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__)) -/** @brief Clear the WWDG's interrupt pending bits +/** @brief Clear the WWDG interrupt pending bits. * bits to clear the selected interrupt pending bits. - * @param __HANDLE__: WWDG handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ WWDG handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag */ -#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) +#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) /** * @brief Check whether the specified WWDG flag is set or not. @@ -218,32 +220,34 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag * @retval The new state of WWDG_FLAG (SET or RESET). */ -#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) +#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) /** - * @brief Clears the WWDG's pending flags. - * @param __HANDLE__: WWDG handle - * @param __FLAG__: specifies the flag to clear. + * @brief Clear the WWDG's pending flags. + * @param __HANDLE__ WWDG handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag * @retval None */ -#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) +#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) -/** @brief Checks if the specified WWDG interrupt source is enabled or disabled. - * @param __HANDLE__: WWDG Handle. - * @param __INTERRUPT__: specifies the WWDG interrupt source to check. - * This parameter can be one of the following values: +/** @brief Check whether the specified WWDG interrupt source is enabled or not. + * @param __HANDLE__ WWDG Handle. + * @param __INTERRUPT__ specifies the WWDG interrupt source to check. + * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early Wakeup Interrupt * @retval state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) /** * @} */ /* Exported functions --------------------------------------------------------*/ + /** @addtogroup WWDG_Exported_Functions * @{ */ @@ -254,12 +258,12 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t /* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); - /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, + pWWDG_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h index a7b7c6ed5f..1710cea0ac 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h @@ -67,7 +67,7 @@ extern "C" { #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ - ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) + ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ @@ -97,9 +97,9 @@ extern "C" { #define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3) #define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ - ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) + ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) #define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) + ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) #define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \ ((__STATE__) == FSMC_NAND_ECC_ENABLE)) @@ -212,7 +212,7 @@ typedef struct uint32_t PageSize; /*!< Specifies the memory page size. This parameter can be a value of @ref FSMC_Page_Size */ -}FSMC_NORSRAM_InitTypeDef; +} FSMC_NORSRAM_InitTypeDef; /** * @brief FSMC NORSRAM Timing parameters structure definition @@ -255,7 +255,7 @@ typedef struct uint32_t AccessMode; /*!< Specifies the asynchronous access mode. This parameter can be a value of @ref FSMC_Access_Mode */ -}FSMC_NORSRAM_TimingTypeDef; +} FSMC_NORSRAM_TimingTypeDef; #endif /* FSMC_BANK1 */ #if defined(FSMC_BANK3) @@ -286,7 +286,7 @@ typedef struct uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ -}FSMC_NAND_InitTypeDef; +} FSMC_NAND_InitTypeDef; #endif #if defined(FSMC_BANK3)||defined(FSMC_BANK4) @@ -319,7 +319,7 @@ typedef struct write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ -}FSMC_NAND_PCC_TimingTypeDef; +} FSMC_NAND_PCC_TimingTypeDef; #endif /* FSMC_BANK3 */ #if defined(FSMC_BANK4) @@ -358,10 +358,10 @@ typedef struct /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank * @{ */ -#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) -#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002U) -#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004U) -#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006U) +#define FSMC_NORSRAM_BANK1 (0x00000000U) +#define FSMC_NORSRAM_BANK2 (0x00000002U) +#define FSMC_NORSRAM_BANK3 (0x00000004U) +#define FSMC_NORSRAM_BANK4 (0x00000006U) /** * @} */ @@ -369,8 +369,8 @@ typedef struct /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing * @{ */ -#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U) -#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U) +#define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) +#define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) /** * @} */ @@ -378,9 +378,9 @@ typedef struct /** @defgroup FSMC_Memory_Type FSMC Memory Type * @{ */ -#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U) -#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U) -#define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U) +#define FSMC_MEMORY_TYPE_SRAM (0x00000000U) +#define FSMC_MEMORY_TYPE_PSRAM (0x00000004U) +#define FSMC_MEMORY_TYPE_NOR (0x00000008U) /** * @} */ @@ -388,9 +388,9 @@ typedef struct /** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width * @{ */ -#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) -#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) -#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) +#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) /** * @} */ @@ -398,8 +398,8 @@ typedef struct /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access * @{ */ -#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U) -#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U) +#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) +#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) /** * @} */ @@ -407,8 +407,8 @@ typedef struct /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode * @{ */ -#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U) -#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U) +#define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) +#define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) /** * @} */ @@ -416,8 +416,8 @@ typedef struct /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity * @{ */ -#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U) -#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U) +#define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) +#define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) /** * @} */ @@ -425,8 +425,8 @@ typedef struct /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode * @{ */ -#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U) -#define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U) +#define FSMC_WRAP_MODE_DISABLE (0x00000000U) +#define FSMC_WRAP_MODE_ENABLE (0x00000400U) /** * @} */ @@ -434,8 +434,8 @@ typedef struct /** @defgroup FSMC_Wait_Timing FSMC Wait Timing * @{ */ -#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U) -#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U) +#define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U) +#define FSMC_WAIT_TIMING_DURING_WS (0x00000800U) /** * @} */ @@ -443,8 +443,8 @@ typedef struct /** @defgroup FSMC_Write_Operation FSMC Write Operation * @{ */ -#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U) -#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U) +#define FSMC_WRITE_OPERATION_DISABLE (0x00000000U) +#define FSMC_WRITE_OPERATION_ENABLE (0x00001000U) /** * @} */ @@ -452,8 +452,8 @@ typedef struct /** @defgroup FSMC_Wait_Signal FSMC Wait Signal * @{ */ -#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U) -#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U) +#define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U) +#define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U) /** * @} */ @@ -461,8 +461,8 @@ typedef struct /** @defgroup FSMC_Extended_Mode FSMC Extended Mode * @{ */ -#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U) -#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U) +#define FSMC_EXTENDED_MODE_DISABLE (0x00000000U) +#define FSMC_EXTENDED_MODE_ENABLE (0x00004000U) /** * @} */ @@ -470,8 +470,8 @@ typedef struct /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait * @{ */ -#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U) -#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U) +#define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) +#define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) /** * @} */ @@ -479,11 +479,11 @@ typedef struct /** @defgroup FSMC_Page_Size FSMC Page Size * @{ */ -#define FSMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U) -#define FSMC_PAGE_SIZE_128 ((uint32_t)0x00010000U) -#define FSMC_PAGE_SIZE_256 ((uint32_t)0x00020000U) -#define FSMC_PAGE_SIZE_512 ((uint32_t)0x00030000U) -#define FSMC_PAGE_SIZE_1024 ((uint32_t)0x00040000U) +#define FSMC_PAGE_SIZE_NONE (0x00000000U) +#define FSMC_PAGE_SIZE_128 (0x00010000U) +#define FSMC_PAGE_SIZE_256 (0x00020000U) +#define FSMC_PAGE_SIZE_512 (0x00030000U) +#define FSMC_PAGE_SIZE_1024 (0x00040000U) /** * @} */ @@ -491,8 +491,8 @@ typedef struct /** @defgroup FSMC_Write_Burst FSMC Write Burst * @{ */ -#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U) -#define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U) +#define FSMC_WRITE_BURST_DISABLE (0x00000000U) +#define FSMC_WRITE_BURST_ENABLE (0x00080000U) /** * @} */ @@ -500,19 +500,19 @@ typedef struct /** @defgroup FSMC_Continous_Clock FSMC Continuous Clock * @{ */ -#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U) -#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U) +#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) +#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) /** * @} */ - /** @defgroup FSMC_Access_Mode FSMC Access Mode +/** @defgroup FSMC_Access_Mode FSMC Access Mode * @{ */ -#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000U) -#define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000U) -#define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000U) -#define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000U) +#define FSMC_ACCESS_MODE_A (0x00000000U) +#define FSMC_ACCESS_MODE_B (0x10000000U) +#define FSMC_ACCESS_MODE_C (0x20000000U) +#define FSMC_ACCESS_MODE_D (0x30000000U) /** * @} */ @@ -530,8 +530,8 @@ typedef struct /** @defgroup FSMC_NAND_Bank FSMC NAND Bank * @{ */ -#define FSMC_NAND_BANK2 ((uint32_t)0x00000010U) -#define FSMC_NAND_BANK3 ((uint32_t)0x00000100U) +#define FSMC_NAND_BANK2 (0x00000010U) +#define FSMC_NAND_BANK3 (0x00000100U) /** * @} */ @@ -539,8 +539,8 @@ typedef struct /** @defgroup FSMC_Wait_feature FSMC Wait feature * @{ */ -#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U) -#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U) +#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U) +#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U) /** * @} */ @@ -549,9 +549,9 @@ typedef struct * @{ */ #if defined(FSMC_BANK4) -#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U) +#define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U) #endif -#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U) +#define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U) /** * @} */ @@ -559,8 +559,8 @@ typedef struct /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width * @{ */ -#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) -#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) +#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U) +#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U) /** * @} */ @@ -568,8 +568,8 @@ typedef struct /** @defgroup FSMC_ECC FSMC ECC * @{ */ -#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U) -#define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U) +#define FSMC_NAND_ECC_DISABLE (0x00000000U) +#define FSMC_NAND_ECC_ENABLE (0x00000040U) /** * @} */ @@ -577,12 +577,12 @@ typedef struct /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size * @{ */ -#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U) -#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U) -#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U) -#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U) -#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U) -#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U) +#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) +#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) +#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) +#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) +#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) +#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) /** * @} */ @@ -597,9 +597,9 @@ typedef struct * @{ */ #if defined(FSMC_BANK3)||defined(FSMC_BANK4) -#define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008U) -#define FSMC_IT_LEVEL ((uint32_t)0x00000010U) -#define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020U) +#define FSMC_IT_RISING_EDGE (0x00000008U) +#define FSMC_IT_LEVEL (0x00000010U) +#define FSMC_IT_FALLING_EDGE (0x00000020U) #endif /* FSMC_BANK3 */ /** * @} @@ -609,10 +609,10 @@ typedef struct * @{ */ #if defined(FSMC_BANK3)||defined(FSMC_BANK4) -#define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U) -#define FSMC_FLAG_LEVEL ((uint32_t)0x00000002U) -#define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U) -#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040U) +#define FSMC_FLAG_RISING_EDGE (0x00000001U) +#define FSMC_FLAG_LEVEL (0x00000002U) +#define FSMC_FLAG_FALLING_EDGE (0x00000004U) +#define FSMC_FLAG_FEMPT (0x00000040U) #endif /* FSMC_BANK3 */ /** * @} @@ -642,7 +642,8 @@ typedef struct * @param __BANK__ FSMC_NORSRAM Bank * @retval None */ -#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCRx_MBKEN) +#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + |= FSMC_BCRx_MBKEN) /** * @brief Disable the NORSRAM device access. @@ -650,7 +651,8 @@ typedef struct * @param __BANK__ FSMC_NORSRAM Bank * @retval None */ -#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCRx_MBKEN) +#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + &= ~FSMC_BCRx_MBKEN) /** * @} @@ -659,9 +661,9 @@ typedef struct #if defined(FSMC_BANK3) /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros - * @brief macros to handle NAND device enable/disable - * @{ - */ + * @brief macros to handle NAND device enable/disable + * @{ + */ /** * @brief Enable the NAND device access. @@ -688,9 +690,9 @@ typedef struct #if defined(FSMC_BANK4) /** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros - * @brief macros to handle PCCARD read/write operations - * @{ - */ + * @brief macros to handle PCCARD read/write operations + * @{ + */ /** * @brief Enable the PCCARD device access. * @param __INSTANCE__ FSMC_PCCARD Instance @@ -859,10 +861,14 @@ typedef struct /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init); -HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); -HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); +HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); +HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); /** * @} */ @@ -888,8 +894,10 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Dev * @{ */ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); -HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -900,7 +908,8 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); +HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout); /** * @} */ @@ -917,9 +926,12 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, * @{ */ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); -HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); -HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); -HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing); HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); /** * @} diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h index 71f0aa5c69..c6f41d5d2d 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h @@ -341,7 +341,7 @@ typedef struct */ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) { - register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); MODIFY_REG(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U))); } @@ -381,7 +381,7 @@ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 */ __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) { - register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); return (READ_BIT(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); } @@ -419,7 +419,7 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) */ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) { - register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)), (Speed << (POSITION_VAL(Pin) * 4U))); } @@ -457,7 +457,7 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint */ __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) { - register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); return (READ_BIT(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); } @@ -493,7 +493,7 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) */ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType) { - register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)), (OutputType << (POSITION_VAL(Pin) * 4U))); } @@ -530,7 +530,7 @@ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, */ __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) { - register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); return (READ_BIT(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); } @@ -861,7 +861,9 @@ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMas */ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { - WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); + uint32_t odr = READ_REG(GPIOx->ODR); + uint32_t pinmask = ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU); + WRITE_REG(GPIOx->BSRR, ((odr & pinmask) << 16u) | (~odr & pinmask)); } /** diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_iwdg.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_iwdg.h index 6bd5662385..3a651bf8e4 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_iwdg.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_iwdg.h @@ -45,12 +45,10 @@ extern "C" { /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants * @{ */ - #define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ #define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ #define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ #define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ - /** * @} */ @@ -69,7 +67,6 @@ extern "C" { */ #define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ #define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ - /** * @} */ @@ -143,7 +140,7 @@ extern "C" { */ __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) { - WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE); + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); } /** @@ -154,7 +151,7 @@ __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) { - WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD); + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); } /** @@ -165,7 +162,7 @@ __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) { - WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); } /** @@ -176,7 +173,7 @@ __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) { - WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); } /** @@ -213,7 +210,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale */ __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) { - return (uint32_t)(READ_REG(IWDGx->PR)); + return (READ_REG(IWDGx->PR)); } /** @@ -236,7 +233,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun */ __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) { - return (uint32_t)(READ_REG(IWDGx->RLR)); + return (READ_REG(IWDGx->RLR)); } @@ -256,7 +253,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) { - return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)); + return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); } /** @@ -267,12 +264,11 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) { - return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)); + return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); } - /** - * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not + * @brief Check if flags Prescaler & Reload Value Update are reset or not * @rmtoll SR PVU LL_IWDG_IsReady\n * SR RVU LL_IWDG_IsReady * @param IWDGx IWDG Instance @@ -280,7 +276,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) */ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) { - return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U); + return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL); } /** @@ -296,7 +292,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) * @} */ -#endif /* IWDG) */ +#endif /* IWDG */ /** * @} diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h index 419e491983..804c75f5dc 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h @@ -1520,8 +1520,8 @@ __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) { #if defined(RCC_CFGR2_PREDIV1SRC) - register uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC); - register uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U); + uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC); + uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U); return (uint32_t)(pllsrc | predivsrc); #else return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h index b45654472f..bf0e764669 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h @@ -675,8 +675,8 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) */ __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) { - register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); - register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); return (Ssm | Ssoe); } @@ -1198,10 +1198,10 @@ typedef struct /** @defgroup I2S_LL_EC_DATA_FORMAT Data format * @{ */ -#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */ -#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */ -#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */ -#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */ +#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */ +#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */ /** * @} */ @@ -1536,7 +1536,7 @@ __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) } /** - * @brief Enable the master clock ouput (Pin MCK) + * @brief Enable the master clock output (Pin MCK) * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock * @param SPIx SPI Instance * @retval None @@ -1547,7 +1547,7 @@ __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) } /** - * @brief Disable the master clock ouput (Pin MCK) + * @brief Disable the master clock output (Pin MCK) * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock * @param SPIx SPI Instance * @retval None @@ -1558,7 +1558,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) } /** - * @brief Check if the master clock ouput (Pin MCK) is enabled + * @brief Check if the master clock output (Pin MCK) is enabled * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock * @param SPIx SPI Instance * @retval State of bit (1 or 0). diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h index a3d9dcad3b..354c35a754 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h @@ -198,13 +198,14 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ - uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ } LL_TIM_InitTypeDef; @@ -512,8 +513,8 @@ typedef struct */ #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); @@ -1594,8 +1595,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } @@ -1623,8 +1624,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint */ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } @@ -1653,7 +1654,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); } @@ -1681,7 +1682,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } @@ -1714,7 +1715,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann */ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); } @@ -1742,7 +1743,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); } @@ -1763,8 +1764,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -1785,8 +1786,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -1807,9 +1808,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -1829,8 +1830,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha */ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -1850,8 +1851,8 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -1871,9 +1872,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -1896,8 +1897,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t */ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -1919,8 +1920,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -1944,9 +1945,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2116,8 +2117,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), @@ -2144,8 +2145,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3 */ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2168,8 +2169,8 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2194,8 +2195,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch */ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2219,8 +2220,8 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2257,8 +2258,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2294,8 +2295,8 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui */ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2321,7 +2322,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), ICPolarity << SHIFT_TAB_CCxP[iChannel]); } @@ -2347,7 +2348,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h index 20c1977e86..9993b1736d 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h @@ -377,7 +377,7 @@ typedef struct */ #define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__))) #define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100) -#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100) +#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16) + 50) / 100) /* USART BRR = mantissa + overflow + fraction = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */ #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ @@ -1050,8 +1050,8 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph */ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) { - register uint32_t usartdiv = 0x0U; - register uint32_t brrresult = 0x0U; + uint32_t usartdiv = 0x0U; + uint32_t brrresult = 0x0U; usartdiv = USARTx->BRR; @@ -1101,8 +1101,8 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph */ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk) { - register uint32_t usartdiv = 0x0U; - register uint32_t brrresult = 0x0U; + uint32_t usartdiv = 0x0U; + uint32_t brrresult = 0x0U; usartdiv = USARTx->BRR; diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h index 135d8f7451..5f35ab2f98 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h @@ -602,6 +602,7 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg); HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx); HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed); HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx); HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num); HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); @@ -614,6 +615,11 @@ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx); HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup); +HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len); + +void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len); + uint32_t USB_ReadInterrupts(USB_TypeDef *USBx); uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx); uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum); diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h index e7616fd597..bc016b76ac 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h @@ -236,6 +236,9 @@ void LL_mDelay(uint32_t Delay); */ void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +#if defined(FLASH_ACR_LATENCY) +ErrorStatus LL_SetFlashLatency(uint32_t Frequency); +#endif /* FLASH_ACR_LATENCY */ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_wwdg.h b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_wwdg.h index b8b8d7d7e2..c4ddbd44ea 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_wwdg.h +++ b/system/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_wwdg.h @@ -33,6 +33,7 @@ extern "C" { */ #if defined (WWDG) + /** @defgroup WWDG_LL WWDG * @{ */ @@ -51,18 +52,18 @@ extern "C" { * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions * @{ */ -#define LL_WWDG_CFR_EWI WWDG_CFR_EWI +#define LL_WWDG_CFR_EWI WWDG_CFR_EWI /** * @} */ /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER -* @{ -*/ -#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */ -#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ -#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ -#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ + * @{ + */ +#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ /** * @} */ diff --git a/system/Drivers/STM32F1xx_HAL_Driver/README.md b/system/Drivers/STM32F1xx_HAL_Driver/README.md index a972b7cbcc..0b884ec590 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/README.md +++ b/system/Drivers/STM32F1xx_HAL_Driver/README.md @@ -40,6 +40,7 @@ HAL Driver F1 | CMSIS Device F1 | CMSIS Core | Was delivered in the full MCU pac ------------- | --------------- | ---------- | ------------------------------------- Tag v1.1.4 | Tag v4.3.1 | Tag v5.4.0_cm3 | Tag v1.8.0 (and following, if any, till next new tag) Tag v1.1.5 | Tag v4.3.1 | Tag v5.4.0_cm3 | Tag v1.8.1 (and following, if any, till next new tag) +Tag v1.1.6 | Tag v4.3.2 | Tag v5.4.0_cm3 | Tag v1.8.2 (and following, if any, till next new tag) The full **STM32CubeF1** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF1). diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F1xx_HAL_Driver/Release_Notes.html index 8639489432..1198b1ccdc 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F1xx_HAL_Driver/Release_Notes.html @@ -38,7 +38,7 @@

License

Update History

- +

Main Changes

    @@ -46,6 +46,189 @@

    Main Changes

Contents

    +
  • HAL/LL ADC driver +
      +
    • Update HAL_ADC_Stop_DMA() API to check if DMA state is Busy before calling HAL_DMA_Abort() API to avoid DMA internal error.
      • +
    • update LL_ADC_REG_Init() API to avoid enabling continuous mode and discontinuous mode simultaneously.
      • +
    • +
  • HAL/LL GPIO driver +
      +
    • Update HAL_GPIO_TogglePin() API to allow multi Pin’s toggling.
      • +
    • Update LL_GPIO_TogglePin() API to improve robustness: use BSRR register instead of ODR register.
      • +
    • Update LL GPIO initialization sequence to avoid unwanted pulse on GPIO Pin’s
      • +
    • +
  • HAL/LL I2S driver +
      +
    • Update HAL_I2S_DMAStop() API to be more safe +
        +
      • Add a check on BSY, TXE and RXNE flags before disabling the I2S
        • +
      • +
    • +
  • HAL/LL SPI driver +
      +
    • Update SPI_DMAReceiveCplt() API to handle efficiently the repeated transfers. +
        +
      • Disable TX DMA request only in bidirectional receive mode
        • +
      • +
    • Update HAL_SPI_Init() API +
        +
      • To avoid setting the BaudRatePrescaler in case of Slave Motorola Mode
        • +
      • Use the bit-mask for SPI configuration
        • +
      • +
    • Update Transmit/Receive processes in half-duplex mode +
        +
      • Disable the SPI instance before setting BDIOE bit
        • +
      • +
    • Fix wrong timeout management +
        +
      • Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled
        • +
      • +
    • +
  • HAL NOR driver +
      +
    • Update address calculation in HAL_NOR_ProgramBuffer()
      • +
    • Apply adequate commands according to the command set field value +
        +
      • command set 1 for Micron JS28F512P33
        • +
      • command set 2 for Micron M29W128G and Cypress S29GL128P
        • +
      • +
    • Add new commands operations: +
        +
      • NOR_CMD_READ_ARRAY
        • +
      • NOR_CMD_WORD_PROGRAM
        • +
      • NOR_CMD_BUFFERED_PROGRAM
        • +
      • NOR_CMD_CONFIRM
        • +
      • NOR_CMD_BLOCK_ERASE
        • +
      • NOR_CMD_BLOCK_UNLOCK
        • +
      • NOR_CMD_READ_STATUS_REG
        • +
      • NOR_CMD_CLEAR_STATUS_REG
        • +
      • +
    • Update some APIs in order to be compliant for memories with another command set. +
        +
      • HAL_NOR_Init()
        • +
      • HAL_NOR_Read_ID()
        • +
      • HAL_NOR_ReturnToReadMode()
        • +
      • HAL_NOR_Read()
        • +
      • HAL_NOR_Program()
        • +
      • HAL_NOR_ReadBuffer()
        • +
      • HAL_NOR_ProgramBuffer()
        • +
      • HAL_NOR_Erase_Block()
        • +
      • HAL_NOR_Erase_Chip()
        • +
      • HAL_NOR_GetStatus()
        • +
      • +
    • +
  • HAL SRAM driver +
      +
    • General update to enhance HAL SRAM driver robustness +
        +
      • Update HAL_SRAM_Init() API to avoid activation of burst access for SRAM
        • +
      • +
    • +
  • HAL FSMC driver +
      +
    • Update FSMC_NORSRAM_Init() API in order to resolve compilation issue with MS Visual 2017
      • +
    • Update FSMC_NORSRAM_Extended_Timing_Init() API in order to manage Bus turnaround phase duration FSMC_BWTR1_BUSTURN availability.
      • +
    • +
  • LL UTILS driver +
      +
    • UTILS_SetFlashLatency() API renamed to LL_SetFlashLatency() and set exportable.
      • +
    • +
  • HAL/LL IWDG driver +
      +
    • Update HAL_IWDG_DEFAULT_TIMEOUT define value to consider LSI value instead of hardcoded value.
      • +
    • +
  • HAL/LL TIM driver +
      +
    • Align HAL/LL TIM driver with latest updates and enhancements
      • +
    • Update Encoder interface mode to keep TIM_CCER_CCxNP bits low +
        +
      • Add TIM_ENCODERINPUTPOLARITY_RISING and TIM_ENCODERINPUTPOLARITY_FALLING definitions to determine encoder input polarity.
        • +
      • Add IS_TIM_ENCODERINPUT_POLARITY() macro to check the encoder input polarity.
        • +
      • Update HAL_TIM_Encoder_Init() API
        • +
      • Replace IS_TIM_IC_POLARITY() macro by IS_TIM_ENCODERINPUT_POLARITY() macro.
        • +
      • +
    • Fix bug when using multiple DMA request to different channels of same timer +
        +
      • Introduce DMA burst state management mechanism +
          +
        • Add a new structure for DMA Burst States definition : HAL_TIM_DMABurstStateTypeDef
          • +
        • Update __HAL_TIM_RESET_HANDLE_STATE to support DMABurstState
          • +
        • Add a new API HAL_TIM_DMABurstState() to get the actual state of a DMA burst operation
          • +
        • Add DMABurstState, the DMA burst operation state, in the TIM_HandleTypeDef structure
          • +
        • Add new API TIM_DMAErrorCCxN() for TIM DMA error callback (complementary channel)
          • +
        • Add new API TIM_DMADelayPulseNCplt() for TIM DMA Delay Pulse complete callback (complementary channel)
          • +
        • +
      • +
    • Implement TIM channel state management mechanism +
        +
      • Add new macro +
          +
        • TIM_CHANNEL_STATE_SET_ALL and TIM_CHANNEL_N_STATE_SET_ALL
          • +
        • TIM_CHANNEL_STATE_SET and TIM_CHANNEL_N_STATE_SET
          • +
        • TIM_CHANNEL_STATE_GET and TIM_CHANNEL_N_STATE_GET
          • +
        • +
      • Add new API HAL_TIM_GetActiveChannel()
        • +
      • Add new API HAL_TIM_GetChannelState() to get actual state of the TIM channel
        • +
      • Add a new structure for TIM channel States definition : HAL_TIM_ChannelStateTypeDef
        • +
      • Update __HAL_TIM_RESET_HANDLE_STATE to support ChannelState and ChannelNState
        • +
      • Add a new element in the TIM_HandleTypeDef structure : ChannelState to manage TIM channel operation state
        • +
      • Add a new element in the TIM_HandleTypeDef structure : ChannelNState to manage TIM complementary channel operation state
        • +
      • +
    • Update HAL_TIMEx_MasterConfigSynchronization() API to avoid functional errors and assert fails when using some TIM instances as input trigger. +
        +
      • Replace IS_TIM_SYNCHRO_INSTANCE() macro by IS_TIM_MASTER_INSTANCE() macro.
        • +
      • Add IS_TIM_SLAVE_INSTANCE() macro to check on TIM_SMCR_MSM bit.
        • +
      • +
    • Remove ‘register’ storage class specifier from LL TIM driver.
      • +
    • Add new API HAL_TIM_DMABurst_MultiWriteStart() allowing to configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
      • +
    • Add new API HAL_TIM_DMABurst_MultiReadStart() allowing to configure the DMA Burst to transfer Data from the TIM peripheral to the memory
      • +
    • +
  • HAL/LL UART driver +
      +
    • Update UART polling processes to handle efficiently the Lock mechanism +
        +
      • Move the process unlock at the top of the HAL_UART_Receive() and HAL_UART_Transmit() API.
        • +
      • +
    • Update UART polling and interruption processes to fix issues related to accesses out of user specified buffer. +
        +
      • Update UART_Transmit_IT(), UART_Receive_IT(), HAL_UART_Transmit() and HAL_UART_Receive() APIs.
        • +
      • +
    • Update UART interruption handler to manage correctly the overrun interrupt +
        +
      • Add in the HAL_UART_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
        • +
      • +
    • Update UART BRR calculation for ROM size gain
      • +
    • +
  • HAL/LL USART driver +
      +
    • Update USART interruption handler to manage correctly the overrun interrupt +
        +
      • Add in the HAL_USART_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
        • +
      • +
    • +
  • HAL SMARTCARD driver +
      +
    • Update SMARTCARD interruption handler to manage correctly the overrun interrupt +
        +
      • Add in the HAL_SMARTCARD_IRQHandler() API a check on USART_CR1_RXNEIE bit when an overrun interrupt occurs.
        • +
      • +
    • Update SMARTCARD transmission and reception API to handle memory corruption +
        +
      • HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit_IT() and HAL_SMARTCARD_Receive_IT()
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and enhancements implementation
    • +
+

Contents

+
  • HAL driver
    • Enhance HAL_SetTickFreq() API robustness @@ -97,7 +280,7 @@

      Contents

      -

      Main Changes

      +

      Main Changes

      • General updates to fix known defects and enhancements implementation
      • Add support of HAL callback registration feature
        • @@ -304,7 +487,7 @@

        Main Changes

        -

        Main Changes

        +

        Main Changes

        • Maintenance release to fix known defects and enhancements implementation
        • Generic drivers changes
          • @@ -347,7 +530,7 @@

          Main Changes

          -

          Main Changes

          +

          Main Changes

          • General updates to fix known defects and enhancements implementation
          • Remove Date and version from header files
            • @@ -425,7 +608,7 @@

            Main Changes

            -

            Main Changes

            +

            Main Changes

            • General updates to fix known defects and enhancements implementation
            • HAL Generic update @@ -451,7 +634,7 @@

              Main Changes

              -

              Main Changes

              +

              Main Changes

              • Add Low Layer drivers allowing performance and footprint optimization
                  @@ -733,7 +916,7 @@

                  Main Changes

                  -

                  Main Changes

                  +

                  Main Changes

                  • General updates to fix mainly known I2C defects and enhancements implementation
                  • The following changes done on the HAL drivers require an update on the application code based on HAL V1.0.4 @@ -829,7 +1012,7 @@

                    Main Changes

                    -

                    Main Changes

                    +

                    Main Changes

                    • General updates to fix known defects and enhancements implementation.
                    • HAL RCC @@ -869,7 +1052,7 @@

                      Main Changes

                      -

                      Main Changes

                      +

                      Main Changes

                      • Remove the #if defined(USE_HAL_LEGACY) condition to include Legacy/stm32_hal_legacy.h by default, in stm32f1xx_hal_def.h.
                      @@ -878,7 +1061,7 @@

                      Main Changes

                      -

                      Main Changes

                      +

                      Main Changes

                      • General updates to fix known defects and enhancements implementation.
                      • HAL generic @@ -964,7 +1147,7 @@

                        Main Changes

                        -

                        Main Changes

                        +

                        Main Changes

                        • General updates to fix known defects and enhancements implementation.
                        • HAL generic @@ -1066,7 +1249,7 @@

                          Main Changes

                          -

                          Main Changes

                          +

                          Main Changes

                          • First Official release of STM32F1xx HAL Drivers for all STM32F1 devices.
                          • This release is in line with STM32Cube Firmware specification Rev1.0 document
                            • diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c index fbe94fd628..e34cd3bf9f 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c @@ -53,11 +53,11 @@ * @{ */ /** - * @brief STM32F1xx HAL Driver version number V1.1.5 + * @brief STM32F1xx HAL Driver version number V1.1.6 */ #define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ -#define __STM32F1xx_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */ +#define __STM32F1xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */ #define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\ |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c index b1e2389cce..21bd31c331 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c @@ -1711,20 +1711,23 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* DMA transfer is on going) */ - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Check if DMA channel effectively disabled */ - if (tmp_hal_status == HAL_OK) + if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + } } } diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c index 25555ba08e..6ba68a9b64 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c @@ -486,17 +486,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { + uint32_t odr; + /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - if ((GPIOx->ODR & GPIO_Pin) != 0x00u) - { - GPIOx->BRR = (uint32_t)GPIO_Pin; - } - else - { - GPIOx->BSRR = (uint32_t)GPIO_Pin; - } + /* get current Ouput Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); } /** diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c index 7cbc8ca132..f02014e40e 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c @@ -90,6 +90,10 @@ (+) Pause the DMA Transfer using HAL_I2S_DMAPause() (+) Resume the DMA Transfer using HAL_I2S_DMAResume() (+) Stop the DMA Transfer using HAL_I2S_DMAStop() + In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error + HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data. + In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data + inside DR register and avoid using DeInit/Init process for the next transfer. *** I2S HAL driver macros list *** =================================== @@ -101,6 +105,7 @@ (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not + (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data [..] (@) You can refer to the I2S HAL driver header file for more useful macros @@ -201,6 +206,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -338,7 +344,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) /* I2S standard */ if (hi2s->Init.Standard <= I2S_STANDARD_LSB) { - /* In I2S standard packet lenght is multiplied by 2 */ + /* In I2S standard packet length is multiplied by 2 */ packetlength = packetlength * 2U; } @@ -1369,35 +1375,86 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() */ - /* Disable the I2S Tx/Rx DMA requests */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Abort the I2S DMA tx Stream/Channel */ - if (hi2s->hdmatx != NULL) + if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)) { - /* Disable the I2S DMA tx Stream/Channel */ - if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) + /* Abort the I2S DMA tx Stream/Channel */ + if (hi2s->hdmatx != NULL) { - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - errorcode = HAL_ERROR; + /* Disable the I2S DMA tx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Wait until TXE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + + /* Wait until BSY flag is Reset */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; } + + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + /* Clear UDR flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Disable the I2S Tx DMA requests */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } - /* Abort the I2S DMA rx Stream/Channel */ - if (hi2s->hdmarx != NULL) + else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)) { - /* Disable the I2S DMA rx Stream/Channel */ - if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) + /* Abort the I2S DMA rx Stream/Channel */ + if (hi2s->hdmarx != NULL) + { + /* Disable the I2S DMA rx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + /* Clear OVR flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Disable the I2S Rx DMA request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + + if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX) { - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; errorcode = HAL_ERROR; } + else + { + /* Read DR to Flush RX Data */ + READ_REG((hi2s->Instance)->DR); + } } - /* Disable I2S peripheral */ - __HAL_I2S_DISABLE(hi2s); - hi2s->State = HAL_I2S_STATE_READY; return errorcode; diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c index 4d9bb02f20..4c2b11b3b8 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c @@ -16,45 +16,56 @@ (+) The IWDG can be started by either software or hardware (configurable through option byte). - (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even - if the main clock fails. + (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays + active even if the main clock fails. - (+) Once the IWDG is started, the LSI is forced ON and both can not be + (+) Once the IWDG is started, the LSI is forced ON and both cannot be disabled. The counter starts counting down from the reset value (0xFFF). When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, - the IWDG_RLR value is reloaded in the counter and the watchdog reset is - prevented. + the IWDG_RLR value is reloaded into the counter and the watchdog reset + is prevented. (+) The IWDG is implemented in the VDD voltage domain that is still functional - in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). + in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY). IWDGRST flag in RCC_CSR register can be used to inform when an IWDG reset occurs. - (+) Debug mode : When the microcontroller enters debug mode (core halted), + (+) Debug mode: When the microcontroller enters debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module, accessible through - __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros + __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros. [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s - The IWDG timeout may vary due to LSI frequency dispersion. STM32F1xx - devices provide the capability to measure the LSI frequency (LSI clock - connected internally to TIM5 CH4 input capture). The measured value - can be used to have an IWDG timeout with an acceptable accuracy. + The IWDG timeout may vary due to LSI clock frequency dispersion. + STM32F1xx devices provide the capability to measure the LSI clock + frequency (LSI clock is internally connected to TIM5 CH4 input capture). + The measured value can be used to have an IWDG timeout with an + acceptable accuracy. + + [..] Default timeout value (necessary for IWDG_SR status register update): + Constant LSI_VALUE is defined based on the nominal LSI clock frequency. + This frequency being subject to variations as mentioned above, the + default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT + below) may become too short or too long. + In such cases, this default timeout value can be tuned by redefining + the constant LSI_VALUE at user-application level (based, for instance, + on the measured LSI clock frequency as explained above). ##### How to use this driver ##### ============================================================================== [..] (#) Use IWDG using HAL_IWDG_Init() function to : (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI - clock is forced ON and IWDG counter starts downcounting. - (++) Enable write access to configuration register: IWDG_PR & IWDG_RLR. + clock is forced ON and IWDG counter starts counting down. + (++) Enable write access to configuration registers: + IWDG_PR and IWDG_RLR. (++) Configure the IWDG prescaler and counter reload value. This reload value will be loaded in the IWDG counter each time the watchdog is reloaded, then the IWDG will start counting down from this value. - (++) wait for status flags to be reset" + (++) Wait for status flags to be reset. (#) Then the application program must refresh the IWDG counter at regular intervals during normal operation to prevent an MCU reset, using @@ -91,7 +102,7 @@ */ #ifdef HAL_IWDG_MODULE_ENABLED -/** @defgroup IWDG IWDG +/** @addtogroup IWDG * @brief IWDG HAL module driver. * @{ */ @@ -101,10 +112,14 @@ /** @defgroup IWDG_Private_Defines IWDG Private Defines * @{ */ -/* Status register need 5 RC LSI divided by prescaler clock to be updated. With - higher prescaler (256), and according to HSI variation, we need to wait at - least 6 cycles so 48 ms. */ -#define HAL_IWDG_DEFAULT_TIMEOUT 48U +/* Status register needs up to 5 LSI clock periods divided by the clock + prescaler to be updated. The number of LSI clock periods is upper-rounded to + 6 for the timeout value calculation. + The timeout value is also calculated using the highest prescaler (256) and + the LSI_VALUE constant. The value of this constant can be changed by the user + to take into account possible LSI clock period variations. + The timeout value is multiplied by 1000 to be converted in milliseconds. */ +#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE) /** * @} */ @@ -158,10 +173,11 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); - /* Enable IWDG. LSI is turned on automaticaly */ + /* Enable IWDG. LSI is turned on automatically */ __HAL_IWDG_START(hiwdg); - /* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */ + /* Enable write access to IWDG_PR and IWDG_RLR registers by writing + 0x5555 in KR */ IWDG_ENABLE_WRITE_ACCESS(hiwdg); /* Write to IWDG registers the Prescaler & Reload values to work with */ @@ -172,7 +188,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) tickstart = HAL_GetTick(); /* Wait for register to be updated */ - while (hiwdg->Instance->SR != RESET) + while (hiwdg->Instance->SR != 0x00u) { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) { @@ -191,6 +207,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) * @} */ + /** @addtogroup IWDG_Exported_Functions_Group2 * @brief IO operation functions * @@ -205,6 +222,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) * @{ */ + /** * @brief Refresh the IWDG. * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c index df475e2ea2..edd1946ac4 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c @@ -156,7 +156,8 @@ * @param AttSpace_Timing pointer to Attribute space timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) +HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, + FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) { /* Check the NAND handle state */ if (hnand == NULL) @@ -170,7 +171,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_Timing hnand->Lock = HAL_UNLOCKED; #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - if(hnand->MspInitCallback == NULL) + if (hnand->MspInitCallback == NULL) { hnand->MspInitCallback = HAL_NAND_MspInit; } @@ -211,7 +212,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_Timing HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) { #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - if(hnand->MspDeInitCallback == NULL) + if (hnand->MspDeInitCallback == NULL) { hnand->MspDeInitCallback = HAL_NAND_MspDeInit; } @@ -273,7 +274,7 @@ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status -*/ + */ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) { /* Check NAND interrupt Rising edge flag */ @@ -380,7 +381,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN { __IO uint32_t data = 0; __IO uint32_t data1 = 0; - uint32_t deviceAddress; + uint32_t deviceaddress; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -396,25 +397,25 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - if(hnand->Init.NandBank == FSMC_NAND_BANK2) + if (hnand->Init.NandBank == FSMC_NAND_BANK2) { - deviceAddress = NAND_DEVICE1; + deviceaddress = NAND_DEVICE1; } else { - deviceAddress = NAND_DEVICE2; + deviceaddress = NAND_DEVICE2; } /* Send Read ID command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; __DSB(); /* Read the electronic signature from NAND flash */ if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) { - data = *(__IO uint32_t *)deviceAddress; + data = *(__IO uint32_t *)deviceaddress; /* Return the data read */ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); @@ -424,8 +425,8 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN } else { - data = *(__IO uint32_t *)deviceAddress; - data1 = *((__IO uint32_t *)deviceAddress + 4); + data = *(__IO uint32_t *)deviceaddress; + data1 = *((__IO uint32_t *)deviceaddress + 4); /* Return the data read */ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); @@ -456,7 +457,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN */ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) { - uint32_t deviceAddress; + uint32_t deviceaddress; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -472,17 +473,17 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - if(hnand->Init.NandBank == FSMC_NAND_BANK2) + if (hnand->Init.NandBank == FSMC_NAND_BANK2) { - deviceAddress = NAND_DEVICE1; + deviceaddress = NAND_DEVICE1; } else { - deviceAddress = NAND_DEVICE2; + deviceaddress = NAND_DEVICE2; } /* Send NAND reset command */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -528,12 +529,16 @@ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToRead) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesRead = 0U, nandAddress, nbpages = NumPageToRead; - uint8_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numpagesread = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToRead; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -549,23 +554,23 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - if(hnand->Init.NandBank == FSMC_NAND_BANK2) + if (hnand->Init.NandBank == FSMC_NAND_BANK2) { - deviceAddress = NAND_DEVICE1; + deviceaddress = NAND_DEVICE1; } else { - deviceAddress = NAND_DEVICE2; + deviceaddress = NAND_DEVICE2; } /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) read loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); /* Cards with page size <= 512 bytes */ @@ -573,22 +578,22 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -596,31 +601,31 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); @@ -645,25 +650,25 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *buff = *(uint8_t *)deviceAddress; + *buff = *(uint8_t *)deviceaddress; buff++; } /* Increment read pages number */ - numPagesRead++; + numpagesread++; /* Decrement pages to read */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -689,12 +694,16 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToRead) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesRead = 0, nandAddress, nbpages = NumPageToRead; - uint16_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numpagesread = 0; + uint32_t nandaddress; + uint32_t nbpages = NumPageToRead; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -710,23 +719,23 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - if(hnand->Init.NandBank == FSMC_NAND_BANK2) + if (hnand->Init.NandBank == FSMC_NAND_BANK2) { - deviceAddress = NAND_DEVICE1; + deviceaddress = NAND_DEVICE1; } else { - deviceAddress = NAND_DEVICE2; + deviceaddress = NAND_DEVICE2; } /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) read loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); /* Cards with page size <= 512 bytes */ @@ -734,22 +743,22 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -757,31 +766,31 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); if (hnand->Config.ExtraCommandEnable == ENABLE) @@ -805,25 +814,25 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *buff = *(uint16_t *)deviceAddress; + *buff = *(uint16_t *)deviceaddress; buff++; } /* Increment read pages number */ - numPagesRead++; + numpagesread++; /* Decrement pages to read */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -849,12 +858,16 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToWrite) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite; - uint8_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numpageswritten = 0; + uint32_t nandaddress; + uint32_t nbpages = NumPageToWrite; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -870,25 +883,25 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - if(hnand->Init.NandBank == FSMC_NAND_BANK2) + if (hnand->Init.NandBank == FSMC_NAND_BANK2) { - deviceAddress = NAND_DEVICE1; + deviceaddress = NAND_DEVICE1; } else { - deviceAddress = NAND_DEVICE2; + deviceaddress = NAND_DEVICE2; } /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) write loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); /* Cards with page size <= 512 bytes */ @@ -896,22 +909,22 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -919,26 +932,26 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -946,12 +959,12 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address /* Write data to memory */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *(__IO uint8_t *)deviceAddress = *buff; + *(__IO uint8_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -973,13 +986,13 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address } /* Increment written pages number */ - numPagesWritten++; + numpageswritten++; /* Decrement pages to write */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1005,12 +1018,16 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToWrite) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite; - uint16_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numpageswritten = 0; + uint32_t nandaddress; + uint32_t nbpages = NumPageToWrite; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1026,25 +1043,25 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - if(hnand->Init.NandBank == FSMC_NAND_BANK2) + if (hnand->Init.NandBank == FSMC_NAND_BANK2) { - deviceAddress = NAND_DEVICE1; + deviceaddress = NAND_DEVICE1; } else { - deviceAddress = NAND_DEVICE2; + deviceaddress = NAND_DEVICE2; } /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) write loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); /* Cards with page size <= 512 bytes */ @@ -1052,22 +1069,22 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -1075,26 +1092,26 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -1102,12 +1119,12 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres /* Write data to memory */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *(__IO uint16_t *)deviceAddress = *buff; + *(__IO uint16_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -1129,13 +1146,13 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres } /* Increment written pages number */ - numPagesWritten++; + numpageswritten++; /* Decrement pages to write */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1160,13 +1177,18 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres * @param pBuffer pointer to source buffer to write * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status -*/ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) + */ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumSpareAreaToRead) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead; - uint8_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numsparearearead = 0; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaToRead; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1182,85 +1204,85 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - if(hnand->Init.NandBank == FSMC_NAND_BANK2) + if (hnand->Init.NandBank == FSMC_NAND_BANK2) { - deviceAddress = NAND_DEVICE1; + deviceaddress = NAND_DEVICE1; } else { - deviceAddress = NAND_DEVICE2; + deviceaddress = NAND_DEVICE2; } /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = COLUMN_ADDRESS(hnand); + columnaddress = COLUMN_ADDRESS(hnand); /* Spare area(s) read loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); if (hnand->Config.ExtraCommandEnable == ENABLE) @@ -1284,25 +1306,25 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *buff = *(uint8_t *)deviceAddress; + *buff = *(uint8_t *)deviceaddress; buff++; } /* Increment read spare areas number */ - numSpareAreaRead++; + numsparearearead++; /* Decrement spare areas to read */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1327,13 +1349,18 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status -*/ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) + */ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaToRead) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead; - uint16_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numsparearearead = 0; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaToRead; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1349,85 +1376,85 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - if(hnand->Init.NandBank == FSMC_NAND_BANK2) + if (hnand->Init.NandBank == FSMC_NAND_BANK2) { - deviceAddress = NAND_DEVICE1; + deviceaddress = NAND_DEVICE1; } else { - deviceAddress = NAND_DEVICE2; + deviceaddress = NAND_DEVICE2; } /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U); + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U); /* Spare area(s) read loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); if (hnand->Config.ExtraCommandEnable == ENABLE) @@ -1451,25 +1478,25 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *buff = *(uint16_t *)deviceAddress; + *buff = *(uint16_t *)deviceaddress; buff++; } /* Increment read spare areas number */ - numSpareAreaRead++; + numsparearearead++; /* Decrement spare areas to read */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1495,12 +1522,17 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite; - uint8_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numspareareawritten = 0; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaTowrite; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1516,84 +1548,84 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - if(hnand->Init.NandBank == FSMC_NAND_BANK2) + if (hnand->Init.NandBank == FSMC_NAND_BANK2) { - deviceAddress = NAND_DEVICE1; + deviceaddress = NAND_DEVICE1; } else { - deviceAddress = NAND_DEVICE2; + deviceaddress = NAND_DEVICE2; } /* Page address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = COLUMN_ADDRESS(hnand); + columnaddress = COLUMN_ADDRESS(hnand); /* Spare area(s) write loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -1601,12 +1633,12 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad /* Write data to memory */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *(__IO uint8_t *)deviceAddress = *buff; + *(__IO uint8_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -1628,13 +1660,13 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad } /* Increment written spare areas number */ - numSpareAreaWritten++; + numspareareawritten++; /* Decrement spare areas to write */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1660,12 +1692,17 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite; - uint16_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numspareareawritten = 0; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaTowrite; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1681,84 +1718,84 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - if(hnand->Init.NandBank == FSMC_NAND_BANK2) + if (hnand->Init.NandBank == FSMC_NAND_BANK2) { - deviceAddress = NAND_DEVICE1; + deviceaddress = NAND_DEVICE1; } else { - deviceAddress = NAND_DEVICE2; + deviceaddress = NAND_DEVICE2; } /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U); + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U); /* Spare area(s) write loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -1766,12 +1803,12 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A /* Write data to memory */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *(__IO uint16_t *)deviceAddress = *buff; + *(__IO uint16_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -1793,13 +1830,13 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A } /* Increment written spare areas number */ - numSpareAreaWritten++; + numspareareawritten++; /* Decrement spare areas to write */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1825,7 +1862,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A */ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { - uint32_t DeviceAddress; + uint32_t deviceaddress; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1841,26 +1878,26 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - if(hnand->Init.NandBank == FSMC_NAND_BANK2) + if (hnand->Init.NandBank == FSMC_NAND_BANK2) { - DeviceAddress = NAND_DEVICE1; + deviceaddress = NAND_DEVICE1; } else { - DeviceAddress = NAND_DEVICE2; + deviceaddress = NAND_DEVICE2; } /* Send Erase block command sequence */ - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; __DSB(); /* Update the NAND controller state */ @@ -1927,11 +1964,12 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, + pNAND_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -1939,39 +1977,39 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND /* Process locked */ __HAL_LOCK(hnand); - if(hnand->State == HAL_NAND_STATE_READY) + if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = pCallback; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = pCallback; - break; - case HAL_NAND_IT_CB_ID : - hnand->ItCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = pCallback; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = pCallback; + break; + case HAL_NAND_IT_CB_ID : + hnand->ItCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hnand->State == HAL_NAND_STATE_RESET) + else if (hnand->State == HAL_NAND_STATE_RESET) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = pCallback; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = pCallback; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1996,46 +2034,46 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID * @retval status */ -HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hnand); - if(hnand->State == HAL_NAND_STATE_READY) + if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = HAL_NAND_MspInit; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = HAL_NAND_MspDeInit; - break; - case HAL_NAND_IT_CB_ID : - hnand->ItCallback = HAL_NAND_ITCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = HAL_NAND_MspInit; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = HAL_NAND_MspDeInit; + break; + case HAL_NAND_IT_CB_ID : + hnand->ItCallback = HAL_NAND_ITCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hnand->State == HAL_NAND_STATE_RESET) + else if (hnand->State == HAL_NAND_STATE_RESET) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = HAL_NAND_MspInit; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = HAL_NAND_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = HAL_NAND_MspInit; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = HAL_NAND_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -2055,8 +2093,8 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NA */ /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### NAND Control functions ##### @@ -2176,8 +2214,8 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### NAND State functions ##### @@ -2210,24 +2248,24 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) { uint32_t data; - uint32_t DeviceAddress; + uint32_t deviceaddress; UNUSED(hnand); /* Identify the device address */ - if(hnand->Init.NandBank == FSMC_NAND_BANK2) - { - DeviceAddress = NAND_DEVICE1; - } - else - { - DeviceAddress = NAND_DEVICE2; - } + if (hnand->Init.NandBank == FSMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } /* Send Read status operation command */ - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; /* Read status register data */ - data = *(__IO uint8_t *)DeviceAddress; + data = *(__IO uint8_t *)deviceaddress; /* Return the status */ if ((data & NAND_ERROR) == NAND_ERROR) diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c index eb983530a3..3f0bb9d247 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c @@ -151,9 +151,35 @@ #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30 +#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF +#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040 +#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8 +#define NOR_CMD_CONFIRM (uint16_t)0x00D0 +#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020 +#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060 +#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070 +#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050 + /* Mask on NOR STATUS REGISTER */ +#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040 +#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080 + +/* Address of the primary command set */ +#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013 + +/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */ +#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */ +#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */ +#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */ +#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */ +#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */ +#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */ +#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */ +#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */ +#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */ +#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */ /** * @} @@ -200,8 +226,11 @@ static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; * @param ExtTiming pointer to NOR extended mode timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming) +HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, + FSMC_NORSRAM_TimingTypeDef *ExtTiming) { + uint32_t deviceaddress; + /* Check the NOR handle parameter */ if (hnor == NULL) { @@ -214,7 +243,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeD hnor->Lock = HAL_UNLOCKED; #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - if(hnor->MspInitCallback == NULL) + if (hnor->MspInitCallback == NULL) { hnor->MspInitCallback = HAL_NOR_MspInit; } @@ -252,7 +281,29 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeD /* Initialize the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - return HAL_OK; + /* Select the NOR device address */ + if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FSMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Get the value of the command set */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); + + return HAL_NOR_ReturnToReadMode(hnor); } /** @@ -264,7 +315,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeD HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) { #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - if(hnor->MspDeInitCallback == NULL) + if (hnor->MspDeInitCallback == NULL) { hnor->MspDeInitCallback = HAL_NOR_MspDeInit; } @@ -367,6 +418,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I { uint32_t deviceaddress; HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ state = hnor->State; @@ -401,15 +453,30 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I } /* Send read ID command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Read the NOR IDs */ - pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); - pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR); - pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR); - pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR); + if (status != HAL_ERROR) + { + /* Read the NOR IDs */ + pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); + pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR); + pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR); + pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR); + } /* Check the NOR controller state */ hnor->State = state; @@ -422,7 +489,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -435,6 +502,7 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) { uint32_t deviceaddress; HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ state = hnor->State; @@ -468,7 +536,19 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) deviceaddress = NOR_MEMORY_ADRESS4; } - NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } /* Check the NOR controller state */ hnor->State = state; @@ -481,7 +561,7 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -496,6 +576,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint { uint32_t deviceaddress; HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ state = hnor->State; @@ -530,12 +611,27 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint } /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Read the data */ - *pData = (uint16_t)(*(__IO uint32_t *)pAddress); + if (status != HAL_ERROR) + { + /* Read the data */ + *pData = (uint16_t)(*(__IO uint32_t *)pAddress); + } /* Check the NOR controller state */ hnor->State = state; @@ -548,7 +644,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -562,6 +658,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ if (hnor->State == HAL_NOR_STATE_BUSY) @@ -595,12 +692,27 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u } /* Send program data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Write the data */ - NOR_WRITE(pAddress, *pData); + if (status != HAL_ERROR) + { + /* Write the data */ + NOR_WRITE(pAddress, *pData); + } /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -613,7 +725,7 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -625,11 +737,15 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u * @param uwBufferSize number of Half word to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) +HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize) { - uint32_t deviceaddress, size = uwBufferSize, address = uwAddress; + uint32_t deviceaddress; + uint32_t size = uwBufferSize; + uint32_t address = uwAddress; uint16_t *data = pData; HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ state = hnor->State; @@ -664,17 +780,32 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress } /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Read buffer */ - while (size > 0U) + if (status != HAL_ERROR) { - *data = *(__IO uint16_t *)address; - data++; - address += 2U; - size--; + /* Read buffer */ + while (size > 0U) + { + *data = *(__IO uint16_t *)address; + data++; + address += 2U; + size--; + } } /* Check the NOR controller state */ @@ -688,7 +819,7 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -700,12 +831,14 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress * @param uwBufferSize Size of the buffer to write * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) +HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize) { uint16_t *p_currentaddress; const uint16_t *p_endaddress; uint16_t *data = pData; - uint32_t lastloadedaddress, deviceaddress; + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ if (hnor->State == HAL_NOR_STATE_BUSY) @@ -739,32 +872,52 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr } /* Initialize variables */ - p_currentaddress = (uint16_t *)(uwAddress); - p_endaddress = (const uint16_t *)(uwAddress + (uwBufferSize - 1U)); - lastloadedaddress = uwAddress; + p_currentaddress = (uint16_t *)(deviceaddress + uwAddress); + p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U))); - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - /* Write Buffer Load Command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uint16_t)(uwBufferSize - 1U)); + /* Write Buffer Load Command */ + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); + NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + /* Write Buffer Load Command */ + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM); + NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Load Data into NOR Buffer */ - while (p_currentaddress <= p_endaddress) + if (status != HAL_ERROR) { - /* Store last loaded address & data value (for polling) */ - lastloadedaddress = (uint32_t)p_currentaddress; + /* Load Data into NOR Buffer */ + while (p_currentaddress <= p_endaddress) + { + NOR_WRITE(p_currentaddress, *data); - NOR_WRITE(p_currentaddress, *data); + data++; + p_currentaddress ++; + } - data++; - p_currentaddress ++; + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); + } + else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */ + { + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM); + } } - NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); - /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -776,7 +929,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr return HAL_ERROR; } - return HAL_OK; + return status; } @@ -791,6 +944,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) { uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ if (hnor->State == HAL_NOR_STATE_BUSY) @@ -824,12 +978,30 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd } /* Send block erase command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK); + NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM); + NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE); + NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } /* Check the NOR memory status and update the controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -842,7 +1014,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd return HAL_ERROR; } - return HAL_OK; + return status; } @@ -856,6 +1028,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) { uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; UNUSED(Address); /* Check the NOR controller state */ @@ -890,12 +1063,23 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) } /* Send NOR chip erase command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } /* Check the NOR memory status and update the controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -908,7 +1092,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -990,12 +1174,13 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, + pNOR_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_NOR_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -1004,20 +1189,20 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_Cal __HAL_LOCK(hnor); state = hnor->State; - if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) + if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_NOR_MSP_INIT_CB_ID : - hnor->MspInitCallback = pCallback; - break; - case HAL_NOR_MSP_DEINIT_CB_ID : - hnor->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NOR_MSP_INIT_CB_ID : + hnor->MspInitCallback = pCallback; + break; + case HAL_NOR_MSP_DEINIT_CB_ID : + hnor->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1041,7 +1226,7 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_Cal * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID * @retval status */ -HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; HAL_NOR_StateTypeDef state; @@ -1050,20 +1235,20 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C __HAL_LOCK(hnor); state = hnor->State; - if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) + if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_NOR_MSP_INIT_CB_ID : - hnor->MspInitCallback = HAL_NOR_MspInit; - break; - case HAL_NOR_MSP_DEINIT_CB_ID : - hnor->MspDeInitCallback = HAL_NOR_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NOR_MSP_INIT_CB_ID : + hnor->MspInitCallback = HAL_NOR_MspInit; + break; + case HAL_NOR_MSP_DEINIT_CB_ID : + hnor->MspDeInitCallback = HAL_NOR_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1083,8 +1268,8 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C */ /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### NOR Control functions ##### @@ -1106,7 +1291,7 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) { /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_PROTECTED) + if (hnor->State == HAL_NOR_STATE_PROTECTED) { /* Process Locked */ __HAL_LOCK(hnor); @@ -1140,7 +1325,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) { /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_READY) + if (hnor->State == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -1170,8 +1355,8 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) */ /** @defgroup NOR_Exported_Functions_Group4 NOR State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### NOR State functions ##### @@ -1207,7 +1392,8 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) { HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; - uint16_t tmpSR1, tmpSR2; + uint16_t tmpsr1; + uint16_t tmpsr2; uint32_t tickstart; /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ @@ -1217,45 +1403,84 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /* Get tick */ tickstart = HAL_GetTick(); - while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT)) + + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT)) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) { - status = HAL_NOR_STATUS_TIMEOUT; + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + status = HAL_NOR_STATUS_TIMEOUT; + } } - } - /* Read NOR status register (DQ6 and DQ5) */ - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; + /* Read NOR status register (DQ6 and DQ5) */ + tmpsr1 = *(__IO uint16_t *)Address; + tmpsr2 = *(__IO uint16_t *)Address; - /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) - { - return HAL_NOR_STATUS_SUCCESS ; - } + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) + { + return HAL_NOR_STATUS_SUCCESS ; + } - if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) - { - status = HAL_NOR_STATUS_ONGOING; + if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + { + status = HAL_NOR_STATUS_ONGOING; + } + + tmpsr1 = *(__IO uint16_t *)Address; + tmpsr2 = *(__IO uint16_t *)Address; + + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) + { + return HAL_NOR_STATUS_SUCCESS; + } + if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + { + return HAL_NOR_STATUS_ERROR; + } } + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + do + { + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + tmpsr2 = *(__IO uint16_t *)(Address); - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_NOR_STATUS_TIMEOUT; + } + } + } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U); - /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + tmpsr1 = *(__IO uint16_t *)(Address); + if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U) { - return HAL_NOR_STATUS_SUCCESS; + /* Clear the Status Register */ + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + status = HAL_NOR_STATUS_ERROR; } - if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + else { - return HAL_NOR_STATUS_ERROR; + status = HAL_NOR_STATUS_SUCCESS; } } + else + { + /* Primary command set not supported by the driver */ + status = HAL_NOR_STATUS_ERROR; + } /* Return the operation status */ return status; diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pccard.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pccard.c index c0d8f7f9b6..2556d81f3c 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pccard.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pccard.c @@ -162,7 +162,8 @@ * @param IOSpaceTiming IO space timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming) +HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, + FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming) { /* Check the PCCARD controller state */ if (hpccard == NULL) @@ -175,7 +176,7 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_T /* Allocate lock resource and initialize it */ hpccard->Lock = HAL_UNLOCKED; #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) - if(hpccard->MspInitCallback == NULL) + if (hpccard->MspInitCallback == NULL) { hpccard->MspInitCallback = HAL_PCCARD_MspInit; } @@ -223,7 +224,7 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_T HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard) { #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) - if(hpccard->MspDeInitCallback == NULL) + if (hpccard->MspDeInitCallback == NULL) { hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit; } @@ -334,8 +335,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - } - while ((status != PCCARD_STATUS_OK) && timeout); + } while ((status != PCCARD_STATUS_OK) && timeout); if (timeout == 0U) { @@ -368,7 +368,8 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp * @param pStatus pointer to PCCARD status * @retval HAL status */ -HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) +HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, + uint8_t *pStatus) { uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U; uint8_t status = 0; @@ -398,8 +399,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t /* wait till the Status = 0x80 */ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - } - while ((status == 0x80U) && timeout); + } while ((status == 0x80U) && timeout); if (timeout == 0U) { @@ -413,8 +413,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t /* wait till the Status = PCCARD_STATUS_OK */ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - } - while ((status != PCCARD_STATUS_OK) && timeout); + } while ((status != PCCARD_STATUS_OK) && timeout); if (timeout == 0U) { @@ -446,7 +445,8 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t * @param pStatus pointer to PCCARD status * @retval HAL status */ -HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) +HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, + uint8_t *pStatus) { uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U; uint8_t status = 0; @@ -476,8 +476,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ /* Wait till the Status = PCCARD_STATUS_OK */ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - } - while ((status != PCCARD_STATUS_OK) && timeout); + } while ((status != PCCARD_STATUS_OK) && timeout); if (timeout == 0U) { @@ -495,8 +494,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ /* Wait till the Status = PCCARD_STATUS_WRITE_OK */ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - } - while ((status != PCCARD_STATUS_WRITE_OK) && timeout); + } while ((status != PCCARD_STATUS_WRITE_OK) && timeout); if (timeout == 0U) { @@ -615,7 +613,7 @@ HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard) * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. * @retval HAL status -*/ + */ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) { /* Check PCCARD interrupt Rising edge flag */ @@ -703,11 +701,12 @@ __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard) * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, + pPCCARD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -715,39 +714,39 @@ HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HA /* Process locked */ __HAL_LOCK(hpccard); - if(hpccard->State == HAL_PCCARD_STATE_READY) + if (hpccard->State == HAL_PCCARD_STATE_READY) { switch (CallbackId) { - case HAL_PCCARD_MSP_INIT_CB_ID : - hpccard->MspInitCallback = pCallback; - break; - case HAL_PCCARD_MSP_DEINIT_CB_ID : - hpccard->MspDeInitCallback = pCallback; - break; - case HAL_PCCARD_IT_CB_ID : - hpccard->ItCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_PCCARD_MSP_INIT_CB_ID : + hpccard->MspInitCallback = pCallback; + break; + case HAL_PCCARD_MSP_DEINIT_CB_ID : + hpccard->MspDeInitCallback = pCallback; + break; + case HAL_PCCARD_IT_CB_ID : + hpccard->ItCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hpccard->State == HAL_PCCARD_STATE_RESET) + else if (hpccard->State == HAL_PCCARD_STATE_RESET) { switch (CallbackId) { - case HAL_PCCARD_MSP_INIT_CB_ID : - hpccard->MspInitCallback = pCallback; - break; - case HAL_PCCARD_MSP_DEINIT_CB_ID : - hpccard->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_PCCARD_MSP_INIT_CB_ID : + hpccard->MspInitCallback = pCallback; + break; + case HAL_PCCARD_MSP_DEINIT_CB_ID : + hpccard->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -772,46 +771,46 @@ HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HA * @arg @ref HAL_PCCARD_IT_CB_ID PCCARD IT callback ID * @retval status */ -HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback (PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hpccard); - if(hpccard->State == HAL_PCCARD_STATE_READY) + if (hpccard->State == HAL_PCCARD_STATE_READY) { switch (CallbackId) { - case HAL_PCCARD_MSP_INIT_CB_ID : - hpccard->MspInitCallback = HAL_PCCARD_MspInit; - break; - case HAL_PCCARD_MSP_DEINIT_CB_ID : - hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit; - break; - case HAL_PCCARD_IT_CB_ID : - hpccard->ItCallback = HAL_PCCARD_ITCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_PCCARD_MSP_INIT_CB_ID : + hpccard->MspInitCallback = HAL_PCCARD_MspInit; + break; + case HAL_PCCARD_MSP_DEINIT_CB_ID : + hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit; + break; + case HAL_PCCARD_IT_CB_ID : + hpccard->ItCallback = HAL_PCCARD_ITCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hpccard->State == HAL_PCCARD_STATE_RESET) + else if (hpccard->State == HAL_PCCARD_STATE_RESET) { switch (CallbackId) { - case HAL_PCCARD_MSP_INIT_CB_ID : - hpccard->MspInitCallback = HAL_PCCARD_MspInit; - break; - case HAL_PCCARD_MSP_DEINIT_CB_ID : - hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_PCCARD_MSP_INIT_CB_ID : + hpccard->MspInitCallback = HAL_PCCARD_MspInit; + break; + case HAL_PCCARD_MSP_DEINIT_CB_ID : + hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -831,8 +830,8 @@ HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback (PCCARD_HandleTypeDef *hpccard, */ /** @defgroup PCCARD_Exported_Functions_Group3 State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### PCCARD State functions ##### diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_smartcard.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_smartcard.c index db4d74ee0d..cff11b99d3 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_smartcard.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_smartcard.c @@ -755,7 +755,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; + uint8_t *tmp = pData; uint32_t tickstart = 0U; if(hsc->gState == HAL_SMARTCARD_STATE_READY) @@ -783,9 +783,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * { return HAL_TIMEOUT; } - tmp = (uint16_t*) pData; - hsc->Instance->DR = (*tmp & (uint16_t)0x01FF); - pData +=1U; + hsc->Instance->DR = (uint8_t)(*tmp & 0xFFU); + tmp++; } if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) @@ -818,7 +817,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * */ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; + uint8_t *tmp = pData; uint32_t tickstart = 0U; if(hsc->RxState == HAL_SMARTCARD_STATE_READY) @@ -848,9 +847,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p { return HAL_TIMEOUT; } - tmp = (uint16_t*) pData; - *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF); - pData +=1U; + *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFFU); + tmp++; } /* At end of Rx process, restore hsc->RxState to Ready */ @@ -1567,7 +1565,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) } /* SMARTCARD Over-Run interrupt occurred -------------------------------*/ - if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) { hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; } @@ -1996,14 +1994,12 @@ static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc) */ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) { - uint16_t* tmp; /* Check that a Tx process is ongoing */ if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) { - tmp = (uint16_t*) hsc->pTxBuffPtr; - hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); - hsc->pTxBuffPtr += 1U; + hsc->Instance->DR = (uint8_t)(*hsc->pTxBuffPtr & 0xFFU); + hsc->pTxBuffPtr++; if(--hsc->TxXferCount == 0U) { @@ -2058,14 +2054,12 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsc) */ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) { - uint16_t* tmp; /* Check that a Rx process is ongoing */ if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) { - tmp = (uint16_t*) hsc->pRxBuffPtr; - *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF); - hsc->pRxBuffPtr += 1U; + *hsc->pRxBuffPtr = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFFU); + hsc->pRxBuffPtr++; if(--hsc->RxXferCount == 0U) { diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c index d5ef08f914..77158398ec 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c @@ -131,7 +131,7 @@ DataSize = SPI_DATASIZE_8BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | - | Process | Tranfert mode |---------------------|----------------------|----------------------| + | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | @@ -156,7 +156,7 @@ DataSize = SPI_DATASIZE_16BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | - | Process | Tranfert mode |---------------------|----------------------|----------------------| + | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | @@ -355,6 +355,24 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + } + } + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; } #if (USE_SPI_CRC != 0U) assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); @@ -403,9 +421,15 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ - WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | - hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | - hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation)); + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) | + (hspi->Init.DataSize & SPI_CR1_DFF) | + (hspi->Init.CLKPolarity & SPI_CR1_CPOL) | + (hspi->Init.CLKPhase & SPI_CR1_CPHA) | + (hspi->Init.NSS & SPI_CR1_SSM) | + (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); /* Configure : NSS management */ WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE)); @@ -415,7 +439,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /* Configure : CRC Polynomial */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk)); } #endif /* USE_SPI_CRC */ @@ -813,6 +837,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_TX(hspi); } @@ -988,6 +1014,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Configure communication direction: 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_RX(hspi); } @@ -1414,6 +1442,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_TX(hspi); } @@ -1501,6 +1531,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_RX(hspi); } @@ -1671,6 +1703,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_TX(hspi); } @@ -1784,6 +1818,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_RX(hspi); } @@ -2400,7 +2436,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) /* SPI in Error Treatment --------------------------------------------------*/ if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)) - && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) + && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) { /* SPI Overrun error interrupt occurred ----------------------------------*/ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) @@ -2752,8 +2788,17 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) } #endif /* USE_SPI_CRC */ - /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + /* Check if we are in Master RX 2 line mode */ + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + } + else + { + /* Normal case */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + } /* Check the end of the transaction */ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) @@ -3151,7 +3196,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - /* Read 8bit CRC to flush Data Regsiter */ + /* Read 8bit CRC to flush Data Register */ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); /* Disable RXNE and ERR interrupt */ @@ -3242,7 +3287,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { - /* Read 16bit CRC to flush Data Regsiter */ + /* Read 16bit CRC to flush Data Register */ READ_REG(hspi->Instance->DR); /* Disable RXNE interrupt */ @@ -3468,15 +3513,26 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart) { + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) { if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); @@ -3501,6 +3557,12 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, return HAL_TIMEOUT; } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if(count == 0U) + { + tmp_timeout = 0U; + } + count--; } } @@ -3574,7 +3636,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) uint32_t tickstart; __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Disable ERR interrupt */ @@ -3867,9 +3929,9 @@ uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi) #if defined(SPI_CRC_ERROR_WORKAROUND_FEATURE) && (USE_SPI_CRC_ERROR_WORKAROUND != 0U) /* Check how to handle this CRC error (workaround to be applied or not) */ /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */ - if(hspi->Instance == SPI2) + if (hspi->Instance == SPI2) { - if(hspi->Instance->RXCRCR == 0U) + if (hspi->Instance->RXCRCR == 0U) { return (SPI_INVALID_CRC_ERROR); } diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c index fd808ddbf2..9942451f61 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c @@ -136,9 +136,9 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static void SRAM_DMACplt (DMA_HandleTypeDef *hdma); +static void SRAM_DMACplt(DMA_HandleTypeDef *hdma); static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma); -static void SRAM_DMAError (DMA_HandleTypeDef *hdma); +static void SRAM_DMAError(DMA_HandleTypeDef *hdma); /** @endcond */ @@ -171,10 +171,11 @@ static void SRAM_DMAError (DMA_HandleTypeDef *hdma); * @param ExtTiming Pointer to SRAM extended mode timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming) +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, + FSMC_NORSRAM_TimingTypeDef *ExtTiming) { /* Check the SRAM handle parameter */ - if (hsram == NULL) + if ((hsram == NULL) || (hsram->Init.BurstAccessMode == FSMC_BURST_ACCESS_MODE_ENABLE)) { return HAL_ERROR; } @@ -185,7 +186,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTy hsram->Lock = HAL_UNLOCKED; #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - if(hsram->MspInitCallback == NULL) + if (hsram->MspInitCallback == NULL) { hsram->MspInitCallback = HAL_SRAM_MspInit; } @@ -207,7 +208,8 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTy (void)FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); /* Initialize SRAM extended mode timing Interface */ - (void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); + (void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, + hsram->Init.ExtendedMode); /* Enable the NORSRAM device */ __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); @@ -227,7 +229,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTy HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) { #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - if(hsram->MspDeInitCallback == NULL) + if (hsram->MspDeInitCallback == NULL) { hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; } @@ -342,11 +344,12 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint8_t *psramaddress = (uint8_t *)pAddress; - uint8_t * pdestbuff = pDstBuffer; + uint8_t *pdestbuff = pDstBuffer; HAL_SRAM_StateTypeDef state = hsram->State; /* Check the SRAM controller state */ @@ -389,11 +392,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint8_t *psramaddress = (uint8_t *)pAddress; - uint8_t * psrcbuff = pSrcBuffer; + uint8_t *psrcbuff = pSrcBuffer; /* Check the SRAM controller state */ if (hsram->State == HAL_SRAM_STATE_READY) @@ -435,7 +439,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint32_t *psramaddress = pAddress; @@ -452,11 +457,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_BUSY; - /* Check if the size is a 32-bits mulitple */ + /* Check if the size is a 32-bits multiple */ limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); /* Read data from memory */ - for (size = BufferSize; size != limit; size-=2U) + for (size = BufferSize; size != limit; size -= 2U) { *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU); pdestbuff++; @@ -494,11 +499,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint32_t *psramaddress = pAddress; - uint16_t * psrcbuff = pSrcBuffer; + uint16_t *psrcbuff = pSrcBuffer; uint8_t limit; /* Check the SRAM controller state */ @@ -510,11 +516,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_BUSY; - /* Check if the size is a 32-bits mulitple */ + /* Check if the size is a 32-bits multiple */ limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); /* Write data to memory */ - for (size = BufferSize; size != limit; size-=2U) + for (size = BufferSize; size != limit; size -= 2U) { *psramaddress = (uint32_t)(*psrcbuff); psrcbuff++; @@ -552,11 +558,12 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { uint32_t size; - __IO uint32_t * psramaddress = pAddress; - uint32_t * pdestbuff = pDstBuffer; + __IO uint32_t *psramaddress = pAddress; + uint32_t *pdestbuff = pDstBuffer; HAL_SRAM_StateTypeDef state = hsram->State; /* Check the SRAM controller state */ @@ -599,11 +606,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { uint32_t size; - __IO uint32_t * psramaddress = pAddress; - uint32_t * psrcbuff = pSrcBuffer; + __IO uint32_t *psramaddress = pAddress; + uint32_t *psrcbuff = pSrcBuffer; /* Check the SRAM controller state */ if (hsram->State == HAL_SRAM_STATE_READY) @@ -645,7 +653,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { HAL_StatusTypeDef status; HAL_SRAM_StateTypeDef state = hsram->State; @@ -678,7 +687,7 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres } else { - return HAL_ERROR; + status = HAL_ERROR; } return status; @@ -693,7 +702,8 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { HAL_StatusTypeDef status; @@ -718,7 +728,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre } else { - return HAL_ERROR; + status = HAL_ERROR; } return status; @@ -736,12 +746,13 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -750,20 +761,20 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM __HAL_LOCK(hsram); state = hsram->State; - if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = pCallback; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = pCallback; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -789,7 +800,7 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID * @retval status */ -HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; @@ -798,42 +809,42 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SR __HAL_LOCK(hsram); state = hsram->State; - if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = HAL_SRAM_MspInit; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; - break; - case HAL_SRAM_DMA_XFER_CPLT_CB_ID : - hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - break; - case HAL_SRAM_DMA_XFER_ERR_CB_ID : - hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(state == HAL_SRAM_STATE_RESET) + else if (state == HAL_SRAM_STATE_RESET) { switch (CallbackId) { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = HAL_SRAM_MspInit; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -858,12 +869,13 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SR * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_DmaCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -872,20 +884,20 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR __HAL_LOCK(hsram); state = hsram->State; - if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_SRAM_DMA_XFER_CPLT_CB_ID : - hsram->DmaXferCpltCallback = pCallback; - break; - case HAL_SRAM_DMA_XFER_ERR_CB_ID : - hsram->DmaXferErrorCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = pCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -905,8 +917,8 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR */ /** @defgroup SRAM_Exported_Functions_Group3 Control functions - * @brief Control functions - * + * @brief Control functions + * @verbatim ============================================================================== ##### SRAM Control functions ##### @@ -928,7 +940,7 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) { /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) + if (hsram->State == HAL_SRAM_STATE_PROTECTED) { /* Process Locked */ __HAL_LOCK(hsram); @@ -962,7 +974,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) { /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_READY) + if (hsram->State == HAL_SRAM_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsram); @@ -992,8 +1004,8 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) */ /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### SRAM State functions ##### @@ -1035,7 +1047,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) */ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) { - SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent); + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ __HAL_DMA_DISABLE(hdma); @@ -1057,7 +1069,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) { - SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent); + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ __HAL_DMA_DISABLE(hdma); @@ -1079,7 +1091,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) { - SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent); + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ __HAL_DMA_DISABLE(hdma); diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c index 16bc1f96dc..2a018bdc39 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c @@ -198,7 +198,7 @@ all interrupt callbacks are set to the corresponding weak functions: /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup TIM_Private_Functions @@ -218,6 +218,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, @@ -303,6 +304,13 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -336,6 +344,13 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_Base_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -388,19 +403,29 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } - /* Change the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -415,13 +440,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the TIM state*/ + /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ @@ -440,12 +462,28 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -463,12 +501,16 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + /* Return function status */ return HAL_OK; } @@ -487,6 +529,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + /* Set the TIM state */ if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; @@ -504,7 +547,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat } else { - /* nothing to do */ + return HAL_ERROR; } /* Set the DMA Period elapsed callbacks */ @@ -517,6 +560,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -524,8 +568,15 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -552,7 +603,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ + /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ @@ -635,6 +686,13 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -668,6 +726,13 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_OC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -725,6 +790,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); @@ -735,8 +809,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -773,6 +854,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -795,6 +879,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -839,8 +932,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -911,6 +1011,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -935,11 +1038,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -947,12 +1051,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -969,6 +1073,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -989,6 +1094,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1009,6 +1115,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -1028,6 +1135,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -1049,8 +1157,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1125,8 +1240,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1208,6 +1323,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -1241,6 +1363,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_PWM_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1298,6 +1427,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); @@ -1308,8 +1446,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1346,8 +1491,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1370,6 +1515,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1414,8 +1568,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1486,6 +1647,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1510,11 +1674,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -1522,12 +1687,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -1544,6 +1709,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1564,6 +1730,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -1583,6 +1750,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Capture/Compare 3 request */ @@ -1602,6 +1770,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -1623,8 +1792,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1699,8 +1875,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1782,6 +1958,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -1815,6 +1998,13 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_IC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1868,16 +2058,36 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1908,6 +2118,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1926,10 +2140,23 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1967,8 +2194,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -2033,6 +2267,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -2053,16 +2291,21 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { @@ -2070,12 +2313,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -2092,6 +2336,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ @@ -2111,6 +2356,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -2130,6 +2376,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -2149,6 +2396,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -2164,8 +2412,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -2191,6 +2446,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + switch (Channel) { case TIM_CHANNEL_1: @@ -2229,14 +2487,12 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) break; } - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -2273,6 +2529,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. * @param htim TIM One Pulse handle * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: @@ -2328,6 +2587,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /* Configure the OPM Mode */ htim->Instance->CR1 |= OnePulseMode; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -2361,6 +2629,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_OnePulse_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2411,9 +2688,29 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and @@ -2468,6 +2765,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -2483,9 +2786,29 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and @@ -2551,6 +2874,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -2589,6 +2918,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status @@ -2606,15 +2938,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini } /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -2685,6 +3017,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -2719,6 +3060,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_Encoder_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2770,8 +3120,58 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } /* Enable the encoder interface channels */ switch (Channel) @@ -2815,7 +3215,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2844,6 +3244,20 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + /* Return function status */ return HAL_OK; } @@ -2860,8 +3274,58 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ @@ -2911,7 +3375,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2942,8 +3406,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ return HAL_OK; @@ -2965,27 +3440,95 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) { - return HAL_BUSY; + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } } - else if (htim->State == HAL_TIM_STATE_READY) + else if (Channel == TIM_CHANNEL_2) { - if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { - return HAL_ERROR; + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } } else { - htim->State = HAL_TIM_STATE_BUSY; + return HAL_ERROR; } } else { - /* nothing to do */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } } switch (Channel) @@ -3002,6 +3545,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ @@ -3026,6 +3570,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ @@ -3051,6 +3596,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -3064,6 +3610,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the Peripheral */ @@ -3083,6 +3630,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch default: break; } + /* Return function status */ return HAL_OK; } @@ -3100,7 +3648,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -3135,8 +3683,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ return HAL_OK; @@ -3390,8 +3949,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - switch (Channel) { case TIM_CHANNEL_1: @@ -3438,8 +3995,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, break; } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -3470,8 +4025,6 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - if (Channel == TIM_CHANNEL_1) { /* TI1 Configuration */ @@ -3535,8 +4088,6 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -3568,8 +4119,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - switch (Channel) { case TIM_CHANNEL_1: @@ -3644,8 +4193,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, break; } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -3809,20 +4356,68 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength) +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - if (htim->State == HAL_TIM_STATE_BUSY) + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { @@ -3830,7 +4425,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t } else { - htim->State = HAL_TIM_STATE_BUSY; + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else @@ -3849,8 +4444,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3866,8 +4463,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3883,8 +4481,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3900,8 +4499,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3917,8 +4517,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3934,8 +4535,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3951,8 +4553,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3960,14 +4563,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t default: break; } - /* configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -3980,7 +4581,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { - HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -3989,51 +4589,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B { case TIM_DMA_UPDATE: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } - if (HAL_OK == status) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - } + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** @@ -4076,18 +4676,66 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - if (htim->State == HAL_TIM_STATE_BUSY) + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { @@ -4095,7 +4743,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B } else { - htim->State = HAL_TIM_STATE_BUSY; + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else @@ -4114,8 +4762,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4130,15 +4780,17 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC2: { - /* Set the DMA capture/compare callbacks */ + /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; @@ -4146,8 +4798,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4162,8 +4816,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4178,8 +4834,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4194,8 +4852,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4210,8 +4870,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4220,14 +4882,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B break; } - /* configure the DMA Burst Mode */ + /* Configure the DMA Burst Mode */ htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -4240,7 +4900,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { - HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4249,51 +4908,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu { case TIM_DMA_UPDATE: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } - if (HAL_OK == status) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - } + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** @@ -4599,13 +5258,13 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo case TIM_CLOCKSOURCE_ITR1: case TIM_CLOCKSOURCE_ITR2: case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - break; - } + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } default: break; @@ -5535,6 +6194,54 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) return htim->State; } +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + /** * @} */ @@ -5556,13 +6263,38 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** @@ -5570,27 +6302,45 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) * @param hdma pointer to DMA handle. * @retval None */ -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } } else { @@ -5615,8 +6365,6 @@ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; @@ -5656,23 +6404,45 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } } else { @@ -5697,8 +6467,6 @@ void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; @@ -5738,7 +6506,10 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); @@ -5756,8 +6527,6 @@ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedHalfCpltCallback(htim); #else @@ -5774,7 +6543,10 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); @@ -5792,8 +6564,6 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerHalfCpltCallback(htim); #else @@ -5852,7 +6622,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /** * @brief Timer Output Compare 1 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -5927,7 +6697,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 2 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6003,7 +6773,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 3 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6077,7 +6847,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 4 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6187,7 +6957,7 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) { return HAL_ERROR; } @@ -6239,11 +7009,11 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, case TIM_TS_ITR1: case TIM_TS_ITR2: case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - break; - } + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } default: break; diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c index dabdb99630..84522daf69 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c @@ -54,7 +54,7 @@ the commutation event). (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). @@ -90,9 +90,11 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); /* Exported functions --------------------------------------------------------*/ @@ -123,6 +125,9 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. * @param htim TIM Hall Sensor Interface handle * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status @@ -208,6 +213,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen htim->Instance->CR2 &= ~TIM_CR2_MMS; htim->Instance->CR2 |= TIM_TRGO_OC2REF; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -241,6 +255,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) HAL_TIMEx_HallSensor_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -288,17 +311,43 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -324,6 +373,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -336,10 +391,29 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -348,8 +422,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -378,6 +459,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -392,29 +479,36 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } + /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -428,14 +522,22 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Enable the DMA channel for Capture 1*/ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the capture compare 1 Interrupt */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -463,9 +565,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -512,6 +619,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); @@ -519,8 +635,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -554,6 +677,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -576,6 +702,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -614,8 +749,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -684,6 +826,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -708,24 +853,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -733,15 +879,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -752,15 +899,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -771,15 +919,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -798,8 +947,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -863,8 +1019,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -921,6 +1077,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); @@ -928,8 +1093,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -962,6 +1134,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -984,6 +1159,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1021,8 +1205,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1092,6 +1283,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1116,39 +1310,42 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } + switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ @@ -1159,15 +1356,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -1178,15 +1376,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -1205,8 +1404,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1270,8 +1476,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1311,11 +1517,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); + HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - /* Enable the complementary One Pulse output */ + /* Check the TIM channels state */ + if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1336,12 +1558,14 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - /* Disable the complementary One Pulse output */ + /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -1349,6 +1573,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1365,17 +1593,33 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); + HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + /* Check the TIM channels state */ + if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - /* Enable the complementary One Pulse output */ + /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1396,6 +1640,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); @@ -1405,8 +1651,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - /* Disable the complementary One Pulse output */ + /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -1414,6 +1661,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1633,7 +1884,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); @@ -1654,16 +1905,19 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; - /* Reset the MSM Bit */ - tmpsmcr &= ~TIM_SMCR_MSM; - /* Set master mode */ - tmpsmcr |= sMasterConfig->MasterSlaveMode; - /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; - /* Update TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; @@ -1733,6 +1987,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + UNUSED(Remap); return HAL_OK; } @@ -1829,6 +2086,27 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) return htim->State; } +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} /** * @} */ @@ -1881,6 +2159,103 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) } +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c index 1f2ed5dc6c..cc7e300bc8 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c @@ -1026,7 +1026,8 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t *tmp; + uint8_t *pdata8bits; + uint16_t *pdata16bits; uint32_t tickstart = 0U; /* Check that a Tx process is not already ongoing */ @@ -1048,34 +1049,39 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u huart->TxXferSize = Size; huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + while (huart->TxXferCount > 0U) { - huart->TxXferCount--; - if (huart->Init.WordLength == UART_WORDLENGTH_9B) + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t *) pData; - huart->Instance->DR = (*tmp & (uint16_t)0x01FF); - if (huart->Init.Parity == UART_PARITY_NONE) - { - pData += 2U; - } - else - { - pData += 1U; - } + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; } else { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - huart->Instance->DR = (*pData++ & (uint8_t)0xFF); + huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; } + huart->TxXferCount--; } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) @@ -1086,9 +1092,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -1111,7 +1114,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t *tmp; + uint8_t *pdata8bits; + uint16_t *pdata16bits; uint32_t tickstart = 0U; /* Check that a Rx process is not already ongoing */ @@ -1134,53 +1138,51 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui huart->RxXferSize = Size; huart->RxXferCount = Size; + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + /* Check the remain data to be received */ while (huart->RxXferCount > 0U) { - huart->RxXferCount--; - if (huart->Init.WordLength == UART_WORDLENGTH_9B) + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t *) pData; - if (huart->Init.Parity == UART_PARITY_NONE) - { - *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); - pData += 2U; - } - else - { - *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); - pData += 1U; - } - + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF); + pdata16bits++; } else { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if (huart->Init.Parity == UART_PARITY_NONE) + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) { - *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); } else { - *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); } - + pdata8bits++; } + huart->RxXferCount--; } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -2060,7 +2062,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* UART Over-Run interrupt occurred --------------------------------------*/ - if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) { huart->ErrorCode |= HAL_UART_ERROR_ORE; } @@ -2924,18 +2926,11 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { - if (huart->Init.WordLength == UART_WORDLENGTH_9B) + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { tmp = (uint16_t *) huart->pTxBuffPtr; huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); - if (huart->Init.Parity == UART_PARITY_NONE) - { - huart->pTxBuffPtr += 2U; - } - else - { - huart->pTxBuffPtr += 1U; - } + huart->pTxBuffPtr += 2U; } else { @@ -2991,35 +2986,33 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { - uint16_t *tmp; + uint8_t *pdata8bits; + uint16_t *pdata16bits; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) { - if (huart->Init.WordLength == UART_WORDLENGTH_9B) + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { - tmp = (uint16_t *) huart->pRxBuffPtr; - if (huart->Init.Parity == UART_PARITY_NONE) - { - *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); - huart->pRxBuffPtr += 2U; - } - else - { - *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); - huart->pRxBuffPtr += 1U; - } + pdata8bits = NULL; + pdata16bits = (uint16_t *) huart->pRxBuffPtr; + *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); + huart->pRxBuffPtr += 2U; } else { - if (huart->Init.Parity == UART_PARITY_NONE) + pdata8bits = (uint8_t *) huart->pRxBuffPtr; + pdata16bits = NULL; + + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) { - *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); } else { - *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); } + huart->pRxBuffPtr += 1U; } if (--huart->RxXferCount == 0U) @@ -3099,48 +3092,28 @@ static void UART_SetConfig(UART_HandleTypeDef *huart) /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); -#if defined(USART_CR1_OVER8) - /* Check the Over Sampling */ - if(huart->Init.OverSampling == UART_OVERSAMPLING_8) + + if(huart->Instance == USART1) { - /*-------------------------- USART BRR Configuration ---------------------*/ - if(huart->Instance == USART1) - { - pclk = HAL_RCC_GetPCLK2Freq(); - huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); - } - else - { - pclk = HAL_RCC_GetPCLK1Freq(); - huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); - } + pclk = HAL_RCC_GetPCLK2Freq(); } else { - /*-------------------------- USART BRR Configuration ---------------------*/ - if(huart->Instance == USART1) - { - pclk = HAL_RCC_GetPCLK2Freq(); - huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); - } - else - { - pclk = HAL_RCC_GetPCLK1Freq(); - huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); - } + pclk = HAL_RCC_GetPCLK1Freq(); } -#else + /*-------------------------- USART BRR Configuration ---------------------*/ - if(huart->Instance == USART1) +#if defined(USART_CR1_OVER8) + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) { - pclk = HAL_RCC_GetPCLK2Freq(); - huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); } else { - pclk = HAL_RCC_GetPCLK1Freq(); huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } +#else + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); #endif /* USART_CR1_OVER8 */ } diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_usart.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_usart.c index 042bfc3baa..380c997838 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_usart.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_usart.c @@ -537,9 +537,9 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US } /** - * @brief Unregister an UART Callback - * UART callaback is redirected to the weak predefined callback - * @param husart uart handle + * @brief Unregister an USART Callback + * USART callaback is redirected to the weak predefined callback + * @param husart usart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID @@ -731,7 +731,7 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ /** * @brief Simplex Send an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data is handled as a set of u16. In this case, Size must indicate the number * of u16 provided through pTxData. * @param husart Pointer to a USART_HandleTypeDef structure that contains @@ -816,7 +816,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa /** * @brief Full-Duplex Receive an amount of data in blocking mode. * @note To receive synchronous data, dummy data are simultaneously transmitted. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @param husart Pointer to a USART_HandleTypeDef structure that contains @@ -924,7 +924,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat /** * @brief Full-Duplex Send and Receive an amount of data in full-duplex mode (blocking mode). - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @param husart Pointer to a USART_HandleTypeDef structure that contains @@ -1042,7 +1042,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t /** * @brief Simplex Send an amount of data in non-blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data is handled as a set of u16. In this case, Size must indicate the number * of u16 provided through pTxData. * @param husart Pointer to a USART_HandleTypeDef structure that contains @@ -1096,7 +1096,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT /** * @brief Simplex Receive an amount of data in non-blocking mode. * @note To receive synchronous data, dummy data are simultaneously transmitted. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @param husart Pointer to a USART_HandleTypeDef structure that contains @@ -1145,7 +1145,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /** * @brief Full-Duplex Send and Receive an amount of data in full-duplex mode (non-blocking). - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @param husart Pointer to a USART_HandleTypeDef structure that contains @@ -1201,7 +1201,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /** * @brief Simplex Send an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data is handled as a set of u16. In this case, Size must indicate the number * of u16 provided through pTxData. * @param husart Pointer to a USART_HandleTypeDef structure that contains @@ -1266,7 +1266,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p /** * @brief Full-Duplex Receive an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @param husart Pointer to a USART_HandleTypeDef structure that contains @@ -1361,7 +1361,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /** * @brief Full-Duplex Transmit Receive an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @param husart Pointer to a USART_HandleTypeDef structure that contains @@ -1789,7 +1789,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) } /* USART Over-Run interrupt occurred -----------------------------------*/ - if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) { husart->ErrorCode |= HAL_USART_ERROR_ORE; } @@ -2155,8 +2155,6 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - husart->State = HAL_USART_STATE_READY; - /* The USART state is HAL_USART_STATE_BUSY_RX */ if (husart->State == HAL_USART_STATE_BUSY_RX) { @@ -2179,6 +2177,7 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) HAL_USART_TxRxCpltCallback(husart); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ } + husart->State = HAL_USART_STATE_READY; } /* DMA circular mode */ else diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_wwdg.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_wwdg.c index 20ccf01a67..aad4e233a1 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_wwdg.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_wwdg.c @@ -5,84 +5,110 @@ * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: - * + Initialization and de-initialization functions + * + Initialization and Configuration functions * + IO operation functions - * + Peripheral State functions @verbatim ============================================================================== - ##### WWDG specific features ##### + ##### WWDG Specific features ##### ============================================================================== [..] Once enabled the WWDG generates a system reset on expiry of a programmed - time period, unless the program refreshes the counter (downcounter) + time period, unless the program refreshes the counter (T[6;0] downcounter) before reaching 0x3F value (i.e. a reset is generated when the counter - value rolls over from 0x40 to 0x3F). + value rolls down from 0x40 to 0x3F). (+) An MCU reset is also generated if the counter value is refreshed before the counter has reached the refresh window value. This implies that the counter must be refreshed in a limited window. (+) Once enabled the WWDG cannot be disabled except by a system reset. - (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG + (+) If required by application, an Early Wakeup Interrupt can be triggered + in order to be warned before WWDG expiration. The Early Wakeup Interrupt + (EWI) can be used if specific safety operations or data logging must + be performed before the actual reset is generated. When the downcounter + reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt + line to be enabled in NVIC. Once enabled, EWI interrupt cannot be + disabled except by a system reset. + (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG reset occurs. (+) The WWDG counter input clock is derived from the APB clock divided by a programmable prescaler. (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler) - (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock + (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz) + where T[5;0] are the lowest 6 bits of Counter. (+) WWDG Counter refresh is allowed between the following limits : - (++) min time (mS) = 1000 * (Counter _ Window) / WWDG clock - (++) max time (mS) = 1000 * (Counter _ 0x40) / WWDG clock - - (+) Min-max timeout value at 36 MHz(PCLK1): 910 us / 58.25 ms - - (+) The Early Wakeup Interrupt (EWI) can be used if specific safety - operations or data logging must be performed before the actual reset is - generated. When the downcounter reaches the value 0x40, an EWI interrupt - is generated and the corresponding interrupt service routine (ISR) can - be used to trigger specific actions (such as communications or data - logging), before resetting the device. - In some applications, the EWI interrupt can be used to manage a software - system check and/or system recovery/graceful degradation, without - generating a WWDG reset. In this case, the corresponding interrupt - service routine (ISR) should reload the WWDG counter to avoid the WWDG - reset, then trigger the required actions. - Note:When the EWI interrupt cannot be served, e.g. due to a system lock - in a higher priority task, the WWDG reset will eventually be generated. - - (+) Debug mode : When the microcontroller enters debug mode (core halted), - the WWDG counter either continues to work normally or stops, depending - on DBG_WWDG_STOP configuration bit in DBG module, accessible through - __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros + (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock + (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock + (+) Typical values: + (++) Counter min (T[5;0] = 0x00) at 36MHz (PCLK1) with zero prescaler: + max timeout before reset: approximately 910�s + (++) Counter max (T[5;0] = 0x3F) at 36MHz (PCLK1) with prescaler + dividing by 8: + max timeout before reset: approximately 58.25ms ##### How to use this driver ##### ============================================================================== - [..] - (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). - (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup - Interrupt mode using using HAL_WWDG_Init() function. - This enables WWDG peripheral and the downcounter starts downcounting - from given counter value. - Init function can be called again to modify all watchdog parameters, - however if EWI mode has been set once, it can't be clear until next - reset. + *** Common driver usage *** + =========================== - (+) The application program must refresh the WWDG counter at regular - intervals during normal operation to prevent an MCU reset using + [..] + (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). + (+) Configure the WWDG prescaler, refresh window value, counter value and early + interrupt status using HAL_WWDG_Init() function. This will automatically + enable WWDG and start its downcounter. Time reference can be taken from + function exit. Care must be taken to provide a counter value + greater than 0x40 to prevent generation of immediate reset. + (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is + generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is + triggered by the interrupt service routine, flag will be automatically + cleared and HAL_WWDG_WakeupCallback user callback will be executed. User + can add his own code by customization of callback HAL_WWDG_WakeupCallback. + (+) Then the application program must refresh the WWDG counter at regular + intervals during normal operation to prevent an MCU reset, using HAL_WWDG_Refresh() function. This operation must occur only when - the counter is lower than the window value already programmed. - - (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when - the counter reaches 0x40. User can add his own code in weak function - HAL_WWDG_EarlyWakeupCallback(). + the counter is lower than the refresh window value already programmed. - *** WWDG HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in WWDG HAL driver. + *** Callback registration *** + ============================= - (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source. - (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status. - (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags. + [..] + The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows + the user to configure dynamically the driver callbacks. Use Functions + HAL_WWDG_RegisterCallback() to register a user callback. + + (+) Function HAL_WWDG_RegisterCallback() allows to register following + callbacks: + (++) EwiCallback : callback for Early WakeUp Interrupt. + (++) MspInitCallback : WWDG MspInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to + the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback() + takes as parameters the HAL peripheral handle and the Callback ID. + This function allows to reset following callbacks: + (++) EwiCallback : callback for Early WakeUp Interrupt. + (++) MspInitCallback : WWDG MspInit. + + [..] + When calling HAL_WWDG_Init function, callbacks are reset to the + corresponding legacy weak (surcharged) functions: + HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have + not been registered before. + + [..] + When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + *** WWDG HAL driver macros list *** + =================================== + [..] + Below the list of available macros in WWDG HAL driver. + (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral + (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status + (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags + (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt @endverbatim ****************************************************************************** @@ -164,12 +190,12 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) /* Reset Callback pointers */ - if(hwwdg->EwiCallback == NULL) + if (hwwdg->EwiCallback == NULL) { hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback; } - if(hwwdg->MspInitCallback == NULL) + if (hwwdg->MspInitCallback == NULL) { hwwdg->MspInitCallback = HAL_WWDG_MspInit; } @@ -179,7 +205,7 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) #else /* Init the low level hardware */ HAL_WWDG_MspInit(hwwdg); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /* Set WWDG Counter */ WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); @@ -191,6 +217,7 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) return HAL_OK; } + /** * @brief Initialize the WWDG MSP. * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains @@ -223,17 +250,18 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, + pWWDG_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { status = HAL_ERROR; } else { - switch(CallbackID) + switch (CallbackID) { case HAL_WWDG_EWI_CB_ID: hwwdg->EwiCallback = pCallback; @@ -267,7 +295,7 @@ HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWD { HAL_StatusTypeDef status = HAL_OK; - switch(CallbackID) + switch (CallbackID) { case HAL_WWDG_EWI_CB_ID: hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback; @@ -284,15 +312,15 @@ HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWD return status; } -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup WWDG_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * + * @brief IO operation functions + * @verbatim ============================================================================== ##### IO operation functions ##### @@ -352,14 +380,15 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) #else /* Early Wakeup callback */ HAL_WWDG_EarlyWakeupCallback(hwwdg); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ } } } + /** * @brief WWDG Early Wakeup callback. - * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval None */ diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_adc.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_adc.c index 324a2887be..1a89156cbf 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_adc.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_adc.c @@ -657,6 +657,11 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); + /* ADC group regular continuous mode and discontinuous mode */ + /* can not be enabled simultenaeously */ + assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); + /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ if(LL_ADC_IsEnabled(ADCx) == 0U) diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c index 92db17df06..cc3b01ec2f 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c @@ -203,9 +203,12 @@ * @param Init Pointer to NORSRAM Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init) +HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_InitTypeDef *Init) { uint32_t flashaccess; + uint32_t btcr_reg; + uint32_t mask; /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); @@ -237,36 +240,40 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_ flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE; } - MODIFY_REG(Device->BTCR[Init->NSBank], - (FSMC_BCRx_MBKEN | - FSMC_BCRx_MUXEN | - FSMC_BCRx_MTYP | - FSMC_BCRx_MWID | - FSMC_BCRx_FACCEN | - FSMC_BCRx_BURSTEN | - FSMC_BCRx_WAITPOL | - FSMC_BCRx_WRAPMOD | - FSMC_BCRx_WAITCFG | - FSMC_BCRx_WREN | - FSMC_BCRx_WAITEN | - FSMC_BCRx_EXTMOD | - FSMC_BCRx_ASYNCWAIT | - FSMC_BCRx_CBURSTRW | - 0x00070000U), /* CPSIZE to be defined in CMSIS file */ - (flashaccess | - Init->DataAddressMux | - Init->MemoryType | - Init->MemoryDataWidth | - Init->BurstAccessMode | - Init->WaitSignalPolarity | - Init->WrapMode | - Init->WaitSignalActive | - Init->WriteOperation | - Init->WaitSignal | - Init->ExtendedMode | - Init->AsynchronousWait | - Init->WriteBurst | - Init->PageSize)); + btcr_reg = (flashaccess | \ + Init->DataAddressMux | \ + Init->MemoryType | \ + Init->MemoryDataWidth | \ + Init->BurstAccessMode | \ + Init->WaitSignalPolarity | \ + Init->WaitSignalActive | \ + Init->WriteOperation | \ + Init->WaitSignal | \ + Init->ExtendedMode | \ + Init->AsynchronousWait | \ + Init->WriteBurst); + + btcr_reg |= Init->WrapMode; + btcr_reg |= Init->PageSize; + + mask = (FSMC_BCRx_MBKEN | + FSMC_BCRx_MUXEN | + FSMC_BCRx_MTYP | + FSMC_BCRx_MWID | + FSMC_BCRx_FACCEN | + FSMC_BCRx_BURSTEN | + FSMC_BCRx_WAITPOL | + FSMC_BCRx_WAITCFG | + FSMC_BCRx_WREN | + FSMC_BCRx_WAITEN | + FSMC_BCRx_EXTMOD | + FSMC_BCRx_ASYNCWAIT | + FSMC_BCRx_CBURSTRW); + + mask |= FSMC_BCRx_WRAPMOD; + mask |= 0x00070000U; /* CPSIZE to be defined in CMSIS file */ + + MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); return HAL_OK; @@ -279,7 +286,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_ * @param Bank NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) +HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); @@ -315,7 +323,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM * @param Bank NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ @@ -331,12 +340,12 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO /* Set FSMC_NORSRAM device timing parameters */ MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FSMC_BTRx_DATAST_Pos) | - ((Timing->BusTurnAroundDuration) << FSMC_BTRx_BUSTURN_Pos) | - (((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) | - (((Timing->DataLatency) - 2U) << FSMC_BTRx_DATLAT_Pos) | - (Timing->AccessMode))); + ((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FSMC_BTRx_DATAST_Pos) | + ((Timing->BusTurnAroundDuration) << FSMC_BTRx_BUSTURN_Pos) | + (((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) | + (((Timing->DataLatency) - 2U) << FSMC_BTRx_DATLAT_Pos) | + (Timing->AccessMode))); return HAL_OK; } @@ -353,7 +362,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO * @arg FSMC_EXTENDED_MODE_ENABLE * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) +HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) { /* Check the parameters */ assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode)); @@ -403,8 +413,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDe */ /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2 - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### FSMC_NORSRAM Control functions ##### @@ -490,8 +500,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi */ /** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim ============================================================================== ##### Initialization and de_initialization functions ##### @@ -560,7 +570,8 @@ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDe * @param Bank NAND bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FSMC_NAND_DEVICE(Device)); @@ -599,7 +610,8 @@ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, F * @param Bank NAND bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FSMC_NAND_DEVICE(Device)); @@ -746,7 +758,8 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) +HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout) { uint32_t tickstart; @@ -869,7 +882,8 @@ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_Init * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ -HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) +HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing) { /* Check the parameters */ assert_param(IS_FSMC_PCCARD_DEVICE(Device)); @@ -895,7 +909,8 @@ HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Devic * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ -HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) +HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing) { /* Check the parameters */ assert_param(IS_FSMC_PCCARD_DEVICE(Device)); @@ -921,7 +936,8 @@ HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *De * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ -HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) +HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing) { /* Check the parameters */ assert_param(IS_FSMC_PCCARD_DEVICE(Device)); @@ -981,5 +997,8 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device) /** * @} */ +/** + * @} + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c index fc00383487..43baadfc17 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c @@ -189,12 +189,6 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); - /* Pin Mode configuration */ - LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); - - /* Pull-up Pull-down resistor configuration*/ - LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) { /* Check speed and Output mode parameters */ @@ -207,6 +201,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /* Output mode configuration*/ LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType); } + + /* Pull-up Pull-down resistor configuration*/ + LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); + + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); } pinpos++; } diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c index dd522e3251..9bf4d7e30e 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c @@ -310,7 +310,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; TIM_InitStruct->Autoreload = 0xFFFFFFFFU; TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; - TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; + TIM_InitStruct->RepetitionCounter = 0x00000000U; } /** diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c index 0b89546a9a..15bcca7a26 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c @@ -1894,6 +1894,46 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) return HAL_OK; } +/** + * @brief USB_FlushTxFifo : Flush a Tx FIFO + * @param USBx : Selected device + * @param num : FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(num); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo : Flush Rx FIFO + * @param USBx : Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + /** * @brief Activate and configure an endpoint * @param USBx Selected device diff --git a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c index 1978dc3756..7a1241792d 100644 --- a/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c +++ b/system/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c @@ -140,9 +140,6 @@ */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); -#if defined(FLASH_ACR_LATENCY) -static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency); -#endif /* FLASH_ACR_LATENCY */ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); static ErrorStatus UTILS_PLL_IsBusy(void); /** @@ -246,6 +243,77 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency) SystemCoreClock = HCLKFrequency; } +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @param Frequency SYSCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +#if defined(FLASH_ACR_LATENCY) +ErrorStatus LL_SetFlashLatency(uint32_t Frequency) +{ + uint32_t timeout; + uint32_t getlatency; + uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + ErrorStatus status = SUCCESS; + + /* Frequency cannot be equal to 0 */ + if (Frequency == 0U) + { + status = ERROR; + } + else + { + if (Frequency > UTILS_LATENCY2_FREQ) + { + /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if (Frequency > UTILS_LATENCY1_FREQ) + { + /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + else + { + /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */ + latency = LL_FLASH_LATENCY_0; + } + } + + if (status != ERROR) + { + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + timeout = 2; + do + { + /* Wait for Flash latency to be updated */ + getlatency = LL_FLASH_GetLatency(); + timeout--; + } while ((getlatency != latency) && (timeout > 0)); + + if(getlatency != latency) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + } + + return status; +} +#endif /* FLASH_ACR_LATENCY */ + /** * @brief This function configures system clock with HSI as clock source of the PLL * @note The application need to ensure that PLL is disabled. @@ -393,56 +461,6 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa /** @addtogroup UTILS_LL_Private_Functions * @{ */ -/** - * @brief Update number of Flash wait states in line with new frequency and current - voltage range. - * @param Frequency SYSCLK frequency - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Latency has been modified - * - ERROR: Latency cannot be modified - */ -#if defined(FLASH_ACR_LATENCY) -static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency) -{ - ErrorStatus status = SUCCESS; - - uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ - - /* Frequency cannot be equal to 0 */ - if (Frequency == 0U) - { - status = ERROR; - } - else - { - if (Frequency > UTILS_LATENCY2_FREQ) - { - /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if (Frequency > UTILS_LATENCY1_FREQ) - { - /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */ - } - - LL_FLASH_SetLatency(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (LL_FLASH_GetLatency() != latency) - { - status = ERROR; - } - } - return status; -} -#endif /* FLASH_ACR_LATENCY */ - /** * @brief Function to check that PLL can be modified * @param PLL_InputFrequency PLL input frequency (in Hz) @@ -535,7 +553,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ if (sysclk_frequency_current < SYSCLK_Frequency) { /* Set FLASH latency to highest latency */ - status = UTILS_SetFlashLatency(SYSCLK_Frequency); + status = LL_SetFlashLatency(SYSCLK_Frequency); } #endif /* FLASH_ACR_LATENCY */ @@ -578,7 +596,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ if (sysclk_frequency_current > SYSCLK_Frequency) { /* Set FLASH latency to lowest latency */ - status = UTILS_SetFlashLatency(SYSCLK_Frequency); + status = LL_SetFlashLatency(SYSCLK_Frequency); } #endif /* FLASH_ACR_LATENCY */ diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 2028e1961d..103218f1fa 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -1,7 +1,7 @@ # STM32YYxx HAL Drivers version: * STM32F0: 1.7.4 - * STM32F1: 1.1.5 + * STM32F1: 1.1.6 * STM32F2: 1.2.4 * STM32F3: 1.5.4 * STM32F4: 1.7.9