Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.
This release is compatible with the previous versions.
V1.0.0 / 06-February-2019
-
Main Changes
+
Main Changes
First release
First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
index 818d86a665..276d4f14bb 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal.c
@@ -56,7 +56,7 @@
* @brief STM32WBxx HAL Driver version number
*/
#define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32WBxx_HAL_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
+#define __STM32WBxx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
#define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
index ecf52d2ad7..47d3f1f649 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc.c
@@ -3,7 +3,7 @@
* @file stm32wbxx_hal_adc.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
+ * functionalities of the Analog to Digital Converter (ADC)
* peripheral:
* + Initialization and de-initialization functions
* ++ Initialization and Configuration of ADC
@@ -341,6 +341,11 @@
/* Unit: cycles of CPU clock. */
#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Register CHSELR bits corresponding to ranks 2 to 8 . */
+#define ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8)
+#endif
+
/**
* @}
@@ -394,11 +399,15 @@
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tmpCFGR;
+ uint32_t tmpCFGR = 0UL;
uint32_t tmp_adc_reg_is_conversion_on_going;
__IO uint32_t wait_loop_index = 0UL;
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ uint32_t tmpCFGR2 = 0UL;
+#else
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
+#endif
/* Check ADC handle */
if (hadc == NULL)
@@ -419,6 +428,23 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
+ assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1));
+ assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2));
+
+ assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode));
+
+ if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+
+ if(hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+ }
+ }
+#else
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
@@ -434,6 +460,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
/* DISCEN and CONT bits cannot be set at the same time */
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
@@ -445,8 +472,10 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
+#if !defined (ADC_SUPPORT_2_5_MSPS)
hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
+#endif
hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
@@ -470,7 +499,10 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
hadc->Lock = HAL_UNLOCKED;
}
- /* - Exit from deep-power-down mode and ADC voltage regulator enable */
+ /* - Exit from deep power-down mode and ADC voltage regulator enable */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Feature "deep power-down" not available on ADC peripheral of this STM32WB device */
+#else
if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
{
/* Disable ADC deep power down mode */
@@ -480,6 +512,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
be relaunched or a previously saved calibration factor
re-applied once the ADC voltage regulator is enabled */
}
+#endif
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
{
@@ -525,6 +558,219 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
HAL_ADC_STATE_REG_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Configuration of common ADC parameters */
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Internal voltage regulator (no parameter in HAL ADC init structure) */
+ /* - Clock configuration */
+ /* - ADC resolution */
+ /* Note: If low power mode AutoPowerOff is enabled, ADC enable */
+ /* and disable phases are performed automatically by hardware */
+ /* (in this case, flag ADC_FLAG_RDY is not set). */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ /* Some parameters of this register are not reset, since they are set */
+ /* by other functions and must be kept in case of usage of this */
+ /* function on the fly (update of a parameter of ADC_InitTypeDef */
+ /* without needing to reconfigure all other ADC groups/channels */
+ /* parameters): */
+ /* - internal measurement paths: Vbat, temperature sensor, Vref */
+ /* (set into HAL_ADC_ConfigChannel() ) */
+
+ /* Configuration of ADC resolution */
+ MODIFY_REG(hadc->Instance->CFGR1,
+ ADC_CFGR1_RES ,
+ hadc->Init.Resolution );
+
+ /* Configuration of ADC: */
+ /* - clock */
+ /* - oversampling enable */
+ /* - oversampling ratio */
+ /* - oversampling shift */
+ /* - oversampling discontinuous mode (triggered mode) */
+ /* - trigger frequency mode */
+ tmpCFGR2 |= ( (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
+ hadc->Init.TriggerFrequencyMode
+ );
+
+ MODIFY_REG(hadc->Instance->CFGR2,
+ ADC_CFGR2_CKMODE |
+ ADC_CFGR2_LFTRIG ,
+ tmpCFGR2 );
+
+ /* Configuration of ADC clock mode: asynchronous clock source */
+ /* with selectable prescaler. */
+ if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
+ ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) &&
+ ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4))
+ {
+ MODIFY_REG(ADC1_COMMON->CCR ,
+ ADC_CCR_PRESC ,
+ hadc->Init.ClockPrescaler & ADC_CCR_PRESC );
+ }
+ }
+
+ /* Configuration of ADC: */
+ /* - discontinuous mode */
+ /* - LowPowerAutoWait mode */
+ /* - LowPowerAutoPowerOff mode */
+ /* - continuous conversion mode */
+ /* - overrun */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+ /* - data alignment */
+ /* - resolution */
+ /* - scan direction */
+ /* - DMA continuous request */
+ tmpCFGR |= (ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
+ ADC_CFGR_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
+ ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
+ ADC_CFGR_OVERRUN(hadc->Init.Overrun) |
+ hadc->Init.DataAlign |
+ ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
+ ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) );
+
+ /* Update setting of discontinuous mode only if continuous mode is disabled */
+ if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ {
+ if (hadc->Init.ContinuousConvMode == DISABLE)
+ {
+ /* Enable the selected ADC group regular discontinuous mode */
+ tmpCFGR |= ADC_CFGR1_DISCEN;
+ }
+ else
+ {
+ /* ADC regular group discontinuous was intended to be enabled, */
+ /* but ADC regular group modes continuous and sequencer discontinuous */
+ /* cannot be enabled simultaneously. */
+
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ tmpCFGR |= ( (hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) |
+ hadc->Init.ExternalTrigConvEdge );
+ }
+
+ /* Update ADC configuration register with previous settings */
+ MODIFY_REG(hadc->Instance->CFGR1,
+ ADC_CFGR1_DISCEN |
+ ADC_CFGR1_AUTOFF |
+ ADC_CFGR1_WAIT |
+ ADC_CFGR1_CONT |
+ ADC_CFGR1_OVRMOD |
+ ADC_CFGR1_EXTSEL |
+ ADC_CFGR1_EXTEN |
+ ADC_CFGR1_ALIGN |
+ ADC_CFGR1_SCANDIR |
+ ADC_CFGR1_DMACFG ,
+ tmpCFGR );
+
+ /* Channel sampling time configuration */
+ LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1);
+ LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2);
+
+ /* Configuration of regular group sequencer: */
+ /* - if scan mode is disabled, regular channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* Parameter "NbrOfConversion" is discarded. */
+ /* Note: Scan mode is not present by hardware on this device, but */
+ /* emulated by software for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, regular channels sequence length is set to */
+ /* parameter "NbrOfConversion". */
+ /* Channels must be configured into each rank using function */
+ /* "HAL_ADC_ConfigChannel()". */
+ if(hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
+ {
+ /* Set sequencer scan length by clearing ranks above rank 1 */
+ /* and do not modify rank 1 value. */
+ SET_BIT(hadc->Instance->CHSELR,
+ ADC_CHSELR_SQ2_TO_SQ8);
+ }
+ else if(hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ {
+ /* Count number of ranks available in HAL ADC handle variable */
+ uint32_t ADCGroupRegularSequencerRanksCount;
+
+ /* Parse all ranks from 1 to 8 */
+ for(ADCGroupRegularSequencerRanksCount = 0UL; ADCGroupRegularSequencerRanksCount < (8UL); ADCGroupRegularSequencerRanksCount++)
+ {
+ /* Check each sequencer rank until value of end of sequence */
+ if(((hadc->ADCGroupRegularSequencerRanks >> (ADCGroupRegularSequencerRanksCount * 4UL)) & ADC_CHSELR_SQ1) == ADC_CHSELR_SQ1)
+ {
+ break;
+ }
+ }
+
+ if(ADCGroupRegularSequencerRanksCount == 1UL)
+ {
+ /* Set ADC group regular sequencer: */
+ /* Set sequencer scan length by clearing ranks above rank 1 */
+ /* and do not modify rank 1 value. */
+ SET_BIT(hadc->Instance->CHSELR,
+ ADC_CHSELR_SQ2_TO_SQ8);
+ }
+ else
+ {
+ /* Set ADC group regular sequencer: */
+ /* - Set ADC group regular sequencer to value memorized */
+ /* in HAL ADC handle */
+ /* Note: This value maybe be initialized at a unknown value, */
+ /* therefore afer the first call of "HAL_ADC_Init()", */
+ /* each rank corresponding to parameter "NbrOfConversion" */
+ /* must be set using "HAL_ADC_ConfigChannel()". */
+ /* - Set sequencer scan length by clearing ranks above maximum rank */
+ /* and do not modify other ranks value. */
+ MODIFY_REG(hadc->Instance->CHSELR,
+ ADC_CHSELR_SQ_ALL,
+ (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL)) | (hadc->ADCGroupRegularSequencerRanks)
+ );
+ }
+ }
+
+ /* Check back that ADC registers have effectively been configured to */
+ /* ensure of no potential problem of ADC core peripheral clocking. */
+ /* Check through register CFGR1 (excluding analog watchdog configuration: */
+ /* set into separate dedicated function, and bits of ADC resolution set */
+ /* out of temporary variable 'tmpCFGR'). */
+ if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_RES))
+ == tmpCFGR)
+ {
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Set the ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+#else
/* Configuration of common ADC parameters */
/* Parameters update conditioned to ADC state: */
@@ -564,7 +810,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
/* - overrun Init.Overrun */
/* - discontinuous mode Init.DiscontinuousConvMode */
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
- tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
+ tmpCFGR |= (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
hadc->Init.Overrun |
hadc->Init.DataAlign |
hadc->Init.Resolution |
@@ -662,6 +908,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
/* Initialize the ADC state */
/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
else
{
@@ -710,8 +957,15 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
/* Stop potential conversion on going */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+#else
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+#endif /* ADC_SUPPORT_2_5_MSPS */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/* Disable ADC peripheral if conversions are effectively stopped */
/* Flush register JSQR: reset the queue sequencer when injected */
/* queue sequencer is enabled and ADC disabled. */
@@ -719,6 +973,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
/* internally disabled just after the completion of the last valid */
/* injected sequence. */
SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
+#endif
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
@@ -741,18 +996,69 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
/* system RCC hard reset. */
/* ========== Reset ADC registers ========== */
+#if defined (ADC_SUPPORT_2_5_MSPS)
/* Reset register IER */
- __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
- ADC_IT_JQOVF | ADC_IT_OVR |
- ADC_IT_JEOS | ADC_IT_JEOC |
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 |
+ ADC_IT_AWD1 | ADC_IT_OVR |
ADC_IT_EOS | ADC_IT_EOC |
- ADC_IT_EOSMP | ADC_IT_RDY));
+ ADC_IT_EOSMP | ADC_IT_RDY ) );
/* Reset register ISR */
- __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
- ADC_FLAG_JQOVF | ADC_FLAG_OVR |
- ADC_FLAG_JEOS | ADC_FLAG_JEOC |
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 |
+ ADC_FLAG_AWD1 | ADC_FLAG_OVR |
ADC_FLAG_EOS | ADC_FLAG_EOC |
+ ADC_FLAG_EOSMP | ADC_FLAG_RDY ) );
+
+ /* Reset register CR */
+ /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
+ /* "read-set": no direct reset applicable. */
+
+ /* Reset register CFGR1 */
+ hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN |
+ ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
+ ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES |
+ ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN );
+
+ /* Reset register CFGR2 */
+ /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
+ /* already done above. */
+ hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE;
+
+ /* Reset register SMPR */
+ hadc->Instance->SMPR &= ~ADC_SMPR_SMP1;
+
+ /* Reset register TR1 */
+ hadc->Instance->TR1 &= ~(ADC_TR1_HT1 | ADC_TR1_LT1);
+
+ /* Reset register CHSELR */
+ hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL);
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable */
+
+#else
+ /* Reset register IER */
+ __HAL_ADC_DISABLE_IT(hadc, (
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
+ ADC_IT_EOCAL | ADC_IT_CCRDY |
+#else
+ ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
+ ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_JQOVF |
+#endif
+ ADC_IT_EOS | ADC_IT_EOC | ADC_IT_OVR |
+ ADC_IT_EOSMP | ADC_IT_RDY));
+
+ /* Reset register ISR */
+ __HAL_ADC_CLEAR_FLAG(hadc, (
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+ ADC_FLAG_EOCAL | ADC_FLAG_CCRDY |
+#else
+ ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+ ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_JQOVF |
+#endif
+ ADC_FLAG_EOS | ADC_FLAG_EOC | ADC_FLAG_OVR |
ADC_FLAG_EOSMP | ADC_FLAG_RDY));
/* Reset register CR */
@@ -831,6 +1137,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
/* Reset register CALFACT */
CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* ========== Reset common ADC registers ========== */
@@ -876,9 +1183,14 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Reset HAL ADC handle variable */
+ hadc->ADCGroupRegularSequencerRanks = 0x00000000UL;
+#else
/* Reset injected channel configuration parameters */
hadc->InjectionConfig.ContextQueue = 0;
hadc->InjectionConfig.ChannelCount = 0;
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Set ADC state */
hadc->State = HAL_ADC_STATE_RESET;
@@ -1094,6 +1406,9 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca
hadc->ErrorCallback = HAL_ADC_ErrorCallback;
break;
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
break;
@@ -1101,6 +1416,7 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca
case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
break;
+#endif
case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
@@ -1225,6 +1541,10 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
HAL_ADC_STATE_REG_BUSY);
/* Set ADC error code */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+#else
/* Check if a conversion is on going on ADC group injected */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
@@ -1236,6 +1556,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Clear ADC group regular conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
@@ -1287,8 +1608,13 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
/* Process locked */
__HAL_LOCK(hadc);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* 1. Stop potential conversion on going, on ADC group regular */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+#else
/* 1. Stop potential conversion on going, on ADC groups regular and injected */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
@@ -1300,9 +1626,15 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+#else
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
}
@@ -1353,7 +1685,11 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
/* several ranks and polling for end of each conversion. */
/* For code simplicity sake, this particular case is generalized to */
/* ADC configured in DMA mode and and polling for end of each conversion. */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if(READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) != 0UL)
+#else
if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
+#endif
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
@@ -1420,7 +1756,11 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
/* Clear end of conversion EOC flag of regular group if low power feature */
/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
/* until data register is read using function HAL_ADC_GetValue(). */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_WAIT) == 0UL)
+#else
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY) == 0UL)
+#endif
{
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
}
@@ -1440,7 +1780,9 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti
* @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
* @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
* @arg @ref ADC_OVR_EVENT ADC Overrun event
- * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
+ * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @param Timeout Timeout value in millisecond.
* @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
* Indeed, the latter is reset only if hadc->Init.Overrun field is set
@@ -1531,6 +1873,9 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventTy
break;
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/* Injected context queue overflow event */
case ADC_JQOVF_EVENT:
/* Set ADC state */
@@ -1543,6 +1888,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventTy
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
break;
+#endif
/* Overrun event */
default: /* Case ADC_OVR_EVENT */
@@ -1617,6 +1963,10 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
HAL_ADC_STATE_REG_BUSY);
/* Set ADC error code */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+#else
/* Check if a conversion is on going on ADC group injected */
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
{
@@ -1628,6 +1978,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Clear ADC group regular conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
@@ -1702,8 +2053,13 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
/* Process locked */
__HAL_LOCK(hadc);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* 1. Stop potential conversion on going, on ADC group regular */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+#else
/* 1. Stop potential conversion on going, on ADC groups regular and injected */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
@@ -1719,9 +2075,15 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+#else
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
}
@@ -1768,6 +2130,10 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
HAL_ADC_STATE_REG_BUSY);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+#else
/* Check if a conversion is on going on ADC group injected */
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
{
@@ -1779,6 +2145,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
@@ -1809,7 +2176,11 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Enable ADC DMA mode */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ SET_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
+#else
SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+#endif
/* Start the DMA channel */
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
@@ -1857,13 +2228,21 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
__HAL_LOCK(hadc);
/* 1. Stop potential ADC group regular conversion on going */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+#else
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
{
/* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
+#else
CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+#endif
/* Disable the DMA channel (in case of DMA in circular mode or stop */
/* while DMA transfer is on going) */
@@ -1898,9 +2277,15 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+#else
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
}
@@ -1953,9 +2338,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
uint32_t tmp_isr = hadc->Instance->ISR;
uint32_t tmp_ier = hadc->Instance->IER;
+#if !defined (ADC_SUPPORT_2_5_MSPS)
uint32_t tmp_adc_inj_is_trigger_source_sw_start;
uint32_t tmp_adc_reg_is_trigger_source_sw_start;
uint32_t tmp_cfgr;
+#endif
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -1999,7 +2386,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
{
/* Carry on if continuous mode is disabled */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if (READ_BIT (hadc->Instance->CFGR1, ADC_CFGR1_CONT) != ADC_CFGR1_CONT)
+#else
if (READ_BIT (hadc->Instance->CFGR, ADC_CFGR_CONT) != ADC_CFGR_CONT)
+#endif
{
/* If End of Sequence is reached, disable interrupts */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
@@ -2053,6 +2444,9 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
(((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
@@ -2074,44 +2468,46 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
/* group having no further conversion upcoming (same conditions as */
/* regular group interruption disabling above), */
/* and if injected scan sequence is completed. */
- if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
- ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
- ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
- (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
+ if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
{
- /* If End of Sequence is reached, disable interrupts */
- if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+ if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
+ ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
{
- /* Particular case if injected contexts queue is enabled: */
- /* when the last context has been fully processed, JSQR is reset */
- /* by the hardware. Even if no injected conversion is planned to come */
- /* (queue empty, triggers are ignored), it can start again */
- /* immediately after setting a new context (JADSTART is still set). */
- /* Therefore, state of HAL ADC injected group is kept to busy. */
- if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM) == 0UL)
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
{
- /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
- /* JADSTART==0 (no conversion on going) */
- if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ /* Particular case if injected contexts queue is enabled: */
+ /* when the last context has been fully processed, JSQR is reset */
+ /* by the hardware. Even if no injected conversion is planned to come */
+ /* (queue empty, triggers are ignored), it can start again */
+ /* immediately after setting a new context (JADSTART is still set). */
+ /* Therefore, state of HAL ADC injected group is kept to busy. */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM) == 0UL)
{
- /* Disable ADC end of sequence conversion interrupt */
- __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
+ /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
+ /* JADSTART==0 (no conversion on going) */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Disable ADC end of sequence conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
- /* Set ADC state */
- CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
- if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
- {
- SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
}
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
}
}
}
@@ -2132,6 +2528,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
/* Clear injected group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* ========== Check Analog watchdog 1 flag ========== */
if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
@@ -2230,6 +2627,9 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/* ========== Check Injected context queue overflow flag ========== */
if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
{
@@ -2249,6 +2649,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
@@ -2357,12 +2758,190 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_config_internal_channel;
+ __IO uint32_t wait_loop_index = 0UL;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
+ assert_param(IS_ADC_SAMPLING_TIME_COMMON(sConfig->SamplingTime));
+
+ if((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
+ (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD) )
+ {
+ assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(sConfig->Rank));
+ }
+ else
+ {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+
+ assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel number */
+ /* - Channel sampling time */
+ /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Configure channel: depending on rank setting, add it or remove it from */
+ /* ADC sequencer. */
+ /* If sequencer set to not fully configurable with channel rank set to */
+ /* none, remove the channel from the sequencer. */
+ /* Otherwise (sequencer set to fully configurable or to to not fully */
+ /* configurable with channel rank to be set), configure the selected */
+ /* channel. */
+ if(sConfig->Rank != ADC_RANK_NONE)
+ {
+ /* Regular sequence configuration */
+ /* Note: ADC channel configuration requires few ADC clock cycles */
+ /* to be ready. Processing of ADC settings in this function */
+ /* induce that a specific wait time is not necessary. */
+ /* For more details on ADC channel configuration ready, */
+ /* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */
+ if((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
+ (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD) )
+ {
+ /* Sequencer set to not fully configurable: */
+ /* Set the channel by enabling the corresponding bitfield. */
+ LL_ADC_REG_SetSequencerChAdd(hadc->Instance, sConfig->Channel);
+ }
+ else
+ {
+ /* Sequencer set to fully configurable: */
+ /* Set the channel by entering it into the selected rank. */
+
+ /* Memorize the channel set into variable in HAL ADC handle */
+ MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
+ ADC_CHSELR_SQ1 << (sConfig->Rank & 0x1FUL),
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) << (sConfig->Rank & 0x1FUL));
+
+ /* If the selected rank is below ADC group regular sequencer length, */
+ /* apply the configuration in ADC register. */
+ /* Note: Otherwise, configuration is not applied. */
+ /* To apply it, parameter'NbrOfConversion' must be increased. */
+ if(((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
+ {
+ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
+ }
+ }
+
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
+
+ /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
+ /* internal measurement paths enable: If internal channel selected, */
+ /* enable dedicated internal buffers and path. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit() or removing the channel from sequencer with */
+ /* channel configuration parameter "Rank". */
+ if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+ {
+ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL);
+ while(wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+ else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+ }
+ else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ }
+ }
+ else
+ {
+ /* Regular sequencer configuration */
+ /* Note: Case of sequencer set to fully configurable: */
+ /* Sequencer rank cannot be disabled, only affected to */
+ /* another channel. */
+ /* To remove a rank, use parameter 'NbrOfConversion". */
+ if((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
+ (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD) )
+ {
+ /* Sequencer set to not fully configurable: */
+ /* Reset the channel by disabling the corresponding bitfield. */
+ LL_ADC_REG_SetSequencerChRem(hadc->Instance, sConfig->Channel);
+ }
+
+ /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
+ /* If internal channel selected, enable dedicated internal buffers and */
+ /* paths. */
+ if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+ {
+ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+ if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel);
+ }
+ else if (sConfig->Channel == ADC_CHANNEL_VBAT)
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_VBAT & tmp_config_internal_channel);
+ }
+ else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel);
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ }
+ }
+ }
+
+ /* If a conversion is on going on regular group, no update on regular */
+ /* channel could be done on neither of the channel configuration structure */
+ /* parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+#else
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpOffsetShifted;
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0;
+#if !defined (ADC_SUPPORT_2_5_MSPS)
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
+#endif
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -2404,11 +2983,15 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
/* conversion on going on regular group: */
/* - Channel sampling time */
/* - Channel offset */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+#else
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
)
+#endif /* ADC_SUPPORT_2_5_MSPS */
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
@@ -2549,6 +3132,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
/* Process unlocked */
__HAL_UNLOCK(hadc);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Return function status */
return tmp_hal_status;
@@ -2575,8 +3159,10 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpAWDHighThresholdShifted;
uint32_t tmpAWDLowThresholdShifted;
+#if !defined (ADC_SUPPORT_2_5_MSPS)
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
+#endif
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -2584,14 +3170,23 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
+#else
if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
+#endif
{
assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
}
/* Verify thresholds range */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Verify if thresholds are within the selected ADC resolution */
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+#else
if (hadc->Init.OversamplingMode == ENABLE)
{
/* Case of oversampling enabled: depending on ratio and shift configuration,
@@ -2606,6 +3201,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
}
+#endif
/* Process locked */
__HAL_LOCK(hadc);
@@ -2615,11 +3211,15 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
/* conversion on going on ADC groups regular and injected: */
/* - Analog watchdog channels */
/* - Analog watchdog thresholds */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+#else
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
)
+#endif /* ADC_SUPPORT_2_5_MSPS */
{
/* Analog watchdog configuration */
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
@@ -2634,6 +3234,9 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
LL_ADC_GROUP_REGULAR));
break;
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
LL_ADC_GROUP_INJECTED));
@@ -2643,11 +3246,15 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
LL_ADC_GROUP_REGULAR_INJECTED));
break;
+#endif /* ADC_SUPPORT_2_5_MSPS */
case ADC_ANALOGWATCHDOG_ALL_REG:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
break;
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
case ADC_ANALOGWATCHDOG_ALL_INJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
break;
@@ -2655,6 +3262,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
break;
+#endif /* ADC_SUPPORT_2_5_MSPS */
default: /* ADC_ANALOGWATCHDOG_NONE */
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
@@ -2689,14 +3297,19 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
LL_ADC_DisableIT_AWD1(hadc->Instance);
}
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Feature "ADC analog watchdog 2 and 3" not available on ADC peripheral of this STM32WB device */
+#else
/* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
else
{
switch (AnalogWDGConfig->WatchdogMode)
{
case ADC_ANALOGWATCHDOG_SINGLE_REG:
+#if !defined (ADC_SUPPORT_2_5_MSPS)
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+#endif
/* Update AWD by bitfield to keep the possibility to monitor */
/* several channels by successive calls of this function. */
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
@@ -2710,9 +3323,15 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
+#if !defined (ADC_SUPPORT_2_5_MSPS)
case ADC_ANALOGWATCHDOG_ALL_INJEC:
case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+#endif
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG);
+#else
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
+#endif
break;
default: /* ADC_ANALOGWATCHDOG_NONE */
@@ -2772,6 +3391,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
}
}
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
/* If a conversion is on going on ADC group regular or injected, no update */
@@ -2861,13 +3481,55 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
* @param hadc ADC handle
* @param ConversionGroup ADC group regular and/or injected.
* This parameter can be one of the following values:
- * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
- * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
- * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
+ * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
+ * @arg @ref ADC_INJECTED_GROUP (1) ADC injected conversion type.
+ * @arg @ref ADC_REGULAR_INJECTED_GROUP (1) ADC regular and injected conversion type.
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ UNUSED(ConversionGroup);
+
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Verification if ADC is not already stopped on regular group to bypass */
+ /* this function if not needed. */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ /* Stop potential conversion on going on regular group */
+ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+ if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+ {
+ /* Stop ADC group regular conversion */
+ LL_ADC_REG_StopConversion(hadc->Instance);
+ }
+
+ /* Wait for conversion effectively stopped */
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ while((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL)
+ {
+ if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+
+ }
+#else
uint32_t tickstart;
uint32_t Conversion_Timeout_CPU_cycles = 0UL;
uint32_t conversion_group_reassigned = ConversionGroup;
@@ -2982,6 +3644,7 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t Conversio
}
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Return HAL status */
return HAL_OK;
@@ -2999,6 +3662,7 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t Conversio
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
{
uint32_t tickstart;
+ __IO uint32_t wait_loop_index = 0UL;
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
@@ -3007,7 +3671,11 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
/* Check if conditions to enable the ADC are fulfilled */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+#else
if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+#endif
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
@@ -3021,33 +3689,54 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
/* Enable the ADC peripheral */
LL_ADC_Enable(hadc->Instance);
- /* Wait for ADC effectively enabled */
- tickstart = HAL_GetTick();
-
- while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
- {
- /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
- has been cleared (after a calibration), ADEN bit is reset by the
- calibration logic.
- The workaround is to continue setting ADEN until ADRDY is becomes 1.
- Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
- 4 ADC clock cycle duration */
- /* Note: Test of ADC enabled required due to hardware constraint to */
- /* not enable ADC if already enabled. */
- if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ if((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
+ {
+ /* Delay for temperature sensor buffer stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL);
+ while(wait_loop_index != 0UL)
{
- LL_ADC_Enable(hadc->Instance);
+ wait_loop_index--;
}
+ }
+
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* If low power mode AutoPowerOff is enabled, power-on/off phases are */
+ /* performed automatically by hardware and flag ADC ready is not set. */
+ if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
+#endif /*ADC_SUPPORT_2_5_MSPS */
+ {
+ /* Wait for ADC effectively enabled */
+ tickstart = HAL_GetTick();
- if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
{
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
+ has been cleared (after a calibration), ADEN bit is reset by the
+ calibration logic.
+ The workaround is to continue setting ADEN until ADRDY is becomes 1.
+ Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
+ 4 ADC clock cycle duration */
+ /* Note: Test of ADC enabled required due to hardware constraint to */
+ /* not enable ADC if already enabled. */
+ if(LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ LL_ADC_Enable(hadc->Instance);
+ }
- /* Set ADC error code to ADC peripheral internal error */
- SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
- return HAL_ERROR;
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
}
}
}
@@ -3076,7 +3765,11 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
)
{
/* Check if conditions to disable the ADC are fulfilled */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
+#else
if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
+#endif
{
/* Disable the ADC peripheral */
LL_ADC_Disable(hadc->Instance);
@@ -3136,6 +3829,41 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
/* by external trigger, continuous mode or scan sequence on going */
/* to disable interruption. */
/* Is it the end of the regular sequence ? */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if( (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ && (hadc->Init.ContinuousConvMode == DISABLE)
+ )
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Disable ADC end of single conversion interrupt on group regular */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+
+#else
if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
{
/* Are conversions software-triggered ? */
@@ -3167,6 +3895,7 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
}
}
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
index 132758580d..f29db42e5a 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_adc_ex.c
@@ -3,18 +3,18 @@
* @file stm32wbxx_hal_adc_ex.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
+ * functionalities of the Analog to Digital Converter (ADC)
* peripheral:
* + Operation functions
* ++ Start, stop, get result of conversions of ADC group injected,
- * using 2 possible modes: polling, interruption.
+ * using 2 possible modes: polling, interruption (not available on devices: STM32WB10xx, STM32WB15xx).
* ++ Calibration
* +++ ADC automatic self-calibration
* +++ Calibration factors get or set
* + Control functions
- * ++ Channels configuration on ADC group injected
+ * ++ Channels configuration on ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx)
* + State functions
- * ++ ADC group injected contexts queue management
+ * ++ ADC group injected contexts queue management (not available on devices: STM32WB10xx, STM32WB15xx)
* Other functions (generic functions) are available in file
* "stm32wbxx_hal_adc.c".
*
@@ -99,12 +99,12 @@
(+) Get calibration factors for single or differential ending.
(+) Set calibration factors for single or differential ending.
- (+) Start conversion of ADC group injected.
- (+) Stop conversion of ADC group injected.
- (+) Poll for conversion complete on ADC group injected.
- (+) Get result of ADC group injected channel conversion.
- (+) Start conversion of ADC group injected and enable interruptions.
- (+) Stop conversion of ADC group injected and disable interruptions.
+ (+) Start conversion of ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx).
+ (+) Stop conversion of ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx).
+ (+) Poll for conversion complete on ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx).
+ (+) Get result of ADC group injected channel conversion (not available on devices: STM32WB10xx, STM32WB15xx).
+ (+) Start conversion of ADC group injected and enable interruptions (not available on devices: STM32WB10xx, STM32WB15xx).
+ (+) Stop conversion of ADC group injected and disable interruptions (not available on devices: STM32WB10xx, STM32WB15xx).
@endverbatim
* @{
@@ -118,11 +118,17 @@
* @param SingleDiff Selection of single-ended or differential input
* This parameter can be one of the following values:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
- * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ UNUSED(SingleDiff);
+#endif
+
HAL_StatusTypeDef tmp_hal_status;
__IO uint32_t wait_loop_index = 0UL;
@@ -142,12 +148,22 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+#else
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Start ADC calibration in mode single-ended or differential */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ LL_ADC_StartCalibration(hadc->Instance);
+#else
LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Wait for calibration completion */
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
@@ -192,17 +208,27 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t
* @param hadc ADC handle.
* @param SingleDiff This parameter can be only:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
- * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval Calibration value.
*/
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ UNUSED(SingleDiff);
+#endif
+
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
/* Return the selected ADC calibration value */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ return LL_ADC_GetCalibrationFactor(hadc->Instance);
+#else
return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
+#endif
}
/**
@@ -211,15 +237,25 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t Single
* @param hadc ADC handle
* @param SingleDiff This parameter can be only:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
- * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended (1)
+ *
+ * (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
* @retval HAL state
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
{
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ UNUSED(SingleDiff);
+#endif
+
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmp_adc_is_conversion_on_going_regular;
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
uint32_t tmp_adc_is_conversion_on_going_injected;
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -232,15 +268,27 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32
/* Verification of hardware constraints before modifying the calibration */
/* factors register: ADC must be enabled, no conversion on going. */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+#endif /* ADC_SUPPORT_2_5_MSPS */
if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
&& (tmp_adc_is_conversion_on_going_regular == 0UL)
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
+#endif /* ADC_SUPPORT_2_5_MSPS */
)
{
/* Set the selected ADC calibration value */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ LL_ADC_SetCalibrationFactor(hadc->Instance, CalibrationFactor);
+#else
LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
+#endif
}
else
{
@@ -260,6 +308,9 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32
return tmp_hal_status;
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Enable ADC, start conversion of injected group.
* @note Interruptions enabled in this function: None.
@@ -705,7 +756,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
/* Return function status */
return tmp_hal_status;
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Get ADC injected group conversion result.
* @note Reading register JDRx automatically clears ADC flag JEOC
@@ -797,6 +852,7 @@ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
*/
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Analog watchdog 2 callback in non-blocking mode.
@@ -844,6 +900,9 @@ __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
*/
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Stop ADC conversion of regular group (and injected channels in
* case of auto_injection mode), disable ADC peripheral if no
@@ -1038,11 +1097,15 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
/* Return function status */
return tmp_hal_status;
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
* @brief ADC Extended Peripheral Control functions
*
@@ -1506,7 +1569,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* Return function status */
return tmp_hal_status;
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Enable Injected Queue
* @note This function resets CFGR register JQDIS bit in order to enable the
@@ -1584,6 +1651,7 @@ HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
return tmp_hal_status;
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Disable ADC voltage regulator.
@@ -1615,8 +1683,11 @@ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
return tmp_hal_status;
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature " ADC deep power-down" not available on ADC peripheral of this STM32WB device */
+#else
/**
- * @brief Enter ADC deep-power-down mode
+ * @brief Enter ADC deep power-down mode
* @note This mode is achieved in setting DEEPPWD bit and allows to save power
* in reducing leakage currents. It is particularly interesting before
* entering stop modes.
@@ -1651,6 +1722,7 @@ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
return tmp_hal_status;
}
+#endif
/**
* @}
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_comp.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_comp.c
index 91c1979f1f..be27bc52e6 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_comp.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_comp.c
@@ -18,7 +18,8 @@
[..]
The STM32WBxx device family integrates two analog comparators instances:
- COMP1, COMP2.
+ COMP1, COMP2 except for the STM32WB15xx, STM32WB10xx products featuring only
+ one instance: COMP1.
In the rest of the file, all comments related to a pair of comparators are not
applicable to STM32WB15xx, STM32WB10xx.
(#) Comparators input minus (inverting input) and input plus (non inverting input)
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c
index 12c62c5519..7018678784 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_cryp.c
@@ -6,7 +6,7 @@
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
* + Initialization, de-initialization, set config and get config functions
- * + DES/TDES, AES processing functions
+ * + AES processing functions
* + DMA callback functions
* + CRYP IRQ handler management
* + Peripheral State functions
@@ -32,8 +32,8 @@
(+++) Associate the initialized DMA handle to the CRYP DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the two DMA Streams. The output stream should have higher
- priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+ interrupt on the two DMA channels. The output channel should have higher
+ priority than the input channel HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
(#)Initialize the CRYP according to the specified parameters :
(##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
@@ -44,9 +44,13 @@
(+++) In some specific configurations, the key is written by the application
code out of the HAL scope. In that case, user can still resort to the
HAL APIs as usual but must make sure that pKey pointer is set to NULL.
+ (##) The DataWidthUnit field. It specifies whether the data length (or the payload length for authentication
+ algorithms) is in words or bytes.
(##) The Header used only in AES GCM and CCM Algorithm for authentication.
- (##) The HeaderSize The size of header buffer in word.
- (##) The B0 block is the first authentication block used only in AES CCM mode.
+ (##) The HeaderSize providing the size of the header buffer in words or bytes, depending upon HeaderWidthUnit field.
+ (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) is in words or bytes.
+ (##) The B0 block is the first authentication block used only in AES CCM mode.
+ (##) The KeyIVConfigSkip used to process several messages in a row (please see more information below).
(#)Three processing (encryption/decryption) functions are available:
(##) Polling mode: encryption and decryption APIs are blocking functions
@@ -321,6 +325,7 @@
#define CRYP_PHASE_HEADER_SUSPENDED 0x00000004U /*!< GCM/GMAC/CCM header phase is suspended */
#define CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U /*!< GCM/CCM payload phase is suspended */
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+#define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in DMA mode */
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */
#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */
@@ -345,9 +350,7 @@
* @{
*/
-#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
- (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
- }while(0U)
+#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__))
/**
* @}
@@ -361,6 +364,7 @@
*/
static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
+static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size);
static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
@@ -370,6 +374,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
+static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
@@ -383,6 +388,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
+static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output);
static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input);
@@ -1185,7 +1191,7 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (plaintext)
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(ciphertext)
* @param Timeout Specify Timeout value
* @retval HAL status
@@ -1285,7 +1291,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (ciphertext )
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(plaintext)
* @param Timeout Specify Timeout value
* @retval HAL status
@@ -1385,7 +1391,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (plaintext)
- * @param Size Length of the plaintext buffer in word
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
@@ -1495,7 +1501,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (ciphertext )
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(plaintext)
* @retval HAL status
*/
@@ -1604,7 +1610,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (plaintext)
- * @param Size Length of the plaintext buffer in word.
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
@@ -1731,7 +1737,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Input Pointer to the input buffer (ciphertext )
- * @param Size Length of the plaintext buffer in word
+ * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field)
* @param Output Pointer to the output buffer(plaintext)
* @retval HAL status
*/
@@ -1869,7 +1875,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
/* Clear computation complete flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
+ if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
{
/* if header phase */
@@ -1882,18 +1888,6 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
}
}
- else if (hcryp->Init.Algorithm == CRYP_AES_CCM)
- {
- /* if header phase */
- if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount)
- {
- CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
- }
- else /* if payload phase */
- {
- CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
- }
- }
else /* AES Algorithm ECB,CBC or CTR*/
{
CRYP_AES_IT(hcryp);
@@ -2502,10 +2496,81 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
{
CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t loopcounter;
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
/* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */
CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+ if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED)
+ {
+ /* DMA is disabled, CCF is meaningful. Wait for computation completion before moving forward */
+ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
+
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
+
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
+
+ if ((headersize_in_bytes % 16U) != 0U)
+ {
+ /* Write last words that couldn't be fed by DMA */
+ hcryp->CrypHeaderCount = (uint16_t)((headersize_in_bytes / 16U) * 4U);
+ for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
+ {
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ hcryp->CrypHeaderCount++ ;
+ }
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+
+ /* Wait for computation completion before moving forward */
+ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
+ } /* if ((headersize_in_bytes % 16U) != 0U) */
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Initiate payload DMA IN and processed data DMA OUT transfers */
+ (void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp);
+ }
+
/* Call input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
@@ -2526,7 +2591,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
uint32_t count;
uint32_t npblb;
uint32_t lastwordsize;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t mode;
CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
@@ -2579,44 +2644,21 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
}
/*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
-#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
/*Read the output block from the output FIFO */
for (count = 0U; count < 4U; count++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUTR;
+ temp[count] = hcryp->Instance->DOUTR;
+ }
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ count = 0U;
+ while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (count<4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count];
hcryp->CrypOutCount++;
+ count++;
}
}
@@ -2675,7 +2717,7 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param inputaddr address of the input buffer
- * @param Size size of the input buffer, must be a multiple of 16.
+ * @param Size size of the input and output buffers in words, must be a multiple of 4
* @param outputaddr address of the output buffer
* @retval None
*/
@@ -2733,6 +2775,43 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin
SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
}
+/**
+ * @brief Set the DMA configuration and start the header DMA transfer
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param inputaddr address of the input buffer
+ * @param Size size of the input buffer in words, must be a multiple of 4
+ * @retval None
+ */
+static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size)
+{
+ /* Set the CRYP DMA transfer complete callback */
+ hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
+
+ /* Set the DMA input error callback */
+ hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
+
+ /* Mark that header is fed to the peripheral in DMA mode */
+ hcryp->Phase = CRYP_PHASE_HEADER_DMA_FEED;
+ /* Enable the DMA input stream */
+ if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
+ {
+ /* DMA error code field */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ /* Call error callback */
+ }
+
+ /* Enable IN DMA requests */
+ SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
+
+ return HAL_OK;
+}
+
/**
* @brief Process Data: Write Input data in polling mode and used in AES functions.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
@@ -3162,6 +3241,12 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
uint32_t lastwordsize;
uint32_t npblb;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
+
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
@@ -3171,6 +3256,17 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
}
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
+ /* Manage header size given in bytes to handle cases where
+ header size is not a multiple of 4 bytes */
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
+
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
@@ -3337,27 +3433,43 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
}
}
}
- else if ((hcryp->Init.HeaderSize) < 4U)
+ /* Enter header data */
+ /* Cher first whether header length is small enough to enter the full header in one shot */
+ else if (headersize_in_bytes <= 16U)
{
- for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
+ /* Write header data, padded with zeros if need be */
+ for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ hcryp->CrypHeaderCount++ ;
+ /* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
- /* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
}
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
-
- /* Set to 0 the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
@@ -3370,7 +3482,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
}
else
{
- /* Write the input block in the IN FIFO */
+ /* Write the first input header block in the Input FIFO,
+ the following header data will be fed after interrupt occurrence */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
@@ -3482,12 +3595,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
*/
static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
{
- __IO uint32_t count;
- uint16_t wordsize = hcryp->Size / 4U ;
- uint32_t index;
- uint32_t npblb;
- uint32_t lastwordsize;
- uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t count;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
@@ -3566,193 +3674,87 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
return HAL_ERROR;
}
- /************************ Payload phase ************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
+ }
+ else
+ {
+ /* Initialization and header phases already done, only do payload phase */
+ if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ } /* if (DoKeyIVConfig == 1U) */
- /* Set to 0 the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+ /* Return function status */
+ return HAL_OK;
+}
- /* Select payload phase once the header phase is performed */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
- } /* if (DoKeyIVConfig == 1U) */
+/**
+ * @brief AES CCM encryption/decryption processing in polling mode
+ * for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ;
+ uint32_t loopcounter;
+ uint32_t npblb;
+ uint32_t lastwordsize;
+ uint32_t temp[4] ; /* Temporary CrypOutBuff */
+ uint32_t incount; /* Temporary CrypInCount Value */
+ uint32_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
- if (hcryp->Size == 0U)
+ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
- /* Process unLocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
+ if (hcryp->KeyIVConfig == 1U)
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has already been done, skip it */
+ DoKeyIVConfig = 0U;
+ hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+ }
+ else
+ {
+ /* If the Key and IV configuration has to be done only once
+ and if it has not been done already, do it and set KeyIVConfig
+ to keep track it won't have to be done again next time */
+ hcryp->KeyIVConfig = 1U;
+ hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+ }
}
- else if (hcryp->Size >= 16U)
+ else
{
- /*DMA transfer must not include the last block in case of Size is not %16 */
- wordsize = wordsize - (wordsize % 4U);
-
- /*DMA transfer */
- CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
+ hcryp->SizesSum = hcryp->Size;
}
- else /* length of input data is < 16 */
+
+ if (DoKeyIVConfig == 1U)
{
- /* Compute the number of padding bytes in last block of payload */
- npblb = 16U - (uint32_t)hcryp->Size;
+ /* Reset CrypHeaderCount */
+ hcryp->CrypHeaderCount = 0U;
- /* Set Npblb in case of AES GCM payload encryption to get right tag*/
- if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
- {
- /* Specify the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
- }
+ /********************** Init phase ******************************************/
+
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+
+ /* Set the key */
+ CRYP_SetKey(hcryp, hcryp->Init.KeySize);
- /* Enable CRYP to start the final phase */
+ /* Set the initialization vector (IV) with B0 */
+ hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
+ hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
+ hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
+ hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
+
+ /* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
- /* Number of valid words (lastwordsize) in last block */
- if ((npblb % 4U) == 0U)
- {
- lastwordsize = (16U - npblb) / 4U;
- }
- else
- {
- lastwordsize = ((16U - npblb) / 4U) + 1U;
- }
-
- /* last block optionally pad the data with zeros*/
- for (index = 0U; index < lastwordsize; index ++)
- {
- /* Write the last Input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
- hcryp->CrypInCount++;
- }
- while (index < 4U)
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0U;
- index++;
- }
- /* Wait for CCF flag to be raised */
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
-#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /*Read the output block from the output FIFO */
- for (index = 0U; index < 4U; index++)
- {
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp[index] = hcryp->Instance->DOUTR;
- }
- for (index = 0U; index < lastwordsize; index++)
- {
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
- hcryp->CrypOutCount++;
- }
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
-
- /* Return function status */
- return HAL_OK;
-}
-
-
-/**
- * @brief AES CCM encryption/decryption processing in polling mode
- * for TinyAES peripheral, no encrypt/decrypt performed, only authentication preparation.
- * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
-{
- uint32_t tickstart;
- uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ;
- uint32_t loopcounter;
- uint32_t npblb;
- uint32_t lastwordsize;
- uint32_t temp[4] ; /* Temporary CrypOutBuff */
- uint32_t incount; /* Temporary CrypInCount Value */
- uint32_t outcount; /* Temporary CrypOutCount Value */
- uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
-
- if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
- {
- if (hcryp->KeyIVConfig == 1U)
- {
- /* If the Key and IV configuration has to be done only once
- and if it has already been done, skip it */
- DoKeyIVConfig = 0U;
- hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
- }
- else
- {
- /* If the Key and IV configuration has to be done only once
- and if it has not been done already, do it and set KeyIVConfig
- to keep track it won't have to be done again next time */
- hcryp->KeyIVConfig = 1U;
- hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
- }
- }
- else
- {
- hcryp->SizesSum = hcryp->Size;
- }
-
- if (DoKeyIVConfig == 1U)
- {
- /* Reset CrypHeaderCount */
- hcryp->CrypHeaderCount = 0U;
-
- /********************** Init phase ******************************************/
-
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
-
- /* Set the key */
- CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
- /* Set the initialization vector (IV) with B0 */
- hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
- hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
- hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
- hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- /* just wait for hash computation */
- if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
+ /* just wait for hash computation */
+ if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
@@ -4196,12 +4198,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
*/
static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
{
- __IO uint32_t count = 0U;
- uint16_t wordsize = hcryp->Size / 4U ;
- uint32_t index;
- uint32_t npblb;
- uint32_t lastwordsize;
- uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t count;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
@@ -4282,118 +4279,15 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
return HAL_ERROR;
}
- /******************** Payload phase *****************************************/
-
- /* Set the phase */
- hcryp->Phase = CRYP_PHASE_PROCESS;
-
- /* Set to 0 the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
-
- /* Select payload phase once the header phase is performed */
- MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
-
- } /* if (DoKeyIVConfig == 1U) */
-
- if (hcryp->Size == 0U)
- {
- /* Process unLocked */
- __HAL_UNLOCK(hcryp);
-
- /* Change the CRYP state and phase */
- hcryp->State = HAL_CRYP_STATE_READY;
- }
- else if (hcryp->Size >= 16U)
- {
- /*DMA transfer must not include the last block in case of Size is not %16 */
- wordsize = wordsize - (wordsize % 4U);
-
- /*DMA transfer */
- CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
}
- else /* length of input data is < 16 */
+ else
{
- /* Compute the number of padding bytes in last block of payload */
- npblb = 16U - (uint32_t)hcryp->Size;
-
- /* Set Npblb in case of AES CCM payload decryption to get right tag*/
- if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT)
- {
- /* Specify the number of non-valid bytes using NPBLB register*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
- }
-
- /* Number of valid words (lastwordsize) in last block */
- if ((npblb % 4U) == 0U)
- {
- lastwordsize = (16U - npblb) / 4U;
- }
- else
- {
- lastwordsize = ((16U - npblb) / 4U) + 1U;
- }
-
- /* last block optionally pad the data with zeros*/
- for (index = 0U; index < lastwordsize; index ++)
- {
- /* Write the last Input block in the IN FIFO */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
- hcryp->CrypInCount++;
- }
- while (index < 4U)
- {
- /* pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0U;
- index++;
- }
- /* Wait for CCF flag to be raised */
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
- /*Call registered error callback*/
- hcryp->ErrorCallback(hcryp);
-#else
- /*Call legacy weak error callback*/
- HAL_CRYP_ErrorCallback(hcryp);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF Flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
-
- /*Read the output block from the output FIFO */
- for (index = 0U; index < 4U; index++)
- {
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp[index] = hcryp->Instance->DOUTR;
- }
- for (index = 0U; index < lastwordsize; index++)
+ /* Initialization and header phases already done, only do payload phase */
+ if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
{
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
- hcryp->CrypOutCount++;
+ return HAL_ERROR;
}
-
- /* Change the CRYP state to ready */
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- }
+ } /* if (DoKeyIVConfig == 1U) */
/* Return function status */
return HAL_OK;
@@ -4546,23 +4440,141 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
/**
- * @brief Sets the header phase in polling mode
+ * @brief Sets the payload phase in DMA mode
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
- * the configuration information for CRYP module(Header & HeaderSize)
- * @param Timeout Timeout value
+ * the configuration information for CRYP module
* @retval state
*/
-static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp)
{
- uint32_t loopcounter;
- uint32_t size_in_bytes;
- uint32_t tmp;
- uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU};
-
- /***************************** Header phase for GCM/GMAC or CCM *********************************/
- if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
- {
- size_in_bytes = hcryp->Init.HeaderSize * 4U;
+ uint16_t wordsize = hcryp->Size / 4U ;
+ uint32_t index;
+ uint32_t npblb;
+ uint32_t lastwordsize;
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t count;
+ uint32_t reg;
+
+ /************************ Payload phase ************************************/
+ if (hcryp->Size == 0U)
+ {
+ /* Process unLocked */
+ __HAL_UNLOCK(hcryp);
+
+ /* Change the CRYP state and phase */
+ hcryp->State = HAL_CRYP_STATE_READY;
+ }
+ else if (hcryp->Size >= 16U)
+ {
+ /*DMA transfer must not include the last block in case of Size is not %16 */
+ wordsize = wordsize - (wordsize % 4U);
+
+ /*DMA transfer */
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
+ }
+ else /* length of input data is < 16 */
+ {
+ /* Compute the number of padding bytes in last block of payload */
+ npblb = 16U - (uint32_t)hcryp->Size;
+
+ /* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/
+ reg = hcryp->Instance->CR & (AES_CR_CHMOD|AES_CR_MODE);
+ if ((reg == (CRYP_AES_GCM_GMAC|CRYP_OPERATINGMODE_ENCRYPT)) ||\
+ (reg == (CRYP_AES_CCM|CRYP_OPERATINGMODE_DECRYPT)))
+ {
+ /* Specify the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
+ }
+
+ /* Number of valid words (lastwordsize) in last block */
+ if ((npblb % 4U) == 0U)
+ {
+ lastwordsize = (16U - npblb) / 4U;
+ }
+ else
+ {
+ lastwordsize = ((16U - npblb) / 4U) + 1U;
+ }
+
+ /* last block optionally pad the data with zeros*/
+ for (index = 0U; index < lastwordsize; index ++)
+ {
+ /* Write the last Input block in the IN FIFO */
+ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+ hcryp->CrypInCount++;
+ }
+ while (index < 4U)
+ {
+ /* pad the data with zeros to have a complete block */
+ hcryp->Instance->DINR = 0U;
+ index++;
+ }
+ /* Wait for CCF flag to be raised */
+ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
+ }
+ }
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF Flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+ /*Read the output block from the output FIFO */
+ for (index = 0U; index < 4U; index++)
+ {
+ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ temp[index] = hcryp->Instance->DOUTR;
+ }
+ for (index = 0U; index < lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
+ hcryp->CrypOutCount++;
+ }
+
+ /* Change the CRYP state to ready */
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets the header phase in polling mode
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module(Header & HeaderSize)
+ * @param Timeout Timeout value
+ * @retval state
+ */
+static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t loopcounter;
+ uint32_t size_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
+
+ /***************************** Header phase for GCM/GMAC or CCM *********************************/
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ size_in_bytes = hcryp->Init.HeaderSize * 4U;
}
else
{
@@ -4659,9 +4671,9 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
}
else
{
- /* Enter last bytes, padded with zeroes */
+ /* Enter last bytes, padded with zeros */
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- tmp &= mask[size_in_bytes % 4U];
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
hcryp->Instance->DINR = tmp;
loopcounter++;
/* Pad the data with zeros to have a complete block */
@@ -4691,17 +4703,14 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
}
else
{
- if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
- {
- /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/
- MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
+ /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
}
/* Return function status */
return HAL_OK;
@@ -4715,143 +4724,112 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
*/
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
{
- __IO uint32_t count = 0U;
uint32_t loopcounter;
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
/***************************** Header phase for GCM/GMAC or CCM *********************************/
- if ((hcryp->Init.HeaderSize != 0U))
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
{
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
-
- if ((hcryp->Init.HeaderSize % 4U) == 0U)
- {
- /* HeaderSize %4, no padding */
- for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
- {
- /* Write the input block in the data input register */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
- /*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
+ /* Select header phase */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Enable the CRYP peripheral */
+ __HAL_CRYP_ENABLE(hcryp);
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+ /* Set the phase */
+ hcryp->Phase = CRYP_PHASE_PROCESS;
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- }
+ /* If header size is at least equal to 16 bytes, feed the header through DMA.
+ If size_in_bytes is not a multiple of blocks (is not a multiple of four 32-bit words ),
+ last bytes feeding and padding will be done in CRYP_DMAInCplt() */
+ if (headersize_in_bytes >= 16U)
+ {
+ /* Initiate header DMA transfer */
+ if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK)
+ {
+ return HAL_ERROR;
}
- else
+ }
+ else
+ {
+ if (headersize_in_bytes != 0U)
{
- /*Write header block in the IN FIFO without last block */
- for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
+ /* Header length is larger than 0 and strictly less than 16 bytes */
+ /* Write last complete words */
+ for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
{
- /* Write the Input block in the Data Input register */
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
-
- /*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
- {
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
-
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
- }
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
- /* Clear CCF flag */
- __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
- /* Last block optionally pad the data with zeros*/
- for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
{
- hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
- hcryp->CrypHeaderCount++ ;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
}
- while (loopcounter < 4U)
+ else
{
- /* Pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
}
- /*Wait on CCF flag*/
- count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
- do
+ if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE) != HAL_OK)
{
- count-- ;
- if (count == 0U)
- {
- /* Disable the CRYP peripheral clock */
- __HAL_CRYP_DISABLE(hcryp);
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
- /* Change state */
- hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
- hcryp->State = HAL_CRYP_STATE_READY;
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+ hcryp->State = HAL_CRYP_STATE_READY;
- /* Process unlocked */
- __HAL_UNLOCK(hcryp);
- return HAL_ERROR;
- }
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ return HAL_ERROR;
}
- while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
-
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+ } /* if (headersize_in_bytes != 0U) */
+
+ /* Move to payload phase if header length is null or
+ if the header length was less than 16 and header written by software instead of DMA */
+
+ /* Set to 0 the number of non-valid bytes using NPBLB register*/
+ MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
+
+ /* Select payload phase once the header phase is performed */
+ CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+ /* Initiate payload DMA IN and processed data DMA OUT transfers */
+ if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
+ {
+ return HAL_ERROR;
}
- }
- else
- {
- /* Select header phase */
- CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+ } /* if (headersize_in_bytes >= 16U) */
- /* Enable the CRYP peripheral */
- __HAL_CRYP_ENABLE(hcryp);
- }
/* Return function status */
return HAL_OK;
}
@@ -4868,9 +4846,25 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
uint32_t lastwordsize;
uint32_t npblb;
uint32_t mode;
+ uint32_t headersize_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
+ 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
+ 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
+
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ headersize_in_bytes = hcryp->Init.HeaderSize;
+ }
/***************************** Header phase *********************************/
- if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
+ /* Test whether or not the header phase is over.
+ If the test below is true, move to payload phase */
+ if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
{
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
@@ -4955,9 +4949,9 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
}
}
}
- else if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U))
+ else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U))
{
-
+ /* Can enter full 4 header words */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
/* If suspension flag has been raised, suspend processing
only if not already at the end of the header */
@@ -4992,19 +4986,40 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
hcryp->CrypHeaderCount++;
}
}
- else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
+ else /* Write last header block (4 words), padded with zeros if needed */
{
- /* Last block optionally pad the data with zeros*/
- for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
+
+ for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
+ /* If the header size is a multiple of words */
+ if ((headersize_in_bytes % 4U) == 0U)
+ {
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeros */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ hcryp->CrypHeaderCount++;
+ /* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
- /* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
+ hcryp->CrypHeaderCount++;
+ }
}
}
}
@@ -5014,6 +5029,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @param Timeout Timeout duration.
+ * @note This function can only be used in thread mode.
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
@@ -5037,6 +5053,47 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T
return HAL_OK;
}
+/**
+ * @brief Wait for Computation Complete Flag (CCF) to raise then clear it.
+ * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
+ * the configuration information for CRYP module.
+ * @param Timeout Timeout duration.
+ * @note This function can be used in thread or handler mode.
+ * @retval HAL status
+ */
+static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
+{
+ uint32_t count = Timeout;
+
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ /* Disable the CRYP peripheral clock */
+ __HAL_CRYP_DISABLE(hcryp);
+
+ /* Change state */
+ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcryp);
+ hcryp->State = HAL_CRYP_STATE_READY;
+
+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
+ /*Call registered error callback*/
+ hcryp->ErrorCallback(hcryp);
+#else
+ /*Call legacy weak error callback*/
+ HAL_CRYP_ErrorCallback(hcryp);
+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
+ }
+ }
+ while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
+
+ /* Clear CCF flag */
+ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+}
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
/**
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
index ce938822f7..e7c9a5ca9b 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_flash_ex.c
@@ -607,6 +607,7 @@ static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32
* @arg @ref OB_STOP_RST or @ref OB_STOP_NORST
* @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST
* @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST
+ * @arg @ref OB_IRH_ENABLE or @ref OB_IRH_DISABLE (*)
* @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW
* @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN
* @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN
@@ -616,6 +617,7 @@ static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32
* @arg @ref OB_SRAM2_RST_ERASE or @ref OB_SRAM2_RST_NOT_ERASE
* @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN
* @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET
+ * @arg @ref OB_RESET_MODE_INPUT_ONLY or @ref OB_RESET_MODE_GPIO or @ref OB_RESET_MODE_INPUT_OUTPUT (*)
* @arg @ref OB_AGC_TRIM_0 or @ref OB_AGC_TRIM_1 or ... or @ref OB_AGC_TRIM_7
* @param RDPLevel: specifies the read protection level.
* This parameter can be one of the following values:
@@ -768,21 +770,35 @@ static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam)
MODIFY_REG(sfr_reg_val, FLASH_SFR_SFSA, (((pOBParam->SecureFlashStartAddr - FLASH_BASE) / FLASH_PAGE_SIZE) << FLASH_SFR_SFSA_Pos));
/* Configure SRRVR register */
+#if defined(FLASH_SRRVR_SBRSA_A)
+ MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRSA_A | FLASH_SRRVR_SBRSA_B), \
+ (((((pOBParam->SecureRAM2aStartAddr - SRAM2A_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_A_Pos)) | \
+ ((((pOBParam->SecureRAM2bStartAddr - SRAM2B_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_B_Pos))));
+#else
MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRSA | FLASH_SRRVR_SNBRSA), \
(((((pOBParam->SecureRAM2aStartAddr - SRAM2A_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_Pos)) | \
((((pOBParam->SecureRAM2bStartAddr - SRAM2B_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SNBRSA_Pos))));
+#endif
/* If Full System Secure mode is requested, clear all the corresponding bit */
/* Else set the corresponding bit */
if (pOBParam->SecureMode == SYSTEM_IN_SECURE_MODE)
{
CLEAR_BIT(sfr_reg_val, FLASH_SFR_FSD);
+#if defined(FLASH_SRRVR_BRSD_A)
+ CLEAR_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD_A | FLASH_SRRVR_BRSD_B));
+#else
CLEAR_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD));
+#endif
}
else
{
SET_BIT(sfr_reg_val, FLASH_SFR_FSD);
+#if defined(FLASH_SRRVR_BRSD_A)
+ SET_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD_A | FLASH_SRRVR_BRSD_B));
+#else
SET_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD));
+#endif
}
/* Update Flash registers */
@@ -870,6 +886,7 @@ static uint32_t FLASH_OB_GetRDP(void)
* @arg @ref OB_STOP_RST or @ref OB_STOP_RST
* @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST
* @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST
+ * @arg @ref OB_IRH_ENABLE or @ref OB_IRH_DISABLE (*)
* @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW
* @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN
* @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN
@@ -879,6 +896,7 @@ static uint32_t FLASH_OB_GetRDP(void)
* @arg @ref OB_SRAM2_RST_ERASE or @ref OB_SRAM2_RST_NOT_ERASE
* @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN
* @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET
+ * @arg @ref OB_RESET_MODE_INPUT_ONLY or @ref OB_RESET_MODE_GPIO or @ref OB_RESET_MODE_INPUT_OUTPUT (*)
* @arg @ref OB_AGC_TRIM_0 or @ref OB_AGC_TRIM_1 or ... or @ref OB_AGC_TRIM_7
*/
static uint32_t FLASH_OB_GetUser(void)
@@ -952,12 +970,20 @@ static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint3
*SecureFlashStartAddr = ((user_config * FLASH_PAGE_SIZE) + FLASH_BASE);
/* Get Secure SRAM2a start address */
+#if defined(FLASH_SRRVR_SBRSA_A)
+ user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA_A) >> FLASH_SRRVR_SBRSA_A_Pos);
+#else
user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA) >> FLASH_SRRVR_SBRSA_Pos);
+#endif
*SecureRAM2aStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2A_BASE);
/* Get Secure SRAM2b start address */
+#if defined(FLASH_SRRVR_SBRSA_B)
+ user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA_B) >> FLASH_SRRVR_SBRSA_B_Pos);
+#else
user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SNBRSA) >> FLASH_SRRVR_SNBRSA_Pos);
+#endif
*SecureRAM2bStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2B_BASE);
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
index 9f0e2ce88f..6e9af79aec 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_i2c.c
@@ -93,7 +93,7 @@
[..]
(+) A specific option field manage the different steps of a sequential transfer
(+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
- (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition
(++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
@@ -112,7 +112,7 @@
or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
- Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+ Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
without stopping the communication and so generate a restart condition.
(++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
interface.
@@ -122,7 +122,7 @@
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
- (+) Differents sequential I2C interfaces are listed below:
+ (+) Different sequential I2C interfaces are listed below:
(++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
(+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
@@ -4835,7 +4835,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
- /* Check if all Datas have already been sent */
+ /* Check if all data have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
if (hi2c->XferCount > 0U)
{
@@ -5719,7 +5719,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
}
else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
- /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
+ /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
I2C_ITSlaveSeqCplt(hi2c);
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
@@ -5856,7 +5856,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
- /* If state is an abort treatment on goind, don't change state */
+ /* If state is an abort treatment on going, don't change state */
/* This change will be do later */
if (hi2c->State != HAL_I2C_STATE_ABORT)
{
@@ -6570,7 +6570,7 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
}
/**
- * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
* @param hi2c I2C handle.
* @retval None
*/
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
index af8a039fd4..d91020508b 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr.c
@@ -127,11 +127,13 @@ void HAL_PWR_DeInit(void)
/* Clear all flags */
LL_PWR_WriteReg(SCR,
- LL_PWR_SCR_CC2HF
- | LL_PWR_SCR_C802AF
+ LL_PWR_SCR_CC2HF
| LL_PWR_SCR_CBLEAF
| LL_PWR_SCR_CCRPEF
+#if defined(PWR_CR3_E802A)
+ | LL_PWR_SCR_C802AF
| LL_PWR_SCR_C802WUF
+#endif
| LL_PWR_SCR_CBLEWUF
#if defined(PWR_CR5_SMPSEN)
| LL_PWR_SCR_CBORHF
@@ -222,8 +224,9 @@ void HAL_PWR_DisableBkUpAccess(void)
(+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
(+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
- (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
- (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
+ (+) Standby mode with SRAM2a: all clocks are stopped except LSI and LSE, SRAM2a content preserved, main regulator off, low power regulator on.
+ Note: On devices STM32WB15xx, STM32WB10xx, retention is extended to SRAM1, SRAM2a, SRAM2b.
+ (+) Standby mode without SRAM2a: all clocks are stopped except LSI and LSE, main and low power regulators off.
(+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
@@ -266,6 +269,7 @@ void HAL_PWR_DisableBkUpAccess(void)
The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
(++) HAL_PWREx_EnterSTOP0Mode() for mode 0, HAL_PWREx_EnterSTOP1Mode() for mode 1, HAL_PWREx_EnterSTOP2Mode() for mode 2
or for porting reasons HAL_PWR_EnterSTOPMode().
+ Note: Low power Stop2 mode is not available on devices STM32WB15xx, STM32WB10xx.
(+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
(++) PWR_MAINREGULATOR_ON: Regulator in main mode (STOP0 mode)
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
index 3b394c622f..6b17ea78d2 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_pwr_ex.c
@@ -281,7 +281,7 @@ void HAL_PWREx_DisableBLEActivityIT(void)
CLEAR_BIT(PWR->CR3, PWR_CR3_EBLEA);
}
-
+#if defined(PWR_CR3_E802A)
/**
* @brief Enable 802.15.4 Activity interrupt.
* @retval None
@@ -299,6 +299,7 @@ void HAL_PWREx_Disable802ActivityIT(void)
{
CLEAR_BIT(PWR->CR3, PWR_CR3_E802A);
}
+#endif
/**
* @brief Enable CPU2 on-Hold interrupt.
@@ -640,9 +641,11 @@ void HAL_PWREx_ReleaseCore(uint32_t CPU)
/****************************************************************************/
/**
- * @brief Enable BKRAM content retention in Standby mode.
- * @note When RRS bit is set, SRAM is powered by the low-power regulator in
+ * @brief Enable SRAM2a content retention in Standby mode.
+ * @note When RRS bit is set, SRAM2a is powered by the low-power regulator in
* Standby mode and its content is kept.
+ * @note On devices STM32WB15xx, STM32WB10xx, retention is extended
+ * to SRAM1, SRAM2a and SRAM2b.
* @retval None
*/
void HAL_PWREx_EnableSRAMRetention(void)
@@ -651,9 +654,11 @@ void HAL_PWREx_EnableSRAMRetention(void)
}
/**
- * @brief Disable BKRAM content retention in Standby mode.
- * @note When RRS bit is reset, SRAM is powered off in Standby mode
+ * @brief Disable SRAM2a content retention in Standby mode.
+ * @note When RRS bit is reset, SRAM2a is powered off in Standby mode
* and its content is lost.
+ * @note On devices STM32WB15xx, STM32WB10xx, retention is extended
+ * to SRAM1, SRAM2a and SRAM2b.
* @retval None
*/
void HAL_PWREx_DisableSRAMRetention(void)
@@ -678,7 +683,7 @@ void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode)
if((PowerMode & PWR_FLASHPD_LPRUN) != 0U)
{
/* Unlock bit FPDR */
- WRITE_REG(PWR->CR1, 0x0000C1B0U);
+ WRITE_REG(PWR->CR1, 0x0000C1B0UL);
}
/* Set flash power down mode */
@@ -910,7 +915,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigSMPS(PWR_SMPSTypeDef *sConfigSMPS)
*
* (1) SMPS operating mode step down or open depends on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop,
- * - open mode if system low power mode is stop1, stop2, standby or shutdown
+ * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
* @retval None
*/
void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode)
@@ -924,7 +929,7 @@ void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode)
* requested operating mode can differ from effective low power mode.
* - dependency on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop,
- * - open mode if system low power mode is stop1, stop2, standby or shutdown
+ * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
* - dependency on BOR level:
* - bypass mode if supply voltage drops below BOR level
* @note This functions check flags of SMPS operating modes step down
@@ -936,7 +941,7 @@ void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode)
*
* (1) SMPS operating mode step down or open depends on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop,
- * - open mode if system low power mode is stop1, stop2, standby or shutdown
+ * - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
*/
uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void)
{
@@ -1129,7 +1134,6 @@ void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
-
/**
* @brief Enter Stop 1 mode.
* @note In Stop 1 mode, only low power voltage regulator is ON.
@@ -1182,7 +1186,7 @@ void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
-
+#if defined(PWR_SUPPORT_STOP2)
/**
* @brief Enter Stop 2 mode.
* @note In Stop 2 mode, only low power voltage regulator is ON.
@@ -1244,10 +1248,7 @@ void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
/* Reset SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
-
-
-
-
+#endif
/**
* @brief Enter Shutdown mode.
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
index c81b9d680d..518c25589f 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
@@ -320,11 +320,6 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_HSEON | RCC_CR_HSEPRE | RCC_CR_PLLON);
#endif
-#if defined(RCC_CR_HSEBYP)
- /* Reset HSEBYP bit once HSE is OFF */
- LL_RCC_HSE_DisableBypass();
-#endif
-
/* Get Start Tick*/
tickstart = HAL_GetTick();
@@ -454,7 +449,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Update the SystemCoreClock global variable */
- SystemCoreClockUpdate();
+ SystemCoreClock = HAL_RCC_GetHCLKFreq();
+
if (HAL_InitTick(uwTickPrio) != HAL_OK)
{
return HAL_ERROR;
@@ -822,6 +818,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
+#if defined(RCC_HSI48_SUPPORT)
/*------------------------------ HSI48 Configuration -----------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
{
@@ -864,6 +861,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
}
+#endif
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
@@ -1261,7 +1259,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
/*---------------------------------------------------------------------------*/
/* Update the SystemCoreClock global variable */
- SystemCoreClockUpdate();
+ SystemCoreClock = HAL_RCC_GetHCLKFreq();
+
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(HAL_GetTickPrio());
}
@@ -1530,25 +1529,17 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Set all possible values for the Oscillator type parameter ---------------*/
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
- RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSI2 | RCC_OSCILLATORTYPE_HSI48;
+ RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSI2;
+#if defined(RCC_HSI48_SUPPORT)
+ RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
+#endif
/* Get the HSE configuration -----------------------------------------------*/
-#if defined(RCC_CR_HSEBYP)
- if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
- }
- else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_ON;
- }
-#else
if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
{
RCC_OscInitStruct->HSEState = RCC_HSE_ON;
}
-#endif
else
{
RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
@@ -1604,6 +1595,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
}
+#if defined(RCC_HSI48_SUPPORT)
/* Get the HSI48 configuration ---------------------------------------------*/
if ((RCC->CRRCR & RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
{
@@ -1613,7 +1605,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
}
-
+#endif
/* Get the PLL configuration -----------------------------------------------*/
if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
index b6cc1592b5..28be15c52e 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
@@ -139,7 +139,6 @@ static uint32_t RCC_PLLSAI1_GetFreqDomain_Q(void);
* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
* @arg @ref RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock
* @arg @ref RCC_PERIPHCLK_SMPS SMPS peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
*
*
* @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select
@@ -429,23 +428,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
#endif
-#if defined(SPI_I2S_SUPPORT)
- /*-------------------- I2S clock source configuration ----------------------*/
- if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
- {
- /* Check the parameters */
- assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
-
- /* Configure the I2S clock source */
- __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
-
- if (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
- {
- /* Enable RCC_PLL_I2SCLK output */
- __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_I2SCLK);
- }
- }
-#endif
return status;
}
@@ -456,7 +438,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* returns the configuration information for the Extended Peripherals
* clocks(SAI1, LPTIM1, LPTIM2, I2C1, I2C3, LPUART1,
- * USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS, I2S).
+ * USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS).
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
@@ -487,9 +469,6 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SMPS;
#endif
-#if defined(SPI_I2S_SUPPORT)
- PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S;
-#endif
#if defined(SAI1)
/* Get the PLLSAI1 Clock configuration -----------------------------------------------*/
@@ -551,10 +530,6 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
PeriphClkInit->SmpsClockSelection = __HAL_RCC_GET_SMPS_SOURCE();
#endif
-#if defined(SPI_I2S_SUPPORT)
- /* Get the I2S clock source -----------------------------------------------*/
- PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
-#endif
}
/**
@@ -575,7 +550,6 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
* @arg @ref RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock
* @arg @ref RCC_PERIPHCLK_SMPS SMPS peripheral clock
- * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
* @retval Frequency in Hz
*/
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
@@ -724,6 +698,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
else /* HSI48 clock divided by 3 used as RNG clock source */
{
+#if defined(RCC_HSI48_SUPPORT)
if (LL_RCC_HSI48_IsReady() == 1U)
{
frequency = HSI48_VALUE / 3U;
@@ -732,6 +707,9 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
/* Nothing to do as frequency already initialized to 0U */
}
+#else
+ /* Nothing to do as frequency already initialized to 0U */
+#endif
}
}
#if defined(USB)
@@ -1050,19 +1028,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Nothing to do as frequency already initialized to 0U */
}
}
- else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_LSI) /* LSI clock used as RF Wakeup clock source */
- {
- const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady();
- const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady();
- if ((temp_lsi1ready == 1U) || (temp_lsi2ready == 1U))
- {
- frequency = LSI_VALUE;
- }
- else
- {
- /* Nothing to do as frequency already initialized to 0U */
- }
- }
else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024) /* HSE clock used as RF Wakeup clock source */
{
frequency = HSE_VALUE / 1024U;
@@ -1127,32 +1092,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Nothing to do as frequency already initialized to 0U */
}
}
-#endif
-#if defined(SPI_I2S_SUPPORT)
- if (PeriphClk == RCC_PERIPHCLK_I2S)
- {
- switch (LL_RCC_GetI2SClockSource(LL_RCC_I2S_CLKSOURCE))
- {
- case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S Clock is External clock */
- frequency = EXTERNAL_CLOCK_VALUE;
- break;
-
- case LL_RCC_I2S_CLKSOURCE_HSI: /* I2S Clock is HSI Osc. */
- if (LL_RCC_HSI_IsReady() == 1U)
- {
- frequency = HSI_VALUE;
- }
- break;
-
- case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S Clock is PLL */
- frequency = RCC_PLL_GetFreqDomain_P();
- break;
-
- case LL_RCC_I2S_CLKSOURCE_NONE: /* No clock used as I2S clock source */
- default:
- break;
- }
- }
#endif
return (frequency);
}
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c
index c5a24db3a5..9d336dd6ce 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_smbus.c
@@ -1854,7 +1854,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- /* REenable the selected SMBUS peripheral */
+ /* Re-enable the selected SMBUS peripheral */
__HAL_SMBUS_ENABLE(hsmbus);
/* Call the corresponding callback to inform upper layer of End of Transfer */
@@ -2616,7 +2616,7 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre
}
/**
- * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @brief Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.
* @param hsmbus SMBUS handle.
* @retval None
*/
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
index 8059359ab4..df70fd7377 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim.c
@@ -571,6 +571,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1087,6 +1088,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1107,6 +1109,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1127,6 +1130,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -1146,6 +1150,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -1723,6 +1728,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -1743,6 +1749,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -1762,6 +1769,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Capture/Compare 3 request */
@@ -1781,6 +1789,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -2076,7 +2085,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2158,7 +2167,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2310,12 +2319,12 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/* Set the TIM channel state */
if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
{
@@ -2346,6 +2355,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 1 DMA request */
@@ -2365,6 +2375,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -2384,6 +2395,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -2403,6 +2415,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 4 DMA request */
@@ -2452,6 +2465,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -2490,9 +2506,6 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
break;
}
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -2704,9 +2717,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2802,9 +2815,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3139,7 +3152,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
if (Channel == TIM_CHANNEL_1)
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3152,7 +3165,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
else if (Channel == TIM_CHANNEL_2)
{
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3165,9 +3178,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
else
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3293,7 +3306,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha
if (Channel == TIM_CHANNEL_1)
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3306,7 +3319,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha
else if (Channel == TIM_CHANNEL_2)
{
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3319,9 +3332,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha
else
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -3459,12 +3472,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
if (Channel == TIM_CHANNEL_1)
{
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData1 == NULL) && (Length > 0U))
{
@@ -3484,12 +3497,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
else if (Channel == TIM_CHANNEL_2)
{
if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData2 == NULL) && (Length > 0U))
{
@@ -3509,16 +3522,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
else
{
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
+ || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
+ && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
{
@@ -3552,6 +3565,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Input Capture DMA request */
@@ -3576,6 +3590,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Input Capture DMA request */
@@ -3601,6 +3616,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
@@ -3614,6 +3630,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the Peripheral */
@@ -4419,8 +4436,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @arg TIM_DMABASE_CCMR3
* @arg TIM_DMABASE_CCR5
* @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_AF1
- * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -4436,14 +4453,68 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer, uint32_t BurstLength)
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_OR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
{
@@ -4476,8 +4547,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4493,8 +4566,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4510,8 +4584,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4527,8 +4602,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4544,8 +4620,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4561,8 +4638,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4578,8 +4656,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4587,9 +4666,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
default:
break;
}
- /* configure the DMA Burst Mode */
- htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
@@ -4605,7 +4684,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
- HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
@@ -4614,54 +4692,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
{
case TIM_DMA_UPDATE:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
break;
}
case TIM_DMA_CC1:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
break;
}
case TIM_DMA_CC2:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
break;
}
case TIM_DMA_CC3:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
break;
}
case TIM_DMA_CC4:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
break;
}
case TIM_DMA_COM:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
break;
}
case TIM_DMA_TRIGGER:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
break;
}
default:
break;
}
- if (HAL_OK == status)
- {
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
- }
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
/* Change the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
/* Return function status */
- return status;
+ return HAL_OK;
}
/**
@@ -4691,8 +4766,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
* @arg TIM_DMABASE_CCMR3
* @arg TIM_DMABASE_CCR5
* @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_AF1
- * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -4710,12 +4785,66 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_OR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
{
@@ -4748,8 +4877,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4764,15 +4895,17 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
}
case TIM_DMA_CC2:
{
- /* Set the DMA capture/compare callbacks */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
@@ -4780,8 +4913,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4796,8 +4931,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4812,8 +4949,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4828,8 +4967,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4844,8 +4985,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
break;
@@ -4854,14 +4997,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
break;
}
- /* configure the DMA Burst Mode */
+ /* Configure the DMA Burst Mode */
htim->Instance->DCR = (BurstBaseAddress | BurstLength);
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- htim->State = HAL_TIM_STATE_READY;
-
/* Return function status */
return HAL_OK;
}
@@ -4874,7 +5015,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
- HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
@@ -4883,54 +5023,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu
{
case TIM_DMA_UPDATE:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
break;
}
case TIM_DMA_CC1:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
break;
}
case TIM_DMA_CC2:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
break;
}
case TIM_DMA_CC3:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
break;
}
case TIM_DMA_CC4:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
break;
}
case TIM_DMA_COM:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
break;
}
case TIM_DMA_TRIGGER:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
break;
}
default:
break;
}
- if (HAL_OK == status)
- {
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
- }
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
/* Change the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
/* Return function status */
- return status;
+ return HAL_OK;
}
/**
@@ -5286,13 +5423,13 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
case TIM_CLOCKSOURCE_ITR1:
case TIM_CLOCKSOURCE_ITR2:
case TIM_CLOCKSOURCE_ITR3:
- {
- /* Check whether or not the timer instance supports internal trigger input */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+ {
+ /* Check whether or not the timer instance supports internal trigger input */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- break;
- }
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ break;
+ }
default:
break;
@@ -6340,7 +6477,7 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma)
* @param hdma pointer to DMA handle.
* @retval None
*/
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
@@ -6660,7 +6797,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
/**
* @brief Timer Output Compare 1 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6735,7 +6872,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/**
* @brief Timer Output Compare 2 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6811,7 +6948,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/**
* @brief Timer Output Compare 3 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6885,7 +7022,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/**
* @brief Timer Output Compare 4 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6945,7 +7082,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/**
* @brief Timer Output Compare 5 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
@@ -6998,7 +7135,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
/**
* @brief Timer Output Compare 6 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
@@ -7102,7 +7239,7 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
- if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+ if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
{
return HAL_ERROR;
}
@@ -7154,11 +7291,11 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
case TIM_TS_ITR1:
case TIM_TS_ITR2:
case TIM_TS_ITR3:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- break;
- }
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ break;
+ }
default:
break;
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
index e6fb6b2091..1343a822e2 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_tim_ex.c
@@ -352,9 +352,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -432,9 +432,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -518,12 +518,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
/* Set the TIM channel state */
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
- ||(complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
+ || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
- && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
+ && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
{
@@ -553,6 +553,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
/* Enable the DMA channel for Capture 1*/
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the capture compare 1 Interrupt */
@@ -918,6 +919,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -937,6 +939,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -956,6 +959,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@@ -1372,6 +1376,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 1 DMA request */
@@ -1391,6 +1396,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@@ -1410,6 +1416,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
+ /* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@@ -1550,7 +1557,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
/* Check the TIM channels state */
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -1626,7 +1633,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
/* Check the TIM channels state */
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
- || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
+ || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@@ -2662,7 +2669,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
* @param hdma pointer to DMA handle.
* @retval None
*/
-void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
+static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart.c
index e6c7363dad..9b0ded6d71 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart.c
@@ -49,7 +49,7 @@
by calling the customized HAL_USART_MspInit(&husart) API.
[..]
- (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
+ (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to USART API's
HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
@@ -529,9 +529,9 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US
}
/**
- * @brief Unregister an UART Callback
- * UART callaback is redirected to the weak predefined callback
- * @param husart uart handle
+ * @brief Unregister an USART Callback
+ * USART callaback is redirected to the weak predefined callback
+ * @param husart usart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
@@ -732,7 +732,7 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
/**
* @brief Simplex send an amount of data in blocking mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@@ -830,7 +830,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
/**
* @brief Receive an amount of data in blocking mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@@ -942,7 +942,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
/**
* @brief Full-Duplex Send and Receive an amount of data in blocking mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
@@ -1091,7 +1091,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
/**
* @brief Send an amount of data in interrupt mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@@ -1175,7 +1175,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
/**
* @brief Receive an amount of data in interrupt mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@@ -1279,7 +1279,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
/**
* @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
@@ -1377,7 +1377,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
/**
* @brief Send an amount of data in DMA mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@@ -1463,7 +1463,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
* @note When the USART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
* @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@@ -1580,7 +1580,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart_ex.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart_ex.c
index 62186773f2..af2c15bdfd 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart_ex.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_usart_ex.c
@@ -57,10 +57,10 @@
/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
* @{
*/
-/* UART RX FIFO depth */
+/* USART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
-/* UART TX FIFO depth */
+/* USART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
/**
* @}
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c
index e70227cb96..87874df7fe 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_wwdg.c
@@ -21,6 +21,13 @@
before the counter has reached the refresh window value. This
implies that the counter must be refreshed in a limited window.
(+) Once enabled the WWDG cannot be disabled except by a system reset.
+ (+) If required by application, an Early Wakeup Interrupt can be triggered
+ in order to be warned before WWDG expiration. The Early Wakeup Interrupt
+ (EWI) can be used if specific safety operations or data logging must
+ be performed before the actual reset is generated. When the downcounter
+ reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
+ line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
+ disabled except by a system reset.
(+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
reset occurs.
(+) The WWDG counter input clock is derived from the APB clock divided
@@ -34,7 +41,8 @@
(+) Typical values:
(++) Counter min (T[5;0] = 0x00) at 64 MHz (PCLK1) with zero prescaler:
max timeout before reset: approximately 64us
- (++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler dividing by 128:
+ (++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler
+ dividing by 128:
max timeout before reset: approximately 524.28ms
##### How to use this driver #####
@@ -45,16 +53,16 @@
[..]
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
- (+) Set the WWDG prescaler, refresh window and counter value
- using HAL_WWDG_Init() function.
- (+) Start the WWDG using HAL_WWDG_Start() function.
- When the WWDG is enabled the counter value should be configured to
- a value greater than 0x40 to prevent generating an immediate reset.
- (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
- generated when the counter reaches 0x40, and then start the WWDG using
- HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
- add his own code by customization of callback HAL_WWDG_WakeupCallback.
- Once enabled, EWI interrupt cannot be disabled except by a system reset.
+ (+) Configure the WWDG prescaler, refresh window value, counter value and early
+ interrupt status using HAL_WWDG_Init() function. This will automatically
+ enable WWDG and start its downcounter. Time reference can be taken from
+ function exit. Care must be taken to provide a counter value
+ greater than 0x40 to prevent generation of immediate reset.
+ (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
+ generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
+ triggered by the interrupt service routine, flag will be automatically
+ cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
+ can add his own code by customization of callback HAL_WWDG_WakeupCallback.
(+) Then the application program must refresh the WWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_WWDG_Refresh() function. This operation must occur only when
@@ -64,7 +72,7 @@
=============================
[..]
- The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
+ The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
the user to configure dynamically the driver callbacks. Use Functions
HAL_WWDG_RegisterCallback() to register a user callback.
@@ -96,7 +104,7 @@
*** WWDG HAL driver macros list ***
===================================
[..]
- Below the list of most used macros in WWDG HAL driver.
+ Below the list of available macros in WWDG HAL driver.
(+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
(+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
(+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
@@ -197,7 +205,7 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
#else
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/* Set WWDG Counter */
WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
@@ -242,7 +250,8 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
* @param pCallback pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
+ pWWDG_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -303,7 +312,7 @@ HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWD
return status;
}
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
@@ -371,7 +380,7 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
#else
/* Early Wakeup callback */
HAL_WWDG_EarlyWakeupCallback(hwwdg);
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
}
}
}
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
index 2aa46eef4f..f79f745036 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_adc.c
@@ -67,6 +67,12 @@
#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles */
+/* after the channel configuration has been changed. */
+/* Driver timeout is approximated to 6 CPU cycles. */
+#define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
+#endif
/**
* @}
@@ -80,6 +86,22 @@
/* Check of parameters for configuration of ADC hierarchical scope: */
/* common to several ADC instances. */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
+ ( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
+ )
+#else
#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
@@ -97,9 +119,19 @@
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
)
+#endif
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC instance. */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_LL_ADC_CLOCK(__CLOCK__) \
+ ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
+ )
+
+#endif
#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
@@ -112,13 +144,32 @@
|| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
)
+#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
|| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
+ || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
+ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
)
-
+#else
+#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
+ ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
+ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
+ )
+#endif
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group regular */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ )
+#else
#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
@@ -130,6 +181,7 @@
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
)
+#endif
#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
@@ -147,6 +199,25 @@
|| ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
)
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
+ ( ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
+ || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
+ )
+#endif
+
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
+ ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
+ )
+#else
#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
@@ -165,7 +236,13 @@
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
)
-
+#endif
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
+ ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
+ )
+#else
#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
@@ -177,7 +254,7 @@
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
)
-
+#endif
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group injected */
#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
@@ -245,11 +322,19 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
/* Check the parameters */
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Force reset of ADC clock (core clock) */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
+
+ /* Release reset of ADC clock (core clock) */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
+#else
/* Force reset of ADC clock (core clock) */
LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
/* Release reset of ADC clock (core clock) */
LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC);
+#endif /* ADC_SUPPORT_2_5_MSPS */
return SUCCESS;
}
@@ -342,7 +427,11 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
/* Set ADC_CommonInitStruct fields to default values */
/* Set fields of ADC common */
/* (all ADC instances belonging to the same ADC common instance) */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
+#else
ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
@@ -387,6 +476,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
}
}
+#if !defined (ADC_SUPPORT_2_5_MSPS)
/* Set ADC group injected trigger source to SW start to ensure to not */
/* have an external trigger event occurring during the conversion stop */
/* ADC disable process. */
@@ -414,12 +504,28 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
break;
}
}
+#else
+ /* Wait for ADC conversions are effectively stopped */
+ timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
+ while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
+ {
+ timeout_cpu_cycles--;
+ if(timeout_cpu_cycles == 0UL)
+ {
+ /* Time-out error */
+ status = ERROR;
+ break;
+ }
+ }
+#endif /* ADC_SUPPORT_2_5_MSPS */
+#if !defined (ADC_SUPPORT_2_5_MSPS)
/* Flush group injected contexts queue (register JSQR): */
/* Note: Bit JQM must be set to empty the contexts queue (otherwise */
/* contexts queue is maintained with the last active context). */
LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
+#endif
/* Disable the ADC instance */
LL_ADC_Disable(ADCx);
@@ -438,11 +544,19 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
}
/* Check whether ADC state is compliant with expected state */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if (READ_BIT(ADCx->CR,
+ (ADC_CR_ADSTP | ADC_CR_ADSTART
+ | ADC_CR_ADDIS | ADC_CR_ADEN )
+ )
+ == 0UL)
+#else
if (READ_BIT(ADCx->CR,
(ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
| ADC_CR_ADDIS | ADC_CR_ADEN)
)
== 0UL)
+#endif
{
/* ========== Reset ADC registers ========== */
/* Reset register IER */
@@ -452,12 +566,17 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
| LL_ADC_IT_EOS
| LL_ADC_IT_OVR
| LL_ADC_IT_EOSMP
+#if !defined (ADC_SUPPORT_2_5_MSPS)
| LL_ADC_IT_JEOC
| LL_ADC_IT_JEOS
| LL_ADC_IT_JQOVF
+#endif
| LL_ADC_IT_AWD1
| LL_ADC_IT_AWD2
| LL_ADC_IT_AWD3
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ | LL_ADC_IT_CCRDY
+#endif
)
);
@@ -468,15 +587,26 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
| LL_ADC_FLAG_EOS
| LL_ADC_FLAG_OVR
| LL_ADC_FLAG_EOSMP
+#if !defined (ADC_SUPPORT_2_5_MSPS)
| LL_ADC_FLAG_JEOC
| LL_ADC_FLAG_JEOS
| LL_ADC_FLAG_JQOVF
+#endif
| LL_ADC_FLAG_AWD1
| LL_ADC_FLAG_AWD2
| LL_ADC_FLAG_AWD3
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ | LL_ADC_FLAG_CCRDY
+#endif
)
);
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Reset register CR */
+ /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
+ /* "read-set": no direct reset applicable. */
+ CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
+#else
/* Reset register CR */
/* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
/* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
@@ -489,7 +619,66 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
/* already done above. */
CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
+#endif
+
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ /* Reset register CFGR1 */
+ CLEAR_BIT(ADCx->CFGR1,
+ ( ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
+ | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
+ | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
+ | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN )
+ );
+ /* Reset register SMPR */
+ CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
+
+ /* Reset register TR1 */
+ MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
+
+ /* Reset register CHSELR */
+ CLEAR_BIT(ADCx->CHSELR,
+ ( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
+ | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
+ | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
+ | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
+ | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
+ );
+
+ /* Wait for ADC channel configuration ready */
+ timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
+ while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
+ {
+ timeout_cpu_cycles--;
+ if(timeout_cpu_cycles == 0UL)
+ {
+ /* Time-out error */
+ status = ERROR;
+ break;
+ }
+ }
+
+ /* Clear flag ADC channel configuration ready */
+ LL_ADC_ClearFlag_CCRDY(ADCx);
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable */
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
+
+ /* Reset register CFGR2 */
+ /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
+ /* already done above. */
+ /* Note: Register reset last due to selection of asynchronous clock, */
+ /* ADC clock then depends of configuration clock source at system */
+ /* level. */
+ CLEAR_BIT(ADCx->CFGR2,
+ ( ADC_CFGR2_CKMODE
+ | ADC_CFGR2_LFTRIG )
+ );
+
+#else
/* Reset register CFGR */
MODIFY_REG(ADCx->CFGR,
(ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
@@ -507,6 +696,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
| ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
);
+
/* Reset register SMPR1 */
CLEAR_BIT(ADCx->SMPR1,
(ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
@@ -585,6 +775,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
/* Reset register CALFACT */
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+#endif
}
else
{
@@ -640,6 +831,9 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
+#endif
assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
@@ -653,6 +847,24 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
/* - Set ADC data resolution */
/* - Set ADC conversion data alignment */
/* - Set ADC low power mode */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ MODIFY_REG(ADCx->CFGR1,
+ ADC_CFGR1_RES
+ | ADC_CFGR1_ALIGN
+ | ADC_CFGR1_WAIT
+ | ADC_CFGR1_AUTOFF
+ ,
+ ADC_InitStruct->Resolution
+ | ADC_InitStruct->DataAlignment
+ | ADC_InitStruct->LowPowerMode
+ );
+
+ MODIFY_REG(ADCx->CFGR2,
+ ADC_CFGR2_CKMODE
+ ,
+ ADC_InitStruct->Clock
+ );
+#else
MODIFY_REG(ADCx->CFGR,
ADC_CFGR_RES
| ADC_CFGR_ALIGN
@@ -662,7 +874,7 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
| ADC_InitStruct->DataAlignment
| ADC_InitStruct->LowPowerMode
);
-
+#endif
}
else
{
@@ -682,6 +894,9 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
{
/* Set ADC_InitStruct fields to default values */
/* Set fields of ADC instance */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+#endif
ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
@@ -706,6 +921,9 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
+ * @note On devices STM32WB10xx, STM32WB15xx: Before using this function,
+ * ADC group regular sequencer must be configured: refer to function
+ * @ref LL_ADC_REG_SetSequencerConfigurable().
* @note After using this function, other features must be configured
* using LL unitary functions.
* The minimum configuration remaining to be done is:
@@ -727,11 +945,34 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
+ {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
+ }
+ if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
+ || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ )
+ {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+
+ /* ADC group regular continuous mode and discontinuous mode */
+ /* can not be enabled simultenaeously */
+ assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+ || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
+ }
+#else
assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+
+ /* ADC group regular continuous mode and discontinuous mode */
+ /* can not be enabled simultenaeously */
+ assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+ || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
}
+#endif
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
@@ -751,6 +992,52 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
/* - Set ADC group regular overrun behavior */
/* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if( (LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
+ || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ )
+ {
+ /* Case of sequencer mode fixed
+ or sequencer length >= 2 ranks with sequencer mode fully configurable:
+ discontinuous mode configured */
+ MODIFY_REG(ADCx->CFGR1,
+ ADC_CFGR1_EXTSEL
+ | ADC_CFGR1_EXTEN
+ | ADC_CFGR1_DISCEN
+ | ADC_CFGR1_CONT
+ | ADC_CFGR1_DMAEN
+ | ADC_CFGR1_DMACFG
+ | ADC_CFGR1_OVRMOD
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | ADC_REG_InitStruct->SequencerDiscont
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DMATransfer
+ | ADC_REG_InitStruct->Overrun
+ );
+ }
+ else
+ {
+ /* Case of sequencer mode fully configurable
+ and sequencer length 1 rank (sequencer disabled):
+ discontinuous mode discarded (fixed to disable) */
+ MODIFY_REG(ADCx->CFGR1,
+ ADC_CFGR1_EXTSEL
+ | ADC_CFGR1_EXTEN
+ | ADC_CFGR1_DISCEN
+ | ADC_CFGR1_CONT
+ | ADC_CFGR1_DMAEN
+ | ADC_CFGR1_DMACFG
+ | ADC_CFGR1_OVRMOD
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | LL_ADC_REG_SEQ_DISCONT_DISABLE
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DMATransfer
+ | ADC_REG_InitStruct->Overrun
+ );
+ }
+#else
if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
MODIFY_REG(ADCx->CFGR,
@@ -789,9 +1076,17 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
| ADC_REG_InitStruct->Overrun
);
}
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Set ADC group regular sequencer length and scan direction */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+ if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
+ {
+ LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
+ }
+#else
LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
+#endif
}
else
{
@@ -821,6 +1116,9 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
}
+#if defined (ADC_SUPPORT_2_5_MSPS)
+/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
+#else
/**
* @brief Initialize some features of ADC group injected.
* @note These parameters have an impact on ADC scope: ADC group injected.
@@ -847,6 +1145,12 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
* Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
+ * @note Caution if feature ADC group injected contexts queue is enabled
+ * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
+ * using successively several times this function will appear as
+ * having no effect.
+ * To set several features of ADC group injected, use
+ * function @ref LL_ADC_INJ_ConfigQueueContext().
* @param ADCx ADC instance
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
@@ -934,6 +1238,7 @@ void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
}
+#endif
/**
* @}
*/
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_comp.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_comp.c
index f5c19675d1..7495e21827 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_comp.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_comp.c
@@ -55,7 +55,7 @@
|| ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \
)
-/* Note: On this STM32 serie, comparator input plus parameters are */
+/* Note: On this STM32 series, comparator input plus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
/* compatibility with other STM32 families. */
@@ -72,7 +72,7 @@
)
#endif
-/* Note: On this STM32 serie, comparator input minus parameters are */
+/* Note: On this STM32 series, comparator input minus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
/* compatibility with other STM32 families. */
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
index d03933801c..b275ced7da 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_pwr.c
@@ -109,10 +109,12 @@ ErrorStatus LL_PWR_DeInit(void)
/* Clear all flags */
LL_PWR_WriteReg(SCR,
LL_PWR_SCR_CC2HF
- | LL_PWR_SCR_C802AF
| LL_PWR_SCR_CBLEAF
| LL_PWR_SCR_CCRPEF
+#if defined(PWR_CR3_E802A)
+ | LL_PWR_SCR_C802AF
| LL_PWR_SCR_C802WUF
+#endif
| LL_PWR_SCR_CBLEWUF
#if defined(PWR_CR5_SMPSEN)
| LL_PWR_SCR_CBORHF
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
index 23aa838de0..ee185ee234 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_rcc.c
@@ -72,9 +72,6 @@
#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
-#if defined(SPI_I2S_SUPPORT)
-#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
-#endif
/**
* @}
*/
@@ -96,9 +93,6 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);
uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
#endif
-#if defined(SPI_I2S_SUPPORT)
-uint32_t RCC_PLL_GetFreqDomain_I2S(void);
-#endif
uint32_t RCC_GetSystemClockFreq(void);
@@ -190,13 +184,17 @@ ErrorStatus LL_RCC_DeInit(void)
LL_RCC_WriteReg(CIER, 0x00000000U);
/* Clear all interrupt flags */
-#if defined(SAI1)
- vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLLSAI1RDYC | \
- RCC_CICR_CSSC | RCC_CICR_HSI48RDYC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC;
-#else
vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \
- RCC_CICR_CSSC | RCC_CICR_HSI48RDYC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC;
+ RCC_CICR_CSSC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC;
+
+#if defined(SAI1)
+ vl_mask |= RCC_CICR_PLLSAI1RDYC;
+#endif
+
+#if defined(RCC_HSI48_SUPPORT)
+ vl_mask |= RCC_CICR_HSI48RDYC;
#endif
+
LL_RCC_WriteReg(CICR, vl_mask);
/* Clear reset flags */
@@ -210,8 +208,10 @@ ErrorStatus LL_RCC_DeInit(void)
/* RF Wakeup Clock Source selection */
LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_NONE);
+#if defined(RCC_HSI48_SUPPORT)
/* HSI48 reset */
LL_RCC_HSI48_Disable();
+#endif
/* HSECR register write unlock & then reset*/
LL_RCC_WriteReg(HSECR, HSE_CONTROL_UNLOCK_KEY);
@@ -407,7 +407,8 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
* @brief Return I2Cx clock frequency
* @param I2CxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_I2C1_CLKSOURCE
- * @arg @ref LL_RCC_I2C3_CLKSOURCE
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
+ * @note (*) Value not defined for all devices
* @retval I2C clock frequency (in Hz)
* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
*/
@@ -689,6 +690,7 @@ uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource)
}
break;
+#if defined(RCC_HSI48_SUPPORT)
case LL_RCC_CLK48_CLKSOURCE_HSI48: /* HSI48 clock used as CLK48 clock source */
default:
if (LL_RCC_HSI48_IsReady() == 1U)
@@ -696,6 +698,11 @@ uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource)
clk48_frequency = HSI48_VALUE;
}
break;
+#else
+ default:
+ /* Nothing to do */
+ break;
+#endif
}
return clk48_frequency;
@@ -853,7 +860,6 @@ uint32_t LL_RCC_GetRTCClockFreq(void)
uint32_t LL_RCC_GetRFWKPClockFreq(void)
{
uint32_t rfwkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
- uint32_t temp = LL_RCC_LSI2_IsReady();
/* RTCCLK clock frequency */
switch (LL_RCC_GetRFWKPClockSource())
@@ -865,13 +871,6 @@ uint32_t LL_RCC_GetRFWKPClockFreq(void)
}
break;
- case LL_RCC_RFWKP_CLKSOURCE_LSI: /* LSI clock used as RF Wakeup clock source */
- if ((LL_RCC_LSI1_IsReady() == 1UL) || (temp == 1UL))
- {
- rfwkp_frequency = LSI_VALUE;
- }
- break;
-
case LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024: /* HSE clock used as RF Wakeup clock source */
rfwkp_frequency = HSE_VALUE / 1024U;
break;
@@ -885,46 +884,6 @@ uint32_t LL_RCC_GetRFWKPClockFreq(void)
return rfwkp_frequency;
}
-#if defined(SPI_I2S_SUPPORT)
-/**
- * @brief Return I2Sx clock frequency
- * @param I2SxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S_CLKSOURCE
- * @retval I2S clock frequency (in Hz)
- * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLLs (PLL) is not ready
- */
-uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
-{
- uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
-
- /* I2SCLK clock frequency */
- switch (LL_RCC_GetI2SClockSource(I2SxSource))
- {
- case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S2 Clock is PLL"P" */
- if (LL_RCC_PLL_IsReady() == 1U)
- {
- i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
- }
- break;
-
- case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S2 Clock is External clock */
- i2s_frequency = EXTERNAL_CLOCK_VALUE;
- break;
-
- case LL_RCC_I2S_CLKSOURCE_HSI: /* HSI clock used as I2S clock source */
- default:
- if (LL_RCC_HSI_IsReady() == 1U)
- {
- i2s_frequency = HSI_VALUE;
- }
- break;
- }
- return i2s_frequency;
-}
-#endif
/**
* @}
@@ -1363,35 +1322,6 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
}
#endif
-#if defined(SPI_I2S_SUPPORT)
-/**
- * @brief Return PLL clock frequency used for I2S domain
- * @retval PLL clock frequency (in Hz)
- */
-uint32_t RCC_PLL_GetFreqDomain_I2S(void)
-{
- uint32_t pllinputfreq, pllsource;
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
- I2S Domain clock = PLL_VCO / PLLP
- */
- pllsource = LL_RCC_PLL_GetMainSource();
-
- switch (pllsource)
- {
- case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
- pllinputfreq = HSE_VALUE;
- break;
-
- case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
- default:
- pllinputfreq = HSI_VALUE;
- break;
- }
- return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
- LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
-}
-#endif
/**
* @}
diff --git a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
index 19cbaaf7c7..d77d920e50 100644
--- a/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
+++ b/system/Drivers/STM32WBxx_HAL_Driver/Src/stm32wbxx_ll_utils.c
@@ -258,7 +258,7 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
*/
ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency)
{
- ErrorStatus status = SUCCESS;
+ ErrorStatus status = ERROR;
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
uint16_t index;
uint32_t timeout;
@@ -283,11 +283,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency)
const uint32_t UTILS_LATENCY_RANGE[] = {LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_LATENCY_3};
/* Frequency cannot be equal to 0 or greater than max clock */
- if ((HCLK4Frequency == 0U) || (HCLK4Frequency > maxfreq))
- {
- status = ERROR;
- }
- else
+ if ((HCLK4Frequency > 0U) && (HCLK4Frequency <= maxfreq))
{
#if defined(PWR_CR1_VOS)
if (voltagescaling == LL_PWR_REGU_VOLTAGE_SCALE1)
@@ -297,6 +293,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency)
if (HCLK4Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index])
{
latency = UTILS_LATENCY_RANGE[index];
+ status = SUCCESS;
break;
}
}
@@ -308,6 +305,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency)
if (HCLK4Frequency <= UTILS_CLK_SRC_RANGE_VOS2[index])
{
latency = UTILS_LATENCY_RANGE[index];
+ status = SUCCESS;
break;
}
}
@@ -318,11 +316,15 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency)
if (HCLK4Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index])
{
latency = UTILS_LATENCY_RANGE[index];
+ status = SUCCESS;
break;
}
}
#endif
+ }
+ if (status != ERROR)
+ {
LL_FLASH_SetLatency(latency);
/* Check that the new number of wait states is taken into account to access the Flash
diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md
index 115baa3d56..b40d127d91 100644
--- a/system/Drivers/STM32YYxx_HAL_Driver_version.md
+++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md
@@ -13,7 +13,7 @@
* STM32L1: 1.4.3
* STM32L4: 1.12.0
* STM32MP1: 1.3.0
- * STM32WB: 1.6.0
+ * STM32WB: 1.7.0
Release notes of each STM32YYxx HAL Drivers available here:
diff --git a/variants/MKR_SHARKY/variant.cpp b/variants/MKR_SHARKY/variant.cpp
index c8efb14b79..248efaa4f8 100644
--- a/variants/MKR_SHARKY/variant.cpp
+++ b/variants/MKR_SHARKY/variant.cpp
@@ -126,7 +126,7 @@ WEAK void SystemClock_Config(void)
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
- PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSI;
+ PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;