diff --git a/CI/utils/patch/CMSIS/MP1/0001-MP1-Review-HAL-default-configuration.patch b/CI/utils/patch/CMSIS/MP1/0001-MP1-Review-HAL-default-configuration.patch deleted file mode 100644 index 55b55b3eda..0000000000 --- a/CI/utils/patch/CMSIS/MP1/0001-MP1-Review-HAL-default-configuration.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 01b39c624995928905b99b3ce211482d27d0d1bc Mon Sep 17 00:00:00 2001 -From: Bumsik Kim -Date: Sat, 12 Oct 2019 21:50:30 +0900 -Subject: [PATCH 1/1] [MP1] Review HAL default configuration - ---- - .../Device/ST/STM32MP1xx/Include/stm32mp1xx.h | 6 +- - .../STM32MP1xx/stm32mp1xx_hal_conf_default.h | 89 ++++++++++--------- - 2 files changed, 49 insertions(+), 46 deletions(-) - -diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h -index 10395b51..528b9b91 100644 ---- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h -+++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h -@@ -197,7 +197,7 @@ typedef enum - */ - - #if defined (USE_HAL_DRIVER) -- #include "stm32mp1xx_hal_conf.h" -+ #include "stm32mp1xx_hal.h" - #endif /* USE_HAL_DRIVER */ - - --- -2.25.1.windows.1 - diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index 1eaf2203f6..35e8c1ea5b 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -381,17 +381,17 @@ #elif defined(STM32L562xx) #define CMSIS_STARTUP_FILE "startup_stm32l562xx.s" #elif defined(STM32MP151Axx) - #define CMSIS_STARTUP_FILE "startup_stm32mp151a_cm4 .s" + #define CMSIS_STARTUP_FILE "startup_stm32mp151axx_cm4 .s" #elif defined(STM32MP151Cxx) - #define CMSIS_STARTUP_FILE "startup_stm32mp151c_cm4.s" + #define CMSIS_STARTUP_FILE "startup_stm32mp151cxx_cm4.s" #elif defined(STM32MP153Axx) - #define CMSIS_STARTUP_FILE "startup_stm32mp153a_cm4.s" + #define CMSIS_STARTUP_FILE "startup_stm32mp153axx_cm4.s" #elif defined(STM32MP153Cxx) - #define CMSIS_STARTUP_FILE "startup_stm32mp153c_cm4.s" + #define CMSIS_STARTUP_FILE "startup_stm32mp153cxx_cm4.s" #elif defined(STM32MP157Axx) - #define CMSIS_STARTUP_FILE "startup_stm32mp157a_cm4.s" + #define CMSIS_STARTUP_FILE "startup_stm32mp157axx_cm4.s" #elif defined(STM32MP157Cxx) - #define CMSIS_STARTUP_FILE "startup_stm32mp157c_cm4.s" + #define CMSIS_STARTUP_FILE "startup_stm32mp157cxx_cm4.s" #elif defined(STM32MP15xx) #define CMSIS_STARTUP_FILE "startup_stm32mp15xx.s" #elif defined(STM32WB30xx) diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h index 47735188b5..146d50cb85 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h @@ -1088,14 +1088,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2414,17 +2411,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h index 2d8f9d671b..382d562606 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h @@ -1054,14 +1054,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2380,17 +2377,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h index c5b43ad73b..730a8289c9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h @@ -1088,14 +1088,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2462,17 +2459,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h index d914421590..90458f9757 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h @@ -1054,14 +1054,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2428,17 +2425,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h index fd0afa7ea2..9050f6d279 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h @@ -1088,14 +1088,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2414,17 +2411,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h index 33b5008bb0..afe9896a03 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h @@ -1054,14 +1054,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2380,17 +2377,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h index 1b914cfc74..df9d70ff4b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h @@ -1088,14 +1088,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2462,17 +2459,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h index 3386f431c6..48f2c02bfb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h @@ -1054,14 +1054,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2428,17 +2425,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h index d075c6843c..d6f22577d7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h @@ -1189,14 +1189,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2515,17 +2512,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h index 19207bc94c..02a968c72b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h @@ -1155,14 +1155,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2481,17 +2478,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h index 6450ca755a..b814061574 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h @@ -1189,14 +1189,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2563,17 +2560,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h index dd60e2bf63..d000923604 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h @@ -1155,14 +1155,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2529,17 +2526,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h index 56b82fde2a..cf69097b70 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h @@ -1189,14 +1189,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2515,17 +2512,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h index a22cc371ff..926111b554 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h @@ -1155,14 +1155,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2481,17 +2478,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h index 32d003d9cf..9635a58791 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h @@ -1189,14 +1189,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2563,17 +2560,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h index aa4aa280b4..001914847b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h @@ -1155,14 +1155,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2529,17 +2526,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h index 565822a3bd..a431da6d3d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h @@ -1276,14 +1276,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2602,17 +2599,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h index 5cde4836d6..2ebcb3fe8e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h @@ -1242,14 +1242,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2568,17 +2565,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h index 131b2f7533..5d2ef985f6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h @@ -1276,14 +1276,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2650,17 +2647,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h index 550ad156c5..2d452aa907 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h @@ -1242,14 +1242,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2616,17 +2613,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h index 61dc5a88c0..9005038b09 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h @@ -1276,14 +1276,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2602,17 +2599,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h index 031c3c7cd7..6923d1962f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h @@ -1242,14 +1242,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2568,17 +2565,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h index a998be701d..80a9966b2c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_ca7.h @@ -1276,14 +1276,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2650,17 +2647,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h index f63193b89a..166b491c5f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157fxx_cm4.h @@ -1242,14 +1242,11 @@ typedef struct __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */ - __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */ - __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */ + __IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */ - __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */ - __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */ + __IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */ - __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */ - __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */ + __IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */ @@ -2616,17 +2613,16 @@ typedef struct /** * @brief RNG */ - typedef struct { - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */ - __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ - __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */ } RNG_TypeDef; /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h index ada2cc6396..15414aebe1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h @@ -70,7 +70,7 @@ * @brief CMSIS Device version number */ #define __STM32MP1xx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32MP1xx_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ +#define __STM32MP1xx_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ #define __STM32MP1xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32MP1xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32MP1xx_CMSIS_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html index cf43d7fd4a..47f2cee4e4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html @@ -163,11 +163,11 @@

License

-

V1.3.0 / 20-oct-2020

+

V1.4.0 / 26-Feb-2021

Main changes

-
  • Header files: 
    • Rename  RCC bit definition to be more compliant with the name from RCC spec
    • Update STGEN register structure
    • Fix typo in MDMA register definition

+
  • Header files: 
    • Remove C1EMRx registers which does not exist on the silicon
    • Update RNG register structure

Contents

@@ -181,7 +181,13 @@

Contents