diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h index 07328a6abc..bff24a1bc9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h @@ -815,6 +815,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2371,6 +2379,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h index ce0bc8ff7c..c22bec9d03 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h @@ -815,6 +815,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2371,6 +2379,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h index c7abe322e3..27fc4685e6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h @@ -1045,6 +1045,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6460,6 +6468,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h index bb79c19854..aca5fb395b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h @@ -1149,6 +1149,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6760,6 +6768,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410cx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410cx.h index 1cd0c55d1f..3822e7e93c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410cx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410cx.h @@ -713,6 +713,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2450,6 +2458,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410rx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410rx.h index a85d0edbf6..78e26a2eb7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410rx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410rx.h @@ -713,6 +713,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2450,6 +2458,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410tx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410tx.h index 95e6527c61..73942356dd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410tx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410tx.h @@ -703,6 +703,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2440,6 +2448,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h index 6c6ad5fd55..6c536b9cb8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h @@ -818,6 +818,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2374,6 +2382,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412cx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412cx.h index db0deba13a..ce8a5cab17 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412cx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412cx.h @@ -1008,6 +1008,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6524,6 +6532,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412rx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412rx.h index a2ec39f353..1da909089b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412rx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412rx.h @@ -1062,6 +1062,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6578,6 +6586,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412vx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412vx.h index 07079b5ac9..285def203a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412vx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412vx.h @@ -915,8 +915,6 @@ typedef struct #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL) #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL) #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL) #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL) #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) #define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL) @@ -1066,6 +1064,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6582,6 +6588,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412zx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412zx.h index 9dbe1de2da..986ebbf112 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412zx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412zx.h @@ -1068,6 +1068,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6584,6 +6592,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f413xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f413xx.h index 11af7e71da..71abd5ecb5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f413xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f413xx.h @@ -1197,6 +1197,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6900,6 +6908,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f415xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f415xx.h index 8c2853ee4b..692e021f9a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f415xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f415xx.h @@ -1119,6 +1119,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6642,6 +6650,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f417xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f417xx.h index cc4382304b..8ae531ee3a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f417xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f417xx.h @@ -1223,6 +1223,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6939,6 +6947,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f423xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f423xx.h index cc0ae4f35d..4dda16fac8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f423xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f423xx.h @@ -1233,6 +1233,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6936,6 +6944,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f427xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f427xx.h index 222f27a484..8139954781 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f427xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f427xx.h @@ -1243,6 +1243,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -7147,6 +7155,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h index 409b8de70b..873aac6fcc 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h @@ -1299,6 +1299,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -7206,6 +7214,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f437xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f437xx.h index 1b6d1b7178..a2193b07d1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f437xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f437xx.h @@ -1321,6 +1321,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -7339,6 +7347,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f439xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f439xx.h index cbbfa6d069..58c06eea79 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f439xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f439xx.h @@ -1375,6 +1375,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -7393,6 +7401,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h index c3240c7bf9..89fed87895 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h @@ -1166,6 +1166,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6943,6 +6951,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f469xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f469xx.h index 35dd34aecb..57d7db8f33 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f469xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f469xx.h @@ -1390,6 +1390,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -10383,6 +10391,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f479xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f479xx.h index b9379bab2b..43780f93a0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f479xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f479xx.h @@ -1466,6 +1466,14 @@ typedef struct * @{ */ +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -10573,6 +10581,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h index 2f87791530..09d5f085b6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h @@ -106,16 +106,16 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS version number V2.6.6 + * @brief CMSIS version number V2.6.7 */ #define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */ #define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */ #define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32F4xx_CMSIS_VERSION)) + |(__STM32F4xx_CMSIS_VERSION_RC)) /** * @} @@ -225,6 +225,60 @@ typedef enum #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) +/* Use of CMSIS compiler intrinsics for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t val; \ + do { \ + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint16_t val; \ + do { \ + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) /** * @} diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/README.md b/system/Drivers/CMSIS/Device/ST/STM32F4xx/README.md index bc187e43f0..6a700c82d3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/README.md +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/README.md @@ -33,6 +33,7 @@ Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.0 Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.1 Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.2 Tag v2.6.6 | Tag v5.4.0_cm4 | Tag v1.26.0 +Tag v2.6.7 | Tag v5.4.0_cm4 | Tag v1.26.2 The full **STM32CubeF4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF4). diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Release_Notes.html index c5a1cc5096..0d3164f31b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Release_Notes.html @@ -1,24 +1,17 @@ - - - - - - - - - - - - - - - - -Release Notes for STM32F4xx CMSIS - - - - + Release Notes for STM32F4xx CMSIS + + - - -
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Back to Release page
-

Release -Notes for STM32F4xx CMSIS

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Copyright 2017 STMicroelectronics

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Update History

-

V2.6.6 / 12-February-2021

-       Main -Changes
 - - -
  • system_stm32f4xx.c:
    • Protect -Vector table modification following SRAM or FLASH preprocessor -directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS
    • Update SystemInit_ExtMemCtl() API to initialize the tmpreg variable before each time out loop condition.
  • Add License.md and Readme.md files required for GitHub publication
  • Improve GCC startup files robustness.
  • Fix wrong value for GPIO_MODER_MODE8_Msk and GPIO_MODER_MODE2_Pos.
  • Update max number of host channels in FS for STM32F446:
    • Update USB_OTG_FS_HOST_MAX_CHANNEL_NBR value from 8 to 12.
  • Add SMBDEN and SMBHEN bit definition for STM32F410Tx device.

V2.6.5 / 10-February-2020

-       Main -Changes
 - - -
  • All header files
    • Update to use new BSD License format
  • MDK-ARM startup files
    • Update to fix invalid config wizard annotations

V2.6.4 / 06-December-2019

-       Main -Changes
 - - -
  • stm32f446xx.h file
    • Update to support HW flow control on UART4 and UART5 instances
  • stm32f412xx.h, stm32f413xx.h and stm32f423xx.h files
    • Remove unused IS_USB_ALL_INSTANCE() assert macro
  • All header files
    • Remove unused IS_TIM_SYNCHRO_INSTANCE() assert macro
  • system_stm32f4xx.c file
    • Update SystemInit() API to don't reset RCC registers to its reset values

V2.6.3 / 08-February-2019

-       Main -Changes
 - - -
    -
  • CRYP:
    • -
      -
    • Update CMSIS devices with correct CRYP data input register name: DIN instead of DR
      • -
    • Add Bits definition for CRYP CR ALGOMODE AES GCM/CCM
      • -
    -
  • HASH:
    • -
      -
    • Update HASH_DIGEST_TypeDef structure: resize the HR register
      -
    • Remove MDMAT Bits definition
      • -
    -
  • TIM:
    • -
      -
    • Add requires TIM assert macros:
      • -
        -
      • IS_TIM_SYNCHRO_INSTANCE()
        • -
      • IS_TIM_CLOCKSOURCE_TIX_INSTANCE()
        • -
      • IS_TIM_CLOCKSOURCE_ITRX_INSTANCE()
        • -
      -
    -
  • RCC
    • -
      -
    • Add RCC_CSR_BORRSTF bits definition
      • -
    -
  • GPIO
    -
    • -
      -
    • Fix GPIO BRR bits definition
      • -
    • Adjust the GPIO present on STM32F412 devices
      -
      • -
    -
  • SAI
    • -
      -
    • Fix frame length in SAI_xFRCR_FSALL & SAI_xFRCR_FRL bits description
      -
      • -
    -
  • USB:
    • -
      -
    • Add missing Bits Definitions in USB_OTG_DOEPMSK register
      • -
    -
      -
        -
      • USB_OTG_DOEPMSK_AHBERRM
        • -
      • USB_OTG_DOEPMSK_OTEPSPRM
        • -
      • USB_OTG_DOEPMSK_BERRM
        • -
      • USB_OTG_DOEPMSK_NAKM
        • -
      • USB_OTG_DOEPMSK_NYETM
        • -
      -
    -
      -
    • Add missing Bits Definitions in USB_OTG_DIEPINT register
      • -
    -
      -
        -
      • USB_OTG_DIEPINT_INEPNM
      • USB_OTG_DIEPINT_AHBERR
        • -
      • USB_OTG_DOEPINT_OUTPKTERR
        • -
      •  USB_OTG_DOEPINT_NAK
        • -
      • USB_OTG_DOEPINT_STPKTRX
        • -
      -
    • Add missing Bits Definitions in USB_OTG_DCFG register
      • -
        -
      • USB_OTG_DCFG_XCVRDLY
      • USB_OTG_DCFG_ERRATIM
        • -
      -
    -
      -
    • Update USB OTG max number of endpoints (6 FS and 9 HS instead of 5 and 8)
      • -
    -
  • I2C/FMPI2C
    • -
      -
    • Align Bit naming for FMPI2C_CR1 register: FMPI2C_CR1_DFN--> FMPI2C_CR1_DNF
      • -
    • Add IS_SMBUS_ALL_INSTANCE() define
      • -
    -
  • DFSDM
    • -
      -
    • Align Bit naming for DFSDM_FLTICR register: DFSDM_FLTICR_CLRSCSDF--> DFSDM_FLTICR_CLRSCDF
      • -
    -
  • PWR
    • -
      -
    • Remove PWR_CSR_WUPP define: feature not available on STM32F469xx/479xx devices
      • -
    -
-

V2.6.2 / 06-October-2017

-      Main -Changes
 - -
    • Remove Date and Version from all header files
    • USB_OTG register clean up: remove duplicated bits definitions
    • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
      • Remove BKPSRAM_BASE define: feature not available
    • stm32f405xx.h, stm32f407xx.h files
      • Rename HASH_RNG_IRQn to RNG_IRQn: HASH instance not available 
    • stm32f410xx.h, stm32f412xx.h, stm32f413xx.h,  stm32f423xx.h files
      • Add missing wake-up pins defines
    • stm32f412cx.h files
      •  Add support of USART3 instance

V2.6.1 / 14-February-2017

      Main -Changes
 - -
  • General updates in header files to support LL drivers
    • Align Bit naming for RCC_CSR register (ex: RCC_CSR_PADRSTF --> RCC_CSR_PINRSTF)
    • Add new defines for RCC features support:
      • RCC PLLI2S and RCC PLLSAI support
      • RCC PLLR I2S clock source and RCC PLLR system clock support
      • RCC SAI1A PLL source and RCC SAI1B PLL source support
      • RCC AHB2 support
    • Add RCC_DCKCFGR_PLLI2SDIVQ_X and  RCC_DCKCFGR_PLLSAIDIVQ_X bits definition
    • Add new defines for RCC_PLLI2SCFGR_RST_VALUE, RCC_PLLSAICFGR_RST_VALUE and RCC_PLLCFGR_RST_VALUE
    • Add new defines for RTC features support:
      • RTC Tamper 2 support
      • RTC AF2 mapping support
    • Align Bit naming for RTC_CR and RTC_TAFCR registers (ex: RTC_CR_BCK --> RTC_CR_BKP)
    • Add new define to manage RTC backup register number: RTC_BKP_NUMBER
    • Rename IS_UART_INSTANCE() macro to IS_UART_HALFDUPLEX_INSTANCE()
    • Add new defines to check LIN instance: IS_UART_LIN_INSTANCE
    • Remove USART6 instance from STM32F410Tx header file
    • Rename IS_I2S_ALL_INSTANCE_EXT() macro to IS_I2S_EXT_ALL_INSTANCEE()
    • Add IS_I2S_APB1_INSTANCE() macro to check if I2S instance mapping: API1 or APB2
    • Remove SPI_I2S_SUPPORT define for SPI I2S features support: I2S feature is available on all STM32F4xx devices
    • Add SPI_I2S_FULLDUPLEX_SUPPORT define for STM32F413xx/423xx devices
    • Align SPI_I2SCFGR bit naming: SPI_I2SCFGR_ASTRTEN bit is missing for STM32F412xx devices
    • Add new I2S_APB1_APB2_FEATURE define for STM32F4xx devices where I2S IP's are splited between RCC APB1 and APB2 interfaces
    • Add new FLASH_SR_RDERR define in FLASH_SR register
    • Add FLASH_OTP_BASE and  FLASH_OTP_END defnes to manage FLASH OPT area
    • Add bit definitions for ETH_MACDBGR register
    • Add new defines ADC1_COMMON_BASE and ADC123_COMMON_BASE to replace ADC_BASE define
    • Add new defines ADC1_COMMON and ADC123_COMMON to replace ADC define
    • Add new ADC macros: IS_ADC_COMMON_INSTANCE() and IS_ADC_MULTIMODE_MASTER_INSTANCE()
    • Add new defines for ADC multi mode features support
    • Add new ADC aliases ADC_CDR_RDATA_MST and ADC_CDR_RDATA_SLV for compatibilities with all STM32 Families
    • Update TIM CNT and ARR register mask on 32-bits
    • Add new TIM_OR_TI1_RMP define in TIM_OR register
    • Add new TIM macros to check TIM feature instance support:
      • IS_TIM_COUNTER_MODE_SELECT_INSTANCE()
      • IS_TIM_CLOCK_DIVISION_INSTANCE()
      • IS_TIM_COMMUTATION_EVENT_INSTANCE()
      • IS_TIM_OCXREF_CLEAR_INSTANCE()
      • IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE()
      • IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE()
      • IS_TIM_REPETITION_COUNTER_INSTANCE()
      • IS_TIM_ENCODER_INTERFACE_INSTANCE()
      • IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE()
      • IS_TIM_BREAK_INSTANCE()
    • CAN_IER register clean up: remove duplicated bit definitions
    • USB_OTG register: fix the wrong defined values for USB_OTG_GAHBCFG bits

V2.6.0 / 04-November-2016

      Main -Changes
 - -
  • Add support of STM32F413xx and STM32F423xx devices 
    • Add "stm32f413xx.h" and "stm32f423xx.h" files
    • -

      Add startup files  "startup_stm32f413xx.s" and "startup_stm32f423xx.s" for EWARM, MDK-ARM and SW4STM32 toolchains

    • Add Linker files "stm32f413xx_flash.icf", "stm32f413xx_sram.icf", "stm32f423xx_flash.icf" and "stm32f423xx_sram.icf" used within EWARM Workspaces
  • All header files
    • Use _Pos and _Mask macro for all Bit Definitions
    • Update LPTIM_OR Bit Definition
    • Update the defined frequencies by scale for USB exported constants
    • Add UID_BASE, FLASHSIZE_BASE and PACKAGE_BASE defines
    • Add new define DAC_CHANNEL2_SUPPORT to manage DAC channel2 support
    • Use new DAC1 naming
    • Rename PWR_CSR_UDSWRDY define to PWR_CSR_UDRDY in PWR_CSR register
    • Align Bit naming for EXTI_IMR and EXTI_EMR registers (ex: EXTI_IMR_MR0 --> EXTI_IMR_IM0)
    • Add new EXTI_IMR_IM define in EXTI_IMR register
    • Add missing DMA registers definition
    • Add macro to check SMBUS instance support
  • stm32f412cx.h, stm32f412zx.h, stm32f412vx.h, stm32f412rx.h files
    • Add missing SYSCFG register: CFGR2
  • stm32f405xx.h, stm32f407xx.h, stm32f427xx.h, stm32f429xx.h files
    • Remove HASH_RNG_IRQn in IRQn_Type enumeration
  • stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files
    • Remove I2C FLTR register as not supported
  • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files
    • Add missing Bit Definition of ETH_MACDBGR register
  • system_stm32f4xx.c file
    • Add APBPrescTable declaration

V2.5.1 / 28-June-2016

      Main -Changes
 - -
  • stm32f412rx.h, stm32f412vx.h and stm32f412zx.h files:

    • Add QSPI1_V2_1L define to manage the QSPI DMA2 limitation

V2.5.0 / 22-April-2016

      Main -Changes
 - -
  • Add support of STM32F412Cx, STM32F412Rx, STM32F412Vx and STM32F412Zx devices

    • Add "stm32f412Cx.h", "stm32f412Rx.h", "stm32f412Vx.h" and "stm32f412Zx.h" files

    • Add startup files  "startup_stm32f412cx.s", "startup_stm32f412rx.s", "startup_stm32f412vx.s" and "startup_stm32f412zx.s" for EWARM, MDK-ARM and SW4STM32 toolchains

    • Add Linker files "stm32f412cx_flash.icf", "stm32f412cx_sram.icf", "stm32f412rx_flash.icf", "stm32f412rx_sram.icf", "stm32f412vx_flash.icf", "stm32f412vx_sram.icf", "stm32f412zx_flash.icf" and "stm32f412zx_sram.icf" used within EWARM Workspaces
  • Header files for all STM32 devices
    • Remove uint32_t cast and keep only Misra Cast (U) to avoid two types cast duplication
    • Correct some bits definition to be in line with naming used in the Reference Manual
      • WWDG_CR_Tx changed to WWDG_CR_T_x
      • WWDG_CFR_Wx changed to WWDG_CFR_W_x
      • WWDG_CFR_WDGTBx changed to WWDG_CFR_WDGTB_x
  • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files
    • Correct some bits definition to be in line with naming used in the Reference Manual
      • DCMI_RISR_x changed to DCMI_RIS_x
      • DCMI_RISR_OVF_RIS changed to DCMI_RIS_OVR_RIS
      • DCMI_IER_OVF_IE changed to DCMI_IER_OVR_IE
  • stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files
    • Correct some bits definition to be in line with naming used in the Reference Manual
      • SAI_xFRCR_FSPO changed to SAI_xFRCR_FSPOL
    • Rename IS_SAI_BLOCK_PERIPH to IS_SAI_ALL_INSTANCE
  • stm32f410cx.h, stm32f410rx.h, stm32f410tx.h files and stm32f446xx.h
    • Remove FMPI2C_CR1_SWRST and FMPI2C_CR1_WUPEN Bit definition for I2C_CR1 register
  • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files
    • Add missing bits definitions for DMA2D_CR, DMA2D_FGPFCCR, DMA2D_BGPFCCR, DMA2D_OPFCCR registers
  • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
    • Add missing RCC_DCKCFGR register in RCC_TypeDef structure
    • Add missing Bit definition for RCC_DCKCFGR register
  • system_stm32f4xx.c
    • Update SystemInit_ExtMemCtl() API to fix delay optimization problem with GCC compiler: index variable is declared as volatile 
  • stm32f4xx.h
    • Rename __STM32F4xx_CMSIS_DEVICE_VERSION_xx defines to __STM32F4_CMSIS_VERSION_xx (MISRA-C 2004 rule 5.1)

V2.4.3 / 29-January-2016

      Main -Changes

  • -

    Header file for all -STM32 devices -

    -
    • Rename -ADC overrun flags definitions : ADC_CSR_DOVR1, ADC_CSR_DOVR2 and -ADC_CSR_DOVR3 are replaced respectively by ADC_CSR_OVR1, ADC_CSR_OVR2 and -ADC_CSR_OVR3 to be aligned with reference manuals
    • Add missing bits definitions for DAC : DAC_CR_DMAUDRIE1 and DAC_CR_DMAUDRIE2
    • Update CMSIS driver to be compliant with MISRA C 2004 rule 10.6
    • Remove the double definition of USB_OTG_HS_MAX_IN_ENDPOINTS and add a new one for  USB_OTG_HS_MAX_OUT_ENDPOINTS
  • stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files 
    • Change the bit definition value of QUADSPI_CR_FTHRES
  • stm32f446xx.h, stm32f469xx.h, stm32f479xx.h, stm32f429xx.h, stm32f439xx.h files
    • Rename the LTDC_GCR_DTEN to LTDC_GCR_DEN in order to be aligned with the reference manual
    • Rename DCMI_MISR bit definitions to DCMI_MIS
    • Rename DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
    • Add missing bits definitions for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, DCMI_DR registers
  • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f437xx.h files
    • Rename DCMI_MISR bit definitions to DCMI_MIS
    • Rename DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
    • Add missing bits definitions for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, DCMI_DR registers
  • stm32f410cx.h, stm32f410rx.h, stm32f410tx.h files
    • Update the LPTIM SNGSTRT defined value
  • stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files
    • Rename the DMA2D_IFSR bit definitions to DMA2D_IFCR
  • stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files 
    • Correct a wrong value of SAI_xCR2_CPL definition bit 

V2.4.2 / 13-November-2015

-

Main -Changes

  • -

    system_stm32f4xx.c file -

    -
    • update -SystemInit_ExtMemCtl() function implementation to allow the possibility -of simultaneous use of DATA_IN_ExtSRAM and DATA_IN_ExtSDRAM
  • stm32f4xx.h file
    • add symbols for STM32F411xC devices
  • stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files
    • add FSMC_BCRx_CPSIZE bits definitions
    • remove FSMC_BWTRx_CLKDIV and FSMC_BWTRx_DATLAT bits definitions
  • stm32f429xx.h, stm32f427xx.h, stm32f437xx.h files
    • add FMC_BCRx_CPSIZE bits definitions
    • remove FMC_BWTRx_CLKDIV and FMC_BWTRx_DATLAT bits definitions
  • stm32f446xx.h, stm32f469xx.h and stm32f479xx.h
    • update USB_OTG_GlobalTypeDef registers structure to remove ADP control registers
    • add USB_OTG_DOEPMSK_OTEPSPRM and USB_OTG_DOEPINT_OTEPSPR bits definitions
    • Remove ADP related bits definitions
    • add IS_PCD_ALL_INSTANCE() and IS_HCD_ALL_INSTANCE() macros

V2.4.1 / -09-October-2015

-

Main -Changes

-
  • "stm32f469xx.h", -"stm32f479xx.h" -
    • Update -bits definition for DSI_WPCR and DSI_TCCR registers

V2.4.0 / 14-August-2015

-

Main -Changes

  • -

    Add support of STM32F469xx and STM32F479xx devices
    -

    -
    • -

      Add "stm32f469xx.h" and "stm32f479xx.h" files

      -
    • -

      Add startup files  "startup_stm32f469xx.s" and "startup_stm32f479xx.s" for EWARM, MDK-ARM and SW4STM32 toolchains

    • Add Linker files "stm32f469xx_flash.icf", "stm32f469xx_sram.icf", "stm32f479xx_flash.icf" and "stm32f479xx_sram.icf" used within EWARM Workspaces
  • -

    Add support of STM32F410xx devices
    -

    -
    • -

      Add "stm32f410cx.h", "stm32f410tx.h" and "stm32f410rx.h" files

      -
    • -

      Add startup files  "startup_stm32f410cx.s", "startup_stm32f410rx.s" and "startup_stm32f410tx.s" for EWARM, MDK-ARM and SW4STM32 toolchains

    • Add Linker files "stm32f410cx_flash.icf", "stm32f410cx_sram.icf", "stm32f410rx_flash.icf", "stm32f410tx_sram.icf", "stm32f410tx_flash.icf",  and "stm32f410rx_sram.icf" used within EWARM Workspaces

V2.3.2 / 26-June-2015

-

Main -Changes

  • "stm32f405xx.h", "stm32f407xx.h", "stm32f415xx.h" and "stm32f417xx.h"
    • Update FSMC_BTRx_DATAST and FSMC_BWTRx_DATAST (where x can be 1, 2, 3 and 4) mask on 8bits instead of 4bits
  • "stm32f427xx.h", "stm32f437xx.h", "stm32f429xx.h" and "stm32f439xx.h"
    • Update the defined mask value for SAI_xSR_FLVL_2
  • "stm32f415xx.h", "stm32f417xx.h", "stm32f437xx.h" and "stm32f439xx.h"
    • HASH alignement with bits namming used in documentation
        • Rename HASH_IMR_DINIM to HASH_IMR_DINIE
        • Rename HASH_IMR_DCIM to HASH_IMR_DCIE
        • Rename HASH_STR_NBW to HASH_STR_NBW
  • system_stm32f4xx.c
    • Remove __IO on constant table declaration
    • Implement workaround to cover RCC limitation regarding peripheral enable delay
    • SystemInit_ExtMemCtl() update GPIO configuration when external SDRAM is used 

V2.3.1 / 03-April-2015

-Main -Changes -
  • -

    Header file for all -STM32 devices

    -
    • Update SRAM2, SRAM3 and BKPSRAM Bit-Banding base address defined values
    • Keep reference to SRAM3 only for STM32F42xx and STM32F43xx devices
    • Remove CCMDATARAM_BB_BASE: the CCM Data RAM region is not accessible via Bit-Banding
    • Update the RTC_PRER_PREDIV_S defined value to 0x00007FFF instead of 0x00001FFF

V2.3.0 / 02-March-2015

-

Main -Changes

-
  • -

    Add support of STM32F446xx devices
    -

    -
    • -

      Add "stm32f446xx.h" file

      -
    • -

      Add startup file "startup_stm32f446xx.s" for EWARM, MDK-ARM and TrueSTUDIO toolchains

    • Add Linker files "stm32f446xx_flash.icf" and "stm32f446xx_sram.icf" used within EWARM Workspaces
  • -

    Header file for all -STM32 devices

    -
    • Add missing bits definition in the EXTI IMR, EMR, RTSR, FTSR, SWIER and PR registers
    • Update RCC_AHB1RSTR_OTGHRST bit definition
    • Update PWR_CR_VOS bits definition for STM32F40xx and STM32F41xx devices

    • update SAI_xCR1_MCKDIV bit definition

    -

V2.2.0 / -15-December-2014

-

Main -Changes

-
  • -

    stm32f4xx.h

    -
    • -

      Add new constant -definition STM32F4 -

    -
  • -

    system_stm32f4xx.c

    -
    • -

      Fix SDRAM -configuration in SystemInit_ExtMemCtl(): change RowBitsNumber from 11 to 12 (for MT48LC4M32B2 -available on STM324x9I_EVAL board)

    -
  • -

    Header file for all -STM32 devices

    -
    • -

      Add missing bits -definition for CAN, FMC and USB peripherals

      -
    • -

      GPIO_TypeDef: -change the BSRR register definition, the two 16-bits definition BSRRH and BSRRL -are merged in a single 32-bits definition BSRR

V2.1.0 / 19-June-2014

- -

Main -Changes

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    -
  • -

    Add support of STM32F411xExx devices
    -

    -
    • -
      -
    • -

      Add "stm32f411xe.h" file

      -
      • -
    -
      -
    • -

      Add startup file "startup_stm32f411xx.s" for EWARM, MDK-ARM and TrueSTUDIO toolchains

      -
      • -
    -
  • -

    All header files

    -
    • -
      -
    • -

      Add missing defines for GPIO LCKR Register

      -
      • -
    • -

      Add defines for memories -base and end addresses: FLASH, SRAM, BKPSRAM and CCMRAM.

      -
      • -

    • Add -the following aliases for IRQ number and handler definition to ensure -compatibility across the product lines of STM32F4 Series;
      -

      • -
        -
      • -

        example for STM32F405xx.h

        -
        • -
      -
    -
-
#define FMC_IRQn              FSMC_IRQn
- #define FMC_IRQHandler     FSMC_IRQHandler
-
    -
      -
        -
      • -

        and for STM32F427xx.h

        -
        • -
      -
    -
-
#define FSMC_IRQn            FMC_IRQn
- #define FSMC_IRQHandler   FMC_IRQHandler
+ + + +
+


+

+
+ + + + - - -
+ + + + + + + + + +
Back -
+

Release + Notes for STM32F4xx CMSIS

+

Copyright + 2017 STMicroelectronics

+

+
+

 

+ + + + - - -
+

Update History

+

V2.6.7 / 16-July-2021

+     +   Main + + + Changes
+ + +
    +
  • Add missing definition + FLASH_CR_ERRIE to the CMSIS header file.
    • + +
  • Remove unsupported �GPIOF_BASE� + and �GPIOG_BASE� defines from STM32F412Vx + device.
    • + +
  • Add new atomic register access + macros in stm32f4xx.h file.
    • + +
  • Add LSI maximum startup time + datasheet value: LSI_STARTUP_TIME.
    • + +
  • Fix a typo in CMSIS STM32F4xx + version macro (__STM32F4xx_CMSIS_VERSION).
    +
    • +
+

V2.6.6 / 12-February-2021

+     +   Main + + + Changes
+ + +
    +
  • system_stm32f4xx.c:
    • +
      +
    • Protect +Vector + + + table modification following SRAM or + FLASH preprocessor directive by a + generic preprocessor directive : + USER_VECT_TAB_ADDRESS
      • +
    • Update + + + SystemInit_ExtMemCtl() API to initialize + the tmpreg variable before each time out + loop condition.
      +
      • +
    +
  • Add License.md and + Readme.md files required for GitHub + publication
    • +
  • Improve GCC startup + files robustness.
    • +
  • Fix wrong value for + GPIO_MODER_MODE8_Msk and + GPIO_MODER_MODE2_Pos.
    • +
  • Update max number of + host channels in FS for STM32F446:
    • +
      +
    • Update + + + USB_OTG_FS_HOST_MAX_CHANNEL_NBR value + from 8 to 12.
      • +
    +
  • Add SMBDEN and SMBHEN + bit definition for STM32F410Tx device.
    +
    • +
+

V2.6.5 / 10-February-2020

+     +   Main + + + Changes
+ + +
    +
  • All header files
    • +
      +
    • Update + + + to use new BSD License format
      +
      • +
    +
  • MDK-ARM startup files
    • +
      +
    • Update + + + to fix invalid config wizard annotations
      • +
    +
+

V2.6.4 / 06-December-2019

+     +   Main + + + Changes
+ + +
    +
  • stm32f446xx.h file
    • +
      +
    • Update + + + to support HW flow control on UART4 and + UART5 instances
      • +
    +
  • stm32f412xx.h, stm32f413xx.h and stm32f423xx.h files
    • +
      +
    • Remove + + + unused IS_USB_ALL_INSTANCE() assert macro
      • +
    +
  • All header files
    • +
      +
    • Remove + + + unused IS_TIM_SYNCHRO_INSTANCE() assert + macro
      • +
    +
  • system_stm32f4xx.c file
    • +
      +
    • Update + + + SystemInit() API to don't reset RCC + registers to its reset values
      +
      • +
    +
+

V2.6.3 / 08-February-2019

+     +   Main + + + Changes
+ + +
    +
  • CRYP:
    • +
      +
    • Update CMSIS + devices with correct CRYP data input + register name: DIN instead of DR
      • +
    • Add Bits + definition for CRYP CR ALGOMODE AES + GCM/CCM
      • +
    +
  • HASH:
    • +
      +
    • Update + HASH_DIGEST_TypeDef structure: resize + the HR register
      +
      • +
    • Remove MDMAT Bits + definition
      • +
    +
  • TIM:
    • +
      +
    • Add requires TIM + assert macros:
      • +
        +
      • IS_TIM_SYNCHRO_INSTANCE()
        • +
      • IS_TIM_CLOCKSOURCE_TIX_INSTANCE()
        • +
      • IS_TIM_CLOCKSOURCE_ITRX_INSTANCE()
        • +
      +
    +
  • RCC
    • +
      +
    • Add + + + RCC_CSR_BORRSTF bits definition
      • +
    +
  • GPIO
    +
    • +
      +
    • Fix + + + GPIO BRR bits definition
      • +
    • Adjust + + + the GPIO present on STM32F412 devices
      +
      • +
    +
  • SAI
    • +
      +
    • Fix + + + frame length in SAI_xFRCR_FSALL & SAI_xFRCR_FRL bits + description
      +
      • +
    +
  • USB:
    • +
      +
    • Add + + + missing Bits Definitions in + USB_OTG_DOEPMSK register
      • +
    +
      +
        +
      • USB_OTG_DOEPMSK_AHBERRM
        • +
      • USB_OTG_DOEPMSK_OTEPSPRM
        • +
      • USB_OTG_DOEPMSK_BERRM
        • +
      • USB_OTG_DOEPMSK_NAKM
        • +
      • USB_OTG_DOEPMSK_NYETM
        • +
      +
    +
      +
    • Add + + + missing Bits Definitions in + USB_OTG_DIEPINT register
      • +
    +
      +
        +
      • USB_OTG_DIEPINT_INEPNM
        • +
      • USB_OTG_DIEPINT_AHBERR
        • +
      • USB_OTG_DOEPINT_OUTPKTERR
        • +
      •  USB_OTG_DOEPINT_NAK
        • +
      • USB_OTG_DOEPINT_STPKTRX
        • +
      +
    • Add + + + missing Bits Definitions in USB_OTG_DCFG + register
      • +
        +
      • USB_OTG_DCFG_XCVRDLY
        • +
      • USB_OTG_DCFG_ERRATIM
        • +
      +
    +
      +
    • Update + + + USB OTG max number of endpoints (6 FS + and 9 HS instead of 5 and 8)
      • +
    +
  • I2C/FMPI2C
    • +
      +
    • Align + + + Bit naming for FMPI2C_CR1 register: + FMPI2C_CR1_DFN--> FMPI2C_CR1_DNF
      • +
    • Add + + + IS_SMBUS_ALL_INSTANCE() + + + define
      • +
    +
  • DFSDM
    • +
      +
    • Align + + + Bit naming for DFSDM_FLTICR register: + DFSDM_FLTICR_CLRSCSDF--> + DFSDM_FLTICR_CLRSCDF
      • +
    +
  • PWR
    • +
      +
    • Remove PWR_CSR_WUPP + define: feature not available on + STM32F469xx/479xx devices
      • +
    +
+

V2.6.2 / 06-October-2017

+     +   Main + + + Changes
+ + +
    +
      +
    • Remove Date and + Version from all header files
      • +
    • USB_OTG + + + register clean up: remove + duplicated bits definitions
      • +
    • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
      • +
        +
      • Remove + + + BKPSRAM_BASE define: feature not + available
        • +
      +
    • stm32f405xx.h, stm32f407xx.h files
      • +
        +
      • Rename + + + HASH_RNG_IRQn to RNG_IRQn: HASH + instance not available 
        • +
      +
    • stm32f410xx.h, stm32f412xx.h, stm32f413xx.h,  stm32f423xx.h files
      • +
        +
      • Add + + + missing wake-up pins defines
        • +
      +
    • stm32f412cx.h files
      • +
        +
      •  Add + support of USART3 instance
        • +
      +
    +
+

V2.6.1 / 14-February-2017

+     +   Main + + + Changes
+ + +
    +
  • General updates in + header files to support LL drivers
    • +
      +
    • Align + + + Bit naming for RCC_CSR + register (ex: RCC_CSR_PADRSTF + --> RCC_CSR_PINRSTF)
      • +
    • Add + + + new defines for RCC features support:
      • +
        +
      • RCC + + + PLLI2S and RCC PLLSAI support
        • +
      • RCC + + + PLLR I2S clock source and RCC PLLR + system clock support
        • +
      • RCC + + + SAI1A PLL source and RCC SAI1B PLL + source support
        • +
      • RCC + + + AHB2 support
        +
        • +
      +
    • Add + + + RCC_DCKCFGR_PLLI2SDIVQ_X + and  RCC_DCKCFGR_PLLSAIDIVQ_X + bits definition
      • +
    • Add new defines for + RCC_PLLI2SCFGR_RST_VALUE, + RCC_PLLSAICFGR_RST_VALUE and + RCC_PLLCFGR_RST_VALUE
      • +
    • Add + + + new defines for RTC features support:
      • +
        +
      • RTC + + + Tamper 2 support
        • +
      • RTC + + + AF2 mapping support
        +
        • +
      +
    • Align + + + Bit naming for RTC_CR and RTC_TAFCR + registers (ex: RTC_CR_BCK --> RTC_CR_BKP)
      • +
    • Add + + + new define to manage RTC backup register + number: RTC_BKP_NUMBER
      • +
    • Rename + + + IS_UART_INSTANCE() macro to + IS_UART_HALFDUPLEX_INSTANCE()
      • +
    • Add new defines to check + LIN instance: IS_UART_LIN_INSTANCE
      • +
    • Remove + + + USART6 instance from STM32F410Tx header + file
      • +
    • Rename + IS_I2S_ALL_INSTANCE_EXT() macro to + IS_I2S_EXT_ALL_INSTANCEE()
      • +
    • Add + + + IS_I2S_APB1_INSTANCE() macro to check if + I2S instance mapping: API1 or APB2
      +
      • +
    • Remove + + + SPI_I2S_SUPPORT define for SPI I2S + features support: I2S feature is + available on all STM32F4xx devices
      • +
    • Add + + + SPI_I2S_FULLDUPLEX_SUPPORT define for + STM32F413xx/423xx devices
      • +
    • Align + + + SPI_I2SCFGR bit + naming: SPI_I2SCFGR_ASTRTEN bit is + missing for STM32F412xx devices
      • +
    • Add + + + new I2S_APB1_APB2_FEATURE + + + define + + + for STM32F4xx devices where I2S IP's are + splited between RCC APB1 and APB2 + interfaces
      +
      • +
    • Add new FLASH_SR_RDERR define in FLASH_SR register
      • +
    • Add FLASH_OTP_BASE and  FLASH_OTP_END defnes + to manage FLASH OPT area
      +
      • +
    • Add + + + bit definitions for ETH_MACDBGR + register
      • +
    • Add + + + new defines ADC1_COMMON_BASE and + ADC123_COMMON_BASE to replace ADC_BASE + define
      • +
    • Add + + + new defines ADC1_COMMON and + ADC123_COMMON to replace ADC define
      • +
    • Add + + + new ADC macros: IS_ADC_COMMON_INSTANCE() +and IS_ADC_MULTIMODE_MASTER_INSTANCE()
      +
      • +
    • Add + + + new defines for ADC multi mode features + support
      • +
    • Add + + + new ADC aliases ADC_CDR_RDATA_MST and + ADC_CDR_RDATA_SLV for compatibilities + with all STM32 Families
      • +
    • Update + + + TIM CNT and ARR register mask on 32-bits
      • +
    • Add new TIM_OR_TI1_RMP define in TIM_OR register
      • +
    • Add + + + new TIM macros to check TIM feature + instance support:
      • +
        +
      • IS_TIM_COUNTER_MODE_SELECT_INSTANCE()
        • +
      • IS_TIM_CLOCK_DIVISION_INSTANCE()
        • +
      • IS_TIM_COMMUTATION_EVENT_INSTANCE()
        • +
      • IS_TIM_OCXREF_CLEAR_INSTANCE()
        • +
      • IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE()
        • +
      • IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE()
        • +
      • IS_TIM_REPETITION_COUNTER_INSTANCE()
        • +
      • IS_TIM_ENCODER_INTERFACE_INSTANCE()
        • +
      • IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE()
        • +
      • IS_TIM_BREAK_INSTANCE()
        • +
      +
    • CAN_IER + + + register clean up: remove duplicated bit + definitions
      • +
    • USB_OTG + + + register: fix the wrong defined values + for USB_OTG_GAHBCFG bits
      • +
    +
+

V2.6.0 / 04-November-2016

+     +   Main + + + Changes
+ + +
    +
  • Add support of STM32F413xx and STM32F423xx devices 
    • +
      +
    • Add + + + "stm32f413xx.h" and "stm32f423xx.h" + + + files
      • +
    +
      +
    • +

      Add + + + startup files  "startup_stm32f413xx.s" + + + and "startup_stm32f423xx.s" + + + for EWARM, MDK-ARM and SW4STM32 + toolchains

      +
      • +
    • Add + + + Linker files "stm32f413xx_flash.icf", + + + "stm32f413xx_sram.icf", + + + "stm32f423xx_flash.icf" + + + and "stm32f423xx_sram.icf" + + + used + + + within EWARM Workspaces
      • +
    +
  • All header files
    • +
      +
    • Use + + + _Pos and _Mask macro for all Bit + Definitions
      • +
    • Update + + + LPTIM_OR Bit Definition
      • +
    • Update + + + the defined frequencies by scale for USB + exported constants
      • +
    • Add + + + UID_BASE, FLASHSIZE_BASE and + PACKAGE_BASE defines
      • +
    • Add + + + new define DAC_CHANNEL2_SUPPORT to + manage DAC channel2 support
      • +
    • Use + + + new DAC1 naming
      • +
    • Rename + + + PWR_CSR_UDSWRDY define to PWR_CSR_UDRDY + in PWR_CSR register
      • +
    • Align + + + Bit naming for EXTI_IMR and EXTI_EMR + registers (ex: EXTI_IMR_MR0 --> + EXTI_IMR_IM0)
      +
      • +
    • Add + + + new EXTI_IMR_IM define in EXTI_IMR + register
      • +
    • Add + + + missing DMA registers definition
      • +
    • Add + + + macro to check SMBUS instance support
      +
      • +
    +
  • stm32f412cx.h, stm32f412zx.h, stm32f412vx.h, stm32f412rx.h files
    • +
      +
    • Add missing SYSCFG + register: CFGR2
      • +
    +
  • stm32f405xx.h, stm32f407xx.h, stm32f427xx.h, stm32f429xx.h files
    • +
      +
    • Remove + + + HASH_RNG_IRQn in IRQn_Type enumeration
      • +
    +
  • stm32f405xx.h, stm32f407xx.h, stm32f415xx.h, stm32f417xx.h files
    • +
      +
    • Remove + + + I2C FLTR register as not supported
      +
      • +
    +
  • stm32f407xx.h, stm32f417xx.h, stm32f427xx.h, stm32f429xx.h, stm32f437xx.h, stm32f439xx.h, stm32f469xx.h, stm32f479xx.h files
    • +
      +
    • Add + + + missing Bit Definition of ETH_MACDBGR + register
      • +
    +
  • system_stm32f4xx.c file
    • +
      +
    • Add + -
      • -
    -
+ APBPrescTable declaration + + +

V2.5.1 / 28-June-2016

+     +   Main -

V2.0.0 / 18-February-2014

+ Changes
+ + +
    +
  • stm32f412rx.h, + stm32f412vx.h and + stm32f412zx.h files:
    • +
      +
    • +

      Add QSPI1_V2_1L + define to manage the QSPI DMA2 + limitation
      +

      +
      • +
    +
+

V2.5.0 / 22-April-2016

+     +   Main + Changes
+ + +
    +
  • Add support of STM32F412Cx, STM32F412Rx, STM32F412Vx and STM32F412Zx devices
    • +
      +
    • +

      Add + "stm32f412Cx.h", "stm32f412Rx.h", "stm32f412Vx.h" and "stm32f412Zx.h" files

      +
      • +
    • +

      Add startup + files  "startup_stm32f412cx.s", "startup_stm32f412rx.s", "startup_stm32f412vx.s" and + "startup_stm32f412zx.s" + for EWARM, MDK-ARM and SW4STM32 + toolchains

      +
      • +
    • Add Linker files "stm32f412cx_flash.icf", "stm32f412cx_sram.icf", "stm32f412rx_flash.icf", "stm32f412rx_sram.icf", "stm32f412vx_flash.icf", "stm32f412vx_sram.icf", "stm32f412zx_flash.icf" and "stm32f412zx_sram.icf" used within EWARM + Workspaces
      • +
    +
  • Header files for all + STM32 devices
    • +
      +
    • Remove uint32_t cast + and keep only Misra Cast (U) to avoid + two types cast duplication
      • +
    • Correct some bits + definition to be in line with naming + used in the Reference Manual
      • +
        +
      • WWDG_CR_Tx changed + to WWDG_CR_T_x
        • +
      • WWDG_CFR_Wx changed - - - - - - - -

        Main -Changes

        + to         WWDG_CFR_W_x
        • +
      • WWDG_CFR_WDGTBx changed + to WWDG_CFR_WDGTB_x
        • +
      +
    +
  • stm32f407xx.h, + stm32f417xx.h, stm32f427xx.h, + stm32f429xx.h, stm32f437xx.h, + stm32f439xx.h, stm32f446xx.h, stm32f469xx.h, stm32f479xx.h files
    • +
      +
    • Correct some bits + definition to be in line with naming + used in the Reference Manual
      • +
    +
      +
        +
      • DCMI_RISR_x changed + to DCMI_RIS_x
        • +
      • DCMI_RISR_OVF_RIS + + + changed to DCMI_RIS_OVR_RIS
        • +
      • DCMI_IER_OVF_IE + + + changed to DCMI_IER_OVR_IE
        • +
      +
    +
  • stm32f427xx.h, + stm32f429xx.h, stm32f437xx.h, + stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h files
    • +
      +
    • Correct some bits + definition to be in line with naming + used in the Reference Manual
      • +
        +
      • SAI_xFRCR_FSPO changed + + + to SAI_xFRCR_FSPOL
        • +
      +
    • Rename + IS_SAI_BLOCK_PERIPH to + IS_SAI_ALL_INSTANCE
      +
      • +
    +
  • stm32f410cx.h, + stm32f410rx.h, stm32f410tx.h files + + + and stm32f446xx.h
    • +
      +
    • Remove + FMPI2C_CR1_SWRST and FMPI2C_CR1_WUPEN + Bit definition for I2C_CR1 register
      • +
    +
  • stm32f407xx.h, + stm32f417xx.h, stm32f427xx.h, + stm32f437xx.h, stm32f439xx.h, + stm32f469xx.h, stm32f479xx.h files
    • +
      +
    • Add missing bits + definitions for DMA2D_CR, + DMA2D_FGPFCCR, DMA2D_BGPFCCR, + DMA2D_OPFCCR registers
      • +
    +
  • stm32f401xc.h, stm32f401xe.h, stm32f411xe.h files
    • +
      +
    • Add missing RCC_DCKCFGR register + + + in RCC_TypeDef structure
      +
      • +
    • Add + missing Bit definition for RCC_DCKCFGR + register
      • +
    +
  • system_stm32f4xx.c
    +
    • +
      +
    • Update + SystemInit_ExtMemCtl() API to fix delay + optimization problem with GCC compiler: index variable is + declared as volatile 
      • +
    +
  • stm32f4xx.h
    • +
      +
    • Rename + __STM32F4xx_CMSIS_DEVICE_VERSION_xx + defines to + __STM32F4_CMSIS_VERSION_xx (MISRA-C 2004 rule 5.1)
      • +
    +
+ +

V2.4.3 / 29-January-2016

+     +   Main + + + Changes
+
+ +
    +
  • +

    Header file for all STM32 devices +

    +
    • +
      +
    • Rename +ADC + + + overrun flags definitions : + ADC_CSR_DOVR1, ADC_CSR_DOVR2 and + ADC_CSR_DOVR3 are replaced respectively + by ADC_CSR_OVR1, ADC_CSR_OVR2 and + ADC_CSR_OVR3 to be aligned with + reference manuals
      • +
    • Add + + + missing bits definitions for DAC : + DAC_CR_DMAUDRIE1 and DAC_CR_DMAUDRIE2
      • +
    • Update + + + CMSIS driver to be compliant with MISRA + C 2004 rule 10.6
      • +
    • Remove + + + the double definition of + USB_OTG_HS_MAX_IN_ENDPOINTS and add a + new one for  + USB_OTG_HS_MAX_OUT_ENDPOINTS
      • +
    +
  • stm32f446xx.h, + + + stm32f469xx.h, stm32f479xx.h files 
    • +
      +
    • Change + + + the bit definition value of + QUADSPI_CR_FTHRES
      • +
    +
  • + stm32f446xx.h, stm32f469xx.h, + stm32f479xx.h, stm32f429xx.h, + stm32f439xx.h files
    • +
      +
    • Rename + + + the LTDC_GCR_DTEN to LTDC_GCR_DEN in + order to be aligned with the reference + manual
      • +
    • Rename + + + DCMI_MISR bit definitions to DCMI_MIS
      • +
    • Rename + + + DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
      • +
    • Add + + + missing bits definitions for DCMI_ESCR, + DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, + DCMI_DR registers
      • +
    +
  • + stm32f407xx.h, stm32f417xx.h, + stm32f427xx.h, stm32f437xx.h files
    • +
      +
    • Rename + + + DCMI_MISR bit definitions to DCMI_MIS
      • +
    • Rename + + + DCMI_ICR_OVF_ISC to DCMI_ICR_OVR_ISC
      • +
    • Add + + + missing bits definitions for DCMI_ESCR, + DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE, + DCMI_DR registers
      • +
    +
  • + stm32f410cx.h, stm32f410rx.h, + stm32f410tx.h files
    • +
      +
    • Update + + + the + + + LPTIM SNGSTRT defined value
      • +
    +
  • stm32f427xx.h, + stm32f429xx.h, stm32f437xx.h, + stm32f439xx.h, stm32f469xx.h, stm32f479xx.h + + + files
    • +
      +
    • Rename + + + the DMA2D_IFSR bit definitions to + DMA2D_IFCR
      • +
    +
  • stm32f427xx.h, + stm32f429xx.h, stm32f437xx.h, + stm32f439xx.h, stm32f469xx.h, stm32f479xx.h, stm32f446xx.h + + + files 
    • +
      +
    • Correct + + + a wrong value of SAI_xCR2_CPL definition + bit 
      +
      • +
    +
+

V2.4.2 / 13-November-2015

+

Main Changes

+
    +
  • +

    system_stm32f4xx.c file +

    +
    • +
      +
    • update +SystemInit_ExtMemCtl() + + + function implementation to allow the + possibility of simultaneous use of + DATA_IN_ExtSRAM and DATA_IN_ExtSDRAM
      • +
    +
  • stm32f4xx.h + + + file
    • +
      +
    • add + + + symbols for STM32F411xC devices
      +
      • +
    +
  • stm32f405xx.h, + + + stm32f407xx.h, stm32f415xx.h, + stm32f417xx.h files
    • +
      +
    • add + + + FSMC_BCRx_CPSIZE bits definitions
      • +
    • remove + + + FSMC_BWTRx_CLKDIV and FSMC_BWTRx_DATLAT + bits definitions
      • +
    +
  • stm32f429xx.h, + + + stm32f427xx.h, stm32f437xx.h files
    • +
      +
    • add + + + FMC_BCRx_CPSIZE bits definitions
      • +
    • remove + + + FMC_BWTRx_CLKDIV and FMC_BWTRx_DATLAT + bits definitions
      • +
    +
  • stm32f446xx.h, + + + stm32f469xx.h and stm32f479xx.h
    • +
      +
    • update + + + USB_OTG_GlobalTypeDef registers + structure to remove ADP control + registers
      • +
    • add + + + USB_OTG_DOEPMSK_OTEPSPRM and + USB_OTG_DOEPINT_OTEPSPR bits definitions
      • +
    • Remove + + + ADP related bits definitions
      • +
    • add + + + IS_PCD_ALL_INSTANCE() and + IS_HCD_ALL_INSTANCE() macros
      +
      • +
    +
+

V2.4.1 / 09-October-2015

+

Main Changes

+
    +
  • "stm32f469xx.h", + + + "stm32f479xx.h" +
      +
    • Update bits definition for + DSI_WPCR and DSI_TCCR registers
      +
      • +
    +
    • +
+

V2.4.0 / 14-August-2015

+

Main Changes

+
    +
  • +

    Add + + + support of STM32F469xx + and STM32F479xx devices
    +

    +
    • +
      +
    • +

      Add + + + "stm32f469xx.h" and "stm32f479xx.h" + + + files

      +
      • +
    +
      +
    • +

      Add + + + startup files  "startup_stm32f469xx.s" + + + and "startup_stm32f479xx.s" + + + for EWARM, MDK-ARM and SW4STM32 + toolchains

      +
      • +
    • Add + + + Linker files "stm32f469xx_flash.icf", + + + "stm32f469xx_sram.icf", + + + "stm32f479xx_flash.icf" + + + and "stm32f479xx_sram.icf" + + + used + + + within EWARM Workspaces
      • +
    +
  • +

    Add + + + support of STM32F410xx + devices
    +

    +
    • +
      +
    • +

      Add + + + "stm32f410cx.h", "stm32f410tx.h" + and "stm32f410rx.h" + + + files

      +
      • +
    +
      +
    • +

      Add + + + startup files  "startup_stm32f410cx.s", + + + "startup_stm32f410rx.s" and "startup_stm32f410tx.s" + + + for EWARM, MDK-ARM and SW4STM32 + toolchains

      +
      • +
    • Add + + + Linker files "stm32f410cx_flash.icf", + + + "stm32f410cx_sram.icf", + + + "stm32f410rx_flash.icf", "stm32f410tx_sram.icf", + + + "stm32f410tx_flash.icf",  + and "stm32f410rx_sram.icf" + + + used + + + within EWARM Workspaces
      • +
    +
+

V2.3.2 / 26-June-2015

+

Main Changes

+
    +
  • "stm32f405xx.h", + + + "stm32f407xx.h", "stm32f415xx.h" and + "stm32f417xx.h" +
      +
    • Update FSMC_BTRx_DATAST + + + and FSMC_BWTRx_DATAST (where x can + be 1, 2, 3 and 4) mask on 8bits + instead of 4bits
      • +
    +
    • +
  • "stm32f427xx.h", + + + "stm32f437xx.h", "stm32f429xx.h" and + "stm32f439xx.h"
    +
      +
    • Update the defined mask value + for SAI_xSR_FLVL_2
      • +
    +
    • +
  • "stm32f415xx.h", + + + "stm32f417xx.h", "stm32f437xx.h" and + "stm32f439xx.h"
    • +
      +
    • HASH alignement with bits namming + used in documentation +
        +
          +
        • Rename HASH_IMR_DINIM to + HASH_IMR_DINIE
          • +
        +
          +
        • Rename HASH_IMR_DCIM to + HASH_IMR_DCIE
          • +
        +
          +
        • Rename HASH_STR_NBW to + HASH_STR_NBW
          • +
        +
      +
      • +
    +
  • system_stm32f4xx.c
    • +
      +
    • Remove __IO on constant table + declaration
      • +
    +
      +
    • Implement workaround to cover + RCC limitation regarding peripheral + enable delay
      • +
    +
      +
    • SystemInit_ExtMemCtl() + + + update GPIO configuration when external + SDRAM is used 
      • +
    +
+ +

V2.3.1 / 03-April-2015

+ Main Changes +
    +
  • +

    Header file for all STM32 devices

    +
      +
    • Update SRAM2, SRAM3 and + BKPSRAM Bit-Banding base address + defined values
      • +
    • Keep reference to + SRAM3 only for STM32F42xx and + STM32F43xx devices
      • +
    • Remove CCMDATARAM_BB_BASE: the + CCM Data RAM region is not accessible + via Bit-Banding
      +
      • +
    • Update the RTC_PRER_PREDIV_S defined value to 0x00007FFF instead of + 0x00001FFF
      +
      • +
    +
    • +
+

V2.3.0 / 02-March-2015

+

Main Changes

+ +
    +
  • +

    Add + + + support of STM32F446xx + devices
    +

    +
    • +
      +
    • +

      Add + + + "stm32f446xx.h" file

      +
      • +
    +
      +
    • +

      Add + + + startup file "startup_stm32f446xx.s" + for EWARM, MDK-ARM and TrueSTUDIO + toolchains

      +
      • +
    • Add + + + Linker files "stm32f446xx_flash.icf" and + "stm32f446xx_sram.icf" used within EWARM + Workspaces
      • +
    +
  • +

    Header file for all STM32 devices

    +
      +
    • Add missing bits + definition in the EXTI IMR, EMR, RTSR, + FTSR, SWIER and PR registers
      • +
    • Update + RCC_AHB1RSTR_OTGHRST bit definition
      • +
    • Update PWR_CR_VOS + bits definition for STM32F40xx + + + and STM32F41xx + + + devices
      • +
    • +

      update SAI_xCR1_MCKDIV bit + definition
      +

      +
      • +
    +
    • +
+

V2.2.0 / 15-December-2014

+

Main Changes

+ +
    +
  • +

    stm32f4xx.h

    +
      +
    • +

      Add new constant definition STM32F4 +
      +

      +
      • +
    +
    • +
  • +

    system_stm32f4xx.c
    +

    +
      +
    • +

      Fix SDRAM configuration in + SystemInit_ExtMemCtl(): change RowBitsNumber + from 11 to 12 (for MT48LC4M32B2 + available on STM324x9I_EVAL board)
      +

      +
      • +
    +
    • +
  • +

    Header file for all STM32 devices

    +
      +
    • +

      Add missing bits definition + for CAN, FMC and USB peripherals

      +
      • +
    • +

      GPIO_TypeDef: change the BSRR + register definition, the two 16-bits + definition BSRRH and BSRRL are + merged in a single 32-bits + definition BSRR

      +
      • +
    +
    • +
+

V2.1.0 / 19-June-2014

+

Main Changes

+ + + +
    +
  • +

    Add + + + support of STM32F411xExx + devices
    +

    +
    • +
      +
    • +

      Add + + + "stm32f411xe.h" file

      +
      • +
    +
      +
    • +

      Add + + + startup file "startup_stm32f411xx.s" + for EWARM, MDK-ARM and TrueSTUDIO + toolchains

      +
      • +
    +
  • +

    All + + + header files

    +
    • +
      +
    • +

      Add + + + missing defines for GPIO LCKR Register

      +
      • +
    • +

      Add defines for + memories base and end addresses: + FLASH, SRAM, BKPSRAM and CCMRAM.

      +
      • +
    • +

      Add +the + + + following aliases for IRQ number and + handler definition to ensure + compatibility across the product lines + of STM32F4 Series;
      +

      +
      • +
        +
      • +

        example for STM32F405xx.h

        +
        • +
      +
    +
+
#define + + + FMC_IRQn              + + + FSMC_IRQn
+ #define + + + FMC_IRQHandler     + FSMC_IRQHandler
+
    +
      +
        +
      • +

        and for STM32F427xx.h

        +
        • +
      +
    +
+
#define + + + FSMC_IRQn            + + + FMC_IRQn
+ #define + + + FSMC_IRQHandler   FMC_IRQHandler
+
    +
  • "stm32f401xc.h" + + + and "stm32f401xe.h": update to be in line + with latest version of the Reference + + + manual
    • +
      +
    • Remove + + + RNG registers structures and the + corresponding bit definitions
      • +
    • Remove + + + any occurrence to RNG (clock enable, + clock reset,�)
      • +
    • Add + + + the following bit definition for PWR CR + register
      • +
        +
      • #define  PWR_CR_ADCDC1      + + + ((uint32_t)0x00002000)
        • +
      +
        +
      • #define  PWR_CR_LPLVDS       + + + ((uint32_t)0x00000400)     
        • +
      +
        +
      • #define  + + + PWR_CR_MRLVDS   +    ((uint32_t)0x00000800)     
        • +
      +
    +
  • "stm32f427xx.h", + + + "stm32f437xx.h", "stm32f429xx.h" and + "stm32f439xx.h"
    • +
      +
    • Add + + + a new legacy bit definition for PWR to + be in line with latest version of the + Reference manual
      • +
        +
      • #define  PWR_CR_LPUDS        PWR_CR_LPLVDS
        • +
      +
        +
      • #define  +PWR_CR_MRUDS      + PWR_CR_MRLVDS
        • +
      +
    +
  • +

    Update startup + files for EWARM toolchain to cope with + compiler enhancement of the V7.10 + version

    +
    • +
  • +

    system_stm32f4xx.c

    +
    • +
      +
    • Remove + dependency vs. the HAL, to allow using + this file without the need to have the + HAL drivers
      +
      • +
        +
      • Include - + stm32f4xx.h - - + instead of stm32f4xx_hal.h
        • +
      • Add +definition - - + of HSE_VALUE and HSI_VALUE, if they + are not yet defined in the compilation + scope (these values are defined in + stm32f4xx_hal_conf).
        +
        • +
      +
    • +

      Use �__IO const� + instead of �__I�, to avoid any + compilation issue when __cplusplus + switch is defined

      +
      • +
    +
+

V2.0.0 / 18-February-2014

+

Main Changes

+ + + +
    +
  • Update based on STM32Cube + specification
    +
    • +
  • This version and later has to be + used only with STM32CubeF4 based development
    • +
+

V1.3.0 / + 08-November-2013

+

Main Changes

+
    +
  • +

    Add +support + of STM32F401xExx + devices

    +
    • +
  • Update startup files "startup_stm32f401xx.s" for EWARM, MDK-ARM, TrueSTUDIO and + Ride toolchains: Add SPI4 interrupt + handler entry in the vector table
    • +
+

V1.2.1 / + 19-September-2013

+

Main Changes

+
    +
  • +

    system_stm32f4xx.c : Update FMC SDRAM + configuration (RBURST mode activation)
    +

    +
    • +
  • Update startup files "startup_stm32f427_437xx.s" and "startup_stm32f429_439xx.s"  for + TrueSTUDIO and Ride toolchains and + maintain the old name of startup files for + legacy purpose
    • +
+

V1.2.0 / + 11-September-2013

+

Main Changes

+
    +
  • +

    Add +support + of STM32F429/439xx + and STM32F401xCxx + devices

    +
    • +
  • Update - - - + definition of STM32F427/437xx devices : + extension +of + the features to include system clock up to + 180MHz, dual bank Flash, reduced STOP Mode + current, SAI, PCROP, SDRAM and DMA2D
    • +
  • stm32f4xx.h
    +     +
      +
    • Add the + following device defines :
      • +
        +
      • "#define + STM32F40_41xxx" for all STM32405/415/407/417xx devices
        • +
      • "#define + STM32F427_437xx" for all STM32F427/437xx devices
        • +
      • "#define + STM32F429_439xx" for all STM32F429/439xx devices
        • +
      • "#define + STM32F401xx" for all STM32F401xx devices
        • +
      +
    • Maintain the + old device define for legacy purpose
      • +
    • Update IRQ + handler enumeration structure to + support all STM32F4xx Family devices. +  
      • +
    +
    • +
  • Add new startup files "startup_stm32f40_41xxx.s","startup_stm32f427_437xx.s", "startup_stm32f429_439xx.s" and "startup_stm32f401xx.s" for all toolchains and maintain + the old name for startup files for legacy + purpose
    • +
  • system_stm32f4xx.c +
      +
    • Update + the system configuration to + support all STM32F4xx Family devices. +  
      • +
    +
    • +
+

V1.1.0 / + 11-January-2013

+

Main Changes

+
    +
  • Official release for STM32F427x/437x + devices.
    • +
  • stm32f4xx.h
    +     +
      +
    • Update product + define: replace "#define STM32F4XX" by + "#define STM32F40XX" for STM32F40x/41x + devices
      • +
    •  Add new + product define: "#define STM32F427X" + for STM32F427x/437x devices.
      • +
    +
    • +
  • Add new startup files "startup_stm32f427x.s" for all + toolchains
    • +
  • rename startup files "startup_stm32f4xx.s" by "startup_stm32f40xx.s" for all + toolchains
    • +
  • system_stm32f4xx.c +
      +
    • Prefetch Buffer + enabled
      • +
    • Add reference + to STM32F427x/437x devices and + STM324x7I_EVAL board
      • +
    • SystemInit_ExtMemCtl() + function
      +       +
        +
      • Add + configuration of missing FSMC + address and data lines
        +
        • +
      +
        +
      • Change + memory type to SRAM instead of + PSRAM (PSRAM is available only on + STM324xG-EVAL RevA) and update + timing values
        • +
      +
      • +
    +
    • +
+ +

V1.0.2 / 05-March-2012

+

Main Changes

+
    +
  • All source files: license + disclaimer text update and add link to the + License file on ST Internet.
    • +
+

V1.0.1 / 28-December-2011

+

Main Changes

+
    +
  • All source files: update + disclaimer to add reference to + the new license agreement
    • +
  • stm32f4xx.h
    • +
      +
    • Correct bit - - - + definition: RCC_AHB2RSTR_HSAHRST changed + to RCC_AHB2RSTR_HASHRST
      • +
    +
+

V1.0.0 / 30-September-2011

+

Main Changes

+
    +
  • First official release for STM32F40x/41x + devices
    • +
  • Add startup file for TASKING + toolchain
    • +
  • system_stm32f4xx.c: + driver's comments update
    • +
+

V1.0.0RC2 / 26-September-2011

+

Main Changes

+
    +
  • Official version (V1.0.0) + Release Candidate2 for STM32F40x/41x + devices
    • +
  • stm32f4xx.h
    • +
      +
    • Add define for Cortex-M4 + revision __CM4_REV
      • +
    • Correct RCC_CFGR_PPRE2_DIV16 + bit (in RCC_CFGR register) value + to 0x0000E000
      • +
    • Correct some bits + definition to be in line with naming + used in the Reference Manual (RM0090)
      • +
        +
      • GPIO_OTYPER_IDR_x + changed to GPIO_IDR_IDR_x
        • +
      • GPIO_OTYPER_ODR_x + changed to GPIO_ODR_ODR_x
        • +
      • SYSCFG_PMC_MII_RMII + changed to SYSCFG_PMC_MII_RMII_SEL
        • +
      • RCC_APB2RSTR_SPI1 + changed to RCC_APB2RSTR_SPI1RST
        • +
      • DBGMCU_APB1_FZ_DBG_IWDEG_STOP + changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
        • +
      • PWR_CR_PMODE + changed to PWR_CR_VOS
        • +
      • PWR_CSR_REGRDY + changed to PWR_CSR_VOSRDY
        • +
      • Add new define + RCC_AHB1ENR_CCMDATARAMEN
        • +
      • Add new + defines SRAM2_BASE, CCMDATARAM_BASE + and BKPSRAM_BASE
        • +
      +
    • GPIO_TypeDef structure: in the + comment change AFR[2] address + mapping to 0x20-0x24 + instead of 0x24-0x28
      • +
    +
  • system_stm32f4xx.c
    • +
      +
    • SystemInit(): add code + to enable the FPU
      • +
    • SetSysClock(): change + PWR_CR_PMODE + by PWR_CR_VOS
      • +
    • SystemInit_ExtMemCtl(): + remove commented values
      • +
    +
  • startup (for all compilers)
    • +
      +
    • Delete code used to enable the + FPU (moved to system_stm32f4xx.c file)
      • +
    • File�s header updated
      • +
    +
+

V1.0.0RC1 / 25-August-2011

+

Main Changes

+
    +
  • Official version (V1.0.0) + Release Candidate1 for STM32F4xx devices
    • +
+ +
    +
+

License

+
+ Redistribution and use in source and + binary forms, with or without + modification, are permitted provided that + the following conditions are met:
+ +
    +
  1. Redistributions - - - + of source code must retain the above + copyright notice, this list of + conditions and the following + disclaimer.
    2. +
  2. Redistributions +in + binary form must reproduce the above + copyright notice, this list of + conditions and the following + disclaimer in the - - - + documentation and/or other materials + provided with the distribution.
    3. +
  3. Neither - - - - + the name of STMicroelectronics nor the + names of its contributors may be used + to endorse or promote products derived +
    +
    4. +
+        + from this software without specific prior + written permission.
+
+ THIS - - - -
    -
  • Update -based on STM32Cube specification
    -
  • This version and later has to be used only with STM32CubeF4 based development
    • -
-

V1.3.0 / 08-November-2013

-

Main -Changes

+ SOFTWARE IS PROVIDED BY THE COPYRIGHT + HOLDERS AND CONTRIBUTORS "AS IS" AND ANY + EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + THE IMPLIED WARRANTIES OF MERCHANTABILITY + AND FITNESS FOR A PARTICULAR -
    -
  • -

    Add -support of STM32F401xExx devices

  • Update startup files "startup_stm32f401xx.s" for EWARM, MDK-ARM, TrueSTUDIO and Ride toolchains: Add SPI4 interrupt handler entry in the vector table -
    • -
-

V1.2.1 / -19-September-2013

+ PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, -

Main -Changes

-
    -
  • + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + NOT LIMITED TO, PROCUREMENT -

    system_stm32f4xx.c : Update FMC SDRAM configuration (RBURST mode activation)

  • Update startup files "startup_stm32f427_437xx.s" and "startup_stm32f429_439xx.s"  for TrueSTUDIO and Ride toolchains and maintain the old name of startup files for legacy purpose -
    • -
-

V1.2.0 / -11-September-2013

-

Main -Changes

+ OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, + WHETHER IN CONTRACT, STRICT LIABILITY, OR + TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -
    -
  • -

    Add -support of STM32F429/439xx and STM32F401xCxx devices

  • Update definition of STM32F427/437xx devices : extension -of the features to include system clock up to 180MHz, dual bank Flash, reduced -STOP Mode current, SAI, PCROP, SDRAM and DMA2D
  • stm32f4xx.h
     -
    • Add the following device defines :
      • "#define STM32F40_41xxx" for all STM32405/415/407/417xx devices
      • "#define STM32F427_437xx" for all STM32F427/437xx devices
      • "#define STM32F429_439xx" for all STM32F429/439xx devices
      • "#define STM32F401xx" for all STM32F401xx devices
    • Maintain the old device define for legacy purpose
    • Update IRQ handler enumeration structure to support all STM32F4xx Family devices.  
    -
  • Add new startup files "startup_stm32f40_41xxx.s","startup_stm32f427_437xx.s", "startup_stm32f429_439xx.s" and "startup_stm32f401xx.s" for all toolchains and maintain the old name for startup files for legacy purpose -
  • system_stm32f4xx.c -
    • Update the system configuration to support all STM32F4xx Family devices.   -
    • -
-

V1.1.0 / -11-January-2013

- -

Main -Changes

- -
    -
  • Official release for STM32F427x/437x devices. -
  • stm32f4xx.h
     -
    • Update product define: replace -"#define STM32F4XX" by "#define STM32F40XX" for STM32F40x/41x devices -
    •  Add new product define: "#define -STM32F427X" for STM32F427x/437x devices.
    -
  • Add new startup files "startup_stm32f427x.s" for all toolchains -
  • rename startup files "startup_stm32f4xx.s" by "startup_stm32f40xx.s" for all toolchains -
  • system_stm32f4xx.c -
    • Prefetch Buffer enabled -
    • Add reference to STM32F427x/437x -devices and STM324x7I_EVAL board -
    • SystemInit_ExtMemCtl() -function
       -
      • Add configuration of missing FSMC -address and data lines
      -
      • Change memory type to SRAM instead -of PSRAM (PSRAM is available only on STM324xG-EVAL RevA) and update timing -values
    • -
-

V1.0.2 / 05-March-2012

-

Main -Changes

- -
  • All source files: license disclaimer text update and add link to the License file on ST Internet.

V1.0.1 / 28-December-2011

Main -Changes

-
  • All source files: update disclaimer to add reference to the new license agreement
  • stm32f4xx.h
    • Correct bit definition: RCC_AHB2RSTR_HSAHRST changed to RCC_AHB2RSTR_HASHRST

V1.0.0 / 30-September-2011

Main -Changes

-
  • First official release for STM32F40x/41x devices
  • Add startup file for TASKING toolchain
  • system_stm32f4xx.c: driver's comments update

V1.0.0RC2 / 26-September-2011

Main -Changes

-
  • Official version (V1.0.0) Release Candidate2 for STM32F40x/41x devices
  • stm32f4xx.h
    • Add define for Cortex-M4 revision __CM4_REV
    • Correct RCC_CFGR_PPRE2_DIV16 bit (in RCC_CFGR register) value to 0x0000E000
    • Correct some bits definition to be in line with naming used in the Reference Manual (RM0090)
      • GPIO_OTYPER_IDR_x changed to GPIO_IDR_IDR_x
      • GPIO_OTYPER_ODR_x changed to GPIO_ODR_ODR_x
      • SYSCFG_PMC_MII_RMII changed to SYSCFG_PMC_MII_RMII_SEL
      • RCC_APB2RSTR_SPI1 changed to RCC_APB2RSTR_SPI1RST
      • DBGMCU_APB1_FZ_DBG_IWDEG_STOP changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
      • PWR_CR_PMODE changed to PWR_CR_VOS
      • PWR_CSR_REGRDY changed to PWR_CSR_VOSRDY
      • Add new define RCC_AHB1ENR_CCMDATARAMEN
      • Add new defines SRAM2_BASE, CCMDATARAM_BASE and BKPSRAM_BASE
    • GPIO_TypeDef structure: in the comment change AFR[2] address mapping to 0x20-0x24 instead of 0x24-0x28
  • system_stm32f4xx.c
    • SystemInit(): add code to enable the FPU
    • SetSysClock(): change PWR_CR_PMODE by PWR_CR_VOS
    • SystemInit_ExtMemCtl(): remove commented values
  • startup (for all compilers)
    • Delete code used to enable the FPU (moved to system_stm32f4xx.c file)
    • File’s header updated

V1.0.0RC1 / 25-August-2011

Main -Changes

-
  • Official version (V1.0.0) Release Candidate1 for STM32F4xx devices
- -
    -
-

License

-Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met:
- -
  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions -in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived
    -     -
-        from this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -
-
-
-

For -complete documentation on STM32 Microcontrollers -visit www.st.com/STM32

-

-
-

-
-
-

 

-
- \ No newline at end of file + ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + + +
+
+

For + complete documentation on STM32 + Microcontrollers visit www.st.com/STM32

+

+
+

+
+
+

 

+
+ + diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 568c0d984c..246005349b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -4,7 +4,7 @@ * STM32F1: 4.3.3 * STM32F2: 2.2.5 * STM32F3: 2.3.6 - * STM32F4: 2.6.6 + * STM32F4: 2.6.7 * STM32F7: 1.2.6 * STM32G0: 1.4.1 * STM32G4: 1.2.1 diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 299ed70498..ae83378c19 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -38,6 +38,14 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32U5) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF +#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF +#endif /* STM32U5 */ /** * @} */ @@ -210,6 +218,10 @@ extern "C" { * @} */ +/** + * @} + */ + /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ @@ -235,7 +247,7 @@ extern "C" { #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32H7) +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif @@ -382,7 +394,6 @@ extern "C" { #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT #endif /* STM32H7 */ - /** * @} */ @@ -470,15 +481,24 @@ extern "C" { #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE #endif #if defined(STM32H7) -#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 -#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 -#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 -#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 -#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 -#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 -#define FLASH_FLAG_WDW FLASH_FLAG_WBNE -#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U5 */ /** * @} @@ -521,6 +541,7 @@ extern "C" { #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ + /** * @} */ @@ -595,12 +616,12 @@ extern "C" { #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -853,6 +874,10 @@ extern "C" { #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#endif /* STM32U5 */ /** * @} */ @@ -1379,6 +1404,20 @@ extern "C" { */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ @@ -1397,6 +1436,29 @@ extern "C" { * @} */ +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ */ @@ -3329,7 +3391,20 @@ extern "C" { #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 - +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#endif /** * @} */ @@ -3346,7 +3421,7 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3403,13 +3478,22 @@ extern "C" { * @} */ -/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose * @{ */ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + #if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h index f371a9cf13..9041577369 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cec.h @@ -121,14 +121,14 @@ typedef struct * b6 Error information * 0 : No Error * 1 : Error - * b5 IP initialization status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP initialized. HAL CEC Init function already called) + * b5 CEC peripheral initialization status + * 0 : Reset (peripheral not initialized) + * 1 : Init done (peripheral initialized. HAL CEC Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) + * 1 : Busy (peripheral busy with some configuration or internal operations) * b1 (not used) * x : Should be set to 0 * b0 Tx state @@ -138,9 +138,9 @@ typedef struct * RxState value coding follow below described bitmap : * b7-b6 (not used) * xx : Should be set to 00 - * b5 IP initialization status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP initialized) + * b5 CEC peripheral initialization status + * 0 : Reset (peripheral not initialized) + * 1 : Init done (peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h index a1f49eae9e..abd85449b6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h @@ -79,19 +79,19 @@ typedef struct __IO uint32_t ErrorCode; /*!< DAC Error code */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); #if defined(DAC_CHANNEL2_SUPPORT) - void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac); #endif /* DAC_CHANNEL2_SUPPORT */ - void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); - void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); + void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } DAC_HandleTypeDef; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h index 270a92b747..b7f370a8f4 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h @@ -49,29 +49,30 @@ extern "C" { typedef struct { uint32_t Timing; /*!< Specifies the FMPI2C_TIMINGR_register value. - This parameter calculated by referring to FMPI2C initialization - section in Reference manual */ + This parameter calculated by referring to FMPI2C initialization section + in Reference manual */ uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ + This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref FMPI2C_ADDRESSING_MODE */ + This parameter can be a value of @ref FMPI2C_ADDRESSING_MODE */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref FMPI2C_DUAL_ADDRESSING_MODE */ + This parameter can be a value of @ref FMPI2C_DUAL_ADDRESSING_MODE */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ + This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref FMPI2C_OWN_ADDRESS2_MASKS */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref FMPI2C_OWN_ADDRESS2_MASKS */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref FMPI2C_GENERAL_CALL_ADDRESSING_MODE */ + This parameter can be a value of @ref FMPI2C_GENERAL_CALL_ADDRESSING_MODE */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref FMPI2C_NOSTRETCH_MODE */ + This parameter can be a value of @ref FMPI2C_NOSTRETCH_MODE */ } FMPI2C_InitTypeDef; @@ -201,7 +202,8 @@ typedef struct __FMPI2C_HandleTypeDef __IO uint32_t PreviousState; /*!< FMPI2C communication Previous state */ - HAL_StatusTypeDef(*XferISR)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); /*!< FMPI2C transfer IRQ handler function pointer */ + HAL_StatusTypeDef(*XferISR)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< FMPI2C transfer IRQ handler function pointer */ DMA_HandleTypeDef *hdmatx; /*!< FMPI2C Tx DMA handle parameters */ @@ -218,20 +220,32 @@ typedef struct __FMPI2C_HandleTypeDef __IO uint32_t AddrEventCount; /*!< FMPI2C Address Event counter */ #if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Listen Complete callback */ - void (* MemTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Memory Tx Transfer completed callback */ - void (* MemRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Memory Rx Transfer completed callback */ - void (* ErrorCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Error callback */ - void (* AbortCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Abort callback */ - - void (* AddrCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< FMPI2C Slave Address Match callback */ - - void (* MspInitCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Msp Init callback */ - void (* MspDeInitCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Msp DeInit callback */ + void (* MasterTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Error callback */ + void (* AbortCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Abort callback */ + + void (* AddrCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< FMPI2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Msp Init callback */ + void (* MspDeInitCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Msp DeInit callback */ #endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ } FMPI2C_HandleTypeDef; @@ -260,8 +274,11 @@ typedef enum /** * @brief HAL FMPI2C Callback pointer definition */ -typedef void (*pFMPI2C_CallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c); /*!< pointer to an FMPI2C callback function */ -typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an FMPI2C Address Match callback function */ +typedef void (*pFMPI2C_CallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c); +/*!< pointer to an FMPI2C callback function */ +typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an FMPI2C Address Match callback function */ #endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ /** @@ -441,14 +458,14 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint * @retval None */ #if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) -#define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_FMPI2C_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ +#define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_FMPI2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET) -#endif +#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ /** @brief Enable the specified FMPI2C interrupt. * @param __HANDLE__ specifies the FMPI2C Handle. @@ -543,26 +560,27 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint * * @retval None */ -#define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ - : ((__HANDLE__)->Instance->ICR = (__FLAG__))) +#define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified FMPI2C peripheral. * @param __HANDLE__ specifies the FMPI2C Handle. * @retval None */ -#define __HAL_FMPI2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) +#define __HAL_FMPI2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) /** @brief Disable the specified FMPI2C peripheral. * @param __HANDLE__ specifies the FMPI2C Handle. * @retval None */ -#define __HAL_FMPI2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) +#define __HAL_FMPI2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) /** @brief Generate a Non-Acknowledge FMPI2C peripheral in Slave mode. * @param __HANDLE__ specifies the FMPI2C Handle. * @retval None */ -#define __HAL_FMPI2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK)) +#define __HAL_FMPI2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK)) /** * @} */ @@ -602,12 +620,14 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2 */ /* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, @@ -758,10 +778,14 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); ((REQUEST) == FMPI2C_OTHER_AND_LAST_FRAME)) #define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ - (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN))) - -#define FMPI2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 16U)) -#define FMPI2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U)) + (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ + FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ + FMPI2C_CR2_RD_WRN))) + +#define FMPI2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) \ + >> 16U)) +#define FMPI2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) \ + >> 16U)) #define FMPI2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND) #define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)) #define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)) @@ -773,10 +797,15 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); (uint16_t)(0xFF00U))) >> 8U))) #define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) -#define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) +#define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ + (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ + (~FMPI2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ + (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & \ + (~FMPI2C_CR2_RD_WRN))) -#define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == \ +#define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == \ ((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET) #define FMPI2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h index 326b05853a..6a5df0b1a1 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c_ex.h @@ -79,7 +79,7 @@ extern "C" { * @{ */ -/** @addtogroup FMPI2CEx_Exported_Functions_Group1 FMPI2C Extended Filter Mode Functions +/** @addtogroup FMPI2CEx_Exported_Functions_Group1 Filter Mode Functions * @{ */ /* Peripheral Control functions ************************************************/ @@ -89,14 +89,7 @@ HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c * @} */ -/** @addtogroup FMPI2CEx_Exported_Functions_Group2 FMPI2C Extended WakeUp Mode Functions - * @{ - */ -/** - * @} - */ - -/** @addtogroup FMPI2CEx_Exported_Functions_Group3 FMPI2C Extended FastModePlus Functions +/** @addtogroup FMPI2CEx_Exported_Functions_Group3 Fast Mode Plus Functions * @{ */ void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); @@ -105,7 +98,6 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @} */ - /** * @} */ @@ -138,7 +130,7 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); /** @defgroup FMPI2CEx_Private_Functions FMPI2C Extended Private Functions * @{ */ -/* Private functions are defined in stm32f4xx_hal_fmpfmpi2c_ex.c file */ +/* Private functions are defined in stm32f4xx_hal_fmpi2c_ex.c file */ /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h index c0dce28974..9d5e0307ed 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h @@ -28,7 +28,6 @@ extern "C" { #if defined(FMPI2C_CR1_PE) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" -#include "stm32f4xx_hal_fmpsmbus_ex.h" /** @addtogroup STM32F4xx_HAL_Driver * @{ @@ -50,42 +49,43 @@ extern "C" { typedef struct { uint32_t Timing; /*!< Specifies the FMPSMBUS_TIMINGR_register value. - This parameter calculated by referring to FMPSMBUS initialization - section in Reference manual */ + This parameter calculated by referring to FMPSMBUS initialization section + in Reference manual */ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. - This parameter can be a value of @ref FMPSMBUS_Analog_Filter */ + This parameter can be a value of @ref FMPSMBUS_Analog_Filter */ uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ + This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. - This parameter can be a value of @ref FMPSMBUS_addressing_mode */ + This parameter can be a value of @ref FMPSMBUS_addressing_mode */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */ + This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ + This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address + if dual addressing mode is selected + This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */ + This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref FMPSMBUS_nostretch_mode */ + This parameter can be a value of @ref FMPSMBUS_nostretch_mode */ uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. - This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */ + This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */ uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. - This parameter can be a value of @ref FMPSMBUS_peripheral_mode */ + This parameter can be a value of @ref FMPSMBUS_peripheral_mode */ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits FMPSMBUS_TIMEOUT_register value. - (Enable bits and different timeout values) - This parameter calculated by referring to FMPSMBUS initialization - section in Reference manual */ + (Enable bits and different timeout values) + This parameter calculated by referring to FMPSMBUS initialization section + in Reference manual */ } FMPSMBUS_InitTypeDef; /** * @} @@ -104,7 +104,7 @@ typedef struct #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ #define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ #define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ -#define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ +#define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} */ @@ -123,7 +123,7 @@ typedef struct #define HAL_FMPSMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ #define HAL_FMPSMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) -#define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ #define HAL_FMPSMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ /** @@ -161,17 +161,26 @@ typedef struct __IO uint32_t ErrorCode; /*!< FMPSMBUS Error code */ #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Listen Complete callback */ - void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Error callback */ - - void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< FMPSMBUS Slave Address Match callback */ - - void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Msp Init callback */ - void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Msp DeInit callback */ + void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Listen Complete callback */ + void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Error callback */ + + void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< FMPSMBUS Slave Address Match callback */ + + void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Msp Init callback */ + void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Msp DeInit callback */ #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ } FMPSMBUS_HandleTypeDef; @@ -197,8 +206,11 @@ typedef enum /** * @brief HAL FMPSMBUS Callback pointer definition */ -typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< pointer to an FMPSMBUS callback function */ -typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an FMPSMBUS Address Match callback function */ +typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); +/*!< pointer to an FMPSMBUS callback function */ +typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an FMPSMBUS Address Match callback function */ #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ /** @@ -360,9 +372,10 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus #define FMPSMBUS_IT_ADDRI FMPI2C_CR1_ADDRIE #define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE #define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE -#define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | \ - FMPSMBUS_IT_TXI) -#define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI) +#define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | \ + FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI) +#define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | \ + FMPSMBUS_IT_RXI) #define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI) #define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI) /** @@ -410,14 +423,14 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus * @retval None */ #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) -#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \ +#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET) -#endif +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ /** @brief Enable the specified FMPSMBUS interrupts. * @param __HANDLE__ specifies the FMPSMBUS Handle. @@ -493,7 +506,8 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus */ #define FMPSMBUS_FLAG_MASK (0x0001FFFFU) #define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ - (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) + (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \ + ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) /** @brief Clear the FMPSMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the FMPSMBUS Handle. @@ -576,43 +590,52 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \ ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP)) -#define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \ - ((MODE) == FMPSMBUS_AUTOEND_MODE) || \ - ((MODE) == FMPSMBUS_SOFTEND_MODE) || \ - ((MODE) == FMPSMBUS_SENDPEC_MODE) || \ - ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \ - ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \ - ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \ - ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | FMPSMBUS_RELOAD_MODE ))) +#define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \ + ((MODE) == FMPSMBUS_AUTOEND_MODE) || \ + ((MODE) == FMPSMBUS_SOFTEND_MODE) || \ + ((MODE) == FMPSMBUS_SENDPEC_MODE) || \ + ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \ + ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \ + ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \ + ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | \ + FMPSMBUS_RELOAD_MODE ))) #define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \ - ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \ - ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \ + ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \ ((REQUEST) == FMPSMBUS_NO_STARTSTOP)) -#define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ - ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ - ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ - ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \ - ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) +#define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ + ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ + ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ + ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \ + ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) -#define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \ +#define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \ ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) -#define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ - (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | FMPI2C_CR1_PECEN))) -#define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ - (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN))) - -#define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) +#define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ + (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \ + FMPI2C_CR1_PECEN))) +#define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ + FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ + FMPI2C_CR2_RD_WRN))) + +#define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ + (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ + (~FMPI2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & \ + (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | \ + (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) #define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U) #define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U) @@ -631,6 +654,9 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus * @} */ +/* Include FMPSMBUS HAL Extended module */ +#include "stm32f4xx_hal_fmpsmbus_ex.h" + /* Exported functions --------------------------------------------------------*/ /** @addtogroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions * @{ @@ -650,11 +676,14 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, - pFMPSMBUS_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); - -HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, pFMPSMBUS_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, + pFMPSMBUS_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, + pFMPSMBUS_AddrCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ /** @@ -680,10 +709,10 @@ HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, * @{ */ /******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress); HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h index 541ce73228..d5439e7ce8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus_ex.h @@ -38,7 +38,6 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ - /* Exported constants --------------------------------------------------------*/ /** @defgroup FMPSMBUSEx_Exported_Constants FMPSMBUS Extended Exported Constants * @{ @@ -71,7 +70,15 @@ extern "C" { * @{ */ -/** @addtogroup FMPSMBUSEx_Exported_Functions_Group3 FMPSMBUS Extended FastModePlus Functions +/** @addtogroup FMPSMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +/** + * @} + */ + +/** @addtogroup FMPSMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions * @{ */ void HAL_FMPSMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus); @@ -97,8 +104,10 @@ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); /** @defgroup FMPSMBUSEx_Private_Macro FMPSMBUS Extended Private Macros * @{ */ -#define IS_FMPSMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SCL)) == FMPSMBUS_FASTMODEPLUS_SCL) || \ - (((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == FMPSMBUS_FASTMODEPLUS_SDA)) +#define IS_FMPSMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SCL)) == \ + FMPSMBUS_FASTMODEPLUS_SCL) || \ + (((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == \ + FMPSMBUS_FASTMODEPLUS_SDA)) /** * @} */ @@ -107,7 +116,7 @@ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); /** @defgroup FMPSMBUSEx_Private_Functions FMPSMBUS Extended Private Functions * @{ */ -/* Private functions are defined in stm32f4xx_hal_fmpfmpsmbus_ex.c file */ +/* Private functions are defined in stm32f4xx_hal_fmpsmbus_ex.c file */ /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h index ee510cb9bf..fec558979f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h @@ -108,29 +108,28 @@ typedef enum /** @defgroup GPIO_mode_define GPIO mode define * @brief GPIO Configuration Mode - * Elements values convention: 0xX0yz00YZ - * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection - * - z : IO configuration on External IT or Event - * - Y : Output type (Push Pull or Open Drain) - * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits * @{ */ -#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP (MODE_PP | MODE_OUTPUT) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD (MODE_OD | MODE_OUTPUT) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP (MODE_PP | MODE_AF) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD (MODE_OD | MODE_AF) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ -#define GPIO_MODE_IT_RISING (EXTI_MODE | GPIO_MODE_IT | RISING_EDGE) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING (EXTI_MODE | GPIO_MODE_IT | FALLING_EDGE) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING (EXTI_MODE | GPIO_MODE_IT | RISING_EDGE | FALLING_EDGE) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING (EXTI_MODE | GPIO_MODE_EVT | RISING_EDGE) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING (EXTI_MODE | GPIO_MODE_EVT | FALLING_EDGE) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING (EXTI_MODE | GPIO_MODE_EVT | RISING_EDGE | FALLING_EDGE) /*!< External Event Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} @@ -253,21 +252,24 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** @defgroup GPIO_Private_Constants GPIO Private Constants * @{ */ -#define GPIO_MODE 0x00000003U -#define EXTI_MODE 0x10000000U -#define GPIO_MODE_IT 0x00010000U -#define GPIO_MODE_EVT 0x00020000U -#define RISING_EDGE 0x00100000U -#define FALLING_EDGE 0x00200000U -#define GPIO_OUTPUT_TYPE 0x00000010U - -#define MODE_INPUT 0x00000000U /*!< Input Mode */ -#define MODE_OUTPUT 0x00000001U /*!< Output Mode */ -#define MODE_AF 0x00000002U /*!< Alternate Function Mode */ -#define MODE_ANALOG 0x00000003U /*!< Analog Mode */ - -#define MODE_PP 0x00000000U /*!< Push Pull Mode */ -#define MODE_OD 0x00000010U /*!< Open Drain Mode */ +#define GPIO_MODE_Pos 0U +#define GPIO_MODE (0x3UL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0UL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) +#define MODE_AF (0x2UL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4U +#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16U +#define EXTI_MODE (0x3UL << EXTI_MODE_Pos) +#define EXTI_IT (0x1UL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2UL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20U +#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h index f7c0b9d73e..3b73282edf 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h @@ -244,13 +244,6 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer #define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */ #define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */ -/** - * @} - */ -/** @defgroup HASH_alias HASH API alias - * @{ - */ -#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h index c9ac38a956..6025e032c2 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h @@ -111,11 +111,16 @@ typedef struct #define HCD_SPEED_HIGH USBH_HS_SPEED #define HCD_SPEED_FULL USBH_FSLS_SPEED #define HCD_SPEED_LOW USBH_FSLS_SPEED +/** + * @} + */ +/** @defgroup HCD_Device_Speed HCD Device Speed + * @{ + */ #define HCD_DEVICE_SPEED_HIGH 0U #define HCD_DEVICE_SPEED_FULL 1U #define HCD_DEVICE_SPEED_LOW 2U - /** * @} */ @@ -153,7 +158,8 @@ typedef struct #define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) @@ -296,10 +302,10 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); */ /* Private functions prototypes ----------------------------------------------*/ - /** +/** * @} */ - /** +/** * @} */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h index a5ab815fdd..80ea203720 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_lptim.h @@ -97,22 +97,22 @@ typedef struct */ typedef struct { - LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ + LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ - LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */ + LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */ - LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ + LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ - uint32_t OutputPolarity; /*!< Specifies the Output polarity. - This parameter can be a value of @ref LPTIM_Output_Polarity */ + uint32_t OutputPolarity; /*!< Specifies the Output polarity. + This parameter can be a value of @ref LPTIM_Output_Polarity */ - uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare - values is done immediately or after the end of current period. - This parameter can be a value of @ref LPTIM_Updating_Mode */ + uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare + values is done immediately or after the end of current period. + This parameter can be a value of @ref LPTIM_Updating_Mode */ - uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event - or each external event. - This parameter can be a value of @ref LPTIM_Counter_Source */ + uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event + or each external event. + This parameter can be a value of @ref LPTIM_Counter_Source */ } LPTIM_InitTypeDef; /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h index 87b9efa0a9..e28285d475 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h @@ -194,16 +194,20 @@ typedef struct #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ + ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) + #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) +#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) -#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) - -#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK +#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK -#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \ + ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) @@ -418,27 +422,27 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #if defined (USB_OTG_FS) || defined (USB_OTG_HS) #ifndef USB_OTG_DOEPINT_OTEPSPR #define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ -#endif +#endif /* defined USB_OTG_DOEPINT_OTEPSPR */ #ifndef USB_OTG_DOEPMSK_OTEPSPRM #define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ -#endif +#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */ #ifndef USB_OTG_DOEPINT_NAK #define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ -#endif +#endif /* defined USB_OTG_DOEPINT_NAK */ #ifndef USB_OTG_DOEPMSK_NAKM #define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ -#endif +#endif /* defined USB_OTG_DOEPMSK_NAKM */ #ifndef USB_OTG_DOEPINT_STPKTRX #define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ -#endif +#endif /* defined USB_OTG_DOEPINT_STPKTRX */ #ifndef USB_OTG_DOEPMSK_NYETM #define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ -#endif +#endif /* defined USB_OTG_DOEPMSK_NYETM */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /* Private macros ------------------------------------------------------------*/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h index d2c9937c47..cde48592e3 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rng.h @@ -77,7 +77,7 @@ typedef enum typedef struct __RNG_HandleTypeDef #else typedef struct -#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ { RNG_TypeDef *Instance; /*!< Register base address */ @@ -85,7 +85,7 @@ typedef struct __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ - __IO uint32_t ErrorCode; /*!< RNG Error code */ + __IO uint32_t ErrorCode; /*!< RNG Error code */ uint32_t RandomNumber; /*!< Last Generated RNG Data */ @@ -156,14 +156,14 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t /** @defgroup RNG_Error_Definition RNG Error Definition * @{ */ -#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) #define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */ #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ -#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ +#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ -#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ /** * @} */ @@ -189,7 +189,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t } while(0U) #else #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) -#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /** * @brief Enables the RNG peripheral. @@ -284,7 +284,8 @@ void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback); @@ -298,8 +299,10 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng); /** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions * @{ */ -uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */ -uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */ +uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef + *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */ +uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef + *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng); @@ -333,8 +336,8 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); ((IT) == RNG_IT_SEI)) #define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \ - ((FLAG) == RNG_FLAG_CECS) || \ - ((FLAG) == RNG_FLAG_SECS)) + ((FLAG) == RNG_FLAG_CECS) || \ + ((FLAG) == RNG_FLAG_SECS)) /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h index c3d1544455..36f16c757c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_smartcard.h @@ -99,7 +99,7 @@ typedef struct * 01 : (Not Used) * 10 : Timeout * 11 : Error - * b5 IP initilisation status + * b5 IP initialization status * 0 : Reset (IP not initialized) * 1 : Init done (IP initialized. HAL SMARTCARD Init function already called) * b4-b3 (not used) @@ -116,7 +116,7 @@ typedef struct * RxState value coding follow below described bitmap : * b7-b6 (not used) * xx : Should be set to 00 - * b5 IP initilisation status + * b5 IP initialization status * 0 : Reset (IP not initialized) * 1 : Init done (IP initialized) * b4-b2 (not used) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h index 7ec7310380..2322bf0999 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h @@ -65,8 +65,10 @@ typedef struct This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. This parameter can be a value of @ref TIM_AutoReloadPreload */ @@ -218,7 +220,8 @@ typedef struct uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ uint32_t ClearInputFilter; /*!< TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClearInputConfigTypeDef; @@ -264,22 +267,22 @@ typedef struct */ typedef struct { - uint32_t OffStateRunMode; /*!< TIM off state in run mode - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity - This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t BreakFilter; /*!< Specifies the break input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + } TIM_BreakDeadTimeConfigTypeDef; /** @@ -628,10 +631,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ -#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ /** * @} @@ -846,8 +847,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @{ */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event - (if none of the break inputs BRK and BRK2 is active) */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ /** * @} */ @@ -1091,7 +1091,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None - * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ @@ -1252,8 +1253,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder -mode. + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. */ #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) @@ -1327,7 +1328,8 @@ mode. #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** - * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: @@ -1817,11 +1819,11 @@ mode. ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ - } while(0) + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + } while(0) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ @@ -1836,11 +1838,15 @@ mode. ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ - } while(0) + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) /** * @} @@ -2014,14 +2020,14 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_Sla HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h index 24a41147bb..14526e816b 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h @@ -573,7 +573,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) /** @brief Enable CTS flow control * @note This macro allows to enable CTS hardware flow control for a given UART instance, @@ -591,7 +591,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart */ #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ } while(0U) @@ -611,7 +611,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart */ #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ } while(0U) @@ -631,7 +631,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart */ #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ } while(0U) @@ -651,7 +651,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart */ #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ } while(0U) @@ -665,7 +665,8 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) /** @brief Enable UART * @param __HANDLE__ specifies the UART Handle. @@ -702,7 +703,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); @@ -728,7 +730,8 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); @@ -832,7 +835,8 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); #define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*((uint64_t)(_BAUD_))))) #define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) -#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U) +#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U)\ + + 50U) / 100U) /* UART BRR = mantissa + overflow + fraction = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ #define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ @@ -841,7 +845,8 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); #define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_))))) #define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) -#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U) +#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U)\ + + 50U) / 100U) /* UART BRR = mantissa + overflow + fraction = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ #define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h index 0f5f103aad..83615ed219 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_usart.h @@ -430,10 +430,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \ (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK))) + ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK))) #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK))) + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK))) /** @brief Checks whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. @@ -449,7 +449,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK)) + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK)) /** @brief Macro to enable the USART's one bit sample method * @param __HANDLE__ specifies the USART Handle. @@ -461,7 +461,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @param __HANDLE__ specifies the USART Handle. * @retval None */ -#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) +#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) /** @brief Enable USART * @param __HANDLE__ specifies the USART Handle. @@ -496,7 +497,8 @@ void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ @@ -510,13 +512,16 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ /* IO operation functions *******************************************************/ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); @@ -559,7 +564,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); * */ #define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \ - USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE ) + USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE ) #define USART_CR1_REG_INDEX 1U #define USART_CR2_REG_INDEX 2U @@ -613,8 +618,8 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ #define USART_BRR(_PCLK_, _BAUD_) (((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \ - ((USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \ - (USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x07U)) + ((USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \ + (USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x07U)) /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h index cfa8fbe7a8..eddcc97aea 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h @@ -10,7 +10,7 @@ [..] The LL CORTEX driver contains a set of generic APIs that can be used by user: - (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick functions (+) Low power mode configuration (SCB register of Cortex-MCU) (+) MPU API to configure and enable regions diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h index 42031307fa..98bf40b71c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h @@ -1288,7 +1288,6 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D * @{ */ - /** * @brief Get DAC underrun flag for DAC channel 1 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h index 1f2e707b1a..dd08b77c36 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h @@ -70,38 +70,46 @@ typedef struct uint32_t PeripheralMode; /*!< Specifies the peripheral mode. This parameter can be a value of @ref FMPI2C_LL_EC_PERIPHERAL_MODE. - This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetMode(). */ + This feature can be modified afterwards using unitary function + @ref LL_FMPI2C_SetMode(). */ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and the helper macro @ref __LL_FMPI2C_CONVERT_TIMINGS(). - This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetTiming(). */ + This feature can be modified afterwards using unitary function + @ref LL_FMPI2C_SetTiming(). */ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. This parameter can be a value of @ref FMPI2C_LL_EC_ANALOGFILTER_SELECTION. - This feature can be modified afterwards using unitary functions @ref LL_FMPI2C_EnableAnalogFilter() or LL_FMPI2C_DisableAnalogFilter(). */ + This feature can be modified afterwards using unitary functions + @ref LL_FMPI2C_EnableAnalogFilter() or LL_FMPI2C_DisableAnalogFilter(). */ uint32_t DigitalFilter; /*!< Configures the digital noise filter. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. - This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetDigitalFilter(). */ + This feature can be modified afterwards using unitary function + @ref LL_FMPI2C_SetDigitalFilter(). */ uint32_t OwnAddress1; /*!< Specifies the device own address 1. This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. - This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */ + This feature can be modified afterwards using unitary function + @ref LL_FMPI2C_SetOwnAddress1(). */ - uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive + match code or next received byte. This parameter can be a value of @ref FMPI2C_LL_EC_I2C_ACKNOWLEDGE. - This feature can be modified afterwards using unitary function @ref LL_FMPI2C_AcknowledgeNextData(). */ + This feature can be modified afterwards using unitary function + @ref LL_FMPI2C_AcknowledgeNextData(). */ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). This parameter can be a value of @ref FMPI2C_LL_EC_OWNADDRESS1. - This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */ + This feature can be modified afterwards using unitary function + @ref LL_FMPI2C_SetOwnAddress1(). */ } LL_FMPI2C_InitTypeDef; /** * @} @@ -171,10 +179,11 @@ typedef struct /** @defgroup FMPI2C_LL_EC_PERIPHERAL_MODE Peripheral Mode * @{ */ -#define LL_FMPI2C_MODE_I2C 0x00000000U /*!< FMPI2C Master or Slave mode */ -#define LL_FMPI2C_MODE_SMBUS_HOST FMPI2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ -#define LL_FMPI2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */ -#define LL_FMPI2C_MODE_SMBUS_DEVICE_ARP FMPI2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ +#define LL_FMPI2C_MODE_I2C 0x00000000U /*!< FMPI2C Master or Slave mode */ +#define LL_FMPI2C_MODE_SMBUS_HOST FMPI2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ +#define LL_FMPI2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode + (Default address not acknowledge) */ +#define LL_FMPI2C_MODE_SMBUS_DEVICE_ARP FMPI2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ /** * @} */ @@ -209,14 +218,15 @@ typedef struct /** @defgroup FMPI2C_LL_EC_OWNADDRESS2 Own Address 2 Masks * @{ */ -#define LL_FMPI2C_OWNADDRESS2_NOMASK FMPI2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ -#define LL_FMPI2C_OWNADDRESS2_MASK01 FMPI2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ -#define LL_FMPI2C_OWNADDRESS2_MASK02 FMPI2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ -#define LL_FMPI2C_OWNADDRESS2_MASK03 FMPI2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ -#define LL_FMPI2C_OWNADDRESS2_MASK04 FMPI2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ -#define LL_FMPI2C_OWNADDRESS2_MASK05 FMPI2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ -#define LL_FMPI2C_OWNADDRESS2_MASK06 FMPI2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ -#define LL_FMPI2C_OWNADDRESS2_MASK07 FMPI2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/ +#define LL_FMPI2C_OWNADDRESS2_NOMASK FMPI2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ +#define LL_FMPI2C_OWNADDRESS2_MASK01 FMPI2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK02 FMPI2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK03 FMPI2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK04 FMPI2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK05 FMPI2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK06 FMPI2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK07 FMPI2C_OAR2_OA2MASK07 /*!< No comparison is done. + All Address2 are acknowledged. */ /** * @} */ @@ -251,14 +261,21 @@ typedef struct /** @defgroup FMPI2C_LL_EC_MODE Transfer End Mode * @{ */ -#define LL_FMPI2C_MODE_RELOAD FMPI2C_CR2_RELOAD /*!< Enable FMPI2C Reload mode. */ -#define LL_FMPI2C_MODE_AUTOEND FMPI2C_CR2_AUTOEND /*!< Enable FMPI2C Automatic end mode with no HW PEC comparison. */ -#define LL_FMPI2C_MODE_SOFTEND 0x00000000U /*!< Enable FMPI2C Software end mode with no HW PEC comparison. */ -#define LL_FMPI2C_MODE_SMBUS_RELOAD LL_FMPI2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC LL_FMPI2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC LL_FMPI2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */ -#define LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_AUTOEND | FMPI2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_SOFTEND | FMPI2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */ +#define LL_FMPI2C_MODE_RELOAD FMPI2C_CR2_RELOAD /*!< Enable FMPI2C Reload mode. */ +#define LL_FMPI2C_MODE_AUTOEND FMPI2C_CR2_AUTOEND /*!< Enable FMPI2C Automatic end mode + with no HW PEC comparison. */ +#define LL_FMPI2C_MODE_SOFTEND 0x00000000U /*!< Enable FMPI2C Software end mode + with no HW PEC comparison. */ +#define LL_FMPI2C_MODE_SMBUS_RELOAD LL_FMPI2C_MODE_RELOAD /*!< Enable FMPSMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC LL_FMPI2C_MODE_AUTOEND /*!< Enable FMPSMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC LL_FMPI2C_MODE_SOFTEND /*!< Enable FMPSMBUS Software end mode + with HW PEC comparison. */ +#define LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_AUTOEND | FMPI2C_CR2_PECBYTE) +/*!< Enable FMPSMBUS Automatic end mode with HW PEC comparison. */ +#define LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_SOFTEND | FMPI2C_CR2_PECBYTE) +/*!< Enable FMPSMBUS Software end mode with HW PEC comparison. */ /** * @} */ @@ -266,14 +283,23 @@ typedef struct /** @defgroup FMPI2C_LL_EC_GENERATE Start And Stop Generation * @{ */ -#define LL_FMPI2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ -#define LL_FMPI2C_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */ -#define LL_FMPI2C_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) /*!< Generate Start for read request. */ -#define LL_FMPI2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Start for write request. */ -#define LL_FMPI2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ -#define LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */ -#define LL_FMPI2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN | FMPI2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ -#define LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/ +#define LL_FMPI2C_GENERATE_NOSTARTSTOP 0x00000000U +/*!< Don't Generate Stop and Start condition. */ +#define LL_FMPI2C_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) +/*!< Generate Stop condition (Size should be set to 0). */ +#define LL_FMPI2C_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) +/*!< Generate Start for read request. */ +#define LL_FMPI2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) +/*!< Generate Start for write request. */ +#define LL_FMPI2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) +/*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) +/*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_FMPI2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | \ + FMPI2C_CR2_RD_WRN | FMPI2C_CR2_HEAD10R) +/*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) +/*!< Generate Restart for write request, slave 10Bit address.*/ /** * @} */ @@ -281,8 +307,10 @@ typedef struct /** @defgroup FMPI2C_LL_EC_DIRECTION Read Write Direction * @{ */ -#define LL_FMPI2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */ -#define LL_FMPI2C_DIRECTION_READ FMPI2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/ +#define LL_FMPI2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, + slave enters receiver mode. */ +#define LL_FMPI2C_DIRECTION_READ FMPI2C_ISR_DIR /*!< Read transfer request by master, + slave enters transmitter mode.*/ /** * @} */ @@ -290,8 +318,10 @@ typedef struct /** @defgroup FMPI2C_LL_EC_DMA_REG_DATA DMA Register Data * @{ */ -#define LL_FMPI2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ -#define LL_FMPI2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +#define LL_FMPI2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for + transmission */ +#define LL_FMPI2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for + reception */ /** * @} */ @@ -299,8 +329,10 @@ typedef struct /** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout * @{ */ -#define LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */ -#define LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH FMPI2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/ +#define LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect + SCL low level timeout. */ +#define LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH FMPI2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect + both SCL and SDA high level timeout.*/ /** * @} */ @@ -308,9 +340,12 @@ typedef struct /** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection * @{ */ -#define LL_FMPI2C_SMBUS_TIMEOUTA FMPI2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ -#define LL_FMPI2C_SMBUS_TIMEOUTB FMPI2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */ -#define LL_FMPI2C_SMBUS_ALL_TIMEOUT (uint32_t)(FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */ +#define LL_FMPI2C_FMPSMBUS_TIMEOUTA FMPI2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ +#define LL_FMPI2C_FMPSMBUS_TIMEOUTB FMPI2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) + enable bit */ +#define LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT (uint32_t)(FMPI2C_TIMEOUTR_TIMOUTEN | \ + FMPI2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB +(extended clock) enable bits */ /** * @} */ @@ -354,18 +389,22 @@ typedef struct /** * @brief Configure the SDA setup, hold time and the SCL high, low period. * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. - * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc) - * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc) - * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc) - * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc) + * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tscldel = (SCLDEL+1)xtpresc) + * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tsdadel = SDADELxtpresc) + * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tsclh = (SCLH+1)xtpresc) + * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tscll = (SCLL+1)xtpresc) * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -#define __LL_FMPI2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \ - ((((uint32_t)(__PRESCALER__) << FMPI2C_TIMINGR_PRESC_Pos) & FMPI2C_TIMINGR_PRESC) | \ - (((uint32_t)(__DATA_SETUP_TIME__) << FMPI2C_TIMINGR_SCLDEL_Pos) & FMPI2C_TIMINGR_SCLDEL) | \ - (((uint32_t)(__DATA_HOLD_TIME__) << FMPI2C_TIMINGR_SDADEL_Pos) & FMPI2C_TIMINGR_SDADEL) | \ - (((uint32_t)(__CLOCK_HIGH_PERIOD__) << FMPI2C_TIMINGR_SCLH_Pos) & FMPI2C_TIMINGR_SCLH) | \ - (((uint32_t)(__CLOCK_LOW_PERIOD__) << FMPI2C_TIMINGR_SCLL_Pos) & FMPI2C_TIMINGR_SCLL)) +#define __LL_FMPI2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \ + ((((uint32_t)(__PRESCALER__) << FMPI2C_TIMINGR_PRESC_Pos) & FMPI2C_TIMINGR_PRESC) | \ + (((uint32_t)(__SETUP_TIME__) << FMPI2C_TIMINGR_SCLDEL_Pos) & FMPI2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__HOLD_TIME__) << FMPI2C_TIMINGR_SDADEL_Pos) & FMPI2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__SCLH_PERIOD__) << FMPI2C_TIMINGR_SCLH_Pos) & FMPI2C_TIMINGR_SCLH) | \ + (((uint32_t)(__SCLL_PERIOD__) << FMPI2C_TIMINGR_SCLL_Pos) & FMPI2C_TIMINGR_SCLL)) /** * @} */ @@ -429,7 +468,8 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabled(FMPI2C_TypeDef *FMPI2Cx) * @param AnalogFilter This parameter can be one of the following values: * @arg @ref LL_FMPI2C_ANALOGFILTER_ENABLE * @arg @ref LL_FMPI2C_ANALOGFILTER_DISABLE - * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk). + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk). * This parameter is used to configure the digital noise filter on SDA and SCL input. * The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk. * @retval None @@ -445,7 +485,8 @@ __STATIC_INLINE void LL_FMPI2C_ConfigFilters(FMPI2C_TypeDef *FMPI2Cx, uint32_t A * This filter can only be programmed when the FMPI2C is disabled (PE = 0). * @rmtoll CR1 DNF LL_FMPI2C_SetDigitalFilter * @param FMPI2Cx FMPI2C Instance. - * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk). + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk). * This parameter is used to configure the digital noise filter on SDA and SCL input. * The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk. * @retval None @@ -663,7 +704,6 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSlaveByteControl(FMPI2C_TypeDef *FMP return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC) == (FMPI2C_CR1_SBC)) ? 1UL : 0UL); } - /** * @brief Enable General Call. * @note When enabled the Address 0x00 is ACKed. @@ -903,7 +943,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetDataSetupTime(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Configure peripheral mode. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 SMBHEN LL_FMPI2C_SetMode\n * CR1 SMBDEN LL_FMPI2C_SetMode @@ -922,7 +962,7 @@ __STATIC_INLINE void LL_FMPI2C_SetMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t Periphe /** * @brief Get peripheral mode. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 SMBHEN LL_FMPI2C_GetMode\n * CR1 SMBDEN LL_FMPI2C_GetMode @@ -940,7 +980,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetMode(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable SMBus alert (Host or Device mode) - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is drived low and @@ -958,7 +998,7 @@ __STATIC_INLINE void LL_FMPI2C_EnableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Disable SMBus alert (Host or Device mode) - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is not drived (can be used as a standard GPIO) and @@ -976,7 +1016,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 ALERTEN LL_FMPI2C_IsEnabledSMBusAlert * @param FMPI2Cx FMPI2C Instance. @@ -989,7 +1029,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable SMBus Packet Error Calculation (PEC). - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 PECEN LL_FMPI2C_EnableSMBusPEC * @param FMPI2Cx FMPI2C Instance. @@ -1002,7 +1042,7 @@ __STATIC_INLINE void LL_FMPI2C_EnableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Disable SMBus Packet Error Calculation (PEC). - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 PECEN LL_FMPI2C_DisableSMBusPEC * @param FMPI2Cx FMPI2C Instance. @@ -1015,7 +1055,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 PECEN LL_FMPI2C_IsEnabledSMBusPEC * @param FMPI2Cx FMPI2C Instance. @@ -1028,7 +1068,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Configure the SMBus Clock Timeout. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_ConfigSMBusTimeout\n @@ -1037,8 +1077,8 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. * @param TimeoutAMode This parameter can be one of the following values: - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH * @param TimeoutB * @retval None */ @@ -1051,7 +1091,7 @@ __STATIC_INLINE void LL_FMPI2C_ConfigSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint3 /** * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note These bits can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_SetSMBusTimeoutA @@ -1066,7 +1106,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx, uint32_ /** * @brief Get the SMBus Clock TimeoutA setting. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_GetSMBusTimeoutA * @param FMPI2Cx FMPI2C Instance. @@ -1079,14 +1119,14 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Set the SMBus Clock TimeoutA mode. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note This bit can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_SetSMBusTimeoutAMode * @param FMPI2Cx FMPI2C Instance. * @param TimeoutAMode This parameter can be one of the following values: - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH * @retval None */ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutAMode) @@ -1096,13 +1136,13 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx, uin /** * @brief Get the SMBus Clock TimeoutA mode. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_GetSMBusTimeoutAMode * @param FMPI2Cx FMPI2C Instance. * @retval Returned value can be one of the following values: - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH */ __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx) { @@ -1111,7 +1151,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note These bits can only be programmed when TimeoutB is disabled. * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_SetSMBusTimeoutB @@ -1126,7 +1166,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx, uint32_ /** * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_GetSMBusTimeoutB * @param FMPI2Cx FMPI2C Instance. @@ -1139,15 +1179,15 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable the SMBus Clock Timeout. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_EnableSMBusTimeout\n * TIMEOUTR TEXTEN LL_FMPI2C_EnableSMBusTimeout * @param FMPI2Cx FMPI2C Instance. * @param ClockTimeout This parameter can be one of the following values: - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB - * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTB + * @arg @ref LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT * @retval None */ __STATIC_INLINE void LL_FMPI2C_EnableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout) @@ -1157,15 +1197,15 @@ __STATIC_INLINE void LL_FMPI2C_EnableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint3 /** * @brief Disable the SMBus Clock Timeout. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_DisableSMBusTimeout\n * TIMEOUTR TEXTEN LL_FMPI2C_DisableSMBusTimeout * @param FMPI2Cx FMPI2C Instance. * @param ClockTimeout This parameter can be one of the following values: - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB - * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTB + * @arg @ref LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT * @retval None */ __STATIC_INLINE void LL_FMPI2C_DisableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout) @@ -1175,20 +1215,21 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint /** * @brief Check if the SMBus Clock Timeout is enabled or disabled. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_IsEnabledSMBusTimeout\n * TIMEOUTR TEXTEN LL_FMPI2C_IsEnabledSMBusTimeout * @param FMPI2Cx FMPI2C Instance. * @param ClockTimeout This parameter can be one of the following values: - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB - * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTB + * @arg @ref LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout) { - return ((READ_BIT(FMPI2Cx->TIMEOUTR, (FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL); + return ((READ_BIT(FMPI2Cx->TIMEOUTR, (FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN)) == \ + (ClockTimeout)) ? 1UL : 0UL); } /** @@ -1405,7 +1446,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TC(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable Error interrupts. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1425,7 +1466,7 @@ __STATIC_INLINE void LL_FMPI2C_EnableIT_ERR(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Disable Error interrupts. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1607,7 +1648,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_OVR(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Indicate the status of SMBus PEC error flag in reception. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note RESET: Clear default value. * SET: When the received PEC does not match with the PEC register content. @@ -1622,7 +1663,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI /** * @brief Indicate the status of SMBus Timeout detection flag. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note RESET: Clear default value. * SET: When a timeout or extended clock timeout occurs. @@ -1637,7 +1678,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMP /** * @brief Indicate the status of SMBus alert flag. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note RESET: Clear default value. * SET: When SMBus host configuration, SMBus alert enabled and @@ -1744,7 +1785,7 @@ __STATIC_INLINE void LL_FMPI2C_ClearFlag_OVR(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Clear SMBus PEC error flag. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll ICR PECCF LL_FMPI2C_ClearSMBusFlag_PECERR * @param FMPI2Cx FMPI2C Instance. @@ -1757,7 +1798,7 @@ __STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Clear SMBus Timeout detection flag. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll ICR TIMOUTCF LL_FMPI2C_ClearSMBusFlag_TIMEOUT * @param FMPI2Cx FMPI2C Instance. @@ -1770,7 +1811,7 @@ __STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Clear SMBus Alert flag. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll ICR ALERTCF LL_FMPI2C_ClearSMBusFlag_ALERT * @param FMPI2Cx FMPI2C Instance. @@ -1885,7 +1926,8 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetTransferSize(FMPI2C_TypeDef *FMPI2Cx) } /** - * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code + or next received byte. * @note Usage in Slave mode only. * @rmtoll CR2 NACK LL_FMPI2C_AcknowledgeNextData * @param FMPI2Cx FMPI2C Instance. @@ -1926,7 +1968,8 @@ __STATIC_INLINE void LL_FMPI2C_GenerateStopCondition(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). * @note The master sends the complete 10bit slave address read sequence : - * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction. + * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address + in Read direction. * @rmtoll CR2 HEAD10R LL_FMPI2C_EnableAuto10BitRead * @param FMPI2Cx FMPI2C Instance. * @retval None @@ -2087,9 +2130,10 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetAddressMatchCode(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. - * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. + * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition + or an Address Matched is received. * This bit has no effect when RELOAD bit is set. * This bit has no effect in device mode when SBC bit is not set. * @rmtoll CR2 PECBYTE LL_FMPI2C_EnableSMBusPECCompare @@ -2103,7 +2147,7 @@ __STATIC_INLINE void LL_FMPI2C_EnableSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR2 PECBYTE LL_FMPI2C_IsEnabledSMBusPECCompare * @param FMPI2Cx FMPI2C Instance. @@ -2116,7 +2160,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(FMPI2C_TypeDef *FMPI /** * @brief Get the SMBus Packet Error byte calculated. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll PECR PEC LL_FMPI2C_GetSMBusPEC * @param FMPI2Cx FMPI2C Instance. diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h index 0d8e8eaee8..a91bf920d0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_lptim.h @@ -67,22 +67,26 @@ typedef struct uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance. This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE. - This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_SetClockSource().*/ uint32_t Prescaler; /*!< Specifies the prescaler division ratio. This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER. - This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/ + This feature can be modified afterwards using using unitary + function @ref LL_LPTIM_SetPrescaler().*/ uint32_t Waveform; /*!< Specifies the waveform shape. This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM. - This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_ConfigOutput().*/ uint32_t Polarity; /*!< Specifies waveform polarity. This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_ConfigOutput().*/ } LL_LPTIM_InitTypeDef; /** @@ -100,9 +104,9 @@ typedef struct * @{ */ #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */ +#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */ #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */ -#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */ #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */ #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */ @@ -114,13 +118,13 @@ typedef struct * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions * @{ */ -#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */ -#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */ -#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */ -#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */ -#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */ -#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */ -#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */ +#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */ +#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */ +#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */ +#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */ +#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */ +#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */ +#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */ /** * @} */ @@ -812,7 +816,8 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx) } /** - * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source. + * @brief Configure the active edge or edges used by the counter when + the LPTIM is clocked by an external clock source. * @note This function must be called when the LPTIM instance is disabled. * @note When both external clock signal edges are considered active ones, * the LPTIM must also be clocked by an internal clock source with a @@ -1030,7 +1035,8 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated. + * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully + completed. If so, a new one can be initiated. * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). @@ -1052,7 +1058,8 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated. + * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully + completed. If so, a new one can be initiated. * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). @@ -1074,7 +1081,8 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode). + * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance + operates in encoder mode). * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). @@ -1096,7 +1104,8 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode). + * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance + operates in encoder mode). * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). @@ -1248,7 +1257,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) /** * @brief Enable autoreload register write completed interrupt (ARROKIE). - * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK + * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1259,7 +1268,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx) /** * @brief Disable autoreload register write completed interrupt (ARROKIE). - * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK + * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1270,7 +1279,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. - * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK + * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ @@ -1281,7 +1290,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) /** * @brief Enable direction change to up interrupt (UPIE). - * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP + * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1292,7 +1301,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx) /** * @brief Disable direction change to up interrupt (UPIE). - * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP + * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1303,7 +1312,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. - * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP + * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ @@ -1314,7 +1323,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) /** * @brief Enable direction change to down interrupt (DOWNIE). - * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN + * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1325,7 +1334,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx) /** * @brief Disable direction change to down interrupt (DOWNIE). - * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN + * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1336,7 +1345,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. - * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN + * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h index ec61b36e7f..d7ef2f6b1f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h @@ -1075,7 +1075,7 @@ __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) { - return (uint8_t)(READ_REG(SPIx->DR)); + return (*((__IO uint8_t *)&SPIx->DR)); } /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h index e9b0b74268..3f83c98dd9 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h @@ -185,24 +185,29 @@ typedef struct uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetPrescaler().*/ uint32_t CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetCounterMode().*/ uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must + be a number between 0x0000 and 0xFFFFFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetAutoReload().*/ uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetClockDivision().*/ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts @@ -210,10 +215,13 @@ typedef struct This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetRepetitionCounter().*/ } LL_TIM_InitTypeDef; /** @@ -224,43 +232,51 @@ typedef struct uint32_t OCMode; /*!< Specifies the output mode. This parameter can be a value of @ref TIM_LL_EC_OCMODE. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetMode().*/ uint32_t OCState; /*!< Specifies the TIM Output Compare state. This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ + This feature can be modified afterwards using unitary function + LL_TIM_OC_SetCompareCHx (x=1..6).*/ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ } LL_TIM_OC_InitTypeDef; /** @@ -273,22 +289,26 @@ typedef struct uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t ICActiveInput; /*!< Specifies the input. This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ } LL_TIM_IC_InitTypeDef; @@ -300,47 +320,56 @@ typedef struct uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetEncoderMode().*/ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC1Filter; /*!< Specifies the TI1 input filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC2Filter; /*!< Specifies the TI2 input filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ } LL_TIM_ENCODER_InitTypeDef; @@ -353,26 +382,31 @@ typedef struct uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. Prescaler must be set to get a maximum counter period longer than the time interval between 2 consecutive changes on the Hall inputs. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC1Filter; /*!< Specifies the TI1 input filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + This parameter can be a value of + @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. A positive pulse (TRGO event) is generated with a programmable delay every time a change occurs on the Hall inputs. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetCompareCH2().*/ } LL_TIM_HALLSENSOR_InitTypeDef; /** @@ -383,51 +417,63 @@ typedef struct uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. This parameter can be a value of @ref TIM_LL_EC_OSSR - This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() - @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. This parameter can be a value of @ref TIM_LL_EC_OSSI - This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() - @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ uint32_t LockLevel; /*!< Specifies the LOCK level parameters. This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL - @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register - has been written, their content is frozen until the next reset.*/ + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR + register has been written, their content is frozen until the next reset.*/ uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetDeadTime() - @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been + programmed. */ uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ } LL_TIM_BDTR_InitTypeDef; /** @@ -978,10 +1024,17 @@ typedef struct * @retval DTG[0:7] */ #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ - ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ - (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ 0U) /** @@ -1006,7 +1059,8 @@ typedef struct ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) /** - * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler @@ -1018,7 +1072,8 @@ typedef struct / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) /** - * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler @@ -1275,7 +1330,8 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) } /** - * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators + * (when supported) and the digital filters. * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. @@ -1293,7 +1349,8 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi } /** - * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time + * generators (when supported) and the digital filters. * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. @@ -1676,7 +1733,7 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } /** @@ -1705,7 +1762,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } /** @@ -2031,7 +2088,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch } /** - * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * dead-time insertion feature is supported by a timer instance. * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter @@ -2224,7 +2282,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), - ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); } @@ -3303,7 +3362,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). @@ -3325,7 +3385,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). @@ -3347,7 +3408,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). @@ -3369,7 +3431,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). @@ -3654,7 +3717,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) * @} */ -/** @defgroup TIM_LL_EF_DMA_Management DMA-Management +/** @defgroup TIM_LL_EF_DMA_Management DMA Management * @{ */ /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h index 1ddddb48dd..86ee731cb3 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h @@ -359,11 +359,12 @@ typedef struct */ #define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(2*((uint64_t)(__BAUDRATE__))))) #define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100) -#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8) + 50) / 100) +#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8)\ + + 50) / 100) /* UART BRR = mantissa + overflow + fraction = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */ #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ - ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \ + ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \ (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07)) /** @@ -375,11 +376,12 @@ typedef struct */ #define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(4*((uint64_t)(__BAUDRATE__))))) #define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100) -#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16) + 50) / 100) +#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16)\ + + 50) / 100) /* USART BRR = mantissa + overflow + fraction = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */ #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ - (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \ + (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \ (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F)) /** @@ -444,7 +446,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); } /** @@ -455,7 +457,7 @@ __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); } /** @@ -466,7 +468,7 @@ __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); } /** @@ -477,7 +479,7 @@ __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); } /** @@ -495,7 +497,7 @@ __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) { - MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); } /** @@ -2022,7 +2024,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); } /** @@ -2033,7 +2035,7 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); } /** @@ -2044,7 +2046,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); } /** @@ -2055,7 +2057,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TXEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE); } /** @@ -2066,7 +2068,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); } /** @@ -2094,7 +2096,7 @@ __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); } /** @@ -2107,7 +2109,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_CTSIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); } /** @@ -2118,7 +2120,7 @@ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); } /** @@ -2129,7 +2131,7 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); } /** @@ -2140,7 +2142,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); } /** @@ -2151,7 +2153,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); } /** @@ -2162,7 +2164,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); } /** @@ -2190,7 +2192,7 @@ __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); } /** @@ -2203,7 +2205,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); } /** @@ -2314,7 +2316,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); } /** @@ -2325,7 +2327,7 @@ __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); } /** @@ -2347,7 +2349,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); } /** @@ -2358,7 +2360,7 @@ __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); } /** @@ -2382,7 +2384,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx) { /* return address of DR register */ - return ((uint32_t) & (USARTx->DR)); + return ((uint32_t) &(USARTx->DR)); } /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h index 28be518656..ca78e2a350 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h @@ -94,14 +94,15 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed */ + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY */ + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ @@ -131,7 +132,7 @@ typedef struct This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type_ */ + This parameter can be any value of @ref USB_LL_EP_Type */ uint8_t data_pid_start; /*!< Initial data PID This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ @@ -168,15 +169,16 @@ typedef struct uint8_t ep_is_in; /*!< Endpoint direction This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - uint8_t speed; /*!< USB Host speed. - This parameter can be any value of @ref USB_Core_Speed_ */ + uint8_t speed; /*!< USB Host Channel speed. + This parameter can be any value of @ref HCD_Device_Speed: + (HCD_DEVICE_SPEED_xxx) */ uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ uint8_t ep_type; /*!< Endpoint Type. - This parameter can be any value of @ref USB_EP_Type_ */ + This parameter can be any value of @ref USB_LL_EP_Type */ uint16_t max_packet; /*!< Endpoint Max packet size. This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ @@ -397,12 +399,19 @@ typedef struct #define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) #define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) -#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) -#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + #define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) #define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) -#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\ + + USB_OTG_HOST_CHANNEL_BASE\ + + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) + #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #define EP_ADDR_MSK 0xFU diff --git a/system/Drivers/STM32F4xx_HAL_Driver/License.md b/system/Drivers/STM32F4xx_HAL_Driver/License.md index f64c6c040f..c681658bea 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/License.md +++ b/system/Drivers/STM32F4xx_HAL_Driver/License.md @@ -1,3 +1,27 @@ -# Copyright (c) 2016 STMicroelectronics +Copyright 2016 STMicroelectronics. +All rights reserved. -This software component is licensed by STMicroelectronics under the **BSD-3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause). \ No newline at end of file +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors +may be used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/system/Drivers/STM32F4xx_HAL_Driver/README.md b/system/Drivers/STM32F4xx_HAL_Driver/README.md index 60b877734a..715117c3ed 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/README.md +++ b/system/Drivers/STM32F4xx_HAL_Driver/README.md @@ -1,19 +1,21 @@ # STM32CubeF4 HAL Driver MCU Component +![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32f4xx_hal_driver.svg?color=brightgreen) + ## Overview -**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost. +**STM32Cube** is an STMicroelectronics original initiative to ease developers' life by reducing efforts, time and cost. -**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series. +**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. - * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio. - * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series. - * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library... - * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series. + * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. + * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series. + * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library... + * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series. Two models of publication are proposed for the STM32Cube embedded software: - * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series). - * The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions. + * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series). + * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions. ## Description @@ -36,20 +38,21 @@ In this table, you can find the successive versions of this HAL-LL Driver compon It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in this table. -HAL Driver F4 | CMSIS Device F4 | CMSIS Core | Was delivered in the full MCU package -------------- | --------------- | -------------- | ------------------------------------- -Tag v1.7.6 | Tag v2.6.3 | Tag v5.4.0_cm4 | Tag v1.24.1 (and following, if any, till next tag) -Tag v1.7.7 | Tag v2.6.4 | Tag v5.4.0_cm4 | Tag v1.24.2 (and following, if any, till next tag) -Tag v1.7.8 | Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.0 (and following, if any, till next tag) -Tag v1.7.9 | Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.1 (and following, if any, till next tag) -Tag v1.7.10 | Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.2 (and following, if any, till ne1xt tag) -Tag v1.7.11 | Tag v2.6.6 | Tag v5.4.0_cm4 | Tag v1.26.0 (and following, if any, till next tag) -Tag v1.7.12 | Tag v2.6.6 | Tag v5.4.0_cm4 | Tag v1.26.1 (and following, if any, till next tag) +HAL Driver F4 | CMSIS Device F4 | CMSIS Core | Was delivered in the full MCU package +------------- | --------------- | ---------- | ------------------------------------- +Tag v1.7.6 | Tag v2.6.3 | Tag v5.4.0_cm4 | Tag v1.24.1 (and following, if any, till HAL tag) +Tag v1.7.7 | Tag v2.6.4 | Tag v5.4.0_cm4 | Tag v1.24.2 (and following, if any, till HAL tag) +Tag v1.7.8 | Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.0 (and following, if any, till HAL tag) +Tag v1.7.9 | Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.1 (and following, if any, till HAL tag) +Tag v1.7.10| Tag v2.6.5 | Tag v5.4.0_cm4 | Tag v1.25.2 (and following, if any, till HAL tag) +Tag v1.7.11| Tag v2.6.6 | Tag v5.4.0_cm4 | Tag v1.26.0 (and following, if any, till HAL tag) +Tag v1.7.12| Tag v2.6.6 | Tag v5.4.0_cm4 | Tag v1.26.1 (and following, if any, till HAL tag) +Tag v1.7.13| Tag v2.6.7 | Tag v5.4.0_cm4 | Tag v1.26.2 (and following, if any, till HAL tag) The full **STM32CubeF4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF4). ## Troubleshooting -If you have any issue with the **Software content** of this repository, you can file an issue into the firmware repository [STM32CubeF4](https://github.com/STMicroelectronics/STM32CubeF4/issues/new/choose). +If you have any issue with the **software content** of this repository, you can file an issue [here](https://github.com/STMicroelectronics/stm32f4xx_hal_driver/issues/new/choose). -For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). \ No newline at end of file +For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html index 9ae5571d2b..4fafe1b5d5 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html @@ -1,17903 +1,57620 @@ + - - -Release Notes for STM32F4xx HAL Drivers - - - - -
- -
- -

 

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Release Notes for STM32F4xx HAL Drivers

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Copyright 2017 STMicroelectronics

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Update History

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V1.7.12 / 26-March-2021

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Main - Changes

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    -
  • HAL
    • -
      -
    • HAL/LL USART update
      • -
        -
      • Fix typo in - USART_Receive_IT() and USART_TransmitReceive_IT() APIs to avoid - possible compilation issues if the UART driver files are not - included.
        • -
      -
    -
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V1.7.11 / 12-February-2021

-

Main - Changes

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    -
  • General updates to fix known defects and - enhancements implementation
    • -
  • Added new HAL FMPSMBUS extended driver - to support FMPSMBUS fast Mode Plus.
    • -
  • Removed �register� keyword to be compliant with - new C++ rules:
    • -
      -
    • The register storage - class specifier was deprecated in C++11 and removed in C++17.
      • -
    -
  • HAL
    • -
      -
    • HAL update
      • -
    • General updates to fix - known defects and enhancements implementation.
      • -
    • Added new defines for - ARM compiler V6:
      • -
        -
      • __weak
        • -
      • __packed
        • -
      • __NOINLINE
        • -
      -
    • Updated HAL TimeBase - TIM, RTC alarm and RTC WakeUp templates for more - robustness
      • -
        -
      • Updated Hal_Init_Tick() - API to propoerty - store the priority when using the non-default time base.
        • -
      -
    • Updated - PPP_MODULE_ENABLED for FMPSMBUS.
      • -
    • HAL/LL ADC update
      • -
        -
      • Updated to add include - of the LL ADC driver.
        • -
      • Updated the following - APIs to set status HAL_ADC_STATE_ERROR_INTERNAL and error code - HAL_ADC_ERROR_INTERNAL when error occurs:
        • -
          -
        • HAL_ADC_Start()
          • -
        • HAL_ADC_Start_IT()
          • -
        • HAL_ADC_Start_DMA()
          • -
        • HAL_ADCEx_InjectedStart()
          • -
        • HAL_ADCEx_InjectedStart_IT()
          • -
        • HAL_ADCEx_MultiModeStart_DMA()
          • -
        -
      • Updated HAL_ADC_Stop_DMA() - API to check if DMA state is Busy before calling HAL_DMA_Abort() - API to avoid DMA internal error.
        • -
      • Updated IS_ADC_CHANNEL - to support temperature sensor for:
        • -
          -
        • STM32F411xE
          • -
        • STM32F413xx
          • -
        • STM32F423xx
          • -
        -
      • Fixed wrong defined - values for:
        • -
          -
        • LL_ADC_MULTI_REG_DMA_LIMIT_3
          • -
        • LL_ADC_MULTI_REG_DMA_UNLMT_3
          • -
        -
      • Added - __LL_ADC_CALC_VREFANALOG_VOLTAGE() macro to evaluate - analog reference voltage.
        • -
      • Removed __LL_ADC_CALC_TEMPERATURE() - macro for STM32F4x9 devices as the TS_CAL2 is not available.
        • -
      -
    • HAL/LL DAC update
      • -
        -
      • Added restruction - on DAC Channel 2 defines and parametres.
        • -
      • HAL_DAC_MSPINIT_CB_ID - and HAL_DAC_MSPDEINIT_CB_ID used instead of HAL_DAC_MSP_INIT_CB_ID - and HAL_DAC_MSP_DEINIT_CB_ID.
        • -
      • Updated to support dual - mode:
        • -
          -
        • Added two new APIs:
          • -
            -
          • HAL_DACEx_DualStart()
            • -
          • HAL_DACEx_DualStop()
            • -
          -
        -
      • Added position bit - definition to be used instead of __DAC_MASK_SHIFT macro
        • -
          -
        • __DAC_MASK_SHIFT macro - has been removed.
          • -
        -
      • Updated HAL_DAC_Start_DMA() - API to return HAL_ERROR when error occurs.
        • -
      • Updated HAL_DAC_Stop_DMA() - API to not return HAL_ERROR when DAC is already disabled.
        • -
      -
    • HAL CEC update
      • -
        -
      • Updated HAL_CEC_IRQHandler() - API to avoid appending an extra byte to the end of a message.
        • -
      -
    • HAL/LL GPIO update
      • -
        -
      • Updated IS_GPIO_AF() - to add missing values for STM32F401xC and STM32F401xE devices:
        • -
          -
        • GPIO_AF3_TIM9
          • -
        • GPIO_AF3_TIM10
          • -
        • GPIO_AF3_TIM11
          • -
        -
      • Updated LL/HAL GPIO_TogglePin() - APIs to allow multi Pin�s toggling.
        • -
      • Updated HAL_GPIO_Init() - API to avoid the configuration of PUPDR register when Analog mode - is selected.
        • -
      -
    • HAL/LL RCC update
      • -
        -
      • Updated HAL_RCC_OscConfig() - API to add missing checks and to don�t return HAL_ERROR if request - repeats the current PLL configuration.
        • -
      • Updated - IS_RCC_PLLN_VALUE(VALUE) macro in case of STM32F411xE device in - order to be aligned with reference manual.
        • -
      -
    • HAL SD update
      • -
        -
      • Update function SD_FindSCR() - to resolve issue of FIFO blocking when reading.
        • -
      • Update read/write - functions in DMA mode in order to force the DMA - direction, updated functions:
        • -
          -
        • HAL_SD_ReadBlocks_DMA()
          • -
        • HAL_SD_WriteBlocks_DMA()
          • -
        -
      • Add the block size - settings in the initialization functions and remove it from - read/write transactions to avoid repeated and inefficient - reconfiguration, updated functions:
        • -
          -
        • HAL_SD_InitCard()
          • -
        • HAL_SD_GetCardStatus()
          • -
        • HAL_SD_ConfigWideBusOperation() 
          • -
        • HAL_SD_ReadBlocks()
          • -
        • HAL_SD_WriteBlocks()
          • -
        • HAL_SD_ReadBlocks_IT()
          • -
        • HAL_SD_WriteBlocks_IT()
          • -
        • HAL_SD_ReadBlocks_DMA()
          • -
        • HAL_SD_WriteBlocks_DMA()
          • -
        -
      -
    • HAL MMC update
      • -
        -
      • Add the block size - settings in the initialization function and remove it from - read/write transactions to avoid repeated and inefficient - reconfiguration, updated functions:
        • -
          -
        • HAL_MMC_InitCard()
          • -
        • HAL_MMC_ReadBlocks()
          • -
        • HAL_MMC_WriteBlocks()
          • -
        • HAL_MMC_ReadBlocks_IT()
          • -
        • HAL_MMC_WriteBlocks_IT()
          • -
        • HAL_MMC_ReadBlocks_DMA()
          • -
        • HAL_MMC_WriteBlocks_DMA()
          • -
        -
      • Update read/write - functions in DMA mode in order to force the DMA - direction, updated functions:
        • -
          -
        • HAL_MMC_ReadBlocks_DMA()
          • -
        • HAL_MMC_WriteBlocks_DMA()
          • -
        -
      • Deploy new functions MMC_ReadExtCSD() - and SDMMC_CmdSendEXTCSD - () that read and check the sectors number of the device in - order to resolve the issue of wrongly reading big memory size.
        • -
      -
    • HAL NAND update
      • -
        -
      • Update functions - HAL_NAND_Read_SpareArea_16b() and - HAL_NAND_Write_SpareArea_16b() to fix column address calculation - issue.
        • -
      -
    • LL SDMMC update
      • -
        -
      • Update the definition - of SDMMC_DATATIMEOUT constant in order to - allow the user to redefine it in his proper application.
        • -
      • Remove 'register' - storage class specifier from LL SDMMC driver.
        • -
      • Deploy new functions MMC_ReadExtCSD() - and SDMMC_CmdSendEXTCSD - () that read and check the sectors number of the device in order - to resolve the issue of wrongly reading big memory size.
        • -
      -
    • HAL SMBUS update
      • -
        -
      • Support for Fast Mode - Plus to be SMBUS rev 3 compliant.
        • -
      • Added HAL_FMPSMBUSEx_EnableFastModePlus() - and HAL_FMPSMBUSEx_DisableFastModePlus() - APIs to manage Fm+.
        • -
      • Updated SMBUS_MasterTransmit_BTF() - , SMBUS_MasterTransmit_TXE() - and SMBUS_MasterReceive_BTF() - APIs to allow stop generation when CurrentXferOptions - is different from SMBUS_FIRST_FRAME and SMBUS_NEXT_FRAME.
        • -
      • Updated SMBUS_ITError() - API to correct the twice call of HAL_SMBUS_ErrorCallback.
        • -
      -
    • HAL SPI update
      • -
        -
      • Updated HAL_SPI_Init() - API
        • -
          -
        • To avoid setting the BaudRatePrescaler - in case of Slave Motorola Mode.
          • -
        • Use the bit-mask - for SPI configuration.
          • -
        -
      • Updated - Transmit/Receive processes in half-duplex mode
        • -
          -
        • Disable the SPI - instance before setting BDIOE bit.
          • -
        -
      • Fixed wrong timeout management
        • -
      • Calculate Timeout based - on a software loop to avoid blocking issue if Systick is - disabled.
        • -
      -
    • HAL SPDIFRX update
      • -
        -
      • Remove 'register' - storage class specifier from HAL SPDIFRX driver.
        • -
      -
    • HAL I2S update
      • -
        -
      • Updated I2SEx APIs to - correctly support circular transfers
        • -
          -
        • Updated I2SEx_TxRxDMACplt() - API to manage DMA circular mode.
          • -
        -
      • Updated - HAL_I2SEx_TransmitReceive_DMA() API - to set hdmatx - (transfert - callback and half) to NULL.
        • -
      -
    • HAL SAI update
      • -
        -
      • Updated to avoid the - incorrect left/right synchronization.
        • -
          -
        • Updated HAL_SAI_Transmit_DMA() - API to follow the sequence described in the reference manual for - slave transmitter mode.
          • -
        -
      • Updated HAL_SAI_Init() - API to correct the formula in case of SPDIF is wrong.
        • -
      -
    • HAL CRYP update
      • -
        -
      • Updated HAL_CRYP_SetConfig() - and HAL_CRYP_GetConfig() - APIs to set/get the continent of KeyIVConfigSkip - correctly.
        • -
      -
    • HAL EXTI update
      • -
        -
      • __EXTI_LINE__ is now - used instead of __LINE__ which is a standard C macro.
        • -
      -
    • HAL DCMI
      • -
        -
      • Support of HAL callback - registration feature for DCMI extended driver.
        • -
      -
    • HAL/LL TIM update
      • -
        -
      • Updated HAL_TIMEx_OnePulseN_Start() - and HAL_TIMEx_OnePulseN_Stop() - APIs (pooling and IT mode) to take into consideration all OutputChannel - parameters.
        • -
      • Corrected reversed - description of TIM_LL_EC_ONEPULSEMODE One Pulse Mode.
        • -
      • Updated LL_TIM_GetCounterMode() - API to return the correct counter mode.
        • -
      -
    • HAL/LL SMARTCARD update
      • -
        -
      • Fixed invalid - initialization of SMARTCARD configuration by removing FIFO mode - configuration as it is not member of SMARTCARD_InitTypeDef - Structure.
        • -
      • Fixed typos in - SMARTCARD State definition description
        • -
      -
    • HAL/LL IRDA update
      • -
        -
      • Fixed typos in IRDA - State definition description
        • -
      -
    • LL USART update
      • -
        -
      • Remove useless check on - maximum BRR value by removing IS_LL_USART_BRR_MAX() - macro.
        • -
      • Update USART polling - and interruption processes to fix issues related to accesses out - of user specified buffer.
        • -
      -
    • HAL USB update
      • -
        -
      • Enhanced USB OTG host - HAL with USB DMA is enabled:
        • -
          -
        • fixed ping and data - toggle issue,
          • -
        • reworked Channel error - report management
          • -
        -
      -
    -
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V1.7.10 / - 22-October-2020

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Main Changes

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    -
  • General updates to fix known defects.
    • -
  • HAL/LL I2C update
    • -
-
    -
      -
    •   Update to fix hardfault - issue with HAL_I2C_Mem_Write_DMA() API:
      • -
        -
      •   Abort the right - ongoing DMA transfer when memory write access request operation - failed: fix typo �hdmarx� replaced by �hdmatx�
        • -
      -
    -
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V1.7.9 / - 14-August-2020

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Main Changes

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    -
  • General updates to fix known defects and - enhancements implementation
    • -
  • HAL/LL I2C update
    • -
-
    -
      -
    •   Update - HAL_I2C_ER_IRQHandler() - API to fix acknowledge failure issue with I2C memory IT processes
      • -
        -
      •   Add stop - condition generation when NACK occurs.
        • -
      -
    •   Update I2C_DMAXferCplt(), - I2C_DMAError() and I2C_DMAAbort() APIs to fix hardfault - issue when hdmatx - and hdmarx - parameters in i2c handle aren't initialized (NULL pointer).
      • -
        -
      •   Add additional - check on hi2c->hdmtx and hi2c->hdmarx - before resetting DMA Tx/Rx complete callbacks
        • -
      -
    •   Update Sequential - transfer APIs to adjust xfermode condition.
      • -
        -
      •   - Replace hi2c->XferCount - < MAX_NBYTE_SIZE by hi2c->XferCount - <= MAX_NBYTE_SIZE which corresponds to a case without reload
        • -
      -
    -
-
    -
  •  HAL/LL USB update
    • -
      -
    •   Bug fix: USB_ReadPMA() - and USB_WritePMA() - by ensuring 16-bits access to USB PMA memory
      • -
    •   Bug fix: - correct USB RX count calculation
      • -
    •   Fix USB Bulk - transfer double buffer mode
      • -
    •   Remove register - keyword from USB defined macros as no more supported by C++ compiler
      • -
    •   Minor rework on USBD_Start() - and USBD_Stop() - APIs: stopping device will be handled by HAL_PCD_DeInit() - API.
      • -
    •   Remove non used - API for USB device mode.
      • -
    -
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V1.7.8 / - 12-February-2020

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Main Changes

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    -
  • Add new HAL FMPSMBUS and LL FMPI2C - drivers
    • -
  • General updates to fix known defects and - enhancements implementation
    • -
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    -
  • Update HAL CRYP driver to support block by block - decryption without reinitializes the IV and KEY for each call.
    • -
  • Improve code quality by fixing MisraC-2012 violations
    • -
  • HAL/LL USB update
    • -
      -
    •  Add handling USB - host babble error interrupt
      • -
    •  Fix Enabling ULPI - interface for platforms that integrates USB HS PHY
      • -
    •  Fix Host data - toggling for IN Iso transfers
      • -
    •  Ensure to disable - USB EP during endpoint deactivation
      • -
    -
  • HAL CRYP update
    • -
      -
    •  Update HAL CRYP - driver to support block by block decryption without initializing - the IV and KEY at each call.
      • -
        -
      • Add new CRYP Handler - parameters: "KeyIVConfig" and "SizesSum"
        • -
      • Add new CRYP init - parameter: "KeyIVConfigSkip"
        • -
      -
    -
  • HAL I2S update
    • -
      -
    • Update HAL_I2S_DMAStop() - API to be more safe
      • -
        -
      • Add a check on BSY, TXE - and RXNE flags before disabling the I2S
        • -
      -
    • Update HAL_I2S_DMAStop() - API to fix multi-call transfer issue(to avoid re-initializing the - I2S for the next transfer).
      • -
        -
      • Add - __HAL_I2SEXT_FLUSH_RX_DR() and - __HAL_I2S_FLUSH_RX_DR() macros to flush the remaining data inside - DR registers.
        • -
      • Add new ErrorCode - define: HAL_I2S_ERROR_BUSY_LINE_RX
        • -
      -
    -
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V1.7.7 / 06-December-2019

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Main Changes

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    -
  • General updates to fix known defects and - enhancements implementation
    • -
  • HAL Generic update
    • -
      -
    • HAL_SetTickFreq(): update to restore the - previous tick frequency when HAL_InitTick() - configuration failed.
      • -
    -
  • HAL/LL GPIO update
    • -
      -
    • Update GPIO initialization - sequence to avoid unwanted pulse on GPIO Pin's
      • -
    -
  • HAL EXTI update
    • -
-
    -
      -
    • General update to - enhance HAL EXTI driver robustness 
      • -
        -
      • Add additional assert - check on EXTI config lines
        • -
      • Update to compute EXTI - line mask before read/write access to EXTI registers
        -
        -
        • -
      -
    • Update EXTI callbacks - management to be compliant with reference manual: only one PR - register for rising and falling interrupts.
      • -
        -
      • Update - parameters in EXTI_HandleTypeDef structure: - merge HAL EXTI RisingCallback and FallingCallback - in only one PendingCallback
        • -
      • Remove - HAL_EXTI_RISING_CB_ID and HAL_EXTI_FALLING_CB_ID values from EXTI_CallbackIDTypeDef - enumeration.
        -
        -
        • -
      -
    • Update HAL_EXTI_IRQHandler() - API to serve interrupts correctly.
      • -
        -
      • Update to compute EXTI - line mask before handle EXTI interrupt.
        • -
      -
    • Update to - support GPIO port interrupts:
      • -
        -
      • Add new "GPIOSel" - parameter in EXTI_ConfigTypeDef - structure
        • -
      -
    -
  • HAL/LL RCC update
    • -
      -
    • Update HAL_RCCEx_PeriphCLKConfig() - API to support PLLI2S configuration for STM32F42xxx and STM32F43xxx - devices
      • -
    • Update the HAL_RCC_ClockConfig() - and HAL_RCC_DeInit() - API to don't overwrite the custom tick priority
      • -
    • Fix LL_RCC_DeInit() - failure detected with gcc compiler and high - optimization level is selected(-03)
      • -
    • Update HAL_RCC_OscConfig() - API to don't return HAL_ERROR if request repeats the current - PLL configuration
      • -
    -
  • HAL ADC update
    • -
      -
    • Update LL_ADC_REG_Init() - to fix wrong ADC CR1 register configuration
      • -
        -
      • The ADC sequencer - length is part of ADC SQR1 register not of ADC CR1 - register
        • -
      -
    -
  • HAL CRYP update
    • -
      -
    • Update HAL_CRYP_Encrypt() - and HAL_CRYP_Decrypt() - APIs to take into consideration the datatype fed to the DIN - register (1-, 8-, 16-, or 32-bit data) when padding the last - block of the payload, in case the size of this last block is less - than 128 bits.
      • -
    -
  • HAL RNG - update
    • -
      -
    • Update HAL_RNG_IRQHandler() - API to fix error code management issue: error code is assigned - "HAL_RNG_ERROR_CLOCK" in case of clock error and - "HAL_RNG_ERROR_SEED" in case of seed error, not the - opposite.
      • -
    -
  • HAL DFSDM update
    • -
      -
    • Update DFSDM_GetChannelFromInstance() - API to remove unreachable check condition
      • -
    -
  • HAL DMA update
    • -
      -
    • Update HAL_DMA_Start_IT() - API to omit the FIFO error
      • -
    -
  • HAL FLASH update
    • -
      -
    • Update FLASH_Program_DoubleWord() - API to fix with EWARM high level optimization issue
      • -
    -
  • HAL QSPI update
    • -
      -
    • Remove Lock mechanism - from HAL_QSPI_Init() - and HAL_QSPI_DeInit() - APIs -
      • -
    -
  • HAL HASH update
    • -
      -
    • Null pointer on handler - "hhash" - is now checked before accessing structure member "hhash->Init.DataType" - in the following API:
      • -
        -
      • HAL_HASH_Init()
        • -
      -
    • Following interrupt-based - APIs have been added. Interrupt mode could allow the MCU to enter - "Sleep" mode while a data block is being processed. - Please refer to the "##### How to use this driver #####" - section for details about their use.
      • -
        -
      • HAL_HASH_SHA1_Accmlt_IT()
        • -
      • HAL_HASH_MD5_Accmlt_IT()
        • -
      • HAL_HASHEx_SHA224_Accmlt_IT()
        • -
      • HAL_HASHEx_SHA256_Accmlt_IT()
        • -
      -
    • Following aliases - have been added (just for clarity sake) as they shall be - used at the end of the computation of a multi-buffers - message and not at the start:
      • -
        -
      • HAL_HASH_SHA1_Accmlt_End() - to be used instead of HAL_HASH_SHA1_Start()
        • -
      • HAL_HASH_MD5_Accmlt_End() - to be used instead of HAL_HASH_MD5_Start()
        • -
      • HAL_HASH_SHA1_Accmlt_End_IT() - to be used instead of HAL_HASH_SHA1_Start_IT()
        • -
      • HAL_HASH_MD5_Accmlt_End_IT() - to be used instead of HAL_HASH_MD5_Start_IT()
        • -
      • HAL_HASHEx_SHA224_Accmlt_End() - to be used instead of HAL_HASHEx_SHA224_Start()
        • -
      • HAL_HASHEx_SHA256_Accmlt_End() - to be used instead of HAL_HASHEx_SHA256_Start()
        • -
      -
    -
-
    -
      -
        -
      • HAL_HASHEx_SHA224_Accmlt_End_IT() - to be used instead of HAL_HASHEx_SHA224_Start_IT()
        • -
      • HAL_HASHEx_SHA256_Accmlt_End_IT() - to be used instead of HAL_HASHEx_SHA256_Start_IT()
        • -
      -
    -
-
    -
      -
    • MISRAC-2012 rule - R.5.1 (identifiers shall be distinct in the first 31 - characters) constrained the naming of the above listed - aliases (e.g. HAL_HASHEx_SHA256_Accmlt_End() - could not be named HAL_HASHEx_SHA256_Accumulate_End(). - Otherwise the name would have conflicted with HAL_HASHEx_SHA256_Accumulate_End_IT()). - In - order to have aligned names following APIs have been - renamed:
      • -
    -
-
    -
      -
        -
          -
        • HAL_HASH_MD5_Accumulate() - renamed HAL_HASH_MD5_Accmlt()
          • -
        • HAL_HASH_SHA1_Accumulate() - renamed HAL_HASH_SHA1_Accmlt()
          • -
        • HAL_HASHEx_SHA224_Accumulate() - renamed HAL_HASHEx_SHA224_Accmlt()
          • -
        -
      -
    -
-
    -
      -
        -
          -
        • HAL_HASHEx_SHA256_Accumulate() - renamed HAL_HASHEx_SHA256_Accmlt()
          • -
        -
      -
    -
-
    -
      -
    • HASH handler - state is no more - reset to HAL_HASH_STATE_READY once DMA has been started in - the following APIs:
      • -
        -
      • HAL_HASH_MD5_Start_DMA()
        • -
      • HAL_HMAC_MD5_Start_DMA()
        • -
      • HAL_HASH_SHA1_Start_DMA()
        • -
      • HAL_HMAC_SHA1_Start_DMA()
        • -
      -
    • HASH phase state - is now set to HAL_HASH_PHASE_READY once the digest has been read - in the following APIs:
      • -
        -
      • HASH_IT()
        • -
      • HMAC_Processing()
        • -
      • HASH_Start()
        • -
      • HASH_Finish()
        • -
      -
    • Case of a large buffer - scattered around in memory each piece of which is not - necessarily a multiple of 4 bytes in length.
      • -
        -
      • In section "##### - How to use this driver #####", sub-section "*** Remarks - on message length ***" added to provide recommendations to - follow in such case.
        • -
      • No modification of the - driver as the root-cause is at design-level.
        • -
      -
    -
-
    -
  • HAL CAN update
    • -
      -
    • HAL_CAN_GetRxMessage() update to get the - correct value for the RTR (type of frame for the message that - will be transmitted) field in the CAN_RxHeaderTypeDef - structure.
      • -
    -
  • HAL DCMI update
    • -
      -
    • Add new HAL_DCMI_ConfigSyncUnmask() - API to set embedded synchronization delimiters unmasks.
      • -
    -
  • HAL RTC - update
    • -
      -
    • Following IRQ handlers' - implementation has been aligned with the STM32Cube firmware - specification (in case of interrupt lines shared by multiple - events, first check the IT enable bit is set then check the IT flag - is set too):
      • -
        -
      • HAL_RTC_AlarmIRQHandler()
        • -
      • HAL_RTCEx_WakeUpTimerIRQHandler()
        • -
      • HAL_RTCEx_TamperTimeStampIRQHandler()
        • -
      -
    -
-
    -
  • HAL WWDG - update
    • -
      -
    • In "##### WWDG - Specific features #####" descriptive comment section:
      • -
        -
      • Maximal prescaler - value has been corrected (8 instead of 128).
        • -
      • Maximal APB frequency - has been corrected (42MHz instead of 56MHz) and possible timeout - values updated.
        • -
      -
    -
  • HAL DMA2D update
    • -
-
    -
      -
    • Add the following API's - to Start DMA2D CLUT Loading.
      • -
        -
      • HAL_DMA2D_CLUTStartLoad() - Start DMA2D CLUT Loading.
        • -
      • HAL_DMA2D_CLUTStartLoad_IT() - Start DMA2D CLUT Loading with interrupt enabled.
        • -
      -
    • The following old wrong - services will be kept in the HAL DCMI driver for legacy purpose and - a specific Note is added:
      • -
        -
      • HAL_DMA2D_CLUTLoad() - can be replaced with HAL_DMA2D_CLUTStartLoad()
        • -
      • HAL_DMA2D_CLUTLoad_IT() can - be replaced with HAL_DMA2D_CLUTStartLoad_IT()
        • -
      • HAL_DMA2D_ConfigCLUT() - can be omitted as the config can be performed using - the HAL_DMA2D_CLUTStartLoad() API.
        • -
      -
    -
-
    -
  • HAL SDMMC update
    • -
      -
    • Fix  typo in "FileFormatGroup" - parameter in the HAL_MMC_CardCSDTypeDef and HAL_SD_CardCSDTypeDef - structures 
      • -
    • Fix an - improve handle state and error management
      • -
    • Rename the defined MMC - card capacity type to be more meaningful:
      • -
        -
      • Update MMC_HIGH_VOLTAGE_CARD to - MMC LOW_CAPACITY_CARD
        • -
      • Update MMC_DUAL_VOLTAGE_CRAD - to MMC_HIGH_CAPACITY_CARD
        • -
      -
    • Fix management of - peripheral flags depending on commands or data transfers
      • -
        -
      • Add new defines - "SDIO_STATIC_CMD_FLAGS" and "SDIO_STATIC_DATA_FLAGS" 
        • -
      • Updates HAL SD and - HAL MMC drivers to manage the new SDIO static flags.
        -
        -
        • -
      -
    • Due to limitation - SDIO hardware flow control indicated in Errata Sheet:
      • -
        -
      • In 4-bits bus wide - mode, do not use the HAL_SD_WriteBlocks_IT() - or HAL_SD_WriteBlocks() - APIs otherwise underrun will occur and it isn't possible to - activate the flow control.
        • -
      • Use DMA mode when using - 4-bits bus wide mode or decrease the SDIO_CK frequency.
        • -
      -
    -
  • HAL UART update
    • -
      -
    • Update UART polling - processes to handle efficiently the Lock mechanism
      • -
        -
      •  Move the process - unlock at the top of the HAL_UART_Receive() - and HAL_UART_Transmit() - API.
        • -
      -
    • Fix baudrate - calculation error for clock higher than 172Mhz
      • -
        -
      • Add a forced cast on - UART_DIV_SAMPLING8() and UART_DIV_SAMPLING16() macros.
        • -
      • Remove useless - parenthesis from UART_DIVFRAQ_SAMPLING8(), - UART_DIVFRAQ_SAMPLING16(), UART_BRR_SAMPLING8() and - UART_BRR_SAMPLING16() macros to solve some MISRA warnings.
        • -
      -
    • Update UART interruption - handler to manage correctly the overrun interrupt
      • -
        -
      • Add in the HAL_UART_IRQHandler() - API a check on USART_CR1_RXNEIE bit when an overrun interrupt - occurs.
        • -
      -
    • Fix baudrate - calculation error UART9 and UART10
      • -
        -
      • In UART_SetConfig() - API fix UART9 and UART10 clock source when computing baudrate - values by adding a check on these instances and setting clock - sourcePCLK2 instead of PCLK1.
        • -
      -
    • Update UART_SetConfig() - API
      • -
        -
      • Split HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() macros from the UART_BRR_SAMPLING8() - and UART_BRR_SAMPLING8() macros 
        • -
      -
    -
  • HAL USART update
    • -
      -
    • Fix baudrate - calculation error for clock higher than 172Mhz
      • -
        -
      • Add a forced cast on - USART_DIV() - macro.
        • -
      • Remove - useless parenthesis from USART_DIVFRAQ() - macro to solve some MISRA warnings.
        • -
      -
    • Update USART - interruption handler to manage correctly the overrun interrupt
      • -
        -
      • Add in the HAL_USART_IRQHandler() - API a check on USART_CR1_RXNEIE bit when an overrun interrupt - occurs.
        • -
      -
    • Fix baudrate - calculation error UART9 and UART10
      • -
        -
      • In USART_SetConfig() - API fix UART9 and UART10 clock source when computing baudrate - values by adding a check on these instances and setting clock - sourcePCLK2 instead of PCLK1.
        • -
      -
    • Update USART_SetConfig() - API
      • -
        -
      • Split HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() macros from the USART_BRR() macro
        • -
      -
    -
  • HAL IRDA update
    • -
      -
    • Fix baudrate - calculation error for clock higher than 172Mhz
      • -
        -
      • Add a forced cast on - IRDA_DIV() - macro.
        • -
      • Remove - useless parenthesis from IRDA_DIVFRAQ() - macro to solve some MISRA warnings.
        • -
      -
    • Update IRDA interruption - handler to manage correctly the overrun interrupt
      • -
        -
      • Add in the HAL_IRDA_IRQHandler() - API a check on USART_CR1_RXNEIE bit when an overrun interrupt - occurs.
        • -
      -
    • Fix baudrate - calculation error UART9 and UART10
      • -
        -
      • In IRDA_SetConfig() - API fix UART9 and UART10 clock source when computing baudrate - values by adding a check on these instances and setting clock - sourcePCLK2 instead of PCLK1.
        • -
      -
    • Update IRDA_SetConfig() - API
      • -
        -
      • Split HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() macros from the IRDA_BRR() macro
        • -
      -
    -
  • HAL SMARTCARD update
    • -
      -
    • Fix baudrate - calculation error for clock higher than 172Mhz
      • -
        -
      • Add a forced cast on - SMARTCARD_DIV() - macro.
        • -
      • Remove useless parenthesis - from SMARTCARD_DIVFRAQ() - macro to solve some MISRA warnings.
        • -
      -
    • Update SMARTCARD - interruption handler to manage correctly the overrun interrupti
      • -
        -
      • Add in the HAL_SMARTCARD_IRQHandler() - API a check on USART_CR1_RXNEIE bit when an overrun interrupt - occurs.
        • -
      -
    • Update SMARTCARD_SetConfig() - API
      • -
        -
      • Split HAL_RCC_GetPCLK1Freq() - and HAL_RCC_GetPCLK2Freq() macros from the SMARTCARD_BRR() macro
        • -
      -
    -
  • HAL TIM update
    • -
      -
    • Add new macros to enable - and disable the fast mode when using the one pulse mode to output a - waveform with a minimum delay
      • -
        -
      • __HAL_TIM_ENABLE_OCxFAST() - and __HAL_TIM_DISABLE_OCxFAST().
        • -
      -
    • Update Encoder interface - mode to keep TIM_CCER_CCxNP - bits low
      • -
        -
      • Add TIM_ENCODERINPUTPOLARITY_RISING - and TIM_ENCODERINPUTPOLARITY_FALLING definitions to determine - encoder input polarity.
        • -
      • Add - IS_TIM_ENCODERINPUT_POLARITY() macro to - check the encoder input polarity.
        • -
      • Update HAL_TIM_Encoder_Init() - API 
        • -
          -
        • Replace IS_TIM_IC_POLARITY() - macro by IS_TIM_ENCODERINPUT_POLARITY() macro.
          • -
        -
      -
    • Update TIM remapping - input configuration in HAL_TIMEx_RemapConfig() - API
      • -
        -
      • Remove redundant check - on LPTIM_OR_TIM5_ITR1_RMP bit and replace it by check on - LPTIM_OR_TIM9_ITR1_RMP bit.
        • -
      -
    • Update HAL_TIMEx_MasterConfigSynchronization() - API to avoid functional errors and assert fails when using some TIM - instances as input trigger.
      • -
        -
      • Replace IS_TIM_SYNCHRO_INSTANCE() - macro by IS_TIM_MASTER_INSTANCE() macro. 
        • -
      • Add IS_TIM_SLAVE_INSTANCE() - macro to check on TIM_SMCR_MSM bit.
        • -
      -
    • Add lacking TIM input - remapping definition 
      • -
        -
      • Add LL_TIM_TIM11_TI1_RMP_SPDIFRX - and LL_TIM_TIM2_ITR1_RMP_ETH_PTP.
        • -
      • Add lacking definition - for linked LPTIM_TIM input trigger remapping  
        • -
          -
        • Add following definitions - : LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO, - LL_TIM_TIM9_ITR1_RMP_LPTIM, LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO, - LL_TIM_TIM5_ITR1_RMP_LPTIM, LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO and - LL_TIM_TIM1_ITR2_RMP_LPTIM.
          • -
        • Add a new mechanism in - LL_TIM_SetRemap() - API to remap TIM1, TIM9, and TIM5 input triggers mapped on - LPTIM register. 
          • -
        -
      -
    -
  • HAL LPTIM update
    • -
      -
    • Add a polling mechanism - to check on LPTIM_FLAG_XXOK flags in different API 
      • -
        -
      • Add  LPTIM_WaitForFlag() API to wait for flag - set.
        • -
      • Perform new checks on - HAL_LPTIM_STATE_TIMEOUT.
        • -
      -
    • Add lacking definitions - of LPTIM input trigger remapping and its related API
      • -
        -
          -
        • LL_LPTIM_INPUT1_SRC_PAD_AF, - LL_LPTIM_INPUT1_SRC_PAD_PA4, LL_LPTIM_INPUT1_SRC_PAD_PB9 and - LL_LPTIM_INPUT1_SRC_TIM_DAC.
          • -
        • Add a new API - LL_LPTIM_SetInput1Src() to access to the - LPTIM_OR register and remap the LPTIM input trigger.
          • -
        -
      -
    • Perform a new check on - indirect EXTI23 line associated to the LPTIM wake up timer
      • -
        -
      • Condition the use of - the LPTIM Wake-up Timer associated EXTI line configuration's - macros by EXTI_IMR_MR23 bit in different API :
        • -
          -
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE/DDISABLE_FALLING_EDGE()
          • -
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()
          • -
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() 
          • -
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()
          • -
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
          • -
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
          • -
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG()
          • -
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG()
          • -
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() 
          • -
        -
      • Update HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop_IT(), - HAL_LPTIM_Counter_Start_IT() - and HAL_LPTIM_Counter_Stop_IT() - API by adding Enable/Disable rising edge trigger on the LPTIM - Wake-up Timer Exti - line.
        • -
      • Add - __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() in - the end of the HAL_LPTIM_IRQHandler() - API conditioned by EXTI_IMR_MR23 bit.
        • -
      -
    -
  • HAL I2C update
    • -
      -
    • Update HAL_I2C_EV_IRQHandler() - API to fix I2C send break issue 
      • -
        -
      • Add additional check on - hi2c->hdmatx, - hdmatx->XferCpltCallback, - hi2c->hdmarx, - hdmarx->XferCpltCallback - in I2C_Master_SB() - API to avoid enabling DMA request when IT mode is used.
        • -
      -
    • Update HAL_I2C_ER_IRQHandler() - API to fix acknowledge failure issue with I2C memory IT processes
      • -
        -
      •  Add stop - condition generation when NACK occurs.
        • -
      -
    • Update HAL_I2C_Init() - API to force software reset before setting new I2C configuration
      • -
    • Update HAL I2C processes - to report ErrorCode - when wrong I2C start condition occurs
      • -
        -
      •  Add new ErrorCode - define: HAL_I2C_WRONG_START
        • -
      •  Set ErrorCode - parameter in I2C handle to HAL_I2C_WRONG_START
        • -
      -
    • Update I2C_DMAXferCplt(), - I2C_DMAError() and I2C_DMAAbort() APIs to fix hardfault - issue when hdmatx - and hdmarx parameters - in i2c handle aren't initialized (NULL pointer).
      • -
        -
      • Add additional check on - hi2c->hdmtx - and hi2c->hdmarx - before resetting DMA Tx/Rx complete callbacks
        • -
      -
    -
  • HAL FMPI2C update
    • -
      -
    • Fix HAL FMPI2C slave - interrupt handling issue with I2C sequential transfers.
      • -
        -
      • Update FMPI2C_Slave_ISR_IT() - and FMPI2C_Slave_ISR_DMA() APIs to check on STOP condition and - handle it before clearing the ADDR flag
        • -
      -
    -
  • HAL NAND update
    • -
      -
    • Update - HAL_NAND_Write_Page_8b(), HAL_NAND_Write_Page_16b() - and  HAL_NAND_Write_SpareArea_16b() to manage correctly the - time out condition.
      • -
    -
  • HAL SAI update
    • -
      -
    • Optimize SAI_DMATxCplt() - and SAI_DMARxCplt() - APIs to check on "Mode" parameter instead of CIRC - bit in the CR register.
      • -
    • Remove unused - SAI_FIFO_SIZE define
      • -
    • Update HAL_SAI_Receive_DMA() - programming sequence to be inline with - reference manual
      • -
    -
-

V1.7.6 / - 12-April-2019

-

Main Changes

-
    -
  • General updates to fix known defects and - enhancements implementation
    • -
  • HAL I2C update
    • -
      -
    • Fix I2C send break issue - in IT processes
      • -
        -
      • Add additional check on - hi2c->hdmatx - and hi2c->hdmarx to - avoid the DMA request enable when IT mode is used.
        • -
      -
    -
  • HAL SPI update
    • -
      -
    • Update to implement Erratasheet: - BSY bit may stay high at the end of a data transfer in Slave mode
      • -
    -
  • LL LPTIM update
    • -
      -
    • Fix compilation errors - with LL_LPTIM_WriteReg() - and LL_LPTIM_ReadReg() - macros
      • -
    -
  • HAL SDMMC update
    • -
      -
    • Fix preprocessing - compilation issue with SDIO STA STBITERR interrupt
      • -
    -
  • HAL/LL USB update
    • -
      -
    • Updated USB_WritePacket(), - USB_ReadPacket() - APIs to prevent compilation warning with GCC GNU v8.2.0
      • -
    • Rework USB_EPStartXfer() - API to enable the USB endpoint before unmasking the TX FiFo - empty interrupt in case DMA is not used
      • -
    • USB HAL_HCD_Init() - and HAL_PCD_Init() - APIs updated to avoid enabling USB DMA feature for OTG FS instance, - USB DMA feature is available only on OTG HS Instance
      • -
    • Remove duplicated line - in hal_hcd.c - header file comment section
      • -
    • Rework USB HAL driver to - use instance PCD_SPEED_xxx, - HCD_SPEED_xx - speeds instead of OTG register Core speed definition during the - instance initialization
      • -
    • Software Quality - improvement with a fix of CodeSonar - warning on PCD_Port_IRQHandler() - and  HCD_Port_IRQHandler() - interrupt handlers
      • -
    -
-

V1.7.5 / - 08-February-2019

-

Main Changes

-
    -
  • General updates to fix known defects and - enhancements implementation
    • -
  • General updates to fix CodeSonar - compilation warnings
    • -
  • General updates to fix SW4STM32 compilation - errors under Linux
    • -
  • General updates to fix the user manual .chm files
    • -
  • Add support of HAL callback registration feature
    • -
-
    -
  • Add new HAL EXTI - driver
    • -
  • Add new HAL SMBUS - driver
    • -
  • The following changes done on the HAL drivers - require an update on the application code based on older HAL versions
    • -
      -
    • Rework of HAL CRYP - driver (compatibility break)
      • -
        -
      • HAL CRYP driver has - been redesigned with new API's, to bypass limitations on data - Encryption/Decryption management present with previous HAL CRYP - driver version.
        • -
      • The new HAL CRYP driver - is the recommended version. It is located as usual in - Drivers/STM32F4xx_HAL_Driver/Src and - Drivers/STM32f4xx_HAL_Driver/Inc folders. It can be enabled - through switch HAL_CRYP_MODULE_ENABLED in stm32f4xx_hal_conf.h
        • -
      • The legacy HAL CRYP - driver is no longer supported.
        • -
      -
    • Add new AutoReloadPreload - field in TIM_Base_InitTypeDef - structure to allow the possibilities to enable or disable the - TIM Auto Reload Preload.
      • -
    -
-
    -
  • HAL/LL Generic update
    • -
      -
    • Add support of HAL - callback registration feature
      • -
        -
      • The feature disabled by - default is available for the following HAL drivers:
        • -
          -
        • ADC, CAN, CEC, CRYP, - DAC, DCMI, DFSDM, DMA2D, DSI, ETH, HASH, HCD, I2C, FMPI2C, SMBUS,
          - UART, USART, IRDA, SMARTCARD, LPTIM, LTDC, MMC, NAND, NOR, - PCCARD, PCD, QSPI, RNG,
          -           RTC, SAI, SD, SDRAM, - SRAM, SPDIFRX, SPI, I2S, TIM, and WWDG
          • -
        -
      • The feature may be - enabled individually per HAL PPP driver by setting the - corresponding definition USE_HAL_PPP_REGISTER_CALLBACKS - to 1U in stm32f4xx_hal_conf.h project configuration file (template - file stm32f4xx_hal_conf_template.h available from  Drivers/STM32F4xx_HAL_Driver/Inc)
        • -
      • Once enabled , - the user application may resort to HAL_PPP_RegisterCallback() - to register specific callback function(s) and unregister it(them) - with HAL_PPP_UnRegisterCallback().
        • -
      -
    • General updates to fix - MISRA 2012 compilation errors
      • -
        -
      • Replace HAL_GetUID() - API by HAL_GetUIDw0(), HAL_GetUIDw1() and HAL_GetUIDw2()
        • -
      • HAL_IS_BIT_SET()/HAL_IS_BIT_CLR() - macros implementation update
        • -
      • "stdio.h" - include updated with "stddef.h"
        • -
      -
    -
  • HAL GPIO  update
    • -
      -
    • Add missing define for - SPI3 alternate function "GPIO_AF5_SPI3" for STM32F401VE - devices
      • -
    • Remove - "GPIO_AF9_TIM14" from defined alternate function list for - STM32F401xx devices
      • -
    • HAL_GPIO_TogglePin() reentrancy robustness - improvement
      • -
    • HAL_GPIO_DeInit() API update to avoid - potential pending interrupt after call
      • -
    • Update GPIO_GET_INDEX() - API for more compliance with STM32F412Vx/STM32F412Rx/STM32F412Cx - devices
      • -
    • Update GPIO_BRR - registers with Reference Manual regarding registers and bit - definition values
      • -
    -
  • HAL CRYP - update
    • -
      -
    • The CRYP_InitTypeDef - is no more supported, - changed by CRYP_ConfigTypedef - to allow changing parameters using HAL_CRYP_setConfig() - API without reinitialize the CRYP IP using the HAL_CRYP_Init() - API
      • -
    • New parameters added in - the CRYP_ConfigTypeDef - structure: B0 and DataWidthUnit
      • -
    • Input data size - parameter is added in the CRYP_HandleTypeDef - structure
      • -
    • Add new APIs to manage - the CRYP configuration:
      • -
        -
      •  HAL_CRYP_SetConfig()
        • -
      • HAL_CRYP_GetConfig()
        • -
      -
    • Add new APIs to manage - the Key derivation:
      • -
        -
      • HAL_CRYPEx_EnableAutoKeyDerivation()
        • -
      • HAL_CRYPEx_DisableAutoKeyDerivation()
        • -
      -
    • Add new APIs to encrypt - and decrypt data:
      • -
        -
      • HAL_CRYP_Encypt()
        • -
      • HAL_CRYP_Decypt()
        • -
      • HAL_CRYP_Encypt_IT()
        • -
      • HAL_CRYP_Decypt_IT()
        • -
      • HAL_CRYP_Encypt_DMA()
        • -
      • HAL_CRYP_Decypt_DMA()
        • -
      -
    • Add new APIs to generate - TAG:
      • -
        -
      • HAL_CRYPEx_AESGCM_GenerateAuthTAG()
        • -
      • HAL_CRYPEx_AESCCM_Generago teAuthTAG()
        • -
      -
    -
  • HAL LPTIM update
    • -
      -
    • Remove useless LPTIM - Wakeup EXTI related macros from HAL_LPTIM_TimeOut_Start_IT() - API
      • -
    -
  • HAL I2C - update
    • -
      -
    • I2C API changes for - MISRA-C 2012 compliancy:
      • -
        -
      • Rename - HAL_I2C_Master_Sequential_Transmit_IT() to - HAL_I2C_Master_Seq_Transmit_IT()
        • -
      • Rename - HAL_I2C_Master_Sequentiel_Receive_IT() to - HAL_I2C_Master_Seq_Receive_IT()
        • -
      • Rename HAL_I2C_Slave_Sequentiel_Transmit_IT() - to HAL_I2C_Slave_Seq_Transmit_IT()
        • -
      • Rename - HAL_I2C_Slave_Sequentiel_Receive_DMA() to - HAL_I2C_Slave_Seq_Receive_DMA()
        • -
      -
    • SMBUS defined flags are - removed as not used by the HAL I2C driver
      • -
        -
      • I2C_FLAG_SMBALERT
        • -
      • I2C_FLAG_TIMEOUT
        • -
      • I2C_FLAG_PECERR
        • -
      • I2C_FLAG_SMBHOST
        • -
      • I2C_FLAG_SMBDEFAULT
        • -
      -
    • Add support of I2C - repeated start feature in DMA Mode:
      • -
        -
      • With the following new - API's
        • -
          -
        • HAL_I2C_Master_Seq_Transmit_DMA()
          • -
        • HAL_I2C_Master_Seq_Receive_DMA()
          • -
        • HAL_I2C_Slave_Seq_Transmit_DMA()
          • -
        • HAL_I2C_Slave_Seq_Receive_DMA()
          • -
        -
      -
    • Add new I2C transfer - options to easy manage the sequential transfers
      • -
        -
      • I2C_FIRST_AND_NEXT_FRAME
        • -
      • I2C_LAST_FRAME_NO_STOP
        • -
      • I2C_OTHER_FRAME
        • -
      • I2C_OTHER_AND_LAST_FRAME
        • -
      -
    -
  • HAL FMPI2C - update
    • -
      -
    • I2C API changes for - MISRA-C 2012 compliancy:
      • -
        -
      • Rename - HAL_FMPI2C_Master_Sequential_Transmit_IT() to - HAL_FMPI2C_Master_Seq_Transmit_IT()
        • -
      • Rename - HAL_FMPI2C_Master_Sequentiel_Receive_IT() to - HAL_FMPI2C_Master_Seq_Receive_IT()
        • -
      • Rename - HAL_FMPI2C_Master_Sequentiel_Transmit_DMA() to - HAL_FMPI2C_Master_Seq_Transmit_DMA()
        • -
      • Rename - HAL_FMPI2C_Master_Sequentiel_Receive_DMA() to - HAL_FMPI2C_Master_Seq_Receive_DMA()
        • -
      -
    • Rename FMPI2C_CR1_DFN to - FMPI2C_CR1_DNF for more compliance with Reference Manual regarding - registers and bit definition naming
      • -
    • Add support of I2C - repeated start feature in DMA Mode:
      • -
        -
      • With the following new - API's
        • -
          -
        • HAL_FMPI2C_Master_Seq_Transmit_DMA()
          • -
        • HAL_FMPI2C_Master_Seq_Receive_DMA()
          • -
        • HAL_FMPI2C_Slave_Seq_Transmit_DMA()
          • -
        • HAL_FMPI2C_Slave_Seq_Receive_DMA()
          • -
        -
      -
    -
  • HAL FLASH update
    • -
      -
    • Update the FLASH_OB_GetRDP() - API to return the correct RDP level
      • -
    -
  • HAL  RCC update
    • -
      -
    • Remove GPIOD CLK macros - for STM32F412Cx devices (X = D)
      • -
    • Remove GPIOE CLK macros - for STM32F412Rx\412Cx devices: (X = E)
      • -
    • Remove GPIOF/G CLK - macros for STM32F412Vx\412Rx\412Cx devices (X= F or G)
      • -
        -
      • __HAL_RCC_GPIOX_CLK_ENABLE()
        • -
      • __HAL_RCC_GPIOX_CLK_DISABLE()
        • -
      • __HAL_RCC_GPIOX_IS_CLK_ENABLED()
        • -
      • __HAL_RCC_GPIOX_IS_CLK_DISABLED()
        • -
      • __HAL_RCC_GPIOX_FORCE_RESET()
        • -
      -
    -
  • HAL RNG update
    • -
      -
    • Update to manage RNG - error code:
      • -
        -
      • Add ErrorCode - parameter in HAL RNG Handler structure
        • -
      -
    -
  • LL ADC update
    • -
      -
    • Add __LL_ADC_CALC_TEMPERATURE() - helper macro to calculate the temperature (unit: degree Celsius) from - ADC conversion data of internal temperature sensor.
      • -
    • Fix ADC channels - configuration issues on STM32F413xx/423xx devices
      • -
        -
      • To allow possibility to - switch between VBAT and TEMPERATURE channels configurations
        • -
      -
    • HAL_ADC_Start(), HAL_ADC_Start_IT() - and HAL_ADC_Start_DMA() - update to prevention from starting ADC2 or ADC3 once multimode is - enabled
      • -
    -
  • HAL DFSDM  update
    • -
      -
    • General updates to be - compliant with DFSDM bits naming used in CMSIS files.
      • -
    -
  • HAL CAN  update
    • -
      -
    • Update possible values - list for FilterActivation - parameter in CAN_FilterTypeDef - structure
      • -
        -
      • CAN_FILTER_ENABLE - instead of ENABLE
        • -
      • CAN_FILTER_DISABLE - instead of DISABLE
        • -
      -
    -
  • HAL CEC  update
    • -
      -
    • Update HAL CEC State - management method:
      • -
        -
      • Remove HAL_CEC_StateTypeDef - structure parameters
        • -
      • Add new defines for CEC - states
        • -
      -
    -
  • HAL DMA  update
    • -
      -
    • Add clean of callbacks - in HAL_DMA_DeInit() - API
      • -
    -
  • HAL DMA2D  update
    • -
      -
    • Remove unused - DMA2D_ColorTypeDef structure to be compliant with MISRAC 2012 Rule - 2.3
      • -
    • General update to use - dedicated defines for DMA2D_BACKGROUND_LAYER and - DMA2D_FOREGROUND_LAYER instead of numerical values: 0/1.
      • -
    -
  • HAL DSI  update
    • -
      -
    • Fix read multibyte - issue: remove extra call to __HAL_UNLOCK__ from DSI_ShortWrite() - API.
      • -
    -
-
    -
  • HAL/LL RTC update
    • -
-
    -
      -
    • HAL/ LL drivers - optimization
      • -
        -
      • HAL driver: remove - unused variables
        • -
      • LL driver: getter APIs - optimization
        • -
      -
    -
  • HAL PWR update
    • -
      -
    • Remove the followings - API's as feature not supported by STM32F469xx/479xx devices
      • -
        -
      • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
        • -
      • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
        • -
      -
    -
  • HAL SPI update
    • -
      -
    • Update HAL_SPI_StateTypeDef - structure to add new state: HAL_SPI_STATE_ABORT
      • -
    -
  • HAL/LL TIM update
    • -
      -
    • Add new AutoReloadPreload - field in TIM_Base_InitTypeDef - structure
      • -
        -
      • Refer to the TIM - examples to identify the changes
        • -
      -
    • Move the following TIM - structures from stm32f4xx_hal_tim_ex.h into stm32f4xx_hal_tim.h
      • -
        -
      • TIM_MasterConfigTypeDef
        • -
      • TIM_BreakDeadTimeConfigTypeDef
        • -
      -
    • Add new TIM Callbacks - API's:
      • -
        -
      • HAL_TIM_PeriodElapsedHalfCpltCallback()
        • -
      • HAL_TIM_IC_CaptureHalfCpltCallback()
        • -
      • HAL_TIM_PWM_PulseFinishedHalfCpltCallback()
        • -
      • HAL_TIM_TriggerHalfCpltCallback()
        • -
      -
    • TIM API changes for - MISRA-C 2012 compliancy:
      • -
        -
      • Rename HAL_TIM_SlaveConfigSynchronization - to HAL_TIM_SlaveConfigSynchro
        • -
      • Rename HAL_TIM_SlaveConfigSynchronization_IT - to HAL_TIM_SlaveConfigSynchro_IT
        • -
      • Rename HAL_TIMEx_ConfigCommutationEvent - to HAL_TIMEx_ConfigCommutEvent
        • -
      • Rename HAL_TIMEx_ConfigCommutationEvent_IT - to HAL_TIMEx_ConfigCommutEvent_IT
        • -
      • Rename HAL_TIMEx_ConfigCommutationEvent_DMA - to HAL_TIMEx_ConfigCommutEvent_DMA
        • -
      • Rename HAL_TIMEx_CommutationCallback - to HAL_TIMEx_CommutCallback
        • -
      • Rename HAL_TIMEx_DMACommutationCplt - to TIMEx_DMACommutationCplt
        • -
      -
    -
-
    -
  • HAL/LL USB - update
    • -
      -
    • Rework USB interrupt - handler and improve HS DMA support in Device mode
      • -
    • Fix BCD handling fr - OTG instance in device mode
      • -
    • cleanup reference to low - speed in device mode
      • -
    • allow writing TX FIFO in - case of transfer length is equal to available space in the TX FIFO
      • -
    • Fix Toggle OUT interrupt - channel in host mode
      • -
    • Update USB OTG max - number of endpoints (6 FS and 9 HS instead of 5 and 8)
      • -
    • Update USB OTG IP to - enable internal transceiver when starting USB device after - committee BCD negotiation
      • -
    -
  • LL IWDG update
    • -
      -
    • Update LL inline macros - to use IWDGx - parameter instead of IWDG instance defined in CMSIS device
      • -
    -
-

V1.7.4 / - 02-February-2018

-

Main Changes

-
    -
  • General updates to fix known defects and - enhancements implementation
    • -
  • HAL update
    • -
      -
    • Update UNUSED() - macro implementation to avoid GCC warning
      • -
        -
      • The warning is detected - when the UNUSED() - macro is called from C++ file
        • -
      -
    • Update to make RAMFUNC - define as generic type instead of HAL_StatusTypdef - type.
      • -
    -
  • HAL FLASH update
    • -
      -
    • Update - the prototypes of the following APIs after change on RAMFUNC defines 
      • -
        -
      • HAL_FLASHEx_StopFlashInterfaceClk()
        • -
      • HAL_FLASHEx_StartFlashInterfaceClk()
        • -
      • HAL_FLASHEx_EnableFlashSleepMode()
        • -
      • HAL_FLASHEx_DisableFlashSleepMode()
        • -
      -
    -
  • HAL SAI update
    • -
      -
    • Update HAL_SAI_DMAStop() - and HAL_SAI_Abort() - process to fix the lock/unlock audio issue
      • -
    -
-

V1.7.3 / - 22-December-2017

-

Main Changes

-
    -
  • General updates to fix known defects and - enhancements implementation
    • -
  • The following changes done on the HAL drivers - require an update on the application code based on older HAL versions
    • -
      -
    • Rework of HAL CAN driver - (compatibility break) 
      • -
        -
      • A new HAL CAN driver - has been redesigned with new APIs, to bypass limitations on CAN - Tx/Rx FIFO management present with previous HAL CAN driver - version.
        • -
      • The new HAL CAN driver - is the recommended version. It is located as usual in - Drivers/STM32F4xx_HAL_Driver/Src and - Drivers/STM32f4xx_HAL_Driver/Inc folders. It can be enabled - through switch HAL_CAN_MODULE_ENABLED in stm32f4xx_hal_conf.h
        • -
      • The legacy HAL CAN - driver is also present in the release in - Drivers/STM32F4xx_HAL_Driver/Src/Legacy and - Drivers/STM32F4xx_HAL_Driver/Inc/Legacy folders for software - compatibility reasons. Its usage is not recommended as - deprecated. It can however be enabled through switch - HAL_CAN_LEGACY_MODULE_ENABLED in stm32f4xx_hal_conf.h
        • -
      -
    -
  • HAL update
    • -
      -
    • Update HAL driver to - allow user to change systick period to 1ms, 10 ms - or 100 ms - :
      • -
        -
      • Add the following API's :  
        • -
          -
        • HAL_GetTickPrio(): Returns a tick - priority.
          • -
        • HAL_SetTickFreq(): Sets new - tick frequency.
          • -
        • HAL_GetTickFreq(): Returns tick - frequency.
          • -
        -
      • Add HAL_TickFreqTypeDef - enumeration for the different Tick Frequencies: 10 Hz, 100 Hz and - 1KHz (default).
        • -
      -
    -
  • HAL CAN update
    • -
      -
    • Fields of CAN_InitTypeDef - structure are reworked:
      • -
        -
      • SJW to SyncJumpWidth, - BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to TimeTriggeredMode, - ABOM to AutoBusOff, - AWUM to AutoWakeUp, - NART to AutoRetransmission - (inversed), RFLM to ReceiveFifoLocked and TXFP to TransmitFifoPriority
        • -
      -
    • HAL_CAN_Init() is split into both HAL_CAN_Init() - and HAL_CAN_Start() - API's
      • -
    • HAL_CAN_Transmit() is replaced by HAL_CAN_AddTxMessage() - to place Tx Request, then HAL_CAN_GetTxMailboxesFreeLevel() - for polling until completion.
      • -
    • HAL_CAN_Transmit_IT() is replaced by HAL_CAN_ActivateNotification() - to enable transmit IT, then HAL_CAN_AddTxMessage() - for place Tx request.
      • -
    • HAL_CAN_Receive() is replaced by HAL_CAN_GetRxFifoFillLevel() - for polling until reception, then HAL_CAN_GetRxMessage() -
      - to get Rx message.
      • -
    • HAL_CAN_Receive_IT() is replaced by HAL_CAN_ActivateNotification() to - enable receive IT, then HAL_CAN_GetRxMessage()
      - in the receivecallback - to get Rx message
      • -
    • HAL_CAN_Slepp() is renamed as HAL_CAN_RequestSleep()
      • -
    • HAL_CAN_TxCpltCallback() is split into - HAL_CAN_TxMailbox0CompleteCallback(), - HAL_CAN_TxMailbox1CompleteCallback() - and HAL_CAN_TxMailbox2CompleteCallback().
      • -
    • HAL_CAN_RxCpltCallback is split into - HAL_CAN_RxFifo0MsgPendingCallback() - and HAL_CAN_RxFifo1MsgPendingCallback().
      • -
    • More complete "How - to use the new driver" is detailed in the driver header - section itself.
      • -
    -
  • HAL FMPI2C update
    • -
      -
    • Add new option - FMPI2C_LAST_FRAME_NO_STOP for the sequential transfer management
      • -
        -
      • This option allows to - manage a restart condition after several call of the same master - sequential interface. 
        • -
      -
    -
  • HAL RCC update
    • -
      -
    • Add new HAL macros
      • -
        -
      • __HAL_RCC_GET_RTC_SOURCE() - allowing to get the RTC clock source
        • -
      • __HAL_RCC_GET_RTC_HSE_PRESCALER() - allowing to get the HSE clock divider for RTC peripheral
        • -
      -
    • Ensure reset of CIR and - CSR registers when issuing HAL_RCC_DeInit()/LL_RCC_DeInit - functions
      • -
    • Update HAL_RCC_OscConfig() to - keep backup domain enabled when configuring respectively LSE - and RTC clock source
      • -
    • Add new HAL interfaces - allowing to control the activation or deactivation of PLLI2S and - PLLSAI:
      • -
        -
      • HAL_RCCEx_EnablePLLI2S()
        • -
      • HAL_RCCEx_DisablePLLI2S()
        • -
      • HAL_RCCEx_EnablePLLSAI()
        • -
      • HAL_RCCEx_DisablePLLSAI()
        • -
      -
    -
-
    -
  • LL RCC - update 
    • -
      -
    • Add new LL RCC macro
      • -
        -
      • LL_RCC_PLL_SetMainSource() allowing to configure - PLL main clock source
        • -
      -
    -
  • LL FMC / LL FSMC update
    • -
      -
    • Add clear of the PTYP - bit to select the PCARD mode in FMC_PCCARD_Init() - / FSMC_PCCARD_Init()
      • -
    -
-

V1.7.2 / - 06-October-2017

-

Main Changes

-
    -
  • General updates to fix known defects and - enhancements implementation
    • -
  • Fix compilation warning with GCC compiler
    • -
  • Remove Date and version from header files
    • -
  • Update HAL drivers to refer to the new CMSIS - bit position defines instead of usage the POSITION_VAL() - macro
    • -
  • HAL Generic update
    • -
      -
    • stm32f4xx_hal_def.h file - changes: 
      • -
        -
      • Update __weak and - __packed defined values for ARM compiler
        • -
      • Update __ALIGN_BEGIN - and __ALIGN_END defined values for ARM compiler
        • -
      -
    • stm32f4xx_ll_system.h - file: add LL_SYSCFG_REMAP_SDRAM define
      • -
    -
  • HAL ADC update
    • -
      -
    • Fix wrong definition of - ADC channel temperature sensor for STM32F413xx and STM32F423xx - devices.
      • -
    -
  • HAL DMA update
    • -
      -
    • Update values for - the following defines: DMA_FLAG_FEIF0_4 and DMA_FLAG_DMEIF0_4 
      • -
    -
  • HAL DSI update
    • -
      -
    • Fix Extra warning with - SW4STM32 compiler
      • -
    • Fix DSI display issue - when using EWARM w/ high level optimization 
      • -
    • Fix MISRAC errors
      • -
    -
  • HAL FLASH update
    • -
      -
    • HAL_FLASH_Unlock() update to return state - error when the FLASH is already unlocked
      • -
    -
  • HAL FMPI2C update
    • -
      -
    • Update Interface APIs - headers to remove confusing message about device address
      • -
    • Update FMPI2C_WaitOnRXNEFlagUntilTimeout() - to resolve a race condition between STOPF and RXNE Flags
      • -
    • Update FMPI2C_TransferConfig() - to fix wrong bit management.
      • -
    • Update code comments to - use DMA stream instead of DMA channel
      • -
    -
-
    -
  • HAL PWR update
    • -
      -
    • HAL_PWR_EnableWakeUpPin() update description to - add support of PWR_WAKEUP_PIN2 and PWR_WAKEUP_PIN3
      • -
    -
  • HAL NOR update
    • -
      -
    • Add the support of - STM32F412Rx devices
      • -
    -
  • HAL I2C update
    • -
      -
    • Update Interface APIs - headers to remove confusing mesage about - device address
      • -
    • Update - I2C_MasterReceive_RXNE() - and I2C_MasterReceive_BTF() static APIs to fix bad Handling of NACK - in I2C master receive process.
      • -
    -
-
    -
  • HAL RCC update
    • -
      -
    • Update HAL_RCC_GetOscConfig() - API to:
      • -
        -
      • set PLLR in the RCC_OscInitStruct
        • -
      • check on null pointer
        • -
      -
    • Update HAL_RCC_ClockConfig() - API to:
      • -
        -
      • check on null pointer
        • -
      • optimize code size - by updating the handling method of the SWS bits
        • -
      • update to use  - __HAL_FLASH_GET_LATENCY() flash macro instead of - using direct register access to LATENCY bits in FLASH ACR - register.
        • -
      -
    • Update HAL_RCC_DeInit() -  and LL_RCC_DeInit() - APIs to
      • -
        -
      • Be able to return - HAL/LL status
        • -
      • Add checks for HSI, PLL - and PLLI2S -  ready before modifying RCC CFGR registers
        • -
      • Clear all interrupt falgs
        • -
      • Initialize systick - interrupt period
        • -
      -
    • Update HAL_RCC_GetSysClockFreq() - to avoid risk of rounding error which may leads to a wrong returned - value. 
      • -
    -
-

 

-

 

-
    -
  • HAL RNG update
    • -
      -
    • HAL_RNG_Init() remove Lock()/Unlock()
      • -
    -
  • HAL MMC update
    • -
      -
    • HAL_MMC_Erase() API: add missing - () to fix compilation warning detected with SW4STM32 when - extra feature is enabled.
      • -
    -
  • HAL RTC update
    • -
      -
    • HAL_RTC_Init() API: update to force - the wait for synchro before setting TAFCR register when BYPSHAD bit - in CR register is 0.
      • -
    -
  • HAL SAI update
    • -
      -
    • Update HAL_SAI_DMAStop() - API to flush fifo - after disabling SAI
      • -
    -
  • HAL I2S update
    • -
      -
    • Update I2S DMA - fullduplex process to handle I2S Rx and Tx DMA Half transfer - complete callback
      • -
    -
  • HAL TIM update
    • -
      -
    • Update HAL_TIMEx_OCN_xxxx() - and HAL_TIMEx_PWMN_xxx() - API description to remove support of TIM_CHANNEL_4
      • -
    -
  • LL DMA update
    • -
      -
    • Update to clear DMA - flags using WRITE_REG() - instead SET_REG() API to avoid read access to the IFCR register - that is write only.
      • -
    -
  • LL RTC update
    • -
      -
    • Fix warning with static analyzer
      • -
    -
  • LL USART update
    • -
      -
    • Add assert macros to - check USART BaudRate - register
      • -
    -
  • LL I2C update
    • -
      -
    • Rename IS_I2C_CLOCK_SPEED() - and IS_I2C_DUTY_CYCLE() respectively to IS_LL_I2C_CLOCK_SPEED() and - IS_LL_I2C_DUTY_CYCLE() to avoid incompatible macros redefinition.
      • -
    -
  • LL TIM update
    • -
      -
    • Update LL_TIM_EnableUpdateEvent() - API to clear UDIS bit in TIM CR1 register instead of setting it.
      • -
    • Update LL_TIM_DisableUpdateEvent() - API to set UDIS bit in TIM CR1 register instead of clearing it.
      • -
    -
  • LL USART update
    • -
      -
    • Fix MISRA error w/ - IS_LL_USART_BRR() - macro
      • -
    • Fix wrong check when - UART10 instance is used
      • -
    -
-

V1.7.1 / - 14-April-2017

-

Main Changes

-
    -
  • Update CHM UserManuals - to support LL drivers
    • -
  • General updates to fix known defects and - enhancements implementation
    • -
  • HAL CAN update
    • -
      -
    • Add management - of overrun error. 
      • -
    • Allow possibility to - receive messages from the 2 RX FIFOs in parallel via interrupt.
      • -
    • Fix message lost - issue with specific sequence of transmit requests.
      • -
    • Handle transmission - failure with error callback, when NART is enabled.
      • -
    • Add __HAL_CAN_CANCEL_TRANSMIT() - call to abort transmission when timeout is reached
      • -
    -
-
    -
  • HAL PWR update
    • -
      -
    • HAL_PWREx_EnterUnderDriveSTOPMode() API: remove check on - UDRDY flag
      • -
    -
-
    -
  • LL ADC update
    • -
      -
    • Fix wrong ADC group - injected sequence configuration
      • -
        -
      • LL_ADC_INJ_SetSequencerRanks() and LL_ADC_INJ_GetSequencerRanks() - API's update to take in consideration the ADC number of - conversions
        • -
      • Update the defined - values for ADC group injected seqencer ranks 
        • -
      -
    -
-

V1.7.0 / - 17-February-2017

-

Main Changes

-
    -
  • Add Low Layer drivers allowing performance and - footprint optimization
    • -
      -
    • Low Layer drivers - APIs provide register level programming: require deep knowledge of - peripherals described in STM32F4xx Reference Manuals
      • -
    • Low Layer drivers are - available for: ADC, Cortex, CRC, DAC, DMA, DMA2D, EXTI, GPIO, - I2C, IWDG, LPTIM, PWR, RCC, RNG, RTC, SPI, TIM, USART, WWDG - peripherals and additionnal - Low Level Bus, System and Utilities APIs.
      • -
    • Low Layer drivers - APIs are implemented as static inline function in new Inc/stm32f4xx_ll_ppp.h files - for PPP peripherals, there is no configuration file and each stm32f4xx_ll_ppp.h file - must be included in user code.
      • -
    -
  • General updates to fix known defects and - enhancements implementation
    • -
  • Fix extra warnings with GCC compiler
    • -
  • HAL drivers clean up: remove double casting - 'uint32_t' and 'U'
    • -
  • Add new HAL MMC driver
    • -
  • The following changes done on the HAL drivers - require an update on the application code based on older HAL versions
    • -
      -
    • HAL SD update
      • -
        -
      • Overall rework of the - driver for a more efficient implementation
        • -
          -
        • Modify initialization - API and structures
          • -
        • Modify Read / Write - sequences: separate transfer process and SD Cards state management 
          • -
        • Adding interrupt mode - for Read / Write operations
          • -
        • Update the HAL_SD_IRQHandler - function by optimizing the management of interrupt errors
          • -
        -
      • Refer to the following - example to identify the changes: BSP example and USB_Device/MSC_Standalone - application
        • -
      -
    • HAL NAND update
      • -
        -
      • Modify NAND_AddressTypeDef, - NAND_DeviceConfigTypeDef - and NAND_HandleTypeDef - structures fields
        • -
      • Add new HAL_NAND_ConfigDevice - API
        • -
      -
    • HAL DFSDM update
      • -
        -
      • Add support of Multichannel - Delay feature
        • -
          -
        • Add HAL_DFSDM_ConfigMultiChannelDelay - API
          • -
        • The following APIs are - moved to internal static functions: HAL_DFSDM_ClockIn_SourceSelection, - HAL_DFSDM_ClockOut_SourceSelection, - HAL_DFSDM_DataInX_SourceSelection - (X=0,2,4,6), HAL_DFSDM_BitStreamClkDistribution_Config
          • -
        -
      -
    • HAL I2S - update
      • -
        -
      • Add specific - callback API to manage I2S full duplex end of transfer process:
        • -
          -
        • HAL_I2S_TxCpltCallback() - and HAL_I2S_RxCpltCallback() API's will be replaced with only - HAL_I2SEx_TxRxCpltCallback() API. 
          • -
        -
      -
    -
  • HAL update
    • -
      -
    • Modifiy default HAL_Delay - implementation to guarantee minimum delay 
      • -
    -
  • HAL Cortex - update
    • -
      -
    • Move HAL_MPU_Disable() - and HAL_MPU_Enable() - from stm32f4xx_hal_cortex.h to stm32f4xx_hal_cortex.c
      • -
    • Clear the whole MPU - control register in HAL_MPU_Disable() - API
      • -
    -
  • HAL FLASH - update
    • -
      -
    • IS_FLASH_ADDRESS() - macro update to support OTP range
      • -
    • FLASH_Program_DoubleWord(): Replace 64-bit - accesses with 2 double-words operations
      • -
    -
  • LL GPIO - update
    • -
      -
    • Update IS_GPIO_PIN() - macro implementation to be more safe
      • -
    -
  • LL RCC - update
    • -
      -
    • Update IS_RCC_PLLQ_VALUE() - macro implementation: the minimum accepted value is 2 instead - of 4
      • -
    • Rename - RCC_LPTIM1CLKSOURCE_PCLK define to RCC_LPTIM1CLKSOURCE_PCLK1
      • -
    • Fix compilation issue w/ - __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() - and __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() macros for STM32F401xx - devices
      • -
    • Add the - following is clock enabled macros for STM32F401xx devices
      • -
        -
      •  __HAL_RCC_SDIO_IS_CLK_ENABLED()
        • -
      • __HAL_RCC_SPI4_IS_CLK_ENABLED()
        • -
      • __HAL_RCC_TIM10_IS_CLK_ENABLED()
        • -
      -
    • Add the - following is clock enabled macros for STM32F410xx devices
      • -
        -
      •  __HAL_RCC_CRC_IS_CLK_ENABLED()
        • -
      • __HAL_RCC_RNG_IS_CLK_ENABLED()
        • -
      -
    • Update HAL_RCC_DeInit() - to reset the RCC clock configuration to the default reset state.
      • -
    • Remove macros to - configure BKPSRAM from STM32F401xx devices 
      • -
    • Update to refer to AHBPrescTable[] - and APBPrescTable[] - tables defined in system_stm32f4xx.c file instead of APBAHBPrescTable[] - table.
      • -
    -
  • HAL FMPI2C - update
    • -
      -
    • Add FMPI2C_FIRST_AND_NEXT_FRAME - define in Sequential Transfer Options
      • -
    -
  • HAL ADC update
    • -
      -
    • HAL_ADCEx_InjectedConfigChannel(): update the external - trigger injected condition
      • -
    -
  • HAL DMA update
    • -
      -
    • HAL_DMA_Init(): update to check - compatibility between FIFO threshold level and size of the memory - burst 
      • -
    -
  • HAL QSPI update
    • -
      -
    • QSPI_HandleTypeDef structure: Update - transfer parameters on uint32_t instead of uint16_t
      • -
    -
  • HAL UART/USART/IrDA/SMARTCARD update
    • -
      -
    • DMA Receive process; the - code has been updated to clear the USART OVR flag before enabling DMA - receive request.
      • -
    • UART_SetConfig() update to manage - correctly USART6 instance that is not available on STM32F410Tx - devices
      • -
    -
  • HAL CAN update
    • -
      -
    • Remove Lock mechanism - from HAL_CAN_Transmit_IT() - and HAL_CAN_Receive_IT() - processes
      • -
    -
  • HAL TIM update
    • -
      -
    • Add - __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() macro to - disable Master output without check on TIM channel state. 
      • -
    • Update HAL_TIMEx_ConfigBreakDeadTime() - to fix TIM BDTR register corruption.
      • -
    -
  • HAL I2C update
    • -
      -
    • Update HAL_I2C_Master_Transmit() - and HAL_I2C_Slave_Transmit() to avoid sending extra bytes at - the end of the transmit processes
      • -
    • Update HAL_I2C_Mem_Read() - API to fix wrong check on misused parameter �Size�
      • -
    • Update - I2C_MasterReceive_RXNE() - and I2C_MasterReceive_BTF() static APIs to enhance Master - sequential reception process.
      • -
    -
  • HAL SPI update
    • -
      -
    • Add transfer abort - APIs and associated callbacks in interrupt mode
      • -
        -
      • HAL_SPI_Abort()
        • -
      • HAL_SPI_Abort_IT()
        • -
      • HAL_SPI_AbortCpltCallback()
        • -
      -
    -
  • HAL I2S update
    • -
      -
    • Add specific - callback API to manage I2S full duplex end of transfer process:
      • -
        -
      • HAL_I2S_TxCpltCallback() - and HAL_I2S_RxCpltCallback() API's will be replaced with only - HAL_I2SEx_TxRxCpltCallback() API. 
        • -
      -
    • Update I2S - Transmit/Receive polling process to manage Overrun and - Underrun errors
      • -
    • Move the I2S clock - input frequency calculation to HAL RCC driver.
      • -
    • Update the HAL I2SEx - driver to keep only full duplex feature.
      • -
    • HAL_I2S_Init() - API updated to
      • -
        -
      • Fix wrong I2S clock - calculation when PCM mode is used.
        • -
      • Return state HAL_I2S_ERROR_PRESCALER when - the I2S clock is wrongly configured
        • -
      -
    -
-
    -
  • HAL LTDC update
    • -
      -
    • Optimize HAL_LTDC_IRQHandler() - function by using direct register read
      • -
    • Rename the following API's
      • -
        -
      • HAL_LTDC_Relaod() by HAL_LTDC_Reload() 
        • -
      • HAL_LTDC_StructInitFromVideoConfig() by HAL_LTDCEx_StructInitFromVideoConfig()
        • -
      • HAL_LTDC_StructInitFromAdaptedCommandConfig() by HAL_LTDCEx_StructInitFromAdaptedCommandConfig()
        • -
      -
    • Add new defines for LTDC - layers (LTDC_LAYER_1 / LTDC_LAYER_2)
      • -
    • Remove unused asserts
      • -
    -
  • HAL USB - PCD update
    • -
      -
    • Flush all TX FIFOs on - USB Reset
      • -
    • Remove Lock mechanism - from HAL_PCD_EP_Transmit() - and HAL_PCD_EP_Receive() - API's
      • -
    -
-
    -
  • LL USB - update
    • -
      -
    • Enable DMA Burst mode - for USB OTG HS
      • -
    • Fix SD card detection issue
      • -
    -
  • LL SDMMC update
    • -
      -
    • Add new SDMMC_CmdSDEraseStartAdd, - SDMMC_CmdSDEraseEndAdd, - SDMMC_CmdOpCondition - and SDMMC_CmdSwitch - functions
      • -
    -
-

V1.6.0 / - 04-November-2016

-

Main Changes

-
    -
  • Add support of STM32F413xx - and STM32F423xx devices
    • -
  • General updates to fix known defects and - enhancements implementation
    • -
  • HAL CAN - update
    • -
      -
    • Update to add the - support of 3 CAN management
      • -
    -
  • HAL CRYP - update
    • -
      -
    • Update to add the - support of AES features
      • -
    -
  • HAL DFSDM - update
    • -
      -
    • Add definitions for new - external trigger filters
      • -
    • Add definition for new - Channels 4, 5, 6 and 7
      • -
    • Add - functions and API for Filter state configuration and management
      • -
    • Add new functions: 
      • -
        -
      • HAL_DFSDM_BitstreamClock_Start()
        • -
      • HAL_DFSDM_BitstreamClock_Stop()
        • -
      • HAL_DFSDM_BitStreamClkDistribution_Config() 
        • -
      -
    -
  • HAL DMA
    • -
      -
    • Add the support of DMA - Channels from 8 to 15
      • -
    • Update HAL_DMA_DeInit() - function with the check on DMA stream instance
      • -
    -
  • HAL DSI update
    • -
-
    -
      -
    • Update HAL_DSI_ConfigHostTimeouts() - and HAL_DSI_Init() - functions to avoid scratch in DSI_CCR register
      • -
    -
  • HAL FLASH - update
    • -
      -
    • Enhance FLASH_WaitForLastOperation() - function implementation
      • -
    • Update __HAL_FLASH_GET_FLAG() - macro implementation
      • -
    -
  • HAL GPIO update
    • -
      -
    • Add specific alternate - functions definitions
      • -
    -
  • HAL I2C update
    • -
      -
    • Update I2C_DMAError() - function implementation to ignore DMA FIFO error
      • -
    -
  • HAL I2S update
    • -
      -
    • Enhance HAL_I2S_Init() - implementation to test on PCM_SHORT and PCM_LONG standards
      • -
    -
  • HAL IRDA update
    • -
      -
    • Add new functions and - call backs for Transfer Abort
      • -
        -
      • HAL_IRDA_Abort()
        • -
      • HAL_IRDA_AbortTransmit()
        • -
      • HAL_IRDA_AbortReceive()
        • -
      • HAL_IRDA_Abort_IT()
        • -
      • HAL_IRDA_AbortTransmit_IT()
        • -
      • HAL_IRDA_AbortReceive_IT()
        • -
      • HAL_IRDA_AbortCpltCallback()
        • -
      • HAL_IRDA_AbortTransmitCpltCallback()
        • -
      -
    -
-
    -
      -
        -
      • HAL_IRDA_AbortReceiveCpltCallback()
        • -
      -
    -
  • HAL PCD - update
    • -
-
    -
      -
    • Update HAL_PCD_GetRxCount() -  function implementation
      • -
    -
  • HAL RCC update
    • -
      -
    • Update __HAL_RCC_HSE_CONFIG() - macro implementation
      • -
    • Update __HAL_RCC_LSE_CONFIG() macro implementation
      • -
    -
  • HAL SMARTCARD update
    • -
-
    -
      -
    • Add new functions and - call backs for Transfer Abort
      • -
        -
      • HAL_ SMARTCARD_Abort()
        • -
      • HAL_ SMARTCARD_AbortTransmit()
        • -
      • HAL_ SMARTCARD_AbortReceive()
        • -
      • HAL_ SMARTCARD_Abort_IT()
        • -
      • HAL_ SMARTCARD_AbortTransmit_IT()
        • -
      • HAL_ SMARTCARD_AbortReceive_IT()
        • -
      • HAL_ SMARTCARD_AbortCpltCallback()
        • -
      • HAL_ SMARTCARD_AbortTransmitCpltCallback()
        • -
      • HAL_ SMARTCARD_AbortReceiveCpltCallback()
        • -
      -
    -
  • HAL TIM update
    • -
      -
    • Update HAL_TIMEx_RemapConfig() - function to manage TIM internal trigger remap: LPTIM or TIM3_TRGO
      • -
    -
  • HAL UART update
    • -
      -
    • Add Transfer abort - functions and callbacks
      • -
    -
  • HAL USART update
    • -
      -
    • Add Transfer abort - functions and callbacks
      • -
    -
-

V1.5.2 / - 22-September-2016

-

Main Changes

-
    -
  • HAL I2C - update
    • -
      -
    • Fix wrong behavior in - consecutive transfers in case of single byte transmission - (Master/Memory Receive
      - interfaces)
      • -
    • Update - HAL_I2C_Master_Transmit_DMA() / - HAL_I2C_Master_Receive_DMA()/ HAL_I2C_Slave_Transmit_DMA()
      - and HAL_I2C_Slave_Receive_DMA() to manage addressing phase through - interruption instead of polling
      • -
    • Add a check on I2C - handle state at start of all I2C API's to ensure that I2C is ready
      • -
    • Update I2C API's - (Polling, IT and DMA interfaces) to manage I2C XferSize - and XferCount - handle parameters instead of API size parameter to help user to get - information of counter in case of error. 
      • -
    • Update Abort - functionality to manage DMA use case
      • -
    -
  • HAL FMPI2C - update
    • -
      -
    • Update to disable Own - Address - before setting the new Own Address configuration:
      • -
        -
      • Update HAL_FMPI2C_Init() - to disable FMPI2C_OARx_EN bit before any configuration in OARx - registers
        • -
      -
    -
  • HAL CAN update
    • -
      -
    • Update CAN receive - processes to set CAN RxMsg FIFONumber - parameter
      • -
    -
  • HAL UART update
    • -
      -
    • Update UART handle TxXferCount - and RxXferCount parameters - as volatile to avoid eventual issue with High - Speed optimization  
      • -
    -
-

V1.5.1 / - 01-July-2016

-

Main Changes

-
    -
  • HAL GPIO - update
    • -
      -
    • HAL_GPIO_Init()/HAL_GPIO_DeInit() - API's: update GPIO_GET_INDEX() macro implementation to support - all GPIO's
      • -
    -
  • HAL SPI - update
    • -
      -
    • Fix regression issue: - retore HAL_SPI_DMAPause() - and HAL_SPI_DMAResume() API's
      • -
    - -
  • HAL RCC - update
    • -
      -
    • Fix FSMC macros - compilation warnings with STM32F412Rx devices
      • -
    -
  • HAL DMA update
    • -
      -
    • HAL_DMA_PollFortransfer() API clean up
      -
      -
      • -
    -
  • HAL PPP update(PPP - refers to IRDA, UART, USART and SMARTCARD)
    • -
      -
    • Update HAL_PPP_IRQHandler() - to add a check on interrupt source before managing the error 
      • -
    -
-
    -
  • HAL QSPI update
    • -
      -
    • Implement workaround to - fix the limitation pronounced in the Errata sheet 2.1.8 section: In - some specific cases, DMA2 data corruption occurs when managing AHB - and APB2 peripherals in a concurrent way
      • -
    -
-

V1.5.0 / - 06-May-2016

-

Main Changes

-
    -
  • Add support of STM32F412cx, - STM32F412rx, STM32F412vx and STM32F412zx devices
    • -
  • General updates to fix known defects and - enhancements implementation
    • -
  • Add new HAL driver for DFSDM peripheral
    • -
  • Enhance HAL delay and time base implementation:
    • -
      -
    • Add new drivers - stm32f4xx_hal_timebase_rtc_alarm_template.c and - stm32f4xx_hal_timebase_rtc_wakeup_template.c which override the - native HAL time base functions (defined as weak) to either use the - RTC as time base tick source. For more details about the usage of these - drivers, please refer to HAL\HAL_TimeBase_RTC - examples and - FreeRTOS-based - applications
      • -
    -
  • The following changes done on the HAL drivers - require an update on the application code based on HAL V1.4.4
    • -
      -
    • HAL UART, USART, IRDA, - SMARTCARD, SPI, I2C,FMPI2C, - QSPI (referenced as PPP here - below) drivers
      • -
        -
      • Add PPP error - management during DMA process. This requires the following updates - on user application:
        • -
          -
        • Configure and enable - the PPP IRQ in HAL_PPP_MspInit() - function
          • -
        • In stm32f4xx_it.c - file, PPP_IRQHandler() - function: add - a call to HAL_PPP_IRQHandler() - function
          • -
        • Add and customize the - Error Callback API: HAL_PPP_ErrorCallback()
          • -
        -
      -
    • HAL I2C, - FMPI2C (referenced - as PPP here - below) drivers:
      • -
        -
      • Update to avoid waiting - on STOPF/BTF/AF - flag under DMA ISR by using the PPP end - of transfer interrupt in the DMA transfer process. This - requires the following updates on user application:
        • -
          -
        • Configure and enable - the PPP IRQ in HAL_PPP_MspInit() - function
          • -
        • In stm32f4xx_it.c - file, PPP_IRQHandler() - function: add - a call to HAL_PPP_IRQHandler() - function
          • -
        -
      -
    • HAL I2C driver:
      • -
        -
      • I2C transfer processes - IT update: NACK during addressing phase is managed through I2C - Error interrupt instead of HAL state
        • -
      -
    -
-
    -
      -
    • HAL IWDG driver: rework overall - driver for better implementation
      • -
        -
      • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() - and HAL_IWDG_GetState() APIs
        • -
      -
    • HAL WWDG driver: rework overall - driver for better implementation
      • -
        -
      • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() - and HAL_WWDG_GetState() - APIs 
        • -
      • Update the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, - uint32_t counter)  function and API  by removing the -  "counter" parameter
        • -
      -
    • HAL QSPI driver:  Enhance the DMA - transmit process by using PPP TC interrupt instead of - waiting on TC flag under DMA ISR. This requires the following - updates on user application:
      • -
        -
      • Configure and enable - the QSPI IRQ in HAL_QSPI_MspInit() - function
        • -
      • In stm32f4xx_it.c - file, QSPI_IRQHandler() - function: add a call to HAL_QSPI_IRQHandler() - function
        • -
      -
    • HAL CEC driver:  Overall driver - rework with compatibility break versus previous HAL version
      • -
        -
      • Remove HAL CEC polling - Process functions: HAL_CEC_Transmit() - and HAL_CEC_Receive()
        • -
      • Remove HAL CEC receive - interrupt process function HAL_CEC_Receive_IT() - and enable the "receive"  mode during the Init - phase
        • -
      • Rename HAL_CEC_GetReceivedFrameSize() - funtion - to HAL_CEC_GetLastReceivedFrameSize()
        • -
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() - and HAL_CEC_ChangeRxBuffer()
        • -
      • Remove the 'InitiatorAddress' - field from the CEC_InitTypeDef - structure and manage it as a parameter in the HAL_CEC_Transmit_IT() - function
        • -
      • Add new parameter 'RxFrameSize' - in HAL_CEC_RxCpltCallback() - function
        • -
      • Move CEC Rx buffer - pointer from CEC_HandleTypeDef structure to - CEC_InitTypeDef - structure
        • -
      -
    -
-
    -
  • HAL RCC update
    • -
      -
    • Update HAL_RCC_ClockConfig() - function to adjust the SystemCoreClock
      • -
    • Rename macros and - Literals:
      • -
        -
      • RCC_PERIPHCLK_CK48 by RCC_PERIPHCLK_CLK48
        • -
      • IS_RCC_CK48CLKSOURCE by - IS_RCC_CLK48CLKSOURCE
        • -
      • RCC_CK48CLKSOURCE_PLLSAIP - by RCC_CLK48CLKSOURCE_PLLSAIP
        • -
      • RCC_SDIOCLKSOURCE_CK48 by - RCC_SDIOCLKSOURCE_CLK48
        • -
      • RCC_CK48CLKSOURCE_PLLQ - by RCC_CLK48CLKSOURCE_PLLQ
        • -
      -
    • Update HAL_RCCEx_GetPeriphCLKConfig() - and HAL_RCCEx_PeriphCLKConfig() - functions to support TIM Prescaler for STM32F411xx - devices
      • -
    • HAL_RCCEx_PeriphCLKConfig() API: update to fix the - RTC clock configuration issue
      • -
    -
  • HAL CEC update
    • -
      -
    • Overall driver rework - with break of compatibility with HAL V1.4.4
      • -
        -
      • Remove the HAL CEC - polling Process: HAL_CEC_Transmit() - and HAL_CEC_Receive()
        • -
      -
    -
-
    -
      -
        -
      • Remove the HAL CEC - receive interrupt process (HAL_CEC_Receive_IT()) - and manage the "Receive" mode enable within the Init - phase
        • -
      • Rename HAL_CEC_GetReceivedFrameSize() - function to HAL_CEC_GetLastReceivedFrameSize() - function
        • -
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() - and HAL_CEC_ChangeRxBuffer()
        • -
      • Remove the 'InitiatorAddress' - field from the CEC_InitTypeDef - structure and manage it as a parameter in the HAL_CEC_Transmit_IT() - function
        • -
      • Add new parameter 'RxFrameSize' - in HAL_CEC_RxCpltCallback() - function
        • -
      • Move CEC Rx buffer - pointer from CEC_HandleTypeDef structure to - CEC_InitTypeDef - structure
        • -
      -
    • Update driver to - implement the new CEC state machine:
      • -
        -
      • Add new "rxState" field - in CEC_HandleTypeDef - structure to provide the CEC state - information related to Rx Operations
        • -
      • Rename - "state" field in CEC_HandleTypeDef - structure to "gstate": CEC state - information related to global Handle management and Tx Operations
        • -
      • Update CEC process to - manage the new CEC states.
        • -
      • Update - __HAL_CEC_RESET_HANDLE_STATE() macro to handle the - new CEC state parameters (gState, rxState)
        • -
      -
    -
-
    -
  • HAL UART, USART, SMARTCARD and IRDA (referenced as PPP here below) update
    • -
      -
    • Update Polling - management:
      • -
        -
      • The user Timeout - value must be estimated for the overall process duration: the - Timeout measurement is cumulative
        • -
      -
    • Update DMA process:
      • -
        -
      • Update the management - of PPP peripheral errors during DMA process. This requires the - following updates in user application:
        • -
          -
        • Configure and enable - the PPP IRQ in HAL_PPP_MspInit() - function
          • -
        • In stm32f4xx_it.c - file, PPP_IRQHandler() - function: add a call to HAL_PPP_IRQHandler() - function
          • -
        • Add and customize the - Error Callback API: HAL_PPP_ErrorCallback()
          • -
        -
      -
    -
  • HAL FMC update
    • -
      -
    • Update FMC_NORSRAM_Init() - to remove the Burst access mode configuration
      • -
    • Update FMC_SDRAM_Timing_Init() - to fix initialization issue when configuring 2 SDRAM banks
      • -
    -
  • HAL HCD update
    • -
      -
    • Update HCD_Port_IRQHandler() - to unmask disconnect IT only when the port is disabled
      • -
    -
  • HAL I2C/FMPI2C update
    • -
      -
    • Update Polling - management:
      • -
        -
      • The Timeout value must - be estimated for the overall process duration: the Timeout - measurement is cumulative
        • -
      -
    • Add the management of - Abort service: Abort DMA transfer through interrupt
      • -
        -
      • In the case of Master - Abort IT transfer usage:
        • -
          -
        • Add new user - HAL_I2C_AbortCpltCallback() - to inform user of the end of abort process
          • -
        • A new abort state is - defined in the HAL_I2C_StateTypeDef structure
          • -
        -
      -
    • Add the management of - I2C peripheral errors, ACK failure and STOP condition detection - during DMA process. This requires the following updates on user - application:
      • -
        -
      • Configure and enable - the I2C IRQ in HAL_I2C_MspInit() function
        • -
      • In stm32f4xx_it.c file, - I2C_IRQHandler() - function: add a call to HAL_I2C_IRQHandler() function
        • -
      • Add and customize the - Error Callback API: HAL_I2C_ErrorCallback()
        • -
      • Refer to the I2C_EEPROM - or I2C_TwoBoards_ComDMA project examples usage of the API
        • -
      -
    • NACK error during - addressing phase is returned through interrupt instead of - previously through I2C transfer API's
      • -
    • I2C addressing phase is - updated to be managed using interrupt instead of polling (Only - for HAL I2C driver)
      • -
        -
      • Add new static - functions to manage I2C SB, ADDR and ADD10 flags
        • -
      -
    -
  • HAL SPI update
    • -
-
    -
      -
    • Overall driver - optimization to improve performance in polling/interrupt mode to - reach maximum peripheral frequency
      • -
        -
      • Polling mode:
        • -
          -
        • Replace the use of SPI_WaitOnFlagUnitTimeout() - function by "if" statement to check on RXNE/TXE flage - while transferring data
          • -
        -
      -
    -
-
    -
      -
        -
      •  Interrupt mode:
        • -
          -
        • Minimize access on SPI - registers
          • -
        -
      • All modes:
        • -
          -
        • Add the USE_SPI_CRC - switch to minimize the number of statements when CRC calculation - is disabled
          • -
        • Update timeout - management to check on global processes
          • -
        • Update error code - management in all processes
          • -
        -
      -
    • Update DMA process:
      • -
        -
      • Add the management of - SPI peripheral errors during DMA process. This requires the - following updates in the user application:
        • -
          -
        • Configure and enable - the SPI IRQ in HAL_SPI_MspInit() - function
          • -
        • In stm32f4xx_it.c - file, SPI_IRQHandler() - function: add a call to HAL_SPI_IRQHandler() - function
          • -
        • Add and customize the - Error Callback API: HAL_SPI_ErrorCallback()
          • -
        • Refer to the following - example which describe the changes: SPI_FullDuplex_ComDMA
          • -
        -
      -
    • Fix regression in - polling mode:
      • -
        -
      • Add preparing data to - transmit in case of slave mode in HAL_SPI_TransmitReceive() - and HAL_SPI_Transmit()
        • -
      • Add to manage properly - the overrun flag at the end of a HAL_SPI_TransmitReceive()
        • -
      -
    • Fix regression in - interrupt mode:
      • -
        -
      • Add a wait on TXE flag - in SPI_CloseTx_ISR() - and in SPI_CloseTxRx_ISR()
        • -
      • Add to manage properly - the overrun flag in SPI_CloseRxTx_ISR() - and SPI_CloseRx_ISR()
        • -
      -
    -
-
    -
  • HAL DMA2D update
    • -
      -
    • Update the HAL_DMA2D_DeInit() - function to:
      • -
        -
      • Abort transfer in case - of ongoing DMA2D transfer
        • -
      • Reset DMA2D control registers
        • -
      -
    • Update HAL_DMA2D_Abort() - to disable DMA2D interrupts after stopping transfer
      • -
    • Optimize HAL_DMA2D_IRQHandler() - by reading status registers only once
      • -
    • Update HAL_DMA2D_ProgramLineEvent() - function to:
      • -
        -
      • Return HAL error state - in case of wrong line value
        • -
      • Enable line interrupt - after setting the line watermark configuration
        • -
      -
    • Add new HAL_DMA2D_CLUTLoad() - and HAL_DMA2D_CLUTLoad_IT() functions - to start DMA2D CLUT loading
      • -
        -
      • HAL_DMA2D_CLUTLoading_Abort() - function to abort the DMA2D CLUT loading
        • -
      • HAL_DMA2D_CLUTLoading_Suspend() - function to suspend the DMA2D CLUT loading
        • -
      • HAL_DMA2D_CLUTLoading_Resume() - function to resume the DMA2D CLUT loading
        • -
      -
    • Add new DMA2D dead time - management:
      • -
        -
      • HAL_DMA2D_EnableDeadTime() - function to enable DMA2D dead time feature
        • -
      • HAL_DMA2D_DisableDeadTime() - function to disable DMA2D dead time feature
        • -
      • HAL_DMA2D_ConfigDeadTime() - function to configure dead time
        • -
      -
    • Update the name of DMA2D - Input/Output color mode defines to be more clear - for user (DMA2D_INPUT_XXX for input layers Colors, DMA2D_OUTPUT_XXX - for output framebuffer Colors)
      • -
    -
-
    -
  • HAL LTDC update
    • -
-
    -
      -
    • Update HAL_LTDC_IRQHandler() - to manage the case of reload interrupt
      • -
    • Add new callback API HAL_LTDC_ReloadEventCallback()
      • -
    • Add HAL_LTDC_Reload() - to configure LTDC reload feature
      • -
    • Add new No Reload LTDC - variant APIs
      • -
        -
      • HAL_LTDC_ConfigLayer_NoReload() to configure the LTDC - Layer according to the specified without reloading
        • -
      • HAL_LTDC_SetWindowSize_NoReload() to set the LTDC - window size without reloading
        • -
      • HAL_LTDC_SetWindowPosition_NoReload() to set the LTDC - window position without reloading
        • -
      • HAL_LTDC_SetPixelFormat_NoReload() to reconfigure the - pixel format without reloading
        • -
      • HAL_LTDC_SetAlpha_NoReload() to reconfigure the - layer alpha value without reloading
        • -
      • HAL_LTDC_SetAddress_NoReload() to reconfigure the - frame buffer Address without reloading
        • -
      • HAL_LTDC_SetPitch_NoReload() to reconfigure the - pitch for specific cases
        • -
      • HAL_LTDC_ConfigColorKeying_NoReload() to configure the - color keying without reloading
        • -
      • HAL_LTDC_EnableColorKeying_NoReload() to enable the color - keying without reloading
        • -
      • HAL_LTDC_DisableColorKeying_NoReload() to disable the color - keying without reloading
        • -
      • HAL_LTDC_EnableCLUT_NoReload() to enable the color - lookup table without reloading
        • -
      • HAL_LTDC_DisableCLUT_NoReload() to disable the color - lookup table without reloading
        • -
      • Note: Variant functions with - �_NoReload� - post fix allows to set the LTDC configuration/settings without - immediate reload. This is useful in case when the program requires - to modify several LTDC settings (on one or both layers) then - applying (reload) these settings in one shot by calling the - function �HAL_LTDC_Reload�
        • -
      -
    -
  • HAL RTC update 
    • -
      -
    • Add new timeout - implementation based on cpu cycles - for ALRAWF, ALRBWF and WUTWF flags
      • -
    -
-
    -
  • HAL SAI update
    • -
      -
    • Update SAI state in case - of TIMEOUT error within the HAL_SAI_Transmit() - / HAL_SAI_Receive()
      • -
    • Update HAL_SAI_IRQHandler:
      • -
        -
      • Add error management in - case DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT()
        • -
      • Add error management in - case of IT
        • -
      -
    • Move SAI_BlockSynchroConfig() - and SAI_GetInputClock() - functions to stm32f4xx_hal_sai.c/.h files (extension files are kept - empty for projects compatibility reason)
      • -
    -
-
    -
  • HAL DCMI update
    • -
      -
    • Rename DCMI_DMAConvCplt - to DCMI_DMAXferCplt
      • -
    • Update HAL_DCMI_Start_DMA() - function to Enable the DCMI peripheral
      • -
    • Add new timeout - implementation based on cpu cycles for DCMI stop
      • -
    • Add HAL_DCMI_Suspend() - function to suspend DCMI capture
      • -
    • Add HAL_DCMI_Resume() - function to resume capture after DCMI suspend
      • -
    • Update lock mechanism - for DCMI process
      • -
    • Update HAL_DCMI_IRQHandler() - function to:
      • -
        -
      • Add error management in - case DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT()
        • -
      • Optimize code by using - direct register read
        • -
      -
    -
-
    -
  • HAL DMA update
    • -
      -
    • Add new APIs HAL_DMA_RegisterCallback() - and HAL_DMA_UnRegisterCallback - to register/unregister the different callbacks identified by the enum - typedef HAL_DMA_CallbackIDTypeDef
      • -
    • Add new API HAL_DMA_Abort_IT() - to abort DMA transfer under interrupt context
      • -
        -
      • The new registered - Abort callback is called when DMA transfer abortion is completed
        • -
      -
    • Add the check of - compatibility between FIFO threshold level and size of the memory - burst in the HAL_DMA_Init() - API
      • -
    • Add new Error Codes: - HAL_DMA_ERROR_PARAM, HAL_DMA_ERROR_NO_XFER and HAL_DMA_ERROR_NOT_SUPPORTED
      • -
    • Remove all DMA states - related to MEM0/MEM1 in HAL_DMA_StateTypeDef
      • -
    -
  • HAL IWDG update
    • -
      -
    • Overall rework of the - driver for a more efficient implementation
      • -
        -
      • Remove the following - APIs:
        • -
          -
        • HAL_IWDG_Start()
          • -
        • HAL_IWDG_MspInit()
          • -
        • HAL_IWDG_GetState()
          • -
        -
      • Update implementation:
        • -
          -
        • HAL_IWDG_Init(): this function - insures the configuration and the start of the IWDG counter
          • -
        • HAL_IWDG_Refresh(): this function - insures the reload of the IWDG counter
          • -
        -
      • Refer to the following - example to identify the changes: IWDG_Example
        • -
      -
    -
  • HAL LPTIM update
    • -
      -
    • Update HAL_LPTIM_TimeOut_Start_IT() - and HAL_LPTIM_Counter_Start_IT( - ) APIs to configure WakeUp Timer EXTI interrupt to - be able to wakeup - MCU from low power mode by pressing the EXTI line.
      • -
    • Update HAL_LPTIM_TimeOut_Stop_IT() - and HAL_LPTIM_Counter_Stop_IT( - ) APIs to disable WakeUp - Timer EXTI interrupt. 
      • -
    -
  • HAL NOR update
    • -
      -
    • Update NOR_ADDR_SHIFT - macro implementation
      • -
    -
  • HAL PCD update
    • -
      -
    • Update HAL_PCD_IRQHandler() - to get HCLK frequency before setting TRDT value
      • -
    -
  • HAL QSPI update
    • -
-
    -
      -
    • Update to manage QSPI - error management during DMA process
      • -
    • Improve the DMA transmit - process by using QSPI TC interrupt instead of waiting loop on TC - flag under DMA ISR
      • -
    • These two improvements - require the following updates on user application:
      • -
        -
      • Configure and enable - the QSPI IRQ in HAL_QSPI_MspInit() - function
        • -
      • In stm32f4xx_it.c file, - QSPI_IRQHandler() - function: add a call to HAL_QSPI_IRQHandler() function
        • -
      • Add and customize the - Error Callback API: HAL_QSPI_ErrorCallback()
        • -
      -
    • Add the management of - non-blocking transfer abort service: HAL_QSPI_Abort_IT(). - In this case the user must:
      • -
        -
      • Add new callback HAL_QSPI_AbortCpltCallback() - to inform user at the end of abort process
        • -
      • A new value of State in - the HAL_QSPI_StateTypeDef - provides the current state during the abort phase
        • -
      -
    • Polling management - update:
      • -
        -
      • The Timeout value user - must be estimated for the overall process duration: the - Timeout measurement is cumulative. 
        • -
      -
    • Refer to the following - examples, which describe the changes:
      • -
        -
      • QSPI_ReadWrite_DMA
        • -
      • QSPI_MemoryMapped
        • -
      • QSPI_ExecuteInPlace
        • -
      -
    -
-
    -
      -
    • Add two new APIs for the - QSPI fifo - threshold:
      • -
        -
      • HAL_QSPI_SetFifoThreshold(): configure the FIFO - threshold of the QSPI
        • -
      • HAL_QSPI_GetFifoThreshold(): give the current - FIFO threshold
        • -
      -
    • Fix wrong data size - management in HAL_QSPI_Receive_DMA()
      • -
    -
-
    -
  • HAL ADC - update
    • -
      -
    • Add new __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() - macro for STM32F42x and STM32F43x devices to provide the - possibility to convert VrefInt channel when both VrefInt - and Vbat - channels are selected.
      • -
    -
  • HAL SPDIFRX update
    • -
      -
    • Overall driver - update for wait on flag management optimization 
      • -
    -
  • HAL WWDG update 
    • -
      -
    • Overall rework of the - driver for more efficient implementation
      • -
        -
      • Remove the following - APIs:
        • -
          -
        • HAL_WWDG_Start()
          • -
        • HAL_WWDG_Start_IT()
          • -
        • HAL_WWDG_MspDeInit()
          • -
        • HAL_WWDG_GetState()
          • -
        -
      • Update implementation:
        • -
          -
        • HAL_WWDG_Init()
          • -
            -
          • A new parameter - in the Init Structure: EWIMode
            • -
          -
        • HAL_WWDG_MspInit()
          • -
        • HAL_WWDG_Refresh() 
          • -
            -
          • This function insures - the reload of the counter
            • -
          • The - "counter" parameter has been removed
            • -
          -
        • HAL_WWDG_IRQHandler()
          • -
        • HAL_WWDG_EarlyWakeupCallback() is the new prototype - of HAL_WWDG_WakeUpCallback()
          • -
        -
      -
    • Refer to the following - example to identify the changes: WWDG_Example
      • -
    -
-

V1.4.4 / - 22-January-2016

-

Main Changes

-
    -
  • HAL Generic update
    • -
      -
    • stm32f4xx_hal_conf_template.h
      • -
        -
      • Optimize HSE Startup - Timeout value from 5000ms to 100 ms
        • -
      • Add new define - LSE_STARTUP_TIMEOUT
        • -
      • Add new define - USE_SPI_CRC for code cleanup when the CRC calculation is disabled.
        • -
      -
    • Update HAL drivers to - support MISRA C 2004 rule 10.6
      • -
    • Add new - template driver to configure timebase - using TIMER - :
      • -
        -
      • stm32f4xx_hal_timebase_tim_template.c
        • -
      -
    -
-
    -
  • HAL CAN update
    • -
      -
    • Update HAL_CAN_Transmit() - and HAL_CAN_Transmit_IT() - functions to unlock process when all Mailboxes are busy
      • -
    -
-
    -
  • HAL DSI update
    • -
      -
    • Update HAL_DSI_SetPHYTimings() - functions to use the correct mask
      • -
    -
  • HAL UART update
    • -
      -
    • Several update on HAL - UART driver to implement the new UART state machine: 
      • -
        -
      • Add new field in UART_HandleTypeDef - structure: "rxState", - UART state information related to Rx Operations
        • -
      • Rename - "state" field in UART_HandleTypeDef - structure by "gstate": UART state - information related to global Handle management and Tx Operations
        • -
      • Update UART process to - manage the new UART states.
        • -
      • Update - __HAL_UART_RESET_HANDLE_STATE() macro to handle the - new UART state parameters (gState, rxState)
        • -
      -
    • Update - UART_BRR_SAMPLING16() and UART_BRR_SAMPLING8() Macros to fix wrong baudrate - calculation.
      • -
    -
-
    -
  • HAL IRDA update
    • -
      -
    • Several update on HAL - IRDA driver to implement the new UART state machine: 
      • -
        -
      • Add new field in IRDA_HandleTypeDef - structure: "rxState", - IRDA state information related to Rx Operations
        • -
      • Rename - "state" field in UART_HandleTypeDef - structure by "gstate": IRDA state - information related to global Handle management and Tx Operations
        • -
      • Update IRDA process to - manage the new UART states.
        • -
      • Update - __HAL_IRDA_RESET_HANDLE_STATE() macro to handle the - new IRDA state parameters (gState, rxState)
        • -
      -
    • Removal of - IRDA_TIMEOUT_VALUE define
      • -
    • Update IRDA_BRR() - Macro to fix wrong baudrate calculation
      • -
    -
  • HAL SMARTCARD update
    • -
      -
    • Several update on HAL - SMARTCARD driver to implement the new UART state machine: 
      • -
        -
      • Add new field in SMARTCARD_HandleTypeDef - structure: "rxState", - SMARTCARDstate - information related to Rx Operations
        • -
      • Rename - "state" field in UART_HandleTypeDef - structure by "gstate": SMARTCARDstate - information related to global Handle management and Tx Operations
        • -
      • Update SMARTCARD - process to manage the new UART states.
        • -
      • Update - __HAL_SMARTCARD_RESET_HANDLE_STATE() - macro to handle the new SMARTCARD state parameters (gState, - rxState)
        • -
      -
    • Update SMARTCARD_BRR() - macro to fix wrong baudrate calculation
      • -
    -
-
    -
  • HAL  RCC update
    • -
      -
    • Add new default define - value for HSI calibration "RCC_HSICALIBRATION_DEFAULT"
      • -
    • Optimize Internal - oscillators and PLL startup timeout 
      • -
    • Update to avoid the - disable for HSE/LSE oscillators before setting the new RCC HSE/LSE - configuration and add the following notes in HAL_RCC_OscConfig() - API description:
      • -
    -
-

       -             -           * @note   - Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
-     -             -              - *             supported - by this API. User should request a transition to LSE Off
-     -             -              - *             first and - then LSE On or LSE Bypass.
-     -             -              * - @note   Transition HSE Bypass to HSE On and HSE On to HSE - Bypass are not
-     -             -              - *             supported - by this API. User should request a transition to HSE Off
-     -             -              - *             first and - then HSE On or HSE Bypass.

-
    -
      -
    • Optimize the HAL_RCC_ClockConfig() - API implementation.
      • -
    -
-
    -
  • HAL DMA2D update
    • -
      -
    • Update HAL_DMA2D_Abort() - Function to end current DMA2D transfer properly
      • -
    • Update HAL_DMA2D_PollForTransfer() - function to add poll for background CLUT loading (layer 0 and layer - 1).
      • -
    • Update HAL_DMA2D_PollForTransfer() - to set the corresponding ErrorCode in case of error - occurrence
      • -
    • Update HAL_DMA2D_ConfigCLUT() - function to fix wrong CLUT size and color mode settings
      • -
    • Removal of useless macro - __HAL_DMA2D_DISABLE()
      • -
    • Update HAL_DMA2D_Suspend() - to manage correctly the case where no transfer is on going
      • -
    • Update HAL_DMA2D_Resume() to - manage correctly the case where no transfer is on going
      • -
    • Update HAL_DMA2D_Start_IT() - to enable all required interrupts before enabling the transfer.
      • -
    • Add HAL_DMA2D_CLUTLoad_IT() - Function to allow loading a CLUT with interruption model.
      • -
    •  Update HAL_DMA2D_IRQHandler() - to manage the following cases :
      -
      -
      • - -
        -
      • CLUT transfer complete
        • -
      • CLUT access error
        • -
      • Transfer watermark reached
        • -
      -
    • Add new Callback APIs:
      • -
        -
      •  HAL_DMA2D_LineEventCallback() - to signal a transfer watermark reached event
        • -
      •  HAL_DMA2D_CLUTLoadingCpltCallback() - to signal a CLUT loading complete event
        • -
      -
    -
-
    -
      -
    • Miscellaneous - Improvement:
      • -
        -
      • Add - "HAL_DMA2D_ERROR_CAE" new define for CLUT Access error - management.
        • -
      • Add     ï¿½assert_param� - used for parameters check is now done on the top of the exported - functions : before locking the process using __HAL_LOCK
        • -
      -
    -
-

 

-
    -
  • HAL I2C update
    • -
      -
    • Add support of I2C - repeated start feature:
      • -
        -
      • With the following new - API's
        • -
          -
        • HAL_I2C_Master_Sequential_Transmit_IT()
          • -
        • HAL_I2C_Master_Sequential_Receive_IT()
          • -
        • HAL_I2C_Master_Abort_IT()
          • -
        • HAL_I2C_Slave_Sequential_Transmit_IT()
          • -
        • HAL_I2C_Slave_Sequential_Receive_IT()
          • -
        • HAL_I2C_EnableListen_IT()
          • -
        • HAL_I2C_DisableListen_IT()
          • -
        -
      • Add - new user callbacks:
        • -
          -
        • HAL_I2C_ListenCpltCallback()
          • -
        • HAL_I2C_AddrCallback()
          • -
        -
      -
    • Update to generate STOP - condition when a acknowledge failure error is detected
      • -
    • Several update on HAL - I2C driver to implement the new I2C state machine: 
      • -
        -
      • Add new API to get the - I2C mode: HAL_I2C_GetMode()
        • -
      • Update I2C process to - manage the new I2C states.
        • -
      -
    • Fix wrong behaviour - in single byte transmission 
      • -
    • Update I2C_WaitOnFlagUntilTimeout() to - manage the NACK feature.
      • -
    • Update  I2C transmission process - to support the case data size equal 0
      • -
    -
-
    -
  • HAL FMPI2C update
    • -
      -
    • Add support of FMPI2C - repeated start feature:
      • -
        -
      • With the following new - API's
        • -
          -
        • HAL_FMPI2C_Master_Sequential_Transmit_IT()
          • -
        • HAL_FMPI2C_Master_Sequential_Receive_IT()
          • -
        • HAL_FMPI2C_Master_Abort_IT()
          • -
        • HAL_FMPI2C_Slave_Sequential_Transmit_IT()
          • -
        • HAL_FMPI2C_Slave_Sequential_Receive_IT()
          • -
        • HAL_FMPI2C_EnableListen_IT()
          • -
        • HAL_FMPI2C_DisableListen_IT()
          • -
        -
      • Add - new user callbacks:
        • -
          -
        • HAL_FMPI2C_ListenCpltCallback()
          • -
        • HAL_FMPI2C_AddrCallback()
          • -
        -
      -
    • Several update on HAL - I2C driver to implement the new I2C state machine: 
      • -
        -
      • Add new API to get the - FMPI2C mode: HAL_FMPI2C_GetMode()
        • -
      • Update FMPI2C process - to manage the new FMPI2C states.
        • -
      -
    -
-
    -
  • HAL SPI update
    • -
      -
    • Major Update to improve - performance in polling/interrupt mode to reach max frequency:
      • -
        -
      • Polling mode :
        • -
          -
        • Replace use of SPI_WaitOnFlagUnitTimeout() - funnction - by "if" statement to check on RXNE/TXE flage - while transferring data.
          • -
        • Use API data pointer - instead of SPI handle data pointer.
          • -
        • Use a Goto - implementation instead of "if..else" - statements.
          • -
        -
      -
    -
-
    -
      -
        -
      • Interrupt - mode
        • -
          -
        • Minimize access on SPI - registers.
          • -
        • Split the SPI modes - into dedicated static functions to minimize checking statements - under HAL_IRQHandler():
          • -
            -
          • 1lines/2lines modes
            • -
          • 8 bit/ 16 bits data - formats
            • -
          • CRC calculation - enabled/disabled.
            • -
          -
        • Remove - waiting loop under ISR when closing  the - communication.
          • -
        -
      • All modes:  
        • -
          -
        • Adding switch - USE_SPI_CRC to minimize number of statements when CRC calculation - is disabled.
          • -
        • Update Timeout - management to check on global process.
          • -
        • Update Error code - management in all processes.
          • -
        -
      -
    • Add - note to the max frequencies reached in all modes.
      • -
    • Add - note about Master Receive mode restrictions :
      • -
        -
      • Master Receive mode - restriction:
        -       (#) In - Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, - RXONLY=0) or
        -           - bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to - ensure that the SPI
        -           does not - initiate a new transfer the following procedure has to be - respected:
        -           (##) HAL_SPI_DeInit()
        -           (##) HAL_SPI_Init()
        • -
      -
    -
-
    -
  • HAL SAI update
    • -
      -
    • Update for proper - management of the external synchronization input selection
      • -
        -
      • update of HAL_SAI_Init - () funciton
        • -
      • update definition of SAI_Block_SyncExt - and SAI_Block_Synchronization - groups
        • -
      -
    • Update SAI_SLOTACTIVE_X -  defines values
      • -
    • Update HAL_SAI_Init() - function for proper companding mode management
      • -
    • Update SAI_Transmit_ITxxBit() - functions to add the check on transfer counter before writing new - data to SAIx_DR - registers
      • -
    • Update SAI_FillFifo() - function to avoid issue when the number of data to transmit is - smaller than the FIFO size
      • -
    • Update HAL_SAI_EnableRxMuteMode() - function for proper mute management
      • -
    • Update SAI_InitPCM() - function to support 24bits configuration
      • -
    -
  • HAL ETH update
    • -
      -
    • Removal of ETH MAC debug - register defines
      • -
    -
  • HAL FLASH update
    • -
      -
    • Update FLASH_MassErase() - function to apply correctly voltage range parameter
      • -
    -
  • HAL I2S update
    • -
      -
    • Update I2S_DMATxCplt() - and I2S_DMARxCplt() to manage properly FullDuplex - mode without any risk of missing data.
      • -
    -
  • LL FMC update -
    • -
      -
    • Update the FMC_NORSRAM_Init() - function to use BurstAccessMode - field properly -
      • -
    -
  • LL FSMC  update
    • -
      -
    • Update the FSMC_NORSRAM_Init() - function to use BurstAccessMode - field properly
      • -
    -
-


-
-

-

V1.4.4 / 11-December-2015

-

Main Changes

-
    -
  • HAL Generic update
    • -
      -
    • Update HAL weak empty - callbacks to prevent unused argument compilation warnings with some - compilers by calling the following line:
      • -
        -
      • UNUSED(hppp);
        • -
      -
    • STM32Fxxx_User_Manual.chm - files regenerated for HAL V1.4.3
      • -
    -
  • HAL ETH - update 
    • -
      -
    • Update HAL_ETH_Init() - function to add timeout on the Software reset management
      • -
    -
-

V1.4.2 / - 10-November-2015

-

Main Changes

-
    -
  • General updates to fix known defects and - enhancements implementation
    • -
  • One change done on the HAL CRYP requires an - update on the application code based on HAL V1.4.1
    • -
      -
    • Update HAL_CRYP_DESECB_Decrypt() - API to invert pPlainData and pCypherData - parameters
      • -
    -
  • HAL generic update
    • -
      -
    • Update HAL weak empty - callbacks to prevent unused argument compilation warnings with some - compilers by calling the following line:
      • -
        -
      • UNUSED(hppp);
        • -
      -
    -
-
    -
  • HAL CORTEX update
    • -
      -
    • Remove duplication for - __HAL_CORTEX_SYSTICKCLK_CONFIG() macro
      • -
    -
-
    -
  • HAL HASH update
    • -
      -
    • Rename HAL_HASH_STATETypeDef - to HAL_HASH_StateTypeDef
      • -
    • Rename HAL_HASH_PhaseTypeDef - to HAL_HASH_PhaseTypeDef
      • -
    -
  • HAL RCC update
    • -
      -
    • Add new macros - __HAL_RCC_PPP_IS_CLK_ENABLED() to - check on Clock enable/disable status
      • -
    • Update - __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the - disable for the SYSCFG
      • -
    • Update HAL_RCC_MCOConfig() - API to use new defines for the GPIO Speed
      • -
    • Generic update to - improve the PLL VCO min value(100MHz): PLLN, PLLI2S and PLLSAI - min value is 50 instead of 192
      • -
    -
  • HAL FLASH update
    • -
      -
    • __HAL_FLASH_INSTRUCTION_CACHE_RESET() - macro: update to reset -  ICRST bit in the ACR register after setting it.
      • -
    • Update to support until - 15 FLASH wait state (FLASH_LATENCY_15) for STM32F446xx devices -
      • -
    -
-

�  - HAL CRYP update

-
    -
      -
    • Update HAL_CRYP_DESECB_Decrypt() - API to fix the inverted pPlainData and pCypherData - parameters issue
      • -
    -
  • HAL I2S update
    • -
      -
    • Update HAL_I2S_Init() - API to call __HAL_RCC_I2S_CONFIG() macro when external I2S - clock is selected
      • -
    -
  • HAL LTDC update
    • -
      -
    • Update HAL_LTDC_SetWindowPosition() - API to configure Immediate reload register instead - of vertical blanking reload register.
      • -
    -
  • HAL TIM update
    • -
      -
    • Update HAL_TIM_ConfigClockSource() - API to check only the required parameters
      • -
    -
  • HAL NAND update
    • -
      -
    • Update - HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() - APIs to manage correctly the NAND Page access
      • -
    -
  • HAL CAN update
    • -
      -
    • Update to use - "=" instead of "|=" to clear flags in the MSR, - TSR, RF0R and RF1R registers
      • -
    -
  • HAL HCD update
    • -
      -
    • Fix typo in - __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() - macro implementation
      • -
    -
  • HAL PCD update
    • -
      -
    • Update HAL_PCD_IRQHandler() - API to avoid issue when DMA mode enabled for Status Phase IN - stage
      • -
    -
  • LL FMC update
    • -
      -
    • Update the FMC_NORSRAM_Extended_Timing_Init() - API to remove the check on CLKDIvison - and DataLatency - parameters
      • -
    • Update the FMC_NORSRAM_Init() - API to add a check on the PageSize - parameter for STM32F42/43xx devices
      • -
    -
  • LL FSMC update
    • -
      -
    • Update the FSMC_NORSRAM_Extended_Timing_Init() - API to remove the check on CLKDIvison - and DataLatency - parameters
      • -
    -
-

V1.4.1 / - 09-October-2015

-

Main Changes

-
    -
  • HAL DSI update
    • -
      -
    • Update TCCR - register assigned value in HAL_DSI_ConfigHostTimeouts() - function
      • -
    • Update WPCR - register assigned value in HAL_DSI_Init(), - HAL_DSI_SetSlewRateAndDelayTuning(), - HAL_DSI_SetSlewRateAndDelayTuning(), - HAL_DSI_SetLowPowerRXFilter() - / HAL_DSI_SetSDD(), - HAL_DSI_SetLanePinsConfiguration(), - HAL_DSI_SetPHYTimings(), - HAL_DSI_ForceTXStopMode(), - HAL_DSI_ForceRXLowPower(), - HAL_DSI_ForceDataLanesInRX(), - HAL_DSI_SetPullDown() - and HAL_DSI_SetContentionDetectionOff() - functions
      • -
    • Update DSI_HS_PM_ENABLE - define value
      • -
    • Implement workaround for - the hardware limitation: �The time to activate the clock between HS - transmissions is not calculated correctly�
      • -
    -
-

V1.4.0 / - 14-August-2015

-

Main Changes

-
    -
  • Add support of STM32F469xx, - STM32F479xx, STM32F410Cx, STM32F410Rx and STM32F410Tx  devices
    • -
  • General updates to fix known defects and - enhancements implementation
    • -
  • Add new HAL drivers for DSI and LPTIM - peripherals
    • -
-
    -
  • HAL ADC update
    • -
      -
    • Rename - ADC_CLOCKPRESCALER_PCLK_DIV2 define to ADC_CLOCK_SYNC_PCLK_DIV2
      • -
    • Rename - ADC_CLOCKPRESCALER_PCLK_DIV4 define to ADC_CLOCK_SYNC_PCLK_DIV4
      • -
    • Rename - ADC_CLOCKPRESCALER_PCLK_DIV6 define to ADC_CLOCK_SYNC_PCLK_DIV6
      • -
    • Rename - ADC_CLOCKPRESCALER_PCLK_DIV8 define to ADC_CLOCK_SYNC_PCLK_DIV8
      • -
    -
  • HAL CORTEX update
    • -
      -
    • Add specific API for MPU - management
      • -
        -
      • add MPU_Region_InitTypeDef - structure
        • -
      • add new function HAL_MPU_ConfigRegion()
        • -
      -
    -
  • HAL DMA update
    • -
      -
    • Overall driver - update for code optimization
      • -
        -
      • add StreamBaseAddress - and StreamIndex - new fields in the DMA_HandleTypeDef structure
        • -
      • add DMA_Base_Registers - private structure
        • -
      • add static function DMA_CalcBaseAndBitshift()
        • -
      • update HAL_DMA_Init() - function to use the new added static function
        • -
      • update HAL_DMA_DeInit() - function to optimize clear flag operations
        • -
      • update HAL_DMA_Start_IT() - function to optimize interrupts enable
        • -
      • update HAL_DMA_PollForTransfer() - function to optimize check on flags
        • -
      • update HAL_DMA_IRQHandler() - function to optimize interrupt flag management
        • -
      -
    -
  • HAL FLASH update
    • -
      -
    • update HAL_FLASH_Program_IT() - function by removing the pending flag clear
      • -
    • update HAL_FLASH_IRQHandler() - function to improve erase operation procedure
      • -
    • update FLASH_WaitForLastOperation() - function by checking on end of operation flag
      • -
    -
  • HAL GPIO update
    • -
      -
    • Rename GPIO_SPEED_LOW - define to GPIO_SPEED_FREQ_LOW
      • -
    • Rename GPIO_SPEED_MEDIUM - define to GPIO_SPEED_FREQ_MEDIUM
      • -
    • Rename GPIO_SPEED_FAST - define to GPIO_SPEED_FREQ_HIGH
      • -
    • Rename GPIO_SPEED_HIGH - define to GPIO_SPEED_FREQ_VERY_HIGH
      • -
    -
  • HAL I2S update
    • -
      -
    • Move I2S_Clock_Source - defines to extension file to properly add the support of - STM32F410xx devices
      • -
    -
  • HAL LTDC update
    • -
      -
    • rename HAL_LTDC_LineEvenCallback() - function to HAL_LTDC_LineEventCallback()
      • -
    • add new function HAL_LTDC_SetPitch()
      • -
    • add new functions HAL_LTDC_StructInitFromVideoConfig() - and HAL_LTDC_StructInitFromAdaptedCommandConfig() - applicable only to STM32F469xx and STM32F479xx devices
      • -
    -
  • HAL PWR update
    • -
      -
    • move - __HAL_PWR_VOLTAGESCALING_CONFIG() macro to extension - file
      • -
    • move PWR_WAKEUP_PIN2 - define to extension file
      • -
    • add PWR_WAKEUP_PIN3 - define, applicable only to STM32F10xx devices
      • -
    • add new functions HAL_PWREx_EnableWakeUpPinPolarityRisingEdge() - and HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(), - applicable only to STM32F469xx and STM32F479xx devices
      • -
    -
-
    -
  • HAL RTC update
    • -
      -
    • Update HAL_RTCEx_SetWakeUpTimer() - and HAL_RTCEx_SetWakeUpTimer_IT() - functions to properly check on the WUTWF flag
      • -
    -
  • HAL TIM update
    • -
      -
    • add new defines - TIM_SYSTEMBREAKINPUT_HARDFAULT,  TIM_SYSTEMBREAKINPUT_PVD - and TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD, applicable only to - STM32F410xx devices
      • -
    -
-

V1.3.2 / - 26-June-2015

-

Main Changes

-
    -
  • General updates to fix known defects and - enhancements implementation
    • -
  • One changes done on the HAL may - require an update on the application code based on HAL V1.3.1
    • -
      -
    • HASH IT process: update - to call the HAL_HASH_InCpltCallback() - at the end of the complete buffer instead of every each 512 bits
      • -
    -
-
    -
  • HAL RCC update
    • -
      -
    • HAL_RCCEx_PeriphCLKConfig() updates:
      • -
        -
      • Update the LSE check - condition after backup domain reset: - update to check LSE ready flag when LSE oscillator is already - enabled instead of check on LSE oscillator only when LSE is used - as RTC clock source
        • -
      • Use the right macro to - check the PLLI2SQ parameters -
        • -
      -
    -
-
    -
  • HAL RTC update
    • -
      -
    • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() - macro: fix implementation issue
      • -
    • __HAL_RTC_ALARM_GET_IT(), - __HAL_RTC_ALARM_CLEAR_FLAG(), __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(), - __HAL_RTC_TIMESTAMP_CLEAR_FLAG() and __HAL_RTC_TAMPER_CLEAR_FLAG() - macros implementation changed: remove unused cast
      • -
    • IS_RTC_TAMPER() - macro: update to use literal instead of hardcoded value 
      • -
    • Add new parameter SecondFraction - in RTC_TimeTypeDef - structure
      • -
    • HAL_RTC_GetTime() API update to support - the new parameter SecondFraction
      • -
    -
  • HAL ADC update
    • -
      -
    • Add new literal: - ADC_INJECTED_SOFTWARE_START to be used as possible value for the ExternalTrigInjecConvEdge - parameter in the ADC_InitTypeDef - structure to select the ADC software trigger mode.
      • -
    -
  • HAL FLASH update
    • -
      -
    • FLASH_OB_GetRDP() API update to return - uint8_t instead of FlagStatus
      • -
    •  __HAL_FLASH_GET_LATENCY() - new macro add to get the flash latency
      • -
    -
  • HAL SPI update
    • -
      -
    • Fix the wrong definition - of HAL_SPI_ERROR_FLAG literal
      • -
    -
  • HAL I2S update
    • -
      -
    • HAL_I2S_Transmit() - API update to check on busy flag only for I2S slave mode
      • -
    -
  • HAL CRC update
    • -
      -
    • __HAL_CRC_SET_IDR() - macro implementation change to use WRITE_REG() instead of - MODIFY_REG()
      • -
    -
  • HAL DMA2D update
    • -
      -
    • HAL_DMA2D_ConfigLayer() - API update to use "=" instead of "|=" to erase - BGCOLR and FGCOLR registers before setting the new configuration
      • -
    -
  • HAL HASH update
    • -
      -
    • HAL_HASH_MODE_Start_IT() (MODE stands - for MD5, SHA1, SHA224 and SHA36) updates:
      • -
        -
      • Fix processing - fail for small input buffers
        • -
      • Update to unlock the - process and call return HAL_OK at the end of HASH - processing to avoid incorrectly repeating software
        • -
      • Update to properly - manage the HashITCounter
        • -
      • Update to call the HAL_HASH_InCpltCallback() - at the end of the complete buffer instead of every each 512 bits
        • -
      -
    • __HAL_HASH_GET_FLAG() - update to  check the right register when the DINNE flag -  is selected
      • -
    • HAL_HASH_SHA1_Accumulate() - updates:
      • -
        -
      • Add a call to the - new IS_HASH_SHA1_BUFFER_SIZE() macro to check the size - parameter. 
        • -
      • Add the following note - in API description
        • -
      -
    -
-
-

 * - @note  - Input buffer size in bytes must be a multiple of 4 - otherwise the digest computation is corrupted.

-
-
    -
  • HAL RTC update
    • -
      -
    • Update to - define hardware independent literals names:
      • -
        -
      • Rename - RTC_TAMPERPIN_PC13 by  RTC_TAMPERPIN_DEFAULT
        • -
      • Rename RTC_TAMPERPIN_PA0 - by RTC_TAMPERPIN_POS1
        • -
      • Rename - RTC_TAMPERPIN_PI8 by RTC_TAMPERPIN_POS1
        • -
      • Rename - RTC_TIMESTAMPPIN_PC13 by RTC_TIMESTAMPPIN_DEFAULT
        • -
      • Rename - RTC_TIMESTAMPPIN_PA0 by RTC_TIMESTAMPPIN_POS1
        • -
      • Rename - RTC_TIMESTAMPPIN_PI8 by RTC_TIMESTAMPPIN_POS1
        • -
      -
    -
  • HAL ETH update
    • -
      -
    • Remove - duplicated IS_ETH_DUPLEX_MODE() and - IS_ETH_RX_MODE() macros
      • -
    • Remove illegal space - ETH_MAC_READCONTROLLER_FLUSHING macro
      • -
    • Update - ETH_MAC_READCONTROLLER_XXX defined values (XXX can be IDLE, - READING_DATA and READING_STATUS)
      • -
    -
  • HAL PCD update
    • -
      -
    • HAL_PCD_IRQHandler API: fix the bad - Configuration of Turnaround Time
      • -
    -
  • HAL HCD update
    • -
      -
    • Update to use local - variable in USB Host channel re-activation
      • -
    -
  • LL FMC update
    • -
      -
    • FMC_SDRAM_SendCommand() API: remove the - following line: return HAL_ERROR;
      • -
    -
  • LL USB update
    • -
      -
    • USB_FlushTxFifo API: update to - flush all Tx FIFO
      • -
    • Update to use local - variable in USB Host channel re-activation
      • -
    -
-

V1.3.1 / - 25-Mars-2015

-

Main Changes

-
    -
  • HAL PWR update
    • -
      -
    • Fix compilation issue - with STM32F417xx product: update STM32F17xx by STM32F417xx
      • -
    -
  • HAL SPI update
    • -
      -
    • Remove unused variable - to avoid warning with TrueSTUDIO 
      • -
    -
  • HAL I2C update
    • -
      -
    • I2C Polling/IT/DMA - processes: move the wait loop on busy flag at the top of the - processes, to ensure that software not perform any write access to - I2C_CR1 register before hardware clearing STOP bit and to avoid - also the waiting loop on BUSY flag under I2C/DMA ISR.
      • -
    • Update busy - flag Timeout value
      • -
    • I2C Master Receive - Processes update to disable ACK before generate the - STOP 
      • -
    -
  • HAL DAC update
    • -
      -
    • Fix V1.3.0 regression - issue with DAC software trigger configuration
      • -
    -
-

V1.3.0 / - 09-Mars-2015

-

Main Changes

-
    -
  • Add support of STM32F446xx - devices
    • -
  • General updates to fix known defects and - enhancements implementation
    • -
  • Add new HAL drivers for CEC, QSPI, FMPI2C and - SPDIFRX peripherals
    • -
  • Two changes done on the HAL requires an update on - the application code based on HAL V1.2.0
    • -
      -
    • Overall SAI driver - rework to have exhaustive support of the peripheral features: - details are provided in HAL SAI update section below --> Compatibility - with previous version is impacted
      • -
    • CRYP driver updated to - support multi instance,so - user must ensure that the new parameter Instance is initalized - in his application(CRYPHandle.Instance = - CRYP) 
      • -
    -
-
    -
  • HAL Generic update
    • -
      -
    • stm32f4xx_hal_def.h
      • -
        -
      • Remove NULL - definition and add include for stdio.h
        • -
      -
    • stm32_hal_legacy.h
      • -
        -
      • Update method to - manage deference in alias implementation between all STM32 families
        • -
      -
    • stm32f4xx_hal_ppp.c
      • -
        -
      • HAL_PPP_Init(): update to force the - HAL_PPP_STATE_RESET before calling the HAL_PPP_MspInit()
        • -
      -
    -
-
    -
  • HAL RCC update
    • -
      -
    • Add new function HAL_RCCEx_GetPeriphCLKFreq()
      • -
    • Move RCC_PLLInitTypeDef - structure to extension file and add the new PLLR field specific to - STM32F446xx devices
      • -
    • Move the following - functions to extension file and add a __weak attribute in generic driver : - this update is related to new system clock source (PLL/PLLR) - added and only available for STM32F44xx devices
      • -
        -
      • HAL_RCC_OscConfig()
        • -
      • HAL_RCC_GetSysClockFreq()
        • -
      • HAL_RCC_GetOscConfig()
        • -
      -
    • Move the following macro - to extension file as they have device dependent implementation
      • -
        -
      • __HAL_RCC_PLL_CONFIG()
        • -
      • __HAL_RCC_PLLI2S_CONFIG()
        • -
      • __HAL_RCC_I2S_CONFIG()
        • -
      -
    • Add new structure RCC_PLLI2SInitTypeDef - containing new PLLI2S division factors used only w/ - STM32F446xx devices
      • -
    • Add new structure RCC_PLLSAIInitTypeDef - containing new PLLSAI division factors used only w/ - STM32F446xx devices
      • -
    • Add new RCC_PeriphCLKInitTypeDef - to support the peripheral source clock selection for (I2S, SAI, - SDIO, FMPI2C, CEC, SPDIFRX and CLK48)
      • -
    • Update the HAL_RCCEx_PeriphCLKConfig() - and HAL_RCCEx_GetPeriphCLKConfig() - functions to support the new peripherals Clock source selection
      • -
    • Add __HAL_RCC_PLL_CONFIG() - macro (the number of parameter and the implementation depend on the - device part number)
      • -
    • Add __HAL_RCC_PLLI2S_CONFIG() - macro(the number of parameter and the implementation depend on - device part number)
      • -
    • Update __HAL_RCC_PLLSAI_CONFIG() - macro to support new PLLSAI factors (PLLSAIM and PLLSAIP)
      • -
    • Add new macros for clock - enable/Disable for the following peripherals (CEC, SPDIFRX, - SAI2, QUADSPI)
      • -
    • Add the following new - macros for clock source selection :
      • -
        -
      • __HAL_RCC_SAI1_CONFIG() - / __HAL_RCC_GET_SAI1_SOURCE()
        • -
      • __HAL_RCC_SAI2_CONFIG() - / __HAL_RCC_GET_SAI2_SOURCE()
        • -
      • __HAL_RCC_I2S1_CONFIG() - / __HAL_RCC_GET_I2S1_SOURCE()
        • -
      • __HAL_RCC_I2S2_CONFIG() - / __HAL_RCC_GET_I2S2_SOURCE()
        • -
      • __HAL_RCC_CEC_CONFIG() - / __HAL_RCC__GET_CEC_SOURCE()
        • -
      • __HAL_RCC_FMPI2C1_CONFIG() - / __HAL_RCC_GET_FMPI2C1_SOURCE()
        • -
      • __HAL_RCC_SDIO_CONFIG() - / __HAL_RCC_GET_SDIO_SOURCE()
        • -
      • __HAL_RCC_CLK48_CONFIG() - / __HAL_RCC_GET_CLK48_SOURCE()
        • -
      • __HAL_RCC_SPDIFRXCLK_CONFIG() - / __HAL_RCC_GET_SPDIFRX_SOURCE()
        • -
      -
    • __HAL_RCC_PPP_CLK_ENABLE(): - Implement workaround to cover RCC limitation regarding peripheral - enable delay
      • -
    • HAL_RCC_OscConfig() fix issues: 
      • -
        -
      • Add a check on LSERDY - flag when LSE_BYPASS is selected as new state for LSE oscillator.
        • -
      -
    • Add new possible - value RCC_PERIPHCLK_PLLI2S to be selected as PeriphClockSelection - parameter in the -  RCC_PeriphCLKInitTypeDef - structure to allow the possibility to output the PLLI2S on MCO - without activating the I2S or the SAI.
      • -
    • __HAL_RCC_HSE_CONFIG()  macro: add the comment - below:
      • -
    -
-
-

 * - @note   Transition HSE Bypass to HSE On and HSE On to HSE - Bypass are not supported by this macro.
-  *         User should - request a transition to HSE Off first and then HSE On or HSE Bypass.

-
-
    -
      -
    • __HAL_RCC_LSE_CONFIG()  macro: - add the comment below:
      • -
    -
-
-

  * - @note   Transition LSE Bypass to LSE On and LSE On to LSE - Bypass are not supported by this macro.
-   *         User should - request a transition to LSE Off first and then LSE On or LSE Bypass.

-
-
    -
      -
    • Add the following new - macros for PLL source and PLLM selection :
      • -
        -
      • __HAL_RCC_PLL_PLLSOURCE_CONFIG()
        • -
      • __HAL_RCC_PLL_PLLM_CONFIG()
        • -
      -
    • Macros rename:
      • -
        -
      • HAL_RCC_OTGHS_FORCE_RESET() - by HAL_RCC_USB_OTG_HS_FORCE_RESET()
        • -
      • HAL_RCC_OTGHS_RELEASE_RESET() - by HAL_RCC_USB_OTG_HS_RELEASE_RESET()
        • -
      • HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() - by HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()
        • -
      • HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() - by HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()
        • -
      • HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() - by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
        • -
      • HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() - by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
        • -
      -
    • Add __HAL_RCC_SYSCLK_CONFIG() - new macro to configure the system clock source (SYSCLK)
      • -
    • __HAL_RCC_GET_SYSCLK_SOURCE() - updates:
      • -
        -
      • Add new RCC Literals:
        • -
          -
        • RCC_SYSCLKSOURCE_STATUS_HSI
          • -
        • RCC_SYSCLKSOURCE_STATUS_HSE
          • -
        • RCC_SYSCLKSOURCE_STATUS_PLLCLK
          • -
        • RCC_SYSCLKSOURCE_STATUS_PLLRCLK
          • -
        -
      •  Update macro - description to refer to the literals above
        • -
      -
    -
  • HAL PWR update
    • -
      -
    • Add new define - PWR_WAKEUP_PIN2
      • -
    • Add new API to - Control/Get VOS bits of CR register
      • -
        -
      • HAL_PWR_HAL_PWREx_ControlVoltageScaling()
        • -
      • HAL_PWREx_GetVoltageRange()
        • -
      -
    • __HAL_PWR_ VOLTAGESCALING_CONFIG(): Implement workaround - to cover VOS limitation delay when PLL is enabled after setting the - VOS configuration
      • -
    -
  • HAL GPIO update
    • -
      -
    • Add the new Alternate - functions literals related to remap for SPI, USART, I2C, - SPDIFRX, CEC and QSPI
      • -
    • HAL_GPIO_DeInit(): Update to - check if GPIO Pin x is already used in EXTI mode on another GPIO - Port before De-Initialize the EXTI registers
      • -
    -
  • HAL FLASH update
    • -
      -
    • __HAL_FLASH_INSTRUCTION_CACHE_RESET() - macro: update to reset -  ICRST bit in the ACR register after setting it.
      • -
    • __HAL_FLASH_DATA_CACHE_RESET() macro: - update to reset  DCRST bit in the ACR register after - setting it.
      • -
    -
  • HAL ADC update
    • -
      -
    • Add new literal: - ADC_SOFTWARE_START to be used as possible value for the ExternalTrigConv - parameter in the ADC_InitTypeDef - structure to select the ADC software trigger mode.
      • -
    • IS_ADC_CHANNEL() - macro update to don't assert stop the ADC_CHANNEL_TEMPSENSOR - value
      • -
    • HAL_ADC_PollForConversion(): update to manage - particular case when ADC configured in DMA mode and ADC sequencer - with several ranks and polling for end of each conversion
      • -
    • HAL_ADC_Start()/HAL_ADC_Start_IT() - /HAL_ADC_Start_DMA() - update:
      • -
        -
      • unlock the process - before starting the ADC software conversion.
        • -
      • Optimize the ADC - stabilization delays
        • -
      -
    • __HAL_ADC_GET_IT_SOURCE() - update macro implementation
      • -
    • Add more details in 'How - to use this driver' section
      • -
    -
  • HAL DAC update
    • -
      -
    • Add new macro to check - if the specified DAC interrupt source is enabled or disabled
      • -
        -
      • __HAL_DAC_GET_IT_SOURCE()
        • -
      -
    • HAL_DACEx_TriangleWaveGeneration() update to use DAC CR - bit mask definition
      • -
    • HAL_DACEx_NoiseWaveGeneration() update to use DAC CR - bit mask definition
      • -
    -
  • HAL CAN update
    • -
      -
    • CanTxMsgTypeDef structure: - update to use uint8_t Data[8] - instead of uint32_t Data[8]
      • -
    • CanRxMsgTypeDef structure: - update to use uint8_t Data[8] instead - of uint32_t Data[8]
      • -
    -
-
    -
  • HAL RTC update
    • -
      -
    • Update to use CMSIS - mask definition instead of hardcoded values (EXTI_IMR_IM17, EXTI_IMR_IM19..)
      • -
    -
  • HAL LTDC update
    • -
      -
    • LTDC_SetConfig() update to allow the - drawing of partial bitmap in active layer.
      • -
    -
  • HAL USART update
    • -
      -
    • HAL_USART_Init() fix USART baud - rate configuration issue: USART baud rate is twice Higher than - expected
      • -
    -
  • HAL SMARTCARD update
    • -
      -
    • HAL_SMARTCARD_Transmit_IT() update to force the - disable for the ERR interrupt to avoid the OVR interrupt
      • -
    • HAL_SMARTCARD_IRQHandler() update check - condition for transmission end
      • -
    • Clean up: remove - the following literals that aren't used in smartcard mode
      • -
        -
      • SMARTCARD_PARITY_NONE
        • -
      • SMARTCARD_WORDLENGTH_8B
        • -
      • SMARTCARD_STOPBITS_1
        • -
      • SMARTCADR_STOPBITS_2
        • -
      -
    -
  • HAL SPI update
    • -
      -
    • HAL_SPI_Transmit_DMA()/HAL_SPI_Receive_DMA()/HAL_SPI_TarnsmitReceive_DMA() - update to unlock the process before enabling the SPI - peripheral
      • -
    • HAL_SPI_Transmit_DMA() update to manage - correctly the DMA RX stream in SPI Full duplex mode
      • -
    • Section - SPI_Exported_Functions_Group2 update to remove duplication in - *.chm UM
      • -
    -
  • HAL CRYP update
    • -
      -
    • Update to manage multi - instance:
      • -
        -
      • Add new parameter - Instance in the CRYP_HandleTypeDef - Handle structure.
        • -
      • Add new parameter in - all HAL CRYP macros
        • -
          -
        • example: __HAL_CRYP_ENABLE() -  updated by __HAL_CRYP_ENABLE(__HANDLE__)
          • -
        -
      -
    -
  • HAL DCMI update
    • -
      -
    • Add an extension - driver stm32f4xx_hal_dcmi_ex.c/h to manage the support of new - Black and White feature
      • -
    • Add  __weak attribute for HAL_DCMI_Init() - function and add a new implementation in the extension driver to - manage the black and white configuration only available in - the  STM32F446xx devices.
      • -
    • Move DCMI_InitTypeDef - structure to extension driver and add the following new - fields related to black and white feature: ByteSelectMode, ByteSelectStart, LineSelectMode - and LineSelectStart
      • -
    -
  • HAL PCD update
    • -
      -
    • Add the support of LPM feature
      • -
        -
      • add PCD_LPM_StateTypeDef - enum
        • -
      • update PCD_HandleTypeDef - structure to support the LPM feature
        • -
      • add new functions HAL_PCDEx_ActivateLPM(), - HAL_PCDEx_DeActivateLPM() - and HAL_PCDEx_LPM_Callback() - in the stm32f4xx_hal_pcd_ex.h/.c files
        • -
      -
    -
  • HAL TIM update
    • -
      -
    • Add  TIM_TIM11_SPDIFRX define
      • -
    -
  • HAL SAI update
    • -
      -
    • Add stm32f4xx_hal_sai_ex.h/.c - files for the SAI_BlockSynchroConfig() - and the SAI_GetInputClock() - management
      • -
    • Add new defines - HAL_SAI_ERROR_AFSDET, HAL_SAI_ERROR_LFSDET, HAL_SAI_ERROR_CNREADY, - HAL_SAI_ERROR_WCKCFG, HAL_SAI_ERROR_TIMEOUT in the SAI_Error_Code - group -
      • -
    • Add new defines - SAI_SYNCEXT_DISABLE, SAI_SYNCEXT_IN_ENABLE, - SAI_SYNCEXT_OUTBLOCKA_ENABLE, SAI_SYNCEXT_OUTBLOCKB_ENABLE for the - SAI External synchronization
      • -
    • Add new defines - SAI_I2S_STANDARD, SAI_I2S_MSBJUSTIFIED, SAI_I2S_LSBJUSTIFIED, - SAI_PCM_LONG and SAI_PCM_SHORT for the SAI Supported protocol
      • -
    • Add new defines - SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED, - SAI_PROTOCOL_DATASIZE_24BIT and SAI_PROTOCOL_DATASIZE_32BIT for SAI - protocol data size
      • -
    • Add SAI Callback - prototype definition
      • -
    • Update SAI_InitTypeDef - structure by adding new fields: SynchroExt, Mckdiv, - MonoStereoMode, - CompandingMode, - TriState
      • -
    • Update SAI_HandleTypeDef - structure:
      • -
        -
      • remove uint16_t *pTxBuffPtr, - *pRxBuffPtr, - TxXferSize, - RxXferSize, - TxXferCount - and RxXferCount - and replace them respectively by uint8_t *pBuffPtr, - uint16_t XferSize and - uint16_t XferCount
        • -
      • add mutecallback - field
        • -
      • add struct __SAI_HandleTypeDef - *hsai - field
        • -
      -
    • Remove - SAI_CLKSOURCE_PLLR and SAI_CLOCK_PLLSRC defines
      • -
    • Add SAI_CLKSOURCE_NA - define
      • -
    • Add SAI_AUDIO_FREQUENCY_MCKDIV - define
      • -
    • Add SAI_SPDIF_PROTOCOL - define
      • -
    • Add SAI_SYNCHRONOUS_EXT - define
      • -
    • Add new functions HAL_SAI_InitProtocol(), - HAL_SAI_Abort(), - HAL_SAI_EnableTxMuteMode(), - HAL_SAI_DisableTxMuteMode(), - HAL_SAI_EnableRxMuteMode(), - HAL_SAI_DisableRxMuteMode()
      • -
    • Update HAL_SAI_Transmit(), - HAL_SAI_Receive(), - HAL_SAI_Transmit_IT(), - HAL_SAI_Receive_IT(), - HAL_SAI_Transmit_DMA(), - HAL_SAI_Receive_DMA() - functions to use uint8_t *pData instead - of uint16_t *pData - --> This update is mainly impacting the compatibility with - previous driver version.
      • -
    -
  • HAL I2S update
    • -
      -
    • Split the following - functions between Generic and Extended API based on full - duplex management and add the attribute __weak in the Generic API
      • -
        -
      • HAL_I2S_Init(), - HAL_I2S_DMAPause(), HAL_I2S_DMAStop(), HAL_I2S_DMAResume(), HAL_I2S_IRQHandle() -
        • -
      -
    • Move the following - static functions from generic to extension driver
      • -
        -
      •  I2S_DMARxCplt() - and I2S_DMATxCplt()
        • -
      -
    • Remove static attribute - from I2S_Transmit_IT() - and I2S_Receive_IT() functions
      • -
    • Move I2SxEXT() - macro to extension file
      • -
    • Add I2S_CLOCK_PLLR and - I2S_CLOCK_PLLSRC defines for I2S clock source
      • -
    • Add new function I2S_GetInputClock()
      • -
    -
  • HAL LL FMC update
    • -
      -
    • Add WriteFifo - and PageSize - fields in the FMC_NORSRAM_InitTypeDef - structure
      • -
    • Add FMC_PAGE_SIZE_NONE, - FMC_PAGE_SIZE_128, FMC_PAGE_SIZE_256, FMC_PAGE_SIZE_1024, - FMC_WRITE_FIFO_DISABLE, FMC_WRITE_FIFO_ENABLE defines
      • -
    • Update FMC_NORSRAM_Init(), - FMC_NORSRAM_DeInit() - and FMC_NORSRAM_Extended_Timing_Init() functions
      • -
    -
  • HAL LL USB update
    • -
      -
    • Update USB_OTG_CfgTypeDef - structure to support LPM, lpm_enable - field added
      • -
    • Update USB_HostInit() - and USB_DevInit() - functions to support the VBUS Sensing B activation
      • -
    -
-

V1.2.0 / - 26-December-2014

-

Main Changes

-
    -
  • Maintenance release to fix known defects and - enhancements implementation
    • -
-
    -
  • Macros and literals renaming to ensure - compatibles across STM32 series, backward compatibility maintained thanks to new - added file stm32_hal_legacy.h under /Inc/Legacy
    • -
  • Add *.chm UM for all drivers, a UM is provided - for each superset RPN
    • -
  • Update drivers to be C++ compliant
    • -
  • Several update on source code formatting, for - better UM generation (i.e. Doxygen tags - updated)
    • -
  • Two changes done on the HAL requires an update on - the application code based on HAL V1.1.0
    • -
      -
    • LSI_VALUE constant has been - corrected in stm32f4xx_hal_conf.h file, its value changed from 40 KHz - to 32 KHz
      • -
    • UART, USART, IRDA - and SMARTCARD (referenced as PPP here below) drivers: - in DMA transmit process, the code has been updated to avoid waiting - on TC flag under DMA ISR, PPP TC interrupt is used instead. - Below the update to be done on user application:
      • -
        -
      • Configure and enable - the USART IRQ in HAL_PPP_MspInit() - function
        • -
      • In stm32f4xx_it.c file, - PPP_IRQHandler() - function: add a call to HAL_PPP_IRQHandler() function
        • -
      -
    -
-
    -
  • HAL generic update
    • -
-
    -
      -
    • stm32f4xx_hal_def.h
      • -
        -
      • Update NULL definition - to fix C++ compilation issue
        • -
      • Add UNUSED() - macro
        • -
      • Add a new define - __NOINLINE to be used for the no inline code independent from - tool chain
        • -
      -
    • stm32f4xx_hal_conf_template.h
      • -
        -
      • LSI_VALUE constant has been corrected, - its value changed from 40 KHz to 32 KHz
        • -
      -
    -
-
    -
      -
    • Update all macros and - literals naming to be uper case
      • -
    • ErrorCode parameter in PPP_HandleTypeDef - structure updated to uint32_t instead of enum - HAL_PPP_ErrorTypeDef
      • -
    • Remove the unused - FLAG and IT assert macros
      • -
    -
  • HAL ADC update
    • -
      -
    • Fix temperature - sensor channel configuration issue for STM32F427/437xx -  and STM32F429/439xx devices
      • -
    -
  • HAL DAC update
    • -
      -
    • HAL_DAC_ConfigChannel(): update the access to - the DAC peripheral registers via the hdac handle - instance
      • -
    • HAL_DAC_IRQHandler(): update to check on - both DAC_FLAG_DMAUDR1 and DAC_FLAG_DMAUDR2
      • -
    • HAL_DACEx_NoiseWaveGenerate(): update to reset DAC - CR register before setting the new DAC configuration
      • -
    • HAL_DACEx_TriangleWaveGenerate(): update to reset DAC - CR register before setting the new DAC configuration
      • -
    -
  • HAL CAN update
    • -
      -
    • Unlock the CAN process - when communication error occurred
      • -
    -
  • HAL CORTEX update
    • -
      -
    • Add new macro IS_NVIC_DEVICE_IRQ() - to check on negative values of IRQn - parameter
      • -
    -
-

�  - HAL CRYP update

-
    -
      -
    • HAL_CRYP_DESECB_Decrypt_DMA(): fix the inverted pPlainData - and pCypherData - parameters issue
      • -
    • CRYPEx_GCMCCM_SetInitVector(): remove the IVSize - parameter as the key length 192bits and 256bits are not supported - by this version
      • -
    • Add restriction for - the CCM Encrypt/Decrypt API's that only - DataType - equal to 8bits is supported
      • -
    • HAL_CRYPEx_AESGCM_Finish():
      • -
        -
      • Add restriction - that the implementation is limited to 32bits inputs data length  - (Plain/Cyphertext, Header) compared with GCM stadards - specifications (800-38D)
        • -
      • Update Size parameter - on 32bits instead of 16bits
        • -
      • Fix issue with 16-bit - Data Type: update to use intrinsic __ROR() - instead of __REV16()
        • -
      -
    -
-

�  - HAL DCMI update

-
    -
      -
    • HAL_DCMI_ConfigCROP(): Invert assert macros - to check Y0 and Ysize - parameters
      • -
    -
-

�  - HAL DMA update

-
    -
      -
    • HAL_DMA_Init(): Update to - clear the DBM bit in the SxCR - register before setting the new configuration
      • -
    • DMA_SetConfig(): add to - clear the DBM bit in the SxCR - register
      • -
    -
-

�  - HAL FLASH update

-
    -
      -
    • Add "HAL_" - prefix in the defined values for the FLASH error code
      • -
        -
      • Example: FLASH_ERROR_PGP - renamed by HAL_FLASH_ERROR_PGP
        • -
      -
    • Clear the Flash ErrorCode - in the FLASH_WaitForLastOperation() - function
      • -
    • Update FLASH_SetErrorCode() - function to use "|=" operant to update the Flash ErrorCode - parameter in the FLASH handle
      • -
    • IS_FLASH_ADDRESS(): Update the macro check - using '<=' condition instead of '<'
      • -
    • IS_OPTIONBYTE(): Update the macro check - using '<=' condition instead of '<'
      • -
    • Add "FLASH_" - prefix in the defined values of FLASH Type Program parameter
      • -
        -
      • Example: TYPEPROGRAM_BYTE - renamed by FLASH_TYPEPROGRAM_BYTE
        • -
      -
    • Add "FLASH_" - prefix in the defined values of FLASH Type Erase parameter
      • -
        -
      • Example: TYPEERASE_SECTORS - renamed by FLASH_TYPEERASE_SECTORS
        • -
      -
    • Add "FLASH_" - prefix in the defined values of FLASH Voltage Range parameter
      • -
        -
      • Example: VOLTAGE_RANGE_1 - renamed by FLASH_VOLTAGE_RANGE_1
        • -
      -
    • Add "OB_" - prefix in the defined values of FLASH WRP State parameter
      • -
        -
      • Example: WRPSTATE_ENABLE - renamed by OB_WRPSTATE_ENABLE
        • -
      -
    • Add "OB_" - prefix in the defined values of the FLASH PCROP State parameter
      • -
        -
      • PCROPSTATE_DISABLE  updated by OB_PCROP_STATE_DISABLE
        • -
      • PCROPSTATE_ENABLE  updated by OB_PCROP_STATE_ENABLE
        • -
      -
    • Change "OBEX" - prefix by "OPTIONBYTE" prefix in these defines:
      • -
        -
      • OBEX_PCROP by - OPTIONBYTE_PCROP 
        • -
      • OBEX_BOOTCONFIG by - OPTIONBYTE_BOOTCONFIG
        • -
      -
    -
-

�  - HAL ETH update

-
    -
      -
    • Fix macros naming typo
      • -
    -
-
    -
      -
        -
      • Update - __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() - by __HAL_ETH_EXTI_SET_RISING_EDGE_TRIGGER()
        • -
      • Update __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() - by __HAL_ETH_EXTI_SET_FALLING_EDGE_TRIGGER()
        • -
      -
    -
-

�  - HAL PWR update

-
    -
      -
    • Add new API to manage - SLEEPONEXIT and SEVONPEND bits of SCR register
      • -
        -
      • HAL_PWR_DisableSleepOnExit()
        • -
      • HAL_PWR_EnableSleepOnExit()
        • -
      • HAL_PWR_EnableSEVOnPend()
        • -
      • HAL_PWR_DisableSEVOnPend()
        • -
      -
    • HAL_PWR_EnterSTOPMode()
      • -
        -
      • Update to clear - the CORTEX SLEEPDEEP bit of SCR register before entering in - sleep mode
        • -
      • Update usage of __WFE() - in low power entry function: if there is a pending event, calling - __WFE() will not enter the CortexM4 core to sleep mode. The - solution is to made the call below; the first __WFE() is - always ignored and clears the event if one was already pending, - the second is always applied
        • -
      -
    -
-
-

__SEV()
- __WFE()
- __WFE()

-
-
    -
      -
    • Add new PVD - configuration modes
      • -
        -
      • PWR_PVD_MODE_NORMAL -
        • -
      • PWR_PVD_MODE_EVENT_RISING  -
        • -
      • PWR_PVD_MODE_EVENT_FALLING
        • -
      • PWR_PVD_MODE_EVENT_RISING_FALLING
        • -
      -
    • Add new macros to manage - PVD Trigger
      • -
        -
      • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() -
        • -
      • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE( -
        • -
      • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() -
        • -
      • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
        • -
      • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() -
        • -
      • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
        • -
      -
    • PVD macros:
      • -
        -
      • Remove the __EXTILINE__ - parameter
        • -
      • Update to use prefix - "__HAL_PWR_PVD_" instead of  prefix - "__HAL_PVD"
        • -
      -
    -
-
    -
      -
    • Rename HAL_PWR_PVDConfig() - by HAL_PWR_ConfigPVD()
      • -
    • Rename HAL_PWREx_ActivateOverDrive() - by HAL_PWREx_EnableOverDrive() -
      • -
    • Rename HAL_PWREx_DeactivateOverDrive() - by HAL_PWREx_DisableOverDrive() -
      • -
    -
  • HAL GPIO update
    • -
      -
    • HAL_GPIO_Init()/HAL_GPIO_DeInit(): add a call to the - CMSIS assert macro to check GPIO instance: - IS_GPIO_ALL_INSTANCE() 
      • -
    • HAL_GPIO_WritePin(): update to write in - BSRR register
      • -
    • Rename GPIO_GET_SOURCE() - by GET_GPIO_INDEX() and move this later to file  - stm32f4xx_hal_gpio_ex.h
      • -
    • Add new define for - alternate function GPIO_AF5_SPI3 for STM32F429xx/439xx and - STM32F427xx/437xx devices
      • -
    -
  • HAL HASH update
    • -
      -
    • HAL_HASH_MD5_Start_IT(): - fix input address - management issue
      • -
    -
  • HAL RCC update
    • -
      -
    • Rename the following Macros
      • -
        -
      • __PPP_CLK_ENABLE()  - by __HAL_RCC_PPP_CLK_ENABLE()
        • -
      • __PPP_CLK_DISABLE()  - by __HAL_RCC_PPP_CLK_DISABLE()
        • -
      • __PPP_FORCE_RESET()  - by __HAL_RCC_PPP_FORCE_RESET()
        • -
      • __PPP_RELEASE_RESET()  - by __HAL_RCC_PPP_RELEASE_RESET()
        • -
      • __PPP_CLK_SLEEP_ENABLE() - by __HAL_RCC_PPP_CLK_SLEEP_ENABLE()
        • -
      • __PPP_CLK_SLEEP_DISABLE() - by __HAL_RCC_PPP_CLK_SLEEP_DISABLE()
        • -
      -
    • IS_RCC_PLLSAIN_VALUE() - macro: update the check condition
      • -
    • Add description of RCC - known Limitations
      • -
    • Rename HAL_RCC_CCSCallback() - by HAL_RCC_CSSCallback()
      • -
    • HAL_RCC_OscConfig() fix issues: 
      • -
        -
      • Remove the disable of - HSE oscillator when HSE_BYPASS is used as system clock - source or as PPL clock source
        • -
      • Add a check on HSERDY - flag when HSE_BYPASS is selected as new state for HSE - oscillator.
        • -
      -
    • Rename __HAL_RCC_I2SCLK() - by __HAL_RCC_I2S_Config()
      • -
    -
-

�  - HAL I2S update

-
    -
      -
    • HAL_I2S_Init(): add check on I2S - instance using CMSIS macro IS_I2S_ALL_INSTANCE() 
      • -
    • HAL_I2S_IRQHandler() - update for compliancy w/ C++
      • -
    • Add use of tmpreg - variable in __HAL_I2S_CLEAR_OVRFLAG() - and __HAL_I2S_CLEAR_UDRFLAG() macro for compliancy with C++
      • -
    • HAL_I2S_GetError(): update to return uint32_t - instead of HAL_I2S_ErrorTypeDef enumeration
      • -
    -
-

�  - HAL I2C update

-
    -
      -
    • Update to - clear the POS bit in the CR1 register at the end - of HAL_I2C_Master_Read_IT() and - HAL_I2C_Mem_Read_IT() process
      • -
    • Rename - HAL_I2CEx_DigitalFilter_Config()  by - HAL_I2CEx_ConfigDigitalFilter()
      • -
    • Rename - HAL_I2CEx_AnalogFilter_Config()  by - HAL_I2CEx_ConfigAnalogFilter()
      • -
    • Add use of tmpreg - variable in __HAL_I2C_CLEAR_ADDRFLAG() - and __HAL_I2C_CLEAR_STOPFLAG() macro for compliancy with C++
      • -
    -
  • HAL IrDA update
    • -
      -
    • DMA transmit process; - the code has been updated to avoid waiting on TC flag under DMA - ISR, IrDA TC interrupt is used instead. Below the update to be done - on user application:
      • -
        -
      • Configure and enable - the USART IRQ in HAL_IRDA_MspInit() - function
        • -
      • In stm32f4xx_it.c file, - UASRTx_IRQHandler() - function: add a call to HAL_IRDA_IRQHandler() function
        • -
      -
    • IT transmit process; the - code has been updated to avoid waiting on TC flag under IRDA ISR, - IrDA TC interrupt is used instead. No impact on user application
      • -
    • Rename Macros: add prefix - "__HAL"
      • -
        -
      • __IRDA_ENABLE() - by __HAL_IRDA_ENABLE()
        • -
      • __IRDA_DISABLE() - by __HAL_IRDA_DISABLE()
        • -
      -
    • Add new user macros to - manage the sample method feature
      • -
        -
      • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE()
        • -
      • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE()
        • -
      -
    • HAL_IRDA_Transmit_IT(): update to remove the - enable of the parity error interrupt
      • -
    • Add use of tmpreg - variable in __HAL_IRDA_CLEAR_PEFLAG() - macro for compliancy with C++
      • -
    • HAL_IRDA_Transmit_DMA() update to follow the - right procedure "Transmission using DMA"  in - the reference manual
      • -
        -
      • Add clear the TC flag - in the SR register before enabling the DMA transmit - request
        • -
      -
    -
  • HAL IWDG update
    • -
      -
    • Rename the defined IWDG - keys: 
      • -
        -
      • KR_KEY_RELOAD by - IWDG_KEY_RELOAD
        • -
      • KR_KEY_ENABLE by - IWDG_KEY_ENABLE
        • -
      • KR_KEY_EWA by - IWDG_KEY_WRITE_ACCESS_ENABLE
        • -
      • KR_KEY_DWA by - IWDG_KEY_WRITE_ACCESS_DISABLE
        • -
      -
    •  Add new macros - __HAL_IWDG_RESET_HANDLE_STATE() and - __HAL_IWDG_CLEAR_FLAG() 
      • -
    • Update - __HAL_IWDG_ENABLE_WRITE_ACCESS() and - __HAL_IWDG_DISABLE_WRITE_ACCESS() as private macro
      • -
    -
-

�  - HAL SPI update

-
    -
      -
    • HAL_SPI_TransmitReceive_DMA() update to remove the -  DMA Tx Error Callback initialization when SPI RxOnly - mode is selected
      • -
    • Add use of UNUSED(tmpreg) - in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), - __HAL_SPI_CLEAR_FREFLAG() to fix "Unused variable" - warning with TrueSTUDIO.
      • -
    • Rename Literals: remove - "D" from "DISABLED" and "ENABLED"
      • -
        -
      • SPI_TIMODE_DISABLED by - SPI_TIMODE_DISABLE
        • -
      • SPI_TIMODE_ENABLED by SPI_TIMODE_ENABLE
        • -
      • SPI_CRCCALCULATION_DISABLED - by -  SPI_CRCCALCULATION_DISABLE
        • -
      • SPI_CRCCALCULATION_ENABLED - by -  SPI_CRCCALCULATION_ENABLE
        • -
      -
    • Add use of tmpreg - variable in __HAL_SPI_CLEAR_MODFFLAG(), - __HAL_SPI_CLEAR_FREFLAG() and __HAL_SPI_CLEAR_OVRFLAG() macros for compliancy - with C++
      • -
    -
-

�  - HAL SDMMC update

-
    -
      -
    • IS_SDIO_ALL_INSTANCE() -  macro moved to CMSIS files
      • -
    -
  • HAL LTDC update
    • -
      -
    • HAL_LTDC_ConfigCLUT: optimize the function - when pixel format is LTDC_PIXEL_FORMAT_AL44 
      • -
        -
      • Update the size of - color look up table to 16 instead of 256 when the pixel - format is LTDC_PIXEL_FORMAT_AL44
        • -
      -
    -
  • HAL NAND update
    • -
      -
    • Rename NAND Address - structure to NAND_AddressTypeDef - instead of NAND_AddressTypedef
      • -
    • Update the used - algorithm of these functions
      • -
        -
      • HAL_NAND_Read_Page()
        • -
      • HAL_NAND_Write_Page()
        • -
      • HAL_NAND_Read_SpareArea()
        • -
      • HAL_NAND_Write_SpareArea()
        • -
      -
    • HAL_NAND_Write_Page(): move initialization - of tickstart - before while loop
      • -
    • HAL_NAND_Erase_Block(): add whait - until NAND status is ready before exiting this function
      • -
    -
  • HAL NOR update
    • -
      -
    • Rename NOR Address - structure to NOR_AddressTypeDef - instead of NOR_AddressTypedef
      • -
    • NOR Status literals renamed
      • -
        -
      • NOR_SUCCESS by - HAL_NOR_STATUS_SUCCESS
        • -
      • NOR_ONGOING by - HAL_NOR_STATUS_ONGOING
        • -
      • NOR_ERROR by - HAL_NOR_STATUS_ERROR
        • -
      • NOR_TIMEOUT by - HAL_NOR_STATUS_TIMEOUT
        • -
      -
    • HAL_NOR_GetStatus() update to fix Timeout - issue and exit from waiting loop when timeout occurred
      • -
    -
  • HAL PCCARD update
    • -
      -
    • Rename PCCARD Address - structure to HAL_PCCARD_StatusTypeDef - instead of CF_StatusTypedef
      • -
    • PCCARD Status literals renamed
      • -
        -
      • CF_SUCCESS by - HAL_PCCARD_STATUS_SUCCESS
        • -
      • CF_ONGOING by - HAL_PCCARD_STATUS_ONGOING
        • -
      • CF_ERROR - by HAL_PCCARD_STATUS_ERROR
        • -
      • CF_TIMEOUT by - HAL_PCCARD_STATUS_TIMEOUT
        • -
      -
    • Update "CF" by - "PCCARD" in functions, literals and - macros
      • -
    -
  • HAL PCD update
    • -
      -
    • Rename functions
      • -
        -
      • HAL_PCD_ActiveRemoteWakeup() by HAL_PCD_ActivateRemoteWakeup()
        • -
      • HAL_PCD_DeActiveRemoteWakeup() by HAL_PCD_DeActivateRemoteWakeup()
        • -
      -
    • Rename literals
      • -
        -
      • USB_FS_EXTI_TRIGGER_RISING_EDGE - by USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
        • -
      • USB_FS_EXTI_TRIGGER_FALLING_EDGE - by USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
        • -
      • USB_FS_EXTI_TRIGGER_BOTH_EDGE() - by USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
        • -
      • USB_HS_EXTI_TRIGGER_RISING_EDGE - by USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 
        • -
      • USB_HS_EXTI_TRIGGER_FALLING_EDGE - by USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
        • -
      • USB_HS_EXTI_TRIGGER_BOTH_EDGE - by USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
        • -
      • USB_HS_EXTI_LINE_WAKEUP - by USB_OTG_HS_EXTI_LINE_WAKEUP
        • -
      • USB_FS_EXTI_LINE_WAKEUP - by USB_OTG_FS_EXTI_LINE_WAKEUP
        • -
      -
    • Rename USB EXTI macros (FS, - HS referenced as SUBBLOCK here below)
      • -
        -
      • __HAL_USB_SUBBLOCK_EXTI_ENABLE_IT() -  by  __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_IT()  
        • -
      • __HAL_USB_SUBBLOCK_EXTI_DISABLE_IT() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_DISABLE_IT()
        • -
      • __HAL_USB_SUBBLOCK_EXTI_GET_FLAG() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GET_FLAG() 
        • -
      • __HAL_USB_SUBBLOCK_EXTI_CLEAR_FLAG() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_CLEAR_FLAG()
        • -
      • __HAL_USB_SUBBLOCK_EXTI_SET_RISING_EGDE_TRIGGER() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_EDGE()
        • -
      • __HAL_USB_SUBBLOCK_EXTI_SET_FALLING_EGDE_TRIGGER() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
        • -
      • __HAL_USB_SUBBLOCK_EXTI_SET_FALLINGRISING_TRIGGER() - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
        • -
      • __HAL_USB_SUBBLOCK_EXTI_GENERATE_SWIT()  - by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GENERATE_SWIT()                                       -
        • -
      -
    -
-
    -
  • HAL RNG update
    • -
      -
    • Add new functions
      • -
        -
      • HAL_RNG_GenerateRandomNumber(): to generate a - 32-bits random number, return - random value in argument and return HAL status.
        • -
      • HAL_RNG_GenerateRandomNumber_IT(): to  start - generation of the 32-bits random number, user should call - the HAL_RNG_ReadLastRandomNumber() - function under the HAL_RNG_ReadyCallback() to get - the generated random value.
        • -
      • HAL_RNG_ReadLastRandomNumber(): to return the - last random value stored in the RNG handle
        • -
      -
    • HAL_RNG_GetRandomNumber(): return value update - (obsolete), replaced by HAL_RNG_GenerateRandomNumber()
      • -
    • HAL_RNG_GetRandomNumber_IT(): wrong implementation - (obsolete), replaced by HAL_RNG_GenerateRandomNumber_IT()
      • -
    • __HAL_RNG_CLEAR_FLAG() - macro (obsolete), replaced by new __HAL_RNG_CLEAR_IT() macro
      • -
    • Add new define - for RNG ready interrupt:  RNG_IT_DRDY
      • -
    -
  • HAL RTC update
    • -
      -
    • HAL_RTC_GetTime() and HAL_RTC_GetDate(): - add the comment below
      • -
    -
-
-
-

  - * @note You must call HAL_RTC_GetDate() - after HAL_RTC_GetTime() - to unlock the values
-   - * in the higher-order calendar shadow registers to ensure consistency - between the time and date values.
-   - * Reading RTC current time locks the values in calendar shadow registers - until Current date is read. 

-
-
-
    -
      -
    • Rename literals: add - prefix "__HAL"
      • -
        -
      • FORMAT_BIN by HAL_FORMAT_BIN
        • -
      • FORMAT_BCD - by HAL_FORMAT_BCD
        • -
      -
    • Rename macros (ALARM, - WAKEUPTIMER and TIMESTAMP referenced as SUBBLOCK here - below)
      • -
        -
      • __HAL_RTC_EXTI_ENABLE_IT() - by  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_IT()
        • -
      • __HAL_RTC_EXTI_DISABLE_IT() - by  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_IT()
        • -
      • __HAL_RTC_EXTI_CLEAR_FLAG() - by  __HAL_RTC_SUBBLOCK_EXTI_CLEAR_FLAG()
        • -
      • __HAL_RTC_EXTI_GENERATE_SWIT() - by __HAL_RTC_SUBBLOCK_EXTI_GENERATE_SWIT()
        • -
      -
    • Add new macros (ALARM, - WAKEUPTIMER and TAMPER_TIMESTAMP referenced as SUBBLOCK here - below)
      • -
        -
      • __HAL_RTC_SUBBLOCK_GET_IT_SOURCE() 
        • -
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_EVENT()
        • -
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_EVENT()
        • -
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_FALLING_EDGE()
        • -
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_FALLING_EDGE()
        • -
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_EDGE()
        • -
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_EDGE()
        • -
      •  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_FALLING_EDGE()
        • -
      •  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_FALLING_EDGE()
        • -
      •  __HAL_RTC_SUBBLOCK_EXTI_GET_FLAG()
        • -
      -
    -
  • HAL SAI update
    • -
      -
    • Update SAI_STREOMODE - by SAI_STEREOMODE
      • -
    • Update FIFO status Level - defines in upper case
      • -
    • Rename literals: remove - "D" from "DISABLED" and "ENABLED"
      • -
        -
      • SAI_OUTPUTDRIVE_DISABLED -  by SAI_OUTPUTDRIVE_DISABLE
        • -
      • SAI_OUTPUTDRIVE_ENABLED -  by SAI_OUTPUTDRIVE_ENABLE
        • -
      • SAI_MASTERDIVIDER_ENABLED  by - SAI_MASTERDIVIDER_ENABLE
        • -
      • SAI_MASTERDIVIDER_DISABLED  by - SAI_MASTERDIVIDER_DISABLE
        • -
      -
    -
-
    -
  • HAL SD update
    • -
      -
    • Rename - SD_CMD_SD_APP_STAUS by SD_CMD_SD_APP_STATUS
      • -
    • SD_PowerON() updated to add 1ms - required power up waiting time before starting the SD - initialization sequence
      • -
    • SD_DMA_RxCplt()/SD_DMA_TxCplt(): - add a call to HAL_DMA_Abort()
      • -
    • HAL_SD_ReadBlocks() update to - set the defined DATA_BLOCK_SIZE as SDIO DataBlockSize - parameter
      • -
    • HAL_SD_ReadBlocks_DMA()/HAL_SD_WriteBlocks_DMA() - update to call the HAL_DMA_Start_IT() function - with DMA Datalength - set to BlockSize/4  - as the DMA is configured in word 
      • -
    -
  • HAL SMARTCARD update 
    • -
      -
    • DMA transmit process; - the code has been updated to avoid waiting on TC flag under DMA - ISR, SMARTCARD TC interrupt is used instead. Below the update to be - done on user application:
      • -
        -
      • Configure and enable - the USART IRQ in HAL_SAMRTCARD_MspInit() - function
        • -
      • In stm32f4xx_it.c file, - UASRTx_IRQHandler() - function: add a call to HAL_SMARTCARD_IRQHandler() - function
        • -
      -
    • IT transmit process; the - code has been updated to avoid waiting on TC flag under SMARTCARD - ISR, SMARTCARD TC interrupt is used instead. No impact on user - application
      • -
    • Rename macros: add - prefix "__HAL"
      • -
        -
      • __SMARTCARD_ENABLE() - by __HAL_SMARTCARD_ENABLE()
        • -
      • __SMARTCARD_DISABLE() - by __HAL_SMARTCARD_DISABLE()
        • -
      • __SMARTCARD_ENABLE_IT() - by __HAL_SMARTCARD_ENABLE_IT()
        • -
      • __SMARTCARD_DISABLE_IT() - by __HAL_SMARTCARD_DISABLE_IT()
        • -
      • __SMARTCARD_DMA_REQUEST_ENABLE() - by __HAL_SMARTCARD_DMA_REQUEST_ENABLE()
        • -
      • __SMARTCARD_DMA_REQUEST_DISABLE() - by __HAL_SMARTCARD_DMA_REQUEST_DISABLE()
        • -
      -
    • Rename literals: remove - "D" from "DISABLED" and "ENABLED"
      • -
        -
      • SMARTCARD_NACK_ENABLED by - SMARTCARD_NACK_ENABLE
        • -
      • SMARTCARD_NACK_DISABLED by SMARTCARD_NACK_DISABLE
        • -
      -
    • Add new user macros to - manage the sample method feature
      • -
        -
      • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE()
        • -
      • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE()
        • -
      -
    • Add use of tmpreg - variable in __HAL_SMARTCARD_CLEAR_PEFLAG() - macro for compliancy with C++
      • -
    • HAL_SMARTCARD_Transmit_DMA() update to follow the - right procedure "Transmission using DMA"  in - the reference manual
      • -
        -
      • Add clear the TC flag - in the SR register before enabling the DMA transmit - request
        • -
      -
    -
  • HAL TIM update
    • -
      -
    • Add TIM_CHANNEL_ALL as - possible value for all Encoder Start/Stop APIs Description
      • -
    • HAL_TIM_OC_ConfigChannel() remove call to - IS_TIM_FAST_STATE() assert macro
      • -
    • HAL_TIM_PWM_ConfigChannel() add a call to - IS_TIM_FAST_STATE() assert macro to check the OCFastMode - parameter
      • -
    • HAL_TIM_DMADelayPulseCplt() Update to set the TIM - Channel before to call  HAL_TIM_PWM_PulseFinishedCallback()
      • -
    • HAL_TIM_DMACaptureCplt() update to set the TIM - Channel before to call  HAL_TIM_IC_CaptureCallback()
      • -
    • TIM_ICx_ConfigChannel() update to fix - Timer CCMR1 register corruption when setting ICFilter - parameter
      • -
    • HAL_TIM_DMABurst_WriteStop()/HAL_TIM_DMABurst_ReadStop() - update to abort the DMA transfer for the specifc TIM - channel
      • -
    • Add new function for TIM - Slave configuration in IT mode: HAL_TIM_SlaveConfigSynchronization_IT() 
      • -
    • HAL_TIMEx_ConfigBreakDeadTime() add an assert check on - Break & DeadTime - parameters values
      • -
    • HAL_TIMEx_OCN_Start_IT() add the enable of - Break Interrupt for all output modes
      • -
    • Add new macros to - ENABLE/DISABLE URS bit in TIM CR1 register:
      • -
        -
      • __HAL_TIM_URS_ENABLE()
        • -
      • __HAL_TIM_URS_DISABLE()
        • -
      -
    • Add new macro for TIM - Edge modification: __HAL_TIM_SET_CAPTUREPOLARITY()
      • -
    -
  • HAL UART update
    • -
      -
    • Add IS_LIN_WORD_LENGTH() - and IS_LIN_OVERSAMPLING()  macros: to check respectively WordLength - and OverSampling - parameters in LIN mode
      • -
    • DMA transmit process; - the code has been updated to avoid waiting on TC flag under DMA - ISR, UART TC interrupt is used instead. Below the update to be done - on user application:
      • -
        -
      • Configure and enable - the USART IRQ in HAL_UART_MspInit() - function
        • -
      • In stm32f4xx_it.c file, - USARTx_IRQHandler() - function: add a call to HAL_UART_IRQHandler() function
        • -
      -
    • IT transmit process; the - code has been updated to avoid waiting on TC flag under - UART ISR, UART TC interrupt is used instead. No impact on user - application
      • -
    • Rename macros:
      • -
        -
      • __HAL_UART_ONEBIT_ENABLE() - by __HAL_UART_ONE_BIT_SAMPLE_ENABLE()
        • -
      • __HAL_UART_ONEBIT_DISABLE() - by __HAL_UART_ONE_BIT_SAMPLE_DISABLE()
        • -
      -
    • Rename literals:
      • -
        -
      • UART_WAKEUPMETHODE_IDLELINE by - UART_WAKEUPMETHOD_IDLELINE
        • -
      • UART_WAKEUPMETHODE_ADDRESSMARK by - UART_WAKEUPMETHOD_ADDRESSMARK
        • -
      -
    • Add use of tmpreg - variable in __HAL_UART_CLEAR_PEFLAG() - macro for compliancy with C++
      • -
    • HAL_UART_Transmit_DMA() update to follow the - right procedure "Transmission using DMA" in the reference - manual
      • -
        -
      • Add clear the TC flag - in the SR register before enabling the DMA transmit - request
        • -
      -
    -
  • HAL USART update
    • -
      -
    • DMA transmit process; - the code has been updated to avoid waiting on TC flag under DMA - ISR, USART TC interrupt is used instead. Below the update to be - done on user application:
      • -
        -
      • Configure and enable - the USART IRQ in HAL_USART_MspInit() - function
        • -
      • In stm32f4xx_it.c file, - USARTx_IRQHandler() - function: add a call to HAL_USART_IRQHandler() - function
        • -
      -
    • IT transmit process; the - code has been updated to avoid waiting on TC flag under - USART ISR, USART TC interrupt is used instead. No impact on - user application
      • -
    • HAL_USART_Init() update to enable - the USART oversampling by 8 by default in order to reach max USART - frequencies
      • -
    • USART_DMAReceiveCplt() update to set the - new USART state after checking on the old state
      • -
    • HAL_USART_Transmit_DMA()/HAL_USART_TransmitReceive_DMA() - update to follow the - right procedure "Transmission using DMA"  in - the reference manual
      • -
        -
      • Add clear the TC flag - in the SR register before enabling the DMA transmit - request
        • -
      -
    • Rename macros:
      • -
        -
      • __USART_ENABLE() - by __HAL_USART_ENABLE()
        • -
      • __USART_DISABLE() - by __HAL_USART_DISABLE()
        • -
      • __USART_ENABLE_IT() - by __HAL_USART_ENABLE_IT()
        • -
      • __USART_DISABLE_IT() - by __HAL_USART_DISABLE_IT()
        • -
      -
    • Rename literals: remove - "D" from "DISABLED" and "ENABLED"
      • -
        -
      • USART_CLOCK_DISABLED by - USART_CLOCK_DISABLE
        • -
      • USART_CLOCK_ENABLED by - USART_CLOCK_ENABLE
        • -
      • USARTNACK_ENABLED by - USART_NACK_ENABLE
        • -
      • USARTNACK_DISABLED by - USART_NACK_DISABLE
        • -
      -
    • Add new user macros to - manage the sample method feature
      • -
        -
      • __HAL_USART_ONE_BIT_SAMPLE_ENABLE()
        • -
      • __HAL_USART_ONE_BIT_SAMPLE_DISABLE()
        • -
      -
    • Add use of tmpreg - variable in __HAL_USART_CLEAR_PEFLAG() - macro for compliancy with C++
      • -
    -
  • HAL WWDG update
    • -
      -
    • Add new parameter in - __HAL_WWDG_ENABLE_IT() - macro
      • -
    • Add new macros to manage - WWDG IT & correction:
      • -
        -
      • __HAL_WWDG_DISABLE()
        • -
      • __HAL_WWDG_DISABLE_IT()
        • -
      • __HAL_WWDG_GET_IT()
        • -
      • __HAL_WWDG_GET_IT_SOURCE()
        • -
      -
    -
-

V1.1.0 / - 19-June-2014

-

Main Changes

-
    -
  • Add support of STM32F411xE - devices
    • -
-
    -
  • HAL generic update
    • -
      -
    • Enhance HAL delay and - time base implementation
      • -
        -
      • Systick timer is used by - default as source of time base, but user can eventually implement - his proper time base source (a general purpose - timer for example or other time source)
        • -
      • Functions affecting - time base configurations are declared as __Weak to make override - possible in case of other implementations in user file, for more - details please refer to HAL_TimeBase example
        • -
      -
    • Fix flag clear - procedure: use atomic write operation "=" instead of - ready-modify-write operation "|=" or "&="
      • -
    • Fix on Timeout - management, Timeout value set to 0 passed to API automatically - exits the function after checking the flag without any wait
      • -
    • Common update for the - following communication peripherals: SPI, UART, USART and IRDA
      • -
        -
      • Add DMA circular mode support
        • -
      • Remove lock from - recursive process
        • -
      -
    • Add new macro - __HAL_RESET_HANDLE_STATE to reset a given handle state
      • -
    • Add a new attribute for - functions executed from internal SRAM and depending from - Compiler implementation
      • -
    • When USE_RTOS == 1 (in - stm32l0xx_hal_conf.h), the __HAL_LOCK() is - not defined instead of being defined empty
      • -
    • Miscellaneous comments - and formatting update
      • -
    • stm32f4xx_hal_conf_template.h
      • -
        -
      • Add a new define for - LSI default value LSI_VALUE
        • -
      • Add a new define for - LSE default value LSE_VALUE
        • -
      • Add a new define for - Tick interrupt priority TICK_INT_PRIORITY (needed for the enhanced - time base implementation)
        • -
      -
    • Important - Note: - aliases has been added for any API naming change, to keep - compatibility with previous version
      • -
    -
  • HAL GPIO update
    • -
-
    -
      -
    • Add a new macro __HAL_GPIO_EXTI_GENERATE_SWIT() - to manage the generation of software interrupt on selected EXTI - line
      • -
    • HAL_GPIO_Init(): use temporary - variable when modifying the registers, to avoid unexpected - transition in the GPIO pin configuration
      • -
    • Remove IS_GET_GPIO_PIN - macro
      • -
    • Add a new function HAL_GPIO_LockPin()
      • -
    • Private Macro - __HAL_GET_GPIO_SOURCE renamed into GET_GPIO_SOURCE
      • -
    • Add the support of - STM32F411xx devices - : add the new Alternate functions values related to - new remap added for SPI, USART, I2C
      • -
    • Update the following HAL - GPIO macros description: rename EXTI_Linex - by GPIO_PIN_x
      • -
        -
      • __HAL_GPIO_EXTI_CLEAR_IT()
        • -
      • __HAL_GPIO_EXTI_GET_IT()
        • -
      • __HAL_GPIO_EXTI_CLEAR_FLAG()
        • -
      • __HAL_GPIO_EXTI_GET_FLAG()
        • -
      -
    -
-

�  - HAL DMA update

-
    -
      -
    • Fix in HAL_DMA_PollForTransfer() - to:
      • -
        -
      • set DMA error code in - case of HAL_ERROR status
        • -
      • set HAL Unlock before - DMA state update
        • -
      -
    -
-

�  - HAL DMA2D update

-
    -
      -
    • Add configuration of - source address in case of A8 or A4 M2M_PFC DMA2D mode
      • -
    -
  • HAL FLASH update
    • -
-
    -
      -
    • Functions reorganization - update, depending on the features supported by each STM32F4 device
      • -
    • Add new driver - (stm32f4xx_hal_flash_ramfunc.h/.c) to manage function executed from - RAM, these functions are available only for STM32F411xx Devices
      • -
        -
      • FLASH_StopFlashInterfaceClk()  : Stop the flash - interface while System Run
        • -
      • FLASH_StartFlashInterfaceClk() : Stop the flash - interface while System Run
        • -
      • FLASH_EnableFlashSleepMode() : Enable the flash - sleep while System Run
        • -
      • FLASH_DisableFlashSleepMode() :  Disable the - flash sleep while System Run
        • -
      -
    -
-
    -
  • HAL PWR update
    • -
-
    -
      -
    • HAL_PWR_PVDConfig(): add clear of the EXTI - trigger before new configuration
      • -
    • Fix in HAL_PWR_EnterSTANDBYMode() - to not clear Wakeup flag (WUF), which need to be cleared at - application level before to call this function
      • -
    • HAL_PWR_EnterSLEEPMode()
      • -
        -
      • Remove disable and - enable of SysTick - Timer
        • -
      • Update usage of __WFE() - in low power entry function: if there is a pending event, calling - __WFE() will not enter the CortexM4 core to sleep mode. The - solution is to made the call below; the first __WFE() is - always ignored and clears the event if one was already pending, - the second is always applied
        • -
      -
    -
-
-

__SEV()
- __WFE()
- __WFE()

-
-
    -
      -
    • Add new macro for - software event generation __HAL_PVD_EXTI_GENERATE_SWIT()
      • -
    • Remove the following - defines form Generic driver and add them under extension driver - because they are only used within extension functions.
      • -
        -
      • CR_FPDS_BB: used within - HAL_PWREx_EnableFlashPowerDown() - function
        • -
      • CSR_BRE_BB: used within - HAL_PWREx_EnableBkUpReg() - function
        • -
      -
    • Add the support of - STM32F411xx devices add the define STM32F411xE
      • -
        -
      • For STM32F401xC, - STM32F401xE and STM32F411xE devices add the following functions - used to enable or disable the low voltage mode for regulators
        • -
      -
    -
-
    -
      -
        -
          -
        • HAL_PWREx_EnableMainRegulatorLowVoltage()
          • -
        • HAL_PWREx_DisableMainRegulatorLowVoltage()
          • -
        • HAL_PWREx_EnableLowRegulatorLowVoltage()
          • -
        • HAL_PWREx_DisableLowRegulatorLowVoltage()
          • -
        -
      -
    • For STM32F42xxx/43xxx - devices, add a new function for Under Driver management as the - macro already added for this mode is not sufficient: HAL_PWREx_EnterUnderDriveSTOPMode()
      • -
    -
-
    -
  • HAL RCC update
    • -
      -
    • In HAL_RCC_ClockConfig() - function: update the AHB clock divider before clock switch to new - source
      • -
    • Allow to calibrate the - HSI when it is used as system clock source
      • -
    • Rename the following macros
      • -
        -
      • __OTGFS_FORCE_RESET ()  - by __USB_OTG_FS_FORCE_RESET()
        • -
      • __OTGFS_RELEASE_RESET ()  - by  __USB_OTG_FS_RELEASE_RESET()
        • -
      • __OTGFS_CLK_SLEEP_ENABLE - ()  - by  __USB_OTG_FS_CLK_SLEEP_ENABLE()
        • -
      • __OTGFS_CLK_SLEEP_DISABLE - () by  - __USB_OTG_FS_CLK_SLEEP_DISABLE()
        • -
      -
    -
-

 

-
    -
      -
    • Add new field PLLI2SM in - RCC_PLLI2SInitTypeDef structure, this division factor is added for - PLLI2S VCO input clock only STM32F411xE devices => the FW - compatibility is broken vs. STM32F401xx devices
      • -
    • Update HAL_RCCEx_PeriphCLKConfig() - and  HAL_RCCEx_GetPeriphCLKConfig()  - functions to support the new PLLI2SM
      • -
    • Add new function to - manage the new LSE mode - : HAL_RCCEx_SelectLSEMode()
      • -
    • Reorganize the macros - depending from - Part number used and make them more clear
      • -
    -
-

�  HAL UART update

-
    -
      -
    • Add new macros to - control CTS and RTS
      • -
    • Add specific macros to - manage the flags cleared only by a software sequence
      • -
        -
      • __HAL_UART_CLEAR_PEFLAG()
        • -
      • __HAL_UART_CLEAR_FEFLAG()
        • -
      • __HAL_UART_CLEAR_NEFLAG()
        • -
      • __HAL_UART_CLEAR_OREFLAG()
        • -
      • __HAL_UART_CLEAR_IDLEFLAG()
        • -
      -
    • Add several enhancements - without affecting the driver functionalities -
      • -
        -
      • Remove the check on - RXNE set after reading the Data in the DR register
        • -
      • Update the transmit - processes to use TXE instead of TC
        • -
      • Update HAL_UART_Transmit_IT() - to enable UART_IT_TXE instead of UART_IT_TC
        • -
      -
    -
-

�  - HAL USART update

-
    -
      -
    • Add specific macros to - manage the flags cleared only by a software sequence
      • -
        -
      • __HAL_USART_CLEAR_PEFLAG()
        • -
      • __HAL_USART_CLEAR_FEFLAG()
        • -
      • __HAL_USART_CLEAR_NEFLAG()
        • -
      • __HAL_USART_CLEAR_OREFLAG()
        • -
      • __HAL_USART_CLEAR_IDLEFLAG()
        • -
      -
    • Update HAL_USART_Transmit_IT() - to enable USART_IT_TXE instead of USART_IT_TC
      • -
    -
-

�  - HAL IRDA update

-
    -
      -
    • Add specific macros to - manage the flags cleared only by a software sequence
      • -
        -
      • __HAL_IRDA_CLEAR_PEFLAG()
        • -
      • __HAL_ IRDA _CLEAR_FEFLAG()
        • -
      • __HAL_ IRDA _CLEAR_NEFLAG()
        • -
      • __HAL_ IRDA _CLEAR_OREFLAG()
        • -
      • __HAL_ IRDA _CLEAR_IDLEFLAG()
        • -
      -
    • Add several enhancements - without affecting the driver functionalities
      • -
    -
-
    -
      -
        -
      • Remove the check on - RXNE set after reading the Data in the DR register
        • -
      • Update HAL_IRDA_Transmit_IT() - to enable IRDA_IT_TXE instead of IRDA_IT_TC
        • -
      -
    • Add the following APIs - used within DMA process -
      • -
        -
      • HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef - *hirda);
        • -
      • HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef - *hirda);
        • -
      • HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef - *hirda); -
        • -
      • void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef - *hirda);
        • -
      • void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef - *hirda);
        • -
      -
    -
-

�  - HAL SMARTCARD update

-
    -
      -
    • Add specific macros to - manage the flags cleared only by a software sequence
      • -
        -
      • __HAL_SMARTCARD_CLEAR_PEFLAG()
        • -
      • __HAL_SMARTCARD_CLEAR_FEFLAG()
        • -
      • __HAL_SMARTCARD_CLEAR_NEFLAG()
        • -
      • __HAL_SMARTCARD_CLEAR_OREFLAG()
        • -
      • __HAL_SMARTCARD_CLEAR_IDLEFLAG()
        • -
      -
    • Add several enhancements - without affecting the driver functionalities
      • -
        -
      • Add a new state HAL_SMARTCARD_STATE_BUSY_TX_RX - and all processes has been updated accordingly
        • -
      • Update HAL_SMARTCARD_Transmit_IT() - to enable SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC
        • -
      -
    -
-
    -
  • HAL SPI - update -
    • -
      -
    • Bugs fix
      • -
        -
      • SPI interface is used - in synchronous polling mode: at high clock rates like SPI prescaler - 2 and 4, calling
        - HAL_SPI_TransmitReceive() - returns with error HAL_TIMEOUT
        • -
      • HAL_SPI_TransmitReceive_DMA() does not clean up the - TX DMA, so any subsequent SPI calls return the DMA error
        • -
      • HAL_SPI_Transmit_DMA() is failing when data - size is equal to 1 byte
        • -
      -
    • Add the following APIs - used within the DMA process
      • -
    -
-
    -
      -
        -
      • HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef - *hspi);
        • -
      • HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef - *hspi);
        • -
      • HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef - *hspi);
        • -
      • void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef - *hspi);
        • -
      • void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef - *hspi);
        • -
      • void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef - *hspi);
        • -
      -
    -
-
    -
  • HAL RNG update
    • -
      -
        -
      • Add a conditional - define to make this driver visible for all STM32F4xx devices - except STM32F401xx and STM32F411xx Devices.
        • -
      -
    -
  • HAL CRC update
    • -
      -
        -
      • These macros are added - to read/write the CRC IDR register: __HAL_CRC_SET_IDR() - and __HAL_CRC_GET_IDR()
        • -
      -
    -
-
    -
  • HAL DAC update -
    • -
      -
    • Enhance the DMA channel - configuration when used with DAC
      • -
    -
  • HAL TIM update
    • -
      -
    • HAL_TIM_IRQHandler(): update to check the - input capture channel 3 and 4 in CCMR2 instead of CCMR1
      • -
    • __HAL_TIM_PRESCALER() - updated to use '=' instead of '|='
      • -
    • Add the following macro - in TIM HAL driver
      • -
        -
      • __HAL_TIM_GetCompare() -
        • -
      • __HAL_TIM_GetCounter() -
        • -
      • __HAL_TIM_GetAutoreload() -
        • -
      • __HAL_TIM_GetClockDivision() -
        • -
      • __HAL_TIM_GetICPrescaler()
        • -
      -
    -
  • HAL SDMMC update
    • -
-
    -
      -
    • Use of CMSIS constants - instead of magic values
      • -
    • Miscellaneous update in - functions internal coding
      • -
    -
  • HAL NAND update
    • -
      -
    • Fix issue of - macros returning wrong address for NAND blocks
      • -
    • Fix issue - for read/write NAND page/spare area
      • -
    -
  • HAL NOR update
    • -
      -
    • Add the NOR - address bank macro used within the API
      • -
    • Update NOR - API implementation to avoid the use of NOR address bank hard coded
      • -
    -
  • HAL HCD update
    • -
      -
    • HCD_StateTypeDef structure members renamed
      • -
    • These macro are renamed
      • -
        -
      • __HAL_GET_FLAG(__HANDLE__, - __INTERRUPT__)    by __HAL_HCD_GET_FLAG(__HANDLE__, - __INTERRUPT__)
        • -
      • __HAL_CLEAR_FLAG(__HANDLE__, - __INTERRUPT__) by __HAL_HCD_CLEAR_FLAG(__HANDLE__, - __INTERRUPT__) 
        • -
      • __HAL_IS_INVALID_INTERRUPT(__HANDLE__)  - by __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) 
        • -
      -
    -
  • HAL PCD update
    • -
      -
    • HAL_PCD_SetTxFiFo() and HAL_PCD_SetRxFiFo() - renamed into HAL_PCDEx_SetTxFiFo() - and HAL_PCDEx_SetRxFiFo() - and moved to the extension files stm32f4xx_hal_pcd_ex.h/.c
      • -
    • PCD_StateTypeDef structure members renamed
      • -
    • Fix incorrect masking of - TxFIFOEmpty
      • -
    • stm32f4xx_ll_usb.c: fix - issue in HS mode
      • -
    • New macros added
      • -
        -
      • __HAL_PCD_IS_PHY_SUSPENDED()
        • -
      • __HAL_USB_HS_EXTI_GENERATE_SWIT()
        • -
      • __HAL_USB_FS_EXTI_GENERATE_SWIT()
        • -
      -
    • These macro are renamed
      • -
        -
      • __HAL_GET_FLAG(__HANDLE__, - __INTERRUPT__)    by __HAL_PCD_GET_FLAG(__HANDLE__, - __INTERRUPT__)
        • -
      • __HAL_CLEAR_FLAG(__HANDLE__, - __INTERRUPT__) by __HAL_PCD_CLEAR_FLAG(__HANDLE__, - __INTERRUPT__) 
        • -
      • __HAL_IS_INVALID_INTERRUPT(__HANDLE__)  - by __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) 
        • -
      • __HAL_PCD_UNGATE_CLOCK(__HANDLE__) - by __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
        • -
      • __HAL_PCD_GATE_CLOCK(__HANDLE__) - by __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)
        • -
      -
    -
  • HAL ETH update
    • -
      -
    • Update HAL_ETH_GetReceivedFrame_IT() - function to return HAL_ERROR if the received packet is not complete
      • -
    • Use HAL_Delay() - instead of counting loop
      • -
    •  __HAL_ETH_MAC_CLEAR_FLAG() - macro is removed: the MACSR register is read only
      • -
    • Add the following macros - used to Wake up the device from STOP mode by Ethernet event :
      • -
        -
      • __HAL_ETH_EXTI_ENABLE_IT()
        • -
      • __HAL_ETH_EXTI_DISABLE_IT()
        • -
      • __HAL_ETH_EXTI_GET_FLAG()
        • -
      • __HAL_ETH_EXTI_CLEAR_FLAG()
        • -
      • __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER()
        • -
      • __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER()
        • -
      • __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER()
        • -
      -
    -
  • HAL WWDG - update
    • -
      -
    • Update macro parameters - to use underscore: __XXX__
      • -
    • Use of CMSIS constants - instead of magic values
      • -
    • Use MODIFY_REG macro in HAL_WWDG_Init()
      • -
    • Add IS_WWDG_ALL_INSTANCE - in HAL_WWDG_Init() - and HAL_WWDG_DeInit()
      • -
    -
  • HAL IWDG - update
    • -
      -
    • Use WRITE_REG instead of - SET_BIT for all IWDG macros
      • -
    • __HAL_IWDG_CLEAR_FLAG - removed: no IWDG flag cleared by access to SR register
      • -
    • Use MODIFY_REG macro in HAL_IWDG_Init()
      • -
    • Add IS_IWDG_ALL_INSTANCE - in HAL_IWDG_Init()Add - the following macros used to Wake
      • -
    -
-

V1.0.0 / - 18-February-2014

-

Main Changes

-
    -
  • First official release
    • -
-

License

-

Redistribution - and use in source and binary forms, with or without modification, are - permitted provided that the following conditions are met:

-
    -
  1. Redistributions of source code must retain the - above copyright notice, this list of conditions and the following - disclaimer.
    2. -
  2. Redistributions in binary form must reproduce the - above copyright notice, this list of conditions and the following - disclaimer in the documentation and/or other materials provided with - the distribution.
    3. -
  3. Neither the name of STMicroelectronics nor the - names of its contributors may be used to endorse or promote products - derived
    4. -
-

       - from this software without specific prior written permission.
-
- THIS - SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-
-
-
-

For - complete documentation on STM32 - Microcontrollers visit www.st.com/STM32

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Release + + + + Notes for STM32F4xx HAL Drivers

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+ + + + + + +
+ + + + + + + + + +
+

Update + + + + History

+

V1.7.13 + / 16-July-2021

+
+

Main + + + + + Changes
+

+
+
    +
  • +

    HAL + updates

    + +
      + + +
    • HAL EXTI + update +
        +
      • Update + HAL_EXTI_GetConfigLine() + API to set default + configuration value of + Trigger and GPIOSel + before checking each + corresponding registers.
        • +
      +
      • + + +
    • HAL GPIO + update +
        +
      • Update + HAL_GPIO_Init() API to + avoid the configuration + of PUPDR register when + Analog mode is selected.
        • +
      +
      • + + +
    • HAL DMA + update +
        +
      • Update + HAL_DMA_IRQHandler() API + to set the DMA state + before unlocking access + to the DMA handle.
        • +
      +
      • + + +
    • HAL/LL ADC + update +
        +
      • Update + LL_ADC_DeInit() API to + clear missing SQR3 + register.
        • +
      • Update + LL_ADC_DMA_GetRegAddr() + API to prevent unused + argument compilation + warning.
        • +
      • Update HAL + timeout mechanism to + avoid false timeout + detection in case of + preemption.
        • +
      +
      • + + +
    • HAL CAN + update +
        +
      • Update + HAL_CAN_Init() API to be + aligned with referance + manual and to avoid + timeout error:
        • +
      +
      • + + +
    • HAL/LL + RTC_BKP update +
        +
      • Update + __HAL_RTC_�(__HANDLE__, + �) macros to access + registers through + (__HANDLE__)->Instance + pointer and avoid + �unused variable� + warnings.
        • +
      • Correct month + management in + IS_LL_RTC_MONTH() macro.
        • +
      +
      • + + +
    • HAL RNG + update +
        +
      • Update timeout + mechanism to avoid false + timeout detection in + case of preemption.
        • +
      +
      • + + +
    • HAL QSPI + update +
        +
      • ES0305 + workaround disabled for + STM32412xx devices.
        • +
      +
      • + + +
    • HAL I2C + update +
        +
      • Update + HAL_I2C_Mem_Write_DMA() + and + HAL_I2C_Mem_Read_DMA() + APIs to initialize + Devaddress, Memaddress + and EventCount + parameters.
        • +
      • Update to + prevent several calls of + Start bit: +
          +
        • Update + I2C_MemoryTransmit_TXE_BTF() + API to increment + EventCount.
          • +
        +
        • +
      • Update to + avoid I2C interrupt in + endless loop: +
          +
        • Update + HAL_I2C_Master_Transmit_IT(), + HAL_I2C_Master_Receive_IT(), + + HAL_I2C_Master_Transmit_DMA() + + and + HAL_I2C_Master_Receive_DMA() + APIs to unlock the + I2C peripheral + before generating + the start.
          • +
        +
        • +
      • Update to use + the right macro to clear + I2C ADDR flag inside + I2C_Slave_ADDR() API as + it�s indicated in the + reference manual.
        • +
      • Update + I2C_IsAcknowledgeFailed() + API to avoid I2C in busy + state if NACK received + after transmitting + register address.
        • +
      • Update + HAL_I2C_EV_IRQHandler() + and + I2C_MasterTransmit_BTF() + APIs to correctly manage + memory transfers: +
          +
        • Add check + on memory mode + before calling + callbacks + procedures.
          • +
        +
        • +
      +
      • + + +
    • LL USART + update +
        +
      • Handling of + UART concurrent register + access in case of race + condition between Tx and + Rx transfers (HAL UART + and LL LPUART)
        • +
      +
      • + + +
    • HAL SMBUS + update +
        +
      • Updated + HAL_SMBUS_ER_IRQHandler() + API to return the + correct error code + �SMBUS_FLAG_PECERR� in + case of packet error + occurs.
        • +
      +
      • + + +
    • HAL/LL SPI + update +
        +
      • Updated to fix + MISRA-C 2012 Rule-13.2.
        • +
      • Update + LL_SPI_TransmitData8() + API to avoid casting the + result to 8 bits.
        • +
      +
      • + + +
    • HAL UART + update +
        +
      • Fix wrong + comment related to RX + pin configuration within + the description section
        • +
      • Correction on + UART ReceptionType + management in case of + ReceptionToIdle API are + called from RxEvent + callback
        • +
      • Handling of + UART concurrent register + access in case of race + condition between Tx and + Rx transfers (HAL UART + and LL LPUART) +
          +
        • Update CAN + Initialization + sequence to set + "request + initialization" bit + before exit from + sleep mode.
          • +
        +
        • +
      +
      • + + +
    • HAL USB + update +
        + +
      • HAL PCD: add + fix transfer complete + for IN Interrupt + transaction in single + buffer mode
        • + +
      • Race condition + in USB PCD control + endpoint receive ISR.
        • +
      +
      • +
    +
    • +
+

V1.7.12 + / 26-March-2021

+

Main + + + + + Changes

+
    +
  • HAL
    • +
      +
    • HAL/LL + USART update
      • +
        +
      • Fix typo in + USART_Receive_IT() and + USART_TransmitReceive_IT() + APIs to avoid possible + compilation issues if the + UART driver files are not + included.
        • +
      +
    +
+

V1.7.11 + / 12-February-2021

+

Main + + + + + Changes

+
    +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • Added + + + + new HAL + + + + FMPSMBUS extended driver + + + + + to support FMPSMBUS fast Mode + Plus.
    • +
  • Removed + + + + �register� keyword to be + compliant with new C++ rules:
    • +
      +
    • The register + storage class specifier was + deprecated in C++11 and + removed in C++17.
      • +
    +
  • HAL
    • +
      +
    • HAL update
      • +
    • General + updates to fix known defects + and enhancements + implementation.
      • +
    • Added new + defines for ARM compiler V6:
      • +
        +
      • __weak
        • +
      • __packed
        • +
      • __NOINLINE
        • +
      +
    • Updated HAL TimeBase + TIM, RTC alarm and RTC WakeUp + templates for more robustness
      • +
        +
      • Updated Hal_Init_Tick() + API to propoerty + store the priority when + using the non-default time + base.
        • +
      +
    • Updated + PPP_MODULE_ENABLED for + FMPSMBUS.
      • +
    • HAL/LL ADC update
      • +
        +
      • Updated to + add include of the LL ADC + driver.
        • +
      • Updated the + following APIs to set status + HAL_ADC_STATE_ERROR_INTERNAL + and error code + HAL_ADC_ERROR_INTERNAL when + error occurs:
        • +
          +
        • HAL_ADC_Start()
          • +
        • HAL_ADC_Start_IT()
          • +
        • HAL_ADC_Start_DMA()
          • +
        • HAL_ADCEx_InjectedStart()
          • +
        • HAL_ADCEx_InjectedStart_IT()
          • +
        • HAL_ADCEx_MultiModeStart_DMA()
          • +
        +
      • Updated HAL_ADC_Stop_DMA() + API to check if DMA state is + Busy before calling HAL_DMA_Abort() + + + + + API to avoid DMA internal + error.
        • +
      • Updated + IS_ADC_CHANNEL to support + temperature sensor for:
        • +
          +
        • STM32F411xE
          • +
        • STM32F413xx
          • +
        • STM32F423xx
          • +
        +
      • Fixed wrong + defined values for:
        • +
          +
        • LL_ADC_MULTI_REG_DMA_LIMIT_3
          • +
        • LL_ADC_MULTI_REG_DMA_UNLMT_3
          • +
        +
      • Added + __LL_ADC_CALC_VREFANALOG_VOLTAGE() + macro to evaluate analog + reference voltage.
        • +
      • Removed + __LL_ADC_CALC_TEMPERATURE() + macro for STM32F4x9 devices + as the TS_CAL2 is not + available.
        • +
      +
    • HAL/LL DAC update
      • +
        +
      • Added restruction + on DAC Channel 2 defines and + parametres.
        • +
      • HAL_DAC_MSPINIT_CB_ID + + + + + and HAL_DAC_MSPDEINIT_CB_ID + used instead of + HAL_DAC_MSP_INIT_CB_ID and + HAL_DAC_MSP_DEINIT_CB_ID.
        • +
      • Updated to + support dual mode:
        • +
          +
        • Added two + new APIs:
          • +
            +
          • HAL_DACEx_DualStart()
            • +
          • HAL_DACEx_DualStop()
            • +
          +
        +
      • Added + position bit definition to + be used instead of + __DAC_MASK_SHIFT macro
        • +
          +
        • __DAC_MASK_SHIFT + + + + macro has been removed.
          • +
        +
      • Updated HAL_DAC_Start_DMA() + API to return HAL_ERROR when + error occurs.
        • +
      • Updated HAL_DAC_Stop_DMA() + API to not return HAL_ERROR + when DAC is already + disabled.
        • +
      +
    • HAL CEC update
      • +
        +
      • Updated HAL_CEC_IRQHandler() + API to avoid appending an + extra byte to the end of a + message.
        • +
      +
    • HAL/LL GPIO update
      • +
        +
      • Updated + IS_GPIO_AF() to + add missing values for + STM32F401xC and STM32F401xE + devices:
        • +
          +
        • GPIO_AF3_TIM9
          • +
        • GPIO_AF3_TIM10
          • +
        • GPIO_AF3_TIM11
          • +
        +
      • Updated + LL/HAL GPIO_TogglePin() + APIs to allow multi Pin�s + toggling.
        • +
      • Updated HAL_GPIO_Init() + API to avoid the + configuration of PUPDR + register when Analog mode is + selected.
        • +
      +
    • HAL/LL RCC update
      • +
        +
      • Updated HAL_RCC_OscConfig() + API to add missing checks + and to don�t return + HAL_ERROR if request repeats + the current PLL + configuration.
        • +
      • Updated + IS_RCC_PLLN_VALUE(VALUE) + macro in case of STM32F411xE + device in order to + be aligned with reference + manual.
        • +
      +
    • HAL SD update
      • +
        +
      • Update + function SD_FindSCR() + to resolve issue of FIFO + blocking when reading.
        • +
      • Update + read/write functions in DMA + mode in + + + + order to + force the DMA direction, + updated functions:
        • +
          +
        • HAL_SD_ReadBlocks_DMA()
          • +
        • HAL_SD_WriteBlocks_DMA()
          • +
        +
      • Add the + block size settings in the + initialization functions and + remove it from read/write + transactions to avoid + repeated and inefficient + reconfiguration, updated + functions:
        • +
          +
        • HAL_SD_InitCard()
          • +
        • HAL_SD_GetCardStatus()
          • +
        • HAL_SD_ConfigWideBusOperation() 
          • +
        • HAL_SD_ReadBlocks()
          • +
        • HAL_SD_WriteBlocks()
          • +
        • HAL_SD_ReadBlocks_IT()
          • +
        • HAL_SD_WriteBlocks_IT()
          • +
        • HAL_SD_ReadBlocks_DMA()
          • +
        • HAL_SD_WriteBlocks_DMA()
          • +
        +
      +
    • HAL MMC update
      • +
        +
      • Add the + block size settings in the + initialization function and + remove it from read/write + transactions to avoid + repeated and inefficient + reconfiguration, updated + functions:
        • +
          +
        • HAL_MMC_InitCard()
          • +
        • HAL_MMC_ReadBlocks()
          • +
        • HAL_MMC_WriteBlocks()
          • +
        • HAL_MMC_ReadBlocks_IT()
          • +
        • HAL_MMC_WriteBlocks_IT()
          • +
        • HAL_MMC_ReadBlocks_DMA()
          • +
        • HAL_MMC_WriteBlocks_DMA()
          • +
        +
      • Update + read/write functions in DMA + mode in + + + + order to + force the DMA direction, + updated functions:
        • +
          +
        • HAL_MMC_ReadBlocks_DMA()
          • +
        • HAL_MMC_WriteBlocks_DMA()
          • +
        +
      • Deploy new + functions MMC_ReadExtCSD() + and SDMMC_CmdSendEXTCSD + () that read and check the + sectors number of the + device in order to resolve + the issue of wrongly reading + big memory size.
        • +
      +
    • HAL NAND + update
      • +
        +
      • Update + functions + HAL_NAND_Read_SpareArea_16b() + and + HAL_NAND_Write_SpareArea_16b() + to fix column address + calculation issue.
        • +
      +
    • LL SDMMC + update
      • +
        +
      • Update the + definition of + SDMMC_DATATIMEOUT constant in + + + + order to + allow the user to redefine + it in his proper + application.
        • +
      • Remove + 'register' storage class + specifier from LL SDMMC + driver.
        • +
      • Deploy new + functions MMC_ReadExtCSD() + and SDMMC_CmdSendEXTCSD + () that read and check the + sectors number of the device + in order to resolve the + issue of wrongly reading big + memory size.
        • +
      +
    • HAL SMBUS update
      • +
        +
      • Support for + Fast Mode Plus to be SMBUS + rev 3 compliant.
        • +
      • Added HAL_FMPSMBUSEx_EnableFastModePlus() + and HAL_FMPSMBUSEx_DisableFastModePlus() + + + + + APIs to manage Fm+.
        • +
      • Updated SMBUS_MasterTransmit_BTF() + , SMBUS_MasterTransmit_TXE() + + + + + and SMBUS_MasterReceive_BTF() + + + + + APIs to allow stop + generation when CurrentXferOptions + is different from + SMBUS_FIRST_FRAME and + SMBUS_NEXT_FRAME.
        • +
      • Updated SMBUS_ITError() + API to correct the twice + call of HAL_SMBUS_ErrorCallback.
        • +
      +
    • HAL SPI update
      • +
        +
      • Updated HAL_SPI_Init() + API
        • +
          +
        • To avoid + setting the BaudRatePrescaler + in case of Slave Motorola + Mode.
          • +
        • Use the bit-mask + for SPI configuration.
          • +
        +
      • Updated + Transmit/Receive processes + in half-duplex mode
        • +
          +
        • Disable + the SPI instance before + setting BDIOE bit.
          • +
        +
      • Fixed wrong + timeout management
        • +
      • Calculate + Timeout based on a software + loop to avoid blocking issue + if Systick + is disabled.
        • +
      +
    • HAL + SPDIFRX update
      • +
        +
      • Remove + 'register' storage class + specifier from HAL SPDIFRX + driver.
        • +
      +
    • HAL I2S update
      • +
        +
      • Updated + I2SEx APIs to correctly + support circular transfers
        • +
          +
        • Updated + I2SEx_TxRxDMACplt() + API to manage DMA circular + mode.
          • +
        +
      • Updated + HAL_I2SEx_TransmitReceive_DMA() + API to set hdmatx + (transfert + callback and half) to NULL.
        • +
      +
    • HAL SAI update
      • +
        +
      • Updated to + avoid the incorrect + left/right synchronization.
        • +
          +
        • Updated HAL_SAI_Transmit_DMA() + API to follow the sequence + described in the reference + manual for slave + transmitter mode.
          • +
        +
      • Updated HAL_SAI_Init() + API to correct the formula + in case of SPDIF is wrong.
        • +
      +
    • HAL CRYP update
      • +
        +
      • Updated HAL_CRYP_SetConfig() + and HAL_CRYP_GetConfig() + + + + + APIs to set/get the + continent of KeyIVConfigSkip + correctly.
        • +
      +
    • HAL EXTI update
      • +
        +
      • __EXTI_LINE__ + + + + is now used instead of + __LINE__ which is a standard + C macro.
        • +
      +
    • HAL DCMI
      • +
        +
      • Support of + HAL callback registration + feature for DCMI extended + driver.
        • +
      +
    • HAL/LL TIM update
      • +
        +
      • Updated HAL_TIMEx_OnePulseN_Start() + and HAL_TIMEx_OnePulseN_Stop() + + + + + APIs (pooling and IT mode) + to take into consideration + all OutputChannel + parameters.
        • +
      • Corrected + reversed description of + TIM_LL_EC_ONEPULSEMODE One + Pulse Mode.
        • +
      • Updated LL_TIM_GetCounterMode() + API to return the correct + counter mode.
        • +
      +
    • HAL/LL + SMARTCARD update
      • +
        +
      • Fixed + invalid initialization of + SMARTCARD configuration by + removing FIFO mode + configuration as it is not + member of SMARTCARD_InitTypeDef + Structure.
        • +
      • Fixed typos + in SMARTCARD State + definition description
        • +
      +
    • HAL/LL IRDA update
      • +
        +
      • Fixed typos + in IRDA State definition + description
        • +
      +
    • LL USART update
      • +
        +
      • Remove + useless check on maximum BRR + value by removing + IS_LL_USART_BRR_MAX() + macro.
        • +
      • Update + USART polling and + interruption processes to + fix issues related to + accesses out of user + specified buffer.
        • +
      +
    • HAL USB update
      • +
        +
      • Enhanced + USB OTG host HAL with USB + DMA is enabled:
        • +
          +
        • fixed + ping and data toggle + issue,
          • +
        • reworked + Channel error report + management
          • +
        +
      +
    +
+

V1.7.10 + + + + / 22-October-2020

+

Main Changes

+
    +
  • General + + + + updates to fix known defects.
    • +
  • HAL/LL + + + + I2C update
    • +
+
    +
      +
    •   Update + to fix hardfault + issue with HAL_I2C_Mem_Write_DMA() + API:
      • +
        +
      •   + Abort the right ongoing DMA + transfer when memory write + access request operation + failed: fix typo �hdmarx� + replaced by �hdmatx�
        • +
      +
    +
+

V1.7.9 + + + + / 14-August-2020

+

Main Changes

+
    +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • HAL/LL + + + + I2C update
    • +
+
    +
      +
    •   Update + HAL_I2C_ER_IRQHandler() + API to fix acknowledge failure + issue with I2C memory IT + processes
      • +
        +
      •   Add + stop condition generation + when NACK occurs.
        • +
      +
    •   Update + I2C_DMAXferCplt(), + + + + + I2C_DMAError() and + I2C_DMAAbort() APIs to fix hardfault + issue when hdmatx + and hdmarx + parameters in i2c handle + aren't initialized (NULL + pointer).
      • +
        +
      •   Add + additional check on + hi2c->hdmtx + and hi2c->hdmarx + before resetting DMA Tx/Rx + complete callbacks
        • +
      +
    •   Update + Sequential transfer APIs to + adjust xfermode + condition.
      • +
        +
      •   + + + + + Replace hi2c->XferCount + < MAX_NBYTE_SIZE by + hi2c->XferCount + <= MAX_NBYTE_SIZE which + corresponds to a case + without reload
        • +
      +
    +
+
    +
  •  HAL/LL + + + + USB update
    • +
      +
    •   Bug + + + + fix: USB_ReadPMA() + and USB_WritePMA() + + + + + by ensuring 16-bits access to + USB PMA memory
      • +
    •   Bug + + + + fix: correct USB RX count + calculation
      • +
    •   Fix + USB Bulk transfer double + buffer mode
      • +
    •   Remove + register keyword from USB + defined macros as no more + supported by C++ compiler
      • +
    •   Minor + rework on USBD_Start() + and USBD_Stop() + + + + + APIs: stopping device will be + handled by HAL_PCD_DeInit() + + + + + API.
      • +
    •   Remove + non used API for USB device + mode.
      • +
    +
+

V1.7.8 + + + + / 12-February-2020

+

Main Changes

+
    +
  • Add + new HAL FMPSMBUS and LL + + + + FMPI2C drivers
    • +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
+
    +
  • Update + + + + HAL CRYP driver to support block + by block decryption without + reinitializes the IV and KEY for + each call.
    • +
  • Improve + + + + code quality by fixing + MisraC-2012 violations
    • +
  • HAL/LL + + + + USB update
    • +
      +
    •  Add + handling USB host babble error + interrupt
      • +
    •  Fix + Enabling ULPI interface for + platforms that integrates USB + HS PHY
      • +
    •  Fix + Host data toggling for IN Iso + transfers
      • +
    •  Ensure + to disable USB EP during + endpoint deactivation
      • +
    +
  • HAL + + + + CRYP update
    • +
      +
    •  Update + HAL CRYP driver to support + block by block decryption + without initializing the IV + and KEY at each call.
      • +
        +
      • Add new + CRYP Handler parameters: "KeyIVConfig" + and "SizesSum"
        • +
      • Add new + CRYP init + parameter: "KeyIVConfigSkip"
        • +
      +
    +
  • HAL + + + + I2S update
    • +
      +
    • Update + HAL_I2S_DMAStop() + API to be more safe
      • +
        +
      • Add a check + on BSY, TXE and RXNE flags + before disabling the I2S
        • +
      +
    • Update + HAL_I2S_DMAStop() + API to fix multi-call transfer + issue(to avoid re-initializing + the I2S for the next + transfer).
      • +
        +
      • Add + __HAL_I2SEXT_FLUSH_RX_DR() + and __HAL_I2S_FLUSH_RX_DR() + macros to flush the + remaining data inside DR + registers.
        • +
      • Add new ErrorCode + define: + HAL_I2S_ERROR_BUSY_LINE_RX
        • +
      +
    +
+

V1.7.7 + + + + / 06-December-2019

+

Main Changes

+
    +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • HAL + + + + Generic update
    • +
      +
    • HAL_SetTickFreq(): update to + restore the previous tick + frequency when HAL_InitTick() + + + + + configuration failed.
      • +
    +
  • HAL/LL + + + + GPIO update
    • +
      +
    • Update GPIO + initialization sequence to + + + + avoid unwanted pulse on GPIO Pin's
      • +
    +
  • HAL + + + + EXTI update
    • +
+
    +
      +
    • General + update to enhance HAL EXTI + driver robustness 
      • +
        +
      • Add + additional assert check on + EXTI config lines
        • +
      • Update to + compute EXTI line mask + before read/write access + to EXTI registers
        +
        +
        • +
      +
    • Update EXTI + callbacks management to be + compliant with reference + manual: only one PR + register for rising and + falling interrupts.
      • +
        +
      • Update + parameters in EXTI_HandleTypeDef + structure: merge HAL + EXTI RisingCallback + and FallingCallback + in only one PendingCallback
        • +
      • Remove + HAL_EXTI_RISING_CB_ID and + HAL_EXTI_FALLING_CB_ID + values from EXTI_CallbackIDTypeDef + enumeration.
        +
        +
        • +
      +
    • Update + HAL_EXTI_IRQHandler() + API to serve interrupts + correctly.
      • +
        +
      • Update to + compute EXTI line mask + before handle + EXTI interrupt.
        • +
      +
    • Update to + support GPIO port + interrupts:
      • +
        +
      • Add new "GPIOSel" + parameter in EXTI_ConfigTypeDef + structure
        • +
      +
    +
  • HAL/LL + + + + RCC update
    • +
      +
    • Update HAL_RCCEx_PeriphCLKConfig() + API to support PLLI2S + configuration for STM32F42xxx + and STM32F43xxx devices
      • +
    • Update the HAL_RCC_ClockConfig() + and HAL_RCC_DeInit() + + + + + API to don't overwrite the + custom tick priority
      • +
    • Fix LL_RCC_DeInit() + failure detected with gcc + compiler and high optimization + level is selected(-03)
      • +
    • Update HAL_RCC_OscConfig() + API to don't return + HAL_ERROR if request repeats + the current PLL configuration
      • +
    +
  • HAL + + + + ADC update
    • +
      +
    • Update LL_ADC_REG_Init() + to fix wrong ADC CR1 register + configuration
      • +
        +
      • The ADC + sequencer length is part + of ADC SQR1 + register not of ADC CR1 + register
        • +
      +
    +
  • HAL + + + + CRYP update
    • +
      +
    • Update HAL_CRYP_Encrypt() + and HAL_CRYP_Decrypt() + + + + + APIs to take into + consideration the datatype fed + to the DIN register (1-, 8-, + 16-, or 32-bit data) when + padding the last block of the + payload, in case the size of + this last block is less than + 128 bits.
      • +
    +
  • HAL + + + + RNG update
    • +
      +
    • Update HAL_RNG_IRQHandler() + API to fix error code + management issue: error code + is assigned + "HAL_RNG_ERROR_CLOCK" in case + of clock error and + "HAL_RNG_ERROR_SEED" in case + of seed error, not the + opposite.
      • +
    +
  • HAL + + + + DFSDM update
    • +
      +
    • Update DFSDM_GetChannelFromInstance() + API to remove unreachable + check condition
      • +
    +
  • HAL + + + + DMA update
    • +
      +
    • Update HAL_DMA_Start_IT() + API to omit the FIFO error
      • +
    +
  • HAL + + + + FLASH update
    • +
      +
    • Update FLASH_Program_DoubleWord() + API to fix with EWARM high + level optimization issue
      • +
    +
  • HAL + + + + QSPI update
    • +
      +
    • Remove Lock + mechanism from HAL_QSPI_Init() + and HAL_QSPI_DeInit() + + + + + APIs
      • +
    +
  • HAL + + + + HASH update
    • +
      +
    • Null pointer + on handler "hhash" + is now checked before + accessing structure member "hhash->Init.DataType" + in the following API:
      • +
        +
      • HAL_HASH_Init()
        • +
      +
    • Following interrupt-based + APIs have been added. + Interrupt mode could allow the + MCU to enter "Sleep" mode + while a data block is being + processed. Please refer to the + "##### How to use this driver + #####" section for details + about their use.
      • +
        +
      • HAL_HASH_SHA1_Accmlt_IT()
        • +
      • HAL_HASH_MD5_Accmlt_IT()
        • +
      • HAL_HASHEx_SHA224_Accmlt_IT()
        • +
      • HAL_HASHEx_SHA256_Accmlt_IT()
        • +
      +
    • Following aliases + have been added (just for + clarity sake) as they + shall be used at the end + of the computation of a + multi-buffers message and not + at the start:
      • +
        +
      • HAL_HASH_SHA1_Accmlt_End() + to be used instead of + HAL_HASH_SHA1_Start()
        • +
      • HAL_HASH_MD5_Accmlt_End() + to be used instead of + HAL_HASH_MD5_Start()
        • +
      • HAL_HASH_SHA1_Accmlt_End_IT() + to be used instead of + HAL_HASH_SHA1_Start_IT()
        • +
      • HAL_HASH_MD5_Accmlt_End_IT() + to be used instead of + HAL_HASH_MD5_Start_IT()
        • +
      • HAL_HASHEx_SHA224_Accmlt_End() + to be used instead of + HAL_HASHEx_SHA224_Start()
        • +
      • HAL_HASHEx_SHA256_Accmlt_End() + to be used instead of + HAL_HASHEx_SHA256_Start()
        • +
      +
    +
+
    +
      +
        +
      • HAL_HASHEx_SHA224_Accmlt_End_IT() + to be used instead of + HAL_HASHEx_SHA224_Start_IT()
        • +
      • HAL_HASHEx_SHA256_Accmlt_End_IT() + to be used instead of + HAL_HASHEx_SHA256_Start_IT()
        • +
      +
    +
+
    +
      +
    • MISRAC-2012 + rule R.5.1 (identifiers + shall be distinct in the first + 31 characters) constrained the + naming of the above listed + aliases (e.g. + HAL_HASHEx_SHA256_Accmlt_End() + could not be named + HAL_HASHEx_SHA256_Accumulate_End(). + + + + + Otherwise the name would have + conflicted with + HAL_HASHEx_SHA256_Accumulate_End_IT()). + In + + + + + order to + have aligned names following + APIs have been renamed:
      • +
    +
+
    +
      +
        +
          +
        • HAL_HASH_MD5_Accumulate() + renamed + HAL_HASH_MD5_Accmlt()
          • +
        • HAL_HASH_SHA1_Accumulate() + renamed + HAL_HASH_SHA1_Accmlt()
          • +
        • HAL_HASHEx_SHA224_Accumulate() + renamed + HAL_HASHEx_SHA224_Accmlt()
          • +
        +
      +
    +
+
    +
      +
        +
          +
        • HAL_HASHEx_SHA256_Accumulate() + renamed + HAL_HASHEx_SHA256_Accmlt()
          • +
        +
      +
    +
+
    +
      +
    • HASH handler + state is no more + reset to HAL_HASH_STATE_READY + once DMA has been started + in the following APIs:
      • +
        +
      • HAL_HASH_MD5_Start_DMA()
        • +
      • HAL_HMAC_MD5_Start_DMA()
        • +
      • HAL_HASH_SHA1_Start_DMA()
        • +
      • HAL_HMAC_SHA1_Start_DMA()
        • +
      +
    • HASH phase + state is now set to + HAL_HASH_PHASE_READY once + the digest has been read + in the following APIs:
      • +
        +
      • HASH_IT()
        • +
      • HMAC_Processing()
        • +
      • HASH_Start()
        • +
      • HASH_Finish()
        • +
      +
    • Case of a + large buffer scattered around + in memory each piece of which + is not necessarily a multiple + + + + of 4 bytes in length.
      • +
        +
      • In section + "##### How to use this + driver #####", sub-section + "*** Remarks on message + length ***" added to provide + recommendations to follow in + such case.
        • +
      • No + modification of the driver + as the root-cause is at + design-level.
        • +
      +
    +
+
    +
  • HAL CAN + + + + update
    • +
      +
    • HAL_CAN_GetRxMessage() update to + get the correct value for the + RTR (type of frame for + the message that will be + transmitted) field in the CAN_RxHeaderTypeDef + structure.
      • +
    +
  • HAL + + + + DCMI update
    • +
      +
    • Add new HAL_DCMI_ConfigSyncUnmask() + API to set embedded + synchronization delimiters + unmasks.
      • +
    +
  • HAL + + + + RTC update
    • +
      +
    • Following IRQ + handlers' implementation has + been aligned with the + STM32Cube firmware + specification (in case of + interrupt lines shared by + multiple events, first check + the IT enable bit is set then + check the IT flag is set too):
      • +
        +
      • HAL_RTC_AlarmIRQHandler()
        • +
      • HAL_RTCEx_WakeUpTimerIRQHandler()
        • +
      • HAL_RTCEx_TamperTimeStampIRQHandler()
        • +
      +
    +
+
    +
  • HAL + + + + WWDG update
    • +
      +
    • In "##### + WWDG Specific features #####" + descriptive comment section:
      • +
        +
      • Maximal prescaler + value has been corrected (8 + instead of 128).
        • +
      • Maximal APB + frequency has been corrected + (42MHz instead of 56MHz) and + possible timeout values + updated.
        • +
      +
    +
  • HAL + + + + DMA2D update
    • +
+
    +
      +
    • Add the + following API's to Start DMA2D + CLUT Loading.
      • +
        +
      • HAL_DMA2D_CLUTStartLoad() + Start DMA2D CLUT Loading.
        • +
      • HAL_DMA2D_CLUTStartLoad_IT() + Start DMA2D CLUT Loading + with interrupt enabled.
        • +
      +
    • The following + old wrong services will be + kept in the HAL DCMI driver + for legacy purpose and a + specific Note is added:
      • +
        +
      • HAL_DMA2D_CLUTLoad() + can be replaced with + HAL_DMA2D_CLUTStartLoad()
        • +
      • HAL_DMA2D_CLUTLoad_IT() can + + + + + be replaced with + HAL_DMA2D_CLUTStartLoad_IT()
        • +
      • HAL_DMA2D_ConfigCLUT() + can be omitted as the config + can be performed using + the HAL_DMA2D_CLUTStartLoad() + API.
        • +
      +
    +
+
    +
  • HAL + + + + SDMMC update
    • +
      +
    • Fix  + typo in "FileFormatGroup" + parameter in the HAL_MMC_CardCSDTypeDef + and HAL_SD_CardCSDTypeDef + structures 
      • +
    • Fix an + improve handle state and + error management
      • +
    • Rename the + defined MMC card capacity type + to be more meaningful:
      • +
        +
      • Update MMC_HIGH_VOLTAGE_CARD to + + + + + MMC LOW_CAPACITY_CARD
        • +
      • Update MMC_DUAL_VOLTAGE_CRAD + to MMC_HIGH_CAPACITY_CARD
        • +
      +
    • Fix + management of peripheral + flags depending on commands + or data transfers
      • +
        +
      • Add new + defines + "SDIO_STATIC_CMD_FLAGS" + and "SDIO_STATIC_DATA_FLAGS" 
        • +
      • Updates HAL + + + + SD and HAL MMC drivers to + manage the new SDIO static + flags.
        +
        +
        • +
      +
    • Due to + limitation SDIO hardware flow + control indicated in Errata + Sheet:
      • +
        +
      • In 4-bits + bus wide mode, do not use + the HAL_SD_WriteBlocks_IT() + or HAL_SD_WriteBlocks() + + + + + APIs otherwise underrun will + occur and it isn't possible + to activate the flow + control.
        • +
      • Use DMA + mode when using 4-bits bus + wide mode or decrease the + SDIO_CK frequency.
        • +
      +
    +
  • HAL + + + + UART update
    • +
      +
    • Update UART + polling processes to handle + efficiently the Lock mechanism
      • +
        +
      •  Move + the process unlock at the + top of the HAL_UART_Receive() + and HAL_UART_Transmit() + + + + + API.
        • +
      +
    • Fix baudrate + calculation error for clock + higher than 172Mhz
      • +
        +
      • Add a + forced cast on + UART_DIV_SAMPLING8() and + UART_DIV_SAMPLING16() + macros.
        • +
      • Remove + useless parenthesis from + UART_DIVFRAQ_SAMPLING8(), + UART_DIVFRAQ_SAMPLING16(), + UART_BRR_SAMPLING8() and + UART_BRR_SAMPLING16() macros + to solve some MISRA + warnings.
        • +
      +
    • Update UART + interruption handler to manage + correctly the overrun interrupt
      • +
        +
      • Add in + the HAL_UART_IRQHandler() + API a check on + USART_CR1_RXNEIE bit when an + overrun interrupt occurs.
        • +
      +
    • Fix baudrate + calculation error UART9 + and UART10
      • +
        +
      • In UART_SetConfig() + API fix UART9 and UART10 + clock source when computing + baudrate + values by adding a check on + these instances and setting + clock sourcePCLK2 instead of + PCLK1.
        • +
      +
    • Update UART_SetConfig() + API
      • +
        +
      • Split + HAL_RCC_GetPCLK1Freq() + and HAL_RCC_GetPCLK2Freq() + macros from the + UART_BRR_SAMPLING8() and + UART_BRR_SAMPLING8() + macros 
        • +
      +
    +
  • HAL + + + + USART update
    • +
      +
    • Fix baudrate + calculation error for clock + higher than 172Mhz
      • +
        +
      • Add a + forced cast on USART_DIV() + macro.
        • +
      • Remove + useless parenthesis + from USART_DIVFRAQ() + macro to solve some MISRA + warnings.
        • +
      +
    • Update USART + interruption handler to manage + correctly the overrun interrupt
      • +
        +
      • Add in + the HAL_USART_IRQHandler() + API a check on + USART_CR1_RXNEIE bit when an + overrun interrupt occurs.
        • +
      +
    • Fix baudrate + calculation error UART9 + and UART10
      • +
        +
      • In USART_SetConfig() + API fix UART9 and UART10 + clock source when computing + baudrate + values by adding a check on + these instances and setting + clock sourcePCLK2 instead of + PCLK1.
        • +
      +
    • Update USART_SetConfig() + API
      • +
        +
      • Split + HAL_RCC_GetPCLK1Freq() + and HAL_RCC_GetPCLK2Freq() + macros from the USART_BRR() + macro
        • +
      +
    +
  • HAL + + + + IRDA update
    • +
      +
    • Fix baudrate + calculation error for clock + higher than 172Mhz
      • +
        +
      • Add a + forced cast on IRDA_DIV() + macro.
        • +
      • Remove + useless parenthesis + from IRDA_DIVFRAQ() + macro to solve some + MISRA warnings.
        • +
      +
    • Update IRDA + interruption handler to manage + correctly the overrun interrupt
      • +
        +
      • Add in + the HAL_IRDA_IRQHandler() + API a check on + USART_CR1_RXNEIE bit when an + overrun interrupt occurs.
        • +
      +
    • Fix baudrate + calculation error UART9 + and UART10
      • +
        +
      • In IRDA_SetConfig() + API fix UART9 and UART10 + clock source when computing + baudrate + values by adding a check on + these instances and setting + clock sourcePCLK2 instead of + PCLK1.
        • +
      +
    • Update IRDA_SetConfig() + API
      • +
        +
      • Split + HAL_RCC_GetPCLK1Freq() + and HAL_RCC_GetPCLK2Freq() + macros from the IRDA_BRR() + macro
        • +
      +
    +
  • HAL + + + + SMARTCARD update
    • +
      +
    • Fix baudrate + calculation error for clock + higher than 172Mhz
      • +
        +
      • Add a + forced cast on SMARTCARD_DIV() + macro.
        • +
      • Remove useless parenthesis + + + + + from SMARTCARD_DIVFRAQ() + macro to solve some + MISRA warnings.
        • +
      +
    • Update + SMARTCARD interruption handler + to manage correctly the + overrun interrupti
      • +
        +
      • Add in + the HAL_SMARTCARD_IRQHandler() + API a check on + USART_CR1_RXNEIE bit when an + overrun interrupt occurs.
        • +
      +
    • Update SMARTCARD_SetConfig() + API
      • +
        +
      • Split + HAL_RCC_GetPCLK1Freq() + and HAL_RCC_GetPCLK2Freq() + macros from the + SMARTCARD_BRR() macro
        • +
      +
    +
  • HAL + + + + TIM update
    • +
      +
    • Add new + macros to enable and disable + the fast mode when using the + one pulse mode to output a + waveform with a minimum delay
      • +
        +
      • __HAL_TIM_ENABLE_OCxFAST() + and __HAL_TIM_DISABLE_OCxFAST().
        • +
      +
    • Update + Encoder interface mode to + keep TIM_CCER_CCxNP + bits low
      • +
        +
      • Add TIM_ENCODERINPUTPOLARITY_RISING + + + + + and + TIM_ENCODERINPUTPOLARITY_FALLING + definitions to determine + encoder input polarity.
        • +
      • Add + IS_TIM_ENCODERINPUT_POLARITY() + macro to check the + encoder input polarity.
        • +
      • Update HAL_TIM_Encoder_Init() + API 
        • +
          +
        • Replace + IS_TIM_IC_POLARITY() + macro by + IS_TIM_ENCODERINPUT_POLARITY() + macro.
          • +
        +
      +
    • Update TIM + remapping input configuration + in HAL_TIMEx_RemapConfig() + API
      • +
        +
      • Remove + redundant check on + LPTIM_OR_TIM5_ITR1_RMP bit + and replace it by check on + LPTIM_OR_TIM9_ITR1_RMP bit.
        • +
      +
    • Update HAL_TIMEx_MasterConfigSynchronization() + API to avoid functional errors + and assert fails when using + some TIM instances as input + trigger.
      • +
        +
      • Replace IS_TIM_SYNCHRO_INSTANCE() + macro by + IS_TIM_MASTER_INSTANCE() + macro. 
        • +
      • Add IS_TIM_SLAVE_INSTANCE() + macro to check on + TIM_SMCR_MSM bit.
        • +
      +
    • Add lacking + TIM input remapping definition 
      • +
        +
      • Add + LL_TIM_TIM11_TI1_RMP_SPDIFRX + and + LL_TIM_TIM2_ITR1_RMP_ETH_PTP.
        • +
      • Add lacking + definition for linked + LPTIM_TIM input trigger remapping  
        • +
          +
        • Add + following definitions + + + + + : + LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO, + LL_TIM_TIM9_ITR1_RMP_LPTIM, + + + + LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO, + + + + + LL_TIM_TIM5_ITR1_RMP_LPTIM, + + + + LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO + + + + and + LL_TIM_TIM1_ITR2_RMP_LPTIM.
          • +
        • Add a new + mechanism in LL_TIM_SetRemap() + API to remap TIM1, TIM9, + and TIM5 input + triggers mapped on LPTIM + register. 
          • +
        +
      +
    +
  • HAL + + + + LPTIM update
    • +
      +
    • Add a polling + mechanism to check + on LPTIM_FLAG_XXOK flags + in different API 
      • +
        +
      • Add  + LPTIM_WaitForFlag() API to + wait for flag set.
        • +
      • Perform new + checks on + HAL_LPTIM_STATE_TIMEOUT.
        • +
      +
    • Add lacking + definitions of LPTIM input + trigger remapping and its + related API
      • +
        +
          +
        • LL_LPTIM_INPUT1_SRC_PAD_AF, + + + + + LL_LPTIM_INPUT1_SRC_PAD_PA4, + + + + LL_LPTIM_INPUT1_SRC_PAD_PB9 + + + + and + LL_LPTIM_INPUT1_SRC_TIM_DAC.
          • +
        • Add a new + API LL_LPTIM_SetInput1Src() + to access to the LPTIM_OR + register and remap the + LPTIM input trigger.
          • +
        +
      +
    • Perform a new + check on indirect EXTI23 line + associated to the LPTIM wake + up timer
      • +
        +
      • Condition + the use of the LPTIM Wake-up + Timer associated EXTI + line configuration's + macros by EXTI_IMR_MR23 + bit in different API + + + + :
        • +
          +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE/DDISABLE_FALLING_EDGE()
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() 
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG()
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG()
          • +
        • __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() 
          • +
        +
      • Update HAL_LPTIM_TimeOut_Start_IT(), HAL_LPTIM_TimeOut_Stop_IT(), + + + + + HAL_LPTIM_Counter_Start_IT() + + + + + and HAL_LPTIM_Counter_Stop_IT() + + + + + API by adding Enable/Disable + rising edge trigger on + the LPTIM Wake-up Timer + Exti + line.
        • +
      • Add + __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() + in the end of the HAL_LPTIM_IRQHandler() + + + + + API conditioned by + EXTI_IMR_MR23 bit.
        • +
      +
    +
  • HAL + + + + I2C update
    • +
      +
    • Update + HAL_I2C_EV_IRQHandler() + API to fix I2C send break + issue 
      • +
        +
      • Add + additional check on + hi2c->hdmatx, + hdmatx->XferCpltCallback, + hi2c->hdmarx, + hdmarx->XferCpltCallback + in I2C_Master_SB() + API to avoid enabling + DMA request when IT + mode is used.
        • +
      +
    • Update + HAL_I2C_ER_IRQHandler() + API to fix acknowledge failure + issue with I2C memory IT + processes
      • +
        +
      •  Add stop + + + + + condition generation when + NACK occurs.
        • +
      +
    • Update + HAL_I2C_Init() + API to force software reset + before setting new I2C + configuration
      • +
    • Update HAL + I2C processes to report ErrorCode + when wrong I2C start condition + occurs
      • +
        +
      •  Add + new ErrorCode + define: HAL_I2C_WRONG_START
        • +
      •  Set ErrorCode + parameter in I2C handle + to HAL_I2C_WRONG_START
        • +
      +
    • Update I2C_DMAXferCplt(), + + + + + I2C_DMAError() and + I2C_DMAAbort() APIs to fix hardfault + issue when hdmatx + and hdmarx parameters + + + + + in i2c handle aren't + initialized (NULL pointer).
      • +
        +
      • Add + additional check on + hi2c->hdmtx + and hi2c->hdmarx + before resetting DMA + Tx/Rx complete callbacks
        • +
      +
    +
  • HAL + + + + FMPI2C update
    • +
      +
    • Fix HAL + FMPI2C slave interrupt + handling issue with I2C + sequential transfers.
      • +
        +
      • Update + FMPI2C_Slave_ISR_IT() + and FMPI2C_Slave_ISR_DMA() + APIs to check on STOP + condition and handle it + before clearing the ADDR + flag
        • +
      +
    +
  • HAL + + + + NAND update
    • +
      +
    • Update + HAL_NAND_Write_Page_8b(), + + + + HAL_NAND_Write_Page_16b() + and  + HAL_NAND_Write_SpareArea_16b() + to manage correctly the time + out condition.
      • +
    +
  • HAL + + + + SAI update
    • +
      +
    • Optimize SAI_DMATxCplt() + and SAI_DMARxCplt() + + + + + APIs to check on "Mode" + parameter instead of CIRC + bit in the CR register.
      • +
    • Remove unused + SAI_FIFO_SIZE define
      • +
    • Update HAL_SAI_Receive_DMA() + programming sequence to be inline + with reference manual
      • +
    +
+

V1.7.6 + + + + / 12-April-2019

+

Main Changes

+
    +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • HAL + + + + I2C update
    • +
      +
    • Fix I2C send + break issue in IT processes
      • +
        +
      • Add + additional check on + hi2c->hdmatx + and hi2c->hdmarx to + + + + + avoid the DMA request + enable when IT mode is used.
        • +
      +
    +
  • HAL + + + + SPI update
    • +
      +
    • Update to + implement Erratasheet: + BSY bit may stay high at the + end of a data transfer in + Slave mode
      • +
    +
  • LL + + + + LPTIM update
    • +
      +
    • Fix + compilation errors with LL_LPTIM_WriteReg() + and LL_LPTIM_ReadReg() + + + + + macros
      • +
    +
  • HAL + + + + SDMMC update
    • +
      +
    • Fix + preprocessing compilation + issue with SDIO + STA STBITERR interrupt
      • +
    +
  • HAL/LL + + + + USB update
    • +
      +
    • Updated USB_WritePacket(), + + + + + USB_ReadPacket() + + + + + APIs to prevent compilation + warning with GCC GNU v8.2.0
      • +
    • Rework USB_EPStartXfer() + API to enable the USB endpoint + before unmasking the TX FiFo + empty interrupt in case DMA is + not used
      • +
    • USB HAL_HCD_Init() + and HAL_PCD_Init() + + + + + APIs updated to avoid enabling + USB DMA feature for OTG FS + instance, USB DMA feature is + available only on OTG HS + Instance
      • +
    • Remove + duplicated line in hal_hcd.c + header file comment section +
      • +
    • Rework USB + HAL driver to use instance PCD_SPEED_xxx, + HCD_SPEED_xx + speeds instead of OTG register + Core speed definition during + the instance initialization
      • +
    • Software + Quality improvement with a fix + of CodeSonar + warning on PCD_Port_IRQHandler() + and  HCD_Port_IRQHandler() + + + + + interrupt handlers
      • +
    +
+

V1.7.5 + + + + / 08-February-2019

+

Main Changes

+
    +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • General + + + + updates to fix CodeSonar + compilation warnings
    • +
  • General + + + + updates to fix SW4STM32 + compilation errors under Linux
    • +
  • General + + + + updates to fix the user manual + .chm files
    • +
  • Add + support of HAL callback + registration feature
    • +
+
    +
  • Add + new HAL + + + + EXTI driver
    • +
  • Add + new HAL + + + + SMBUS driver
    • +
  • The + + + + following changes done on the + HAL drivers require an update + on the application code based + on older HAL versions
    • +
      +
    • Rework of HAL + CRYP driver (compatibility + break)
      • +
        +
      • HAL CRYP + driver has been redesigned + with new API's, to bypass + limitations on data + Encryption/Decryption + management present with + previous HAL CRYP driver + version.
        • +
      • The new HAL + CRYP driver is the + recommended version. It is + located as usual in + Drivers/STM32F4xx_HAL_Driver/Src + and + Drivers/STM32f4xx_HAL_Driver/Inc + folders. It can be enabled + through switch + HAL_CRYP_MODULE_ENABLED in + stm32f4xx_hal_conf.h
        • +
      • The legacy + HAL CRYP driver is no longer + supported.
        • +
      +
    • Add new AutoReloadPreload + field in TIM_Base_InitTypeDef + structure to allow the + possibilities to enable or + disable the TIM Auto Reload + Preload.
      • +
    +
+
    +
  • HAL/LL + + + + Generic update
    • +
      +
    • Add support + of HAL callback + registration feature
      • +
        +
      • The feature + disabled by default is + available for the following + HAL drivers:
        • +
          +
        • ADC, + CAN, CEC, CRYP, DAC, + DCMI, DFSDM, DMA2D, DSI, + ETH, HASH, HCD, I2C, + FMPI2C, SMBUS,
          + UART, USART, IRDA, + SMARTCARD, LPTIM, LTDC, + MMC, NAND, NOR, + PCCARD, PCD, QSPI, RNG,
          +           RTC, + SAI, SD, SDRAM, SRAM, + SPDIFRX, SPI, I2S, TIM, + and WWDG
          • +
        +
      • The feature + may be enabled individually + per HAL PPP driver + by setting the corresponding + definition USE_HAL_PPP_REGISTER_CALLBACKS + + + + + to 1U in + stm32f4xx_hal_conf.h project + configuration file (template + file + stm32f4xx_hal_conf_template.h + available from  + + + + Drivers/STM32F4xx_HAL_Driver/Inc)
        • +
      • Once enabled + + + + , the user + application may resort to HAL_PPP_RegisterCallback() + + + + + to register specific + callback function(s) and + unregister it(them) with HAL_PPP_UnRegisterCallback().
        • +
      +
    • General + updates to fix MISRA 2012 + compilation errors
      • +
        +
      • Replace HAL_GetUID() + API by HAL_GetUIDw0(), + HAL_GetUIDw1() and + HAL_GetUIDw2()
        • +
      • HAL_IS_BIT_SET()/HAL_IS_BIT_CLR() + macros implementation update
        • +
      • "stdio.h" + include updated with "stddef.h"
        • +
      +
    +
  • HAL + + + + GPIO  + + + + update
    • +
      +
    • Add missing + define for SPI3 alternate + function "GPIO_AF5_SPI3" for + STM32F401VE devices
      • +
    • Remove + "GPIO_AF9_TIM14" from defined + alternate function list for + STM32F401xx devices
      • +
    • HAL_GPIO_TogglePin() reentrancy + robustness improvement
      • +
    • HAL_GPIO_DeInit() API update + to avoid potential pending + interrupt after call
      • +
    • Update + GPIO_GET_INDEX() + API for more compliance with + STM32F412Vx/STM32F412Rx/STM32F412Cx + devices
      • +
    • Update + GPIO_BRR registers with + Reference Manual regarding + registers and bit definition + values
      • +
    +
  • HAL + + + + CRYP update
    • +
      +
    • The CRYP_InitTypeDef + is no more + supported, changed by CRYP_ConfigTypedef + to allow changing parameters + using HAL_CRYP_setConfig() + API without reinitialize the + CRYP IP using the HAL_CRYP_Init() + + + + + API
      • +
    • New + parameters added in the CRYP_ConfigTypeDef + structure: B0 and DataWidthUnit
      • +
    • Input data + size parameter is added in the + CRYP_HandleTypeDef + structure
      • +
    • Add new APIs + to manage the CRYP + configuration:
      • +
        +
      •  HAL_CRYP_SetConfig()
        • +
      • HAL_CRYP_GetConfig()
        • +
      +
    • Add new APIs + to manage the Key derivation:
      • +
        +
      • HAL_CRYPEx_EnableAutoKeyDerivation()
        • +
      • HAL_CRYPEx_DisableAutoKeyDerivation()
        • +
      +
    • Add new APIs + to encrypt and decrypt data:
      • +
        +
      • HAL_CRYP_Encypt()
        • +
      • HAL_CRYP_Decypt()
        • +
      • HAL_CRYP_Encypt_IT()
        • +
      • HAL_CRYP_Decypt_IT()
        • +
      • HAL_CRYP_Encypt_DMA()
        • +
      • HAL_CRYP_Decypt_DMA()
        • +
      +
    • Add new APIs + to generate TAG:
      • +
        +
      • HAL_CRYPEx_AESGCM_GenerateAuthTAG()
        • +
      • HAL_CRYPEx_AESCCM_Generago teAuthTAG()
        • +
      +
    +
  • HAL + + + + LPTIM update
    • +
      +
    • Remove + useless LPTIM Wakeup EXTI + related macros from HAL_LPTIM_TimeOut_Start_IT() + API
      • +
    +
  • HAL + + + + I2C update
    • +
      +
    • I2C API + changes for MISRA-C 2012 + compliancy:
      • +
        +
      • Rename + HAL_I2C_Master_Sequential_Transmit_IT() + to + HAL_I2C_Master_Seq_Transmit_IT()
        • +
      • Rename + HAL_I2C_Master_Sequentiel_Receive_IT() + to + HAL_I2C_Master_Seq_Receive_IT()
        • +
      • Rename + HAL_I2C_Slave_Sequentiel_Transmit_IT() + to + HAL_I2C_Slave_Seq_Transmit_IT() +
        • +
      • Rename + HAL_I2C_Slave_Sequentiel_Receive_DMA() + to + HAL_I2C_Slave_Seq_Receive_DMA()
        • +
      +
    • SMBUS defined + flags are removed as not used + by the HAL I2C driver
      • +
        +
      • I2C_FLAG_SMBALERT
        • +
      • I2C_FLAG_TIMEOUT
        • +
      • I2C_FLAG_PECERR
        • +
      • I2C_FLAG_SMBHOST
        • +
      • I2C_FLAG_SMBDEFAULT
        • +
      +
    • Add support + of I2C repeated start feature + in DMA Mode:
      • +
        +
      • With the + following new API's
        • +
          +
        • HAL_I2C_Master_Seq_Transmit_DMA()
          • +
        • HAL_I2C_Master_Seq_Receive_DMA()
          • +
        • HAL_I2C_Slave_Seq_Transmit_DMA()
          • +
        • HAL_I2C_Slave_Seq_Receive_DMA()
          • +
        +
      +
    • Add new I2C + transfer options to easy + manage the sequential transfers
      • +
        +
      • I2C_FIRST_AND_NEXT_FRAME
        • +
      • I2C_LAST_FRAME_NO_STOP
        • +
      • I2C_OTHER_FRAME
        • +
      • I2C_OTHER_AND_LAST_FRAME
        • +
      +
    +
  • HAL + + + + FMPI2C update
    • +
      +
    • I2C API + changes for MISRA-C 2012 + compliancy:
      • +
        +
      • Rename + HAL_FMPI2C_Master_Sequential_Transmit_IT() + to + HAL_FMPI2C_Master_Seq_Transmit_IT()
        • +
      • Rename + HAL_FMPI2C_Master_Sequentiel_Receive_IT() + to + HAL_FMPI2C_Master_Seq_Receive_IT()
        • +
      • Rename + HAL_FMPI2C_Master_Sequentiel_Transmit_DMA() + to + HAL_FMPI2C_Master_Seq_Transmit_DMA() +
        • +
      • Rename + HAL_FMPI2C_Master_Sequentiel_Receive_DMA() + to + HAL_FMPI2C_Master_Seq_Receive_DMA()
        • +
      +
    • Rename + FMPI2C_CR1_DFN to + FMPI2C_CR1_DNF for more + compliance with Reference + Manual regarding registers and + bit definition naming
      • +
    • Add support + of I2C repeated start feature + in DMA Mode:
      • +
        +
      • With the + following new API's
        • +
          +
        • HAL_FMPI2C_Master_Seq_Transmit_DMA()
          • +
        • HAL_FMPI2C_Master_Seq_Receive_DMA()
          • +
        • HAL_FMPI2C_Slave_Seq_Transmit_DMA()
          • +
        • HAL_FMPI2C_Slave_Seq_Receive_DMA()
          • +
        +
      +
    +
  • HAL + + + + FLASH update
    • +
      +
    • Update the FLASH_OB_GetRDP() + API to return the correct RDP + level
      • +
    +
  • HAL  + RCC + update
    • +
      +
    • Remove GPIOD + CLK macros for STM32F412Cx + devices (X = D)
      • +
    • Remove GPIOE + CLK macros for + STM32F412Rx\412Cx devices: (X + = E)
      • +
    • Remove + GPIOF/G CLK macros for + STM32F412Vx\412Rx\412Cx + devices (X= F or G)
      • +
        +
      • __HAL_RCC_GPIOX_CLK_ENABLE()
        • +
      • __HAL_RCC_GPIOX_CLK_DISABLE()
        • +
      • __HAL_RCC_GPIOX_IS_CLK_ENABLED()
        • +
      • __HAL_RCC_GPIOX_IS_CLK_DISABLED()
        • +
      • __HAL_RCC_GPIOX_FORCE_RESET()
        • +
      +
    +
  • HAL + + + + RNG update
    • +
      +
    • Update to + manage RNG error code:
      • +
        +
      • Add ErrorCode + parameter in HAL RNG Handler + structure
        • +
      +
    +
  • LL + + + + ADC update
    • +
      +
    • Add + __LL_ADC_CALC_TEMPERATURE() + helper macro to calculate the + temperature (unit: degree + Celsius) from ADC conversion + data of internal temperature + sensor.
      • +
    • Fix ADC + channels configuration issues + on STM32F413xx/423xx devices
      • +
        +
      • To allow + possibility to switch + between VBAT and TEMPERATURE + channels configurations
        • +
      +
    • HAL_ADC_Start(), HAL_ADC_Start_IT() + + + + + and HAL_ADC_Start_DMA() + + + + + update to prevention from + starting ADC2 or ADC3 once + multimode is enabled
      • +
    +
  • HAL + + + + DFSDM  + + + + update
    • +
      +
    • General + updates to be compliant with + DFSDM bits naming used in + CMSIS files.
      • +
    +
  • HAL + + + + CAN  + + + + update
    • +
      +
    • Update + possible values list for FilterActivation + parameter in CAN_FilterTypeDef + structure
      • +
        +
      • CAN_FILTER_ENABLE + + + + + instead of ENABLE
        • +
      • CAN_FILTER_DISABLE + + + + + instead of DISABLE
        • +
      +
    +
  • HAL + + + + CEC  + + + + update
    • +
      +
    • Update HAL + CEC State management method:
      • +
        +
      • Remove HAL_CEC_StateTypeDef + structure parameters
        • +
      • Add new + defines for CEC states
        • +
      +
    +
  • HAL + + + + DMA  + + + + update
    • +
      +
    • Add clean of + callbacks in HAL_DMA_DeInit() + API
      • +
    +
  • HAL + + + + DMA2D  + + + + update
    • +
      +
    • Remove unused + DMA2D_ColorTypeDef structure + to be compliant with MISRAC + 2012 Rule 2.3
      • +
    • General + update to use dedicated + defines for + DMA2D_BACKGROUND_LAYER and + DMA2D_FOREGROUND_LAYER instead + of numerical values: 0/1.
      • +
    +
  • HAL + + + + DSI  + + + + update
    • +
      +
    • Fix read + multibyte issue: remove extra + call to __HAL_UNLOCK__ from DSI_ShortWrite() + API.
      • +
    +
+
    +
  • HAL/LL + + + + RTC update
    • +
+
    +
      +
    • HAL/ LL drivers + optimization
      • +
        +
      • HAL driver: + remove unused variables
        • +
      • LL driver: + getter APIs optimization
        • +
      +
    +
  • HAL + + + + PWR update
    • +
      +
    • Remove the + followings API's as feature + not supported by + STM32F469xx/479xx devices
      • +
        +
      • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
        • +
      • HAL_PWREx_EnableWakeUpPinPolarityRisingEdge()
        • +
      +
    +
  • HAL + + + + SPI update
    • +
      +
    • Update HAL_SPI_StateTypeDef + structure to add new state: + HAL_SPI_STATE_ABORT
      • +
    +
  • HAL/LL + + + + TIM update
    • +
      +
    • Add new AutoReloadPreload + field in TIM_Base_InitTypeDef + structure
      • +
        +
      • Refer to + the TIM examples to identify + the changes +
        • +
      +
    • Move the + following TIM structures from + stm32f4xx_hal_tim_ex.h into + stm32f4xx_hal_tim.h
      • +
        +
      • TIM_MasterConfigTypeDef
        • +
      • TIM_BreakDeadTimeConfigTypeDef
        • +
      +
    • Add new TIM + Callbacks API's:
      • +
        +
      • HAL_TIM_PeriodElapsedHalfCpltCallback()
        • +
      • HAL_TIM_IC_CaptureHalfCpltCallback()
        • +
      • HAL_TIM_PWM_PulseFinishedHalfCpltCallback()
        • +
      • HAL_TIM_TriggerHalfCpltCallback()
        • +
      +
    • TIM API + changes for MISRA-C 2012 + compliancy:
      • +
        +
      • Rename HAL_TIM_SlaveConfigSynchronization + to HAL_TIM_SlaveConfigSynchro
        • +
      • Rename HAL_TIM_SlaveConfigSynchronization_IT + to HAL_TIM_SlaveConfigSynchro_IT
        • +
      • Rename HAL_TIMEx_ConfigCommutationEvent + to HAL_TIMEx_ConfigCommutEvent
        • +
      • Rename HAL_TIMEx_ConfigCommutationEvent_IT + to HAL_TIMEx_ConfigCommutEvent_IT
        • +
      • Rename HAL_TIMEx_ConfigCommutationEvent_DMA + to HAL_TIMEx_ConfigCommutEvent_DMA
        • +
      • Rename HAL_TIMEx_CommutationCallback + to HAL_TIMEx_CommutCallback
        • +
      • Rename HAL_TIMEx_DMACommutationCplt + to TIMEx_DMACommutationCplt
        • +
      +
    +
+
    +
  • HAL/LL + + + + USB update
    • +
      +
    • Rework USB + interrupt handler and improve + HS DMA support in Device mode
      • +
    • Fix BCD + handling fr OTG + instance in device mode
      • +
    • cleanup + reference to low speed in + device mode
      • +
    • allow writing + TX FIFO in case of transfer + length is equal to available + space in the TX FIFO
      • +
    • Fix Toggle + OUT interrupt channel in host + mode
      • +
    • Update USB + OTG max number of endpoints (6 + FS and 9 HS instead of 5 and + 8)
      • +
    • Update USB + OTG IP to enable internal + transceiver when starting USB + device after committee BCD negotiation
      • +
    +
  • LL + + + + IWDG update
    • +
      +
    • Update LL + inline macros to use IWDGx + parameter instead of IWDG + instance defined in CMSIS device
      • +
    +
+

V1.7.4 + + + + / 02-February-2018

+

Main Changes

+
    +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • HAL update
    • +
      +
    • Update UNUSED() + macro implementation to avoid + GCC warning
      • +
        +
      • The warning + is detected when the UNUSED() + macro is called from C++ + file
        • +
      +
    • Update to + make RAMFUNC define as generic + type instead of HAL_StatusTypdef + type.
      • +
    +
  • HAL + + + + FLASH update
    • +
      +
    • Update + the prototypes of the + following APIs after change on + RAMFUNC defines 
      • +
        +
      • HAL_FLASHEx_StopFlashInterfaceClk()
        • +
      • HAL_FLASHEx_StartFlashInterfaceClk()
        • +
      • HAL_FLASHEx_EnableFlashSleepMode()
        • +
      • HAL_FLASHEx_DisableFlashSleepMode()
        • +
      +
    +
  • HAL + + + + SAI update
    • +
      +
    • Update HAL_SAI_DMAStop() + and HAL_SAI_Abort() + + + + + process to fix the lock/unlock + audio issue
      • +
    +
+

V1.7.3 + + + + / 22-December-2017

+

Main Changes

+
    +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • The + + + + following changes done on the + HAL drivers require an update + on the application code based + on older HAL versions
    • +
      +
    • Rework of + HAL CAN driver + (compatibility break) 
      • +
        +
      • A new HAL + CAN driver has been + redesigned with new APIs, to + bypass limitations on CAN + Tx/Rx FIFO management + present with previous HAL + CAN driver version.
        • +
      • The new HAL + CAN driver is the + recommended version. It is + located as usual in + Drivers/STM32F4xx_HAL_Driver/Src + and + Drivers/STM32f4xx_HAL_Driver/Inc + folders. It can be enabled + through switch + HAL_CAN_MODULE_ENABLED in + stm32f4xx_hal_conf.h
        • +
      • The legacy + HAL CAN driver is also + present in the release in + Drivers/STM32F4xx_HAL_Driver/Src/Legacy + + + + and + Drivers/STM32F4xx_HAL_Driver/Inc/Legacy + folders for software + compatibility reasons. Its + usage is not recommended as + deprecated. It can + however be enabled through + switch + HAL_CAN_LEGACY_MODULE_ENABLED + in stm32f4xx_hal_conf.h
        • +
      +
    +
  • HAL update
    • +
      +
    • Update HAL + driver to allow user to change + systick + period to 1ms, 10 ms + or 100 ms :
      • +
        +
      • Add the + following API's + + + + :  
        • +
          +
        • HAL_GetTickPrio(): + Returns a tick priority.
          • +
        • HAL_SetTickFreq(): Sets + new tick frequency.
          • +
        • HAL_GetTickFreq(): + Returns tick frequency.
          • +
        +
      • Add HAL_TickFreqTypeDef + enumeration for the + different Tick Frequencies: + 10 Hz, 100 Hz and 1KHz + (default).
        • +
      +
    +
  • HAL + + + + CAN update
    • +
      +
    • Fields of CAN_InitTypeDef + structure are reworked:
      • +
        +
      • SJW to SyncJumpWidth, + BS1 to TimeSeg1, BS2 to + TimeSeg2, TTCM to TimeTriggeredMode, + ABOM to AutoBusOff, + AWUM to AutoWakeUp, + NART to AutoRetransmission + (inversed), RFLM to ReceiveFifoLocked + and TXFP to TransmitFifoPriority
        • +
      +
    • HAL_CAN_Init() is split + into both HAL_CAN_Init() + + + + + and HAL_CAN_Start() + + + + + API's
      • +
    • HAL_CAN_Transmit() is replaced + by HAL_CAN_AddTxMessage() + + + + + to place Tx Request, then HAL_CAN_GetTxMailboxesFreeLevel() + + + + + for polling until completion.
      • +
    • HAL_CAN_Transmit_IT() is replaced + by HAL_CAN_ActivateNotification() + + + + + to enable transmit IT, then HAL_CAN_AddTxMessage() + + + + + for place Tx request.
      • +
    • HAL_CAN_Receive() is replaced + by HAL_CAN_GetRxFifoFillLevel() + + + + + for polling until reception, + then HAL_CAN_GetRxMessage() + + + + +
      + to get Rx message.
      • +
    • HAL_CAN_Receive_IT() is replaced + by HAL_CAN_ActivateNotification() to + + + + + enable receive IT, then HAL_CAN_GetRxMessage()
      + in the receivecallback + to get Rx message
      • +
    • HAL_CAN_Slepp() is renamed + as HAL_CAN_RequestSleep()
      • +
    • HAL_CAN_TxCpltCallback() is split + into + HAL_CAN_TxMailbox0CompleteCallback(), +HAL_CAN_TxMailbox1CompleteCallback() +and HAL_CAN_TxMailbox2CompleteCallback().
      • +
    • HAL_CAN_RxCpltCallback is split + into HAL_CAN_RxFifo0MsgPendingCallback() + and + HAL_CAN_RxFifo1MsgPendingCallback().
      • +
    • More complete + "How to use the new driver" is + detailed in the driver header + section itself.
      • +
    +
  • HAL + + + + FMPI2C update
    • +
      +
    • Add new + option + FMPI2C_LAST_FRAME_NO_STOP for + the sequential transfer management
      • +
        +
      • This option + allows to manage a restart + condition after several call + of the same master + sequential interface. 
        • +
      +
    +
  • HAL + + + + RCC update
    • +
      +
    • Add new HAL macros
      • +
        +
      • __HAL_RCC_GET_RTC_SOURCE() + allowing to get the RTC + clock source
        • +
      • __HAL_RCC_GET_RTC_HSE_PRESCALER() + allowing to get the HSE + clock divider for RTC + peripheral
        • +
      +
    • Ensure reset + of CIR and CSR registers when + issuing HAL_RCC_DeInit()/LL_RCC_DeInit + functions
      • +
    • Update HAL_RCC_OscConfig() to + + + + + keep backup domain enabled + when configuring + respectively LSE and RTC + clock source
      • +
    • Add new HAL + interfaces allowing to control + the activation or deactivation + of PLLI2S and PLLSAI:
      • +
        +
      • HAL_RCCEx_EnablePLLI2S()
        • +
      • HAL_RCCEx_DisablePLLI2S()
        • +
      • HAL_RCCEx_EnablePLLSAI()
        • +
      • HAL_RCCEx_DisablePLLSAI()
        • +
      +
    +
+
    +
  • LL + + + + RCC update 
    • +
      +
    • Add new LL + RCC macro
      • +
        +
      • LL_RCC_PLL_SetMainSource() allowing + to configure PLL main clock + source
        • +
      +
    +
  • LL + + + + FMC / LL FSMC update
    • +
      +
    • Add clear of + the PTYP bit to select the + PCARD mode in FMC_PCCARD_Init() + / FSMC_PCCARD_Init()
      • +
    +
+

V1.7.2 + + + + / 06-October-2017

+

Main Changes

+
    +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • Fix + compilation warning with + GCC compiler
    • +
  • Remove + + + + Date and version + from header files
    • +
  • Update + + + + HAL drivers to refer to the + new CMSIS bit position + defines instead of usage the + POSITION_VAL() + macro
    • +
  • HAL + + + + Generic update
    • +
      +
    • stm32f4xx_hal_def.h + + + + file changes: 
      • +
        +
      • Update + __weak and __packed defined + values for ARM compiler
        • +
      • Update + __ALIGN_BEGIN and + __ALIGN_END defined values + for ARM compiler
        • +
      +
    • stm32f4xx_ll_system.h + + + + + file: + add LL_SYSCFG_REMAP_SDRAM + define
      • +
    +
  • HAL + + + + ADC update
    • +
      +
    • Fix wrong + definition of ADC channel + temperature sensor for + STM32F413xx and STM32F423xx + devices.
      • +
    +
  • HAL + + + + DMA update
    • +
      +
    • Update values + + + + for the following defines: + DMA_FLAG_FEIF0_4 and + DMA_FLAG_DMEIF0_4 
      • +
    +
  • HAL + + + + DSI update
    • +
      +
    • Fix Extra + warning with SW4STM32 compiler
      • +
    • Fix DSI + display issue when using EWARM + w/ high level optimization 
      • +
    • Fix + MISRAC errors
      • +
    +
  • HAL + + + + FLASH update
    • +
      +
    • HAL_FLASH_Unlock() update to + return state error when the + FLASH is already unlocked
      • +
    +
  • HAL + + + + FMPI2C update
    • +
      +
    • Update + Interface APIs headers to + remove confusing message about + device address
      • +
    • Update + FMPI2C_WaitOnRXNEFlagUntilTimeout() + to resolve a race condition + between STOPF and RXNE Flags
      • +
    • Update + FMPI2C_TransferConfig() + to fix wrong bit management.
      • +
    • Update code + comments to use DMA stream + instead of DMA channel
      • +
    +
+
    +
  • HAL + + + + PWR update
    • +
      +
    • HAL_PWR_EnableWakeUpPin() update + description to add support of + PWR_WAKEUP_PIN2 and + PWR_WAKEUP_PIN3
      • +
    +
  • HAL + + + + NOR update
    • +
      +
    • Add the + support of STM32F412Rx devices
      • +
    +
  • HAL + + + + I2C update
    • +
      +
    • Update + Interface APIs headers to + remove confusing mesage + about device address
      • +
    • Update + I2C_MasterReceive_RXNE() + and I2C_MasterReceive_BTF() + static APIs to fix bad + Handling of NACK in I2C master + receive process.
      • +
    +
+
    +
  • HAL + + + + RCC update
    • +
      +
    • Update HAL_RCC_GetOscConfig() + API to:
      • +
        +
      • set PLLR in + the RCC_OscInitStruct
        • +
      • check on + null pointer
        • +
      +
    • Update HAL_RCC_ClockConfig() + API to:
      • +
        +
      • check on + null pointer
        • +
      • optimize code + + + + size by updating the + handling method of the SWS bits
        • +
      • update to use  + + + + + __HAL_FLASH_GET_LATENCY() + + + + flash macro instead of using + direct register access + to LATENCY bits in + FLASH ACR register.
        • +
      +
    • Update HAL_RCC_DeInit() +  and LL_RCC_DeInit() + + + + + APIs to
      • +
        +
      • Be able to + return HAL/LL status
        • +
      • Add checks + for HSI, PLL and PLLI2S +  ready + before modifying RCC CFGR + registers
        • +
      • Clear all + interrupt falgs
        • +
      • Initialize + systick + interrupt period
        • +
      +
    • Update HAL_RCC_GetSysClockFreq() + to avoid risk of rounding + error which may leads to a + wrong returned value. 
      • +
    +
+

 

+

 

+
    +
  • HAL + + + + RNG update
    • +
      +
    • HAL_RNG_Init() remove + Lock()/Unlock()
      • +
    +
  • HAL + + + + MMC update
    • +
      +
    • HAL_MMC_Erase() + API: add missing () to + fix compilation warning + detected with SW4STM32 when + extra feature is enabled.
      • +
    +
  • HAL + + + + RTC update
    • +
      +
    • HAL_RTC_Init() API: update + to force the wait for synchro + before setting TAFCR register + when BYPSHAD bit in CR + register is 0.
      • +
    +
  • HAL + + + + SAI update
    • +
      +
    • Update HAL_SAI_DMAStop() + API to flush fifo + after disabling SAI
      • +
    +
  • HAL + + + + I2S update
    • +
      +
    • Update I2S + DMA fullduplex process to + handle I2S Rx and Tx DMA Half + transfer complete callback
      • +
    +
  • HAL + + + + TIM update
    • +
      +
    • Update HAL_TIMEx_OCN_xxxx() + and HAL_TIMEx_PWMN_xxx() + + + + + API description to remove + support of TIM_CHANNEL_4
      • +
    +
  • LL + + + + DMA update
    • +
      +
    • Update to + clear DMA flags using WRITE_REG() + instead SET_REG() API to avoid + read access to the IFCR + register that is write only.
      • +
    +
  • LL + + + + RTC update
    • +
      +
    • Fix warning + with static analyzer
      • +
    +
  • LL + + + + USART update
    • +
      +
    • Add assert + macros to check USART BaudRate + register
      • +
    +
  • LL + + + + I2C update
    • +
      +
    • Rename + IS_I2C_CLOCK_SPEED() + and IS_I2C_DUTY_CYCLE() + respectively to + IS_LL_I2C_CLOCK_SPEED() and + IS_LL_I2C_DUTY_CYCLE() to + avoid incompatible macros + redefinition.
      • +
    +
  • LL + + + + TIM update
    • +
      +
    • Update LL_TIM_EnableUpdateEvent() + API to clear UDIS bit in TIM + CR1 register instead of + setting it.
      • +
    • Update LL_TIM_DisableUpdateEvent() + API to set UDIS bit in TIM CR1 + register instead of clearing + it.
      • +
    +
  • LL + + + + USART update
    • +
      +
    • Fix MISRA + error w/ IS_LL_USART_BRR() + macro
      • +
    • Fix wrong + check when UART10 instance is + used
      • +
    +
+

V1.7.1 + + + + / 14-April-2017

+

Main Changes

+
    +
  • Update + + + + CHM UserManuals + to support LL drivers
    • +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • HAL + + + + CAN update
    • +
      +
    • Add + management of overrun + error. 
      • +
    • Allow + possibility to receive + messages from the 2 RX FIFOs + in parallel via interrupt.
      • +
    • Fix message + + + + lost issue with specific + sequence of transmit requests.
      • +
    • Handle + transmission failure with + error callback, when NART is + enabled.
      • +
    • Add + __HAL_CAN_CANCEL_TRANSMIT() + call to abort transmission + when timeout is reached
      • +
    +
+
    +
  • HAL + + + + PWR update
    • +
      +
    • HAL_PWREx_EnterUnderDriveSTOPMode() API: remove + check on UDRDY flag
      • +
    +
+
    +
  • LL + + + + ADC update
    • +
      +
    • Fix wrong ADC + group injected sequence configuration
      • +
        +
      • LL_ADC_INJ_SetSequencerRanks() and LL_ADC_INJ_GetSequencerRanks() + + + + + API's update to take in + consideration the ADC number + of conversions
        • +
      • Update + the defined values for + ADC group injected seqencer + ranks 
        • +
      +
    +
+

V1.7.0 + + + + / 17-February-2017

+

Main Changes

+
    +
  • Add + + + + Low Layer drivers allowing + performance and footprint optimization
    • +
      +
    • Low Layer drivers + APIs provide register level + programming: require deep + knowledge of peripherals + described in STM32F4xx + Reference Manuals
      • +
    • Low Layer + drivers are available for: + ADC, Cortex, CRC, DAC, + DMA, DMA2D, EXTI, GPIO, I2C, + IWDG, LPTIM, PWR, RCC, RNG, + RTC, SPI, TIM, USART, WWDG + peripherals and additionnal + Low Level Bus, System and + Utilities APIs.
      • +
    • Low Layer drivers + APIs are implemented as static + inline function in new Inc/stm32f4xx_ll_ppp.h files + + + + + for PPP peripherals, there is + no configuration file and each stm32f4xx_ll_ppp.h file + + + + + must be included in user code.
      • +
    +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • Fix extra + + + + warnings with GCC compiler
    • +
  • HAL + drivers clean up: remove + double casting 'uint32_t' and 'U'
    • +
  • Add + new HAL + + + + MMC driver
    • +
  • The + + + + following changes done on the + HAL drivers require an update + on the application code based + on older HAL versions
    • +
      +
    • HAL SD update
      • +
        +
      • Overall + rework of the driver for a + more + efficient implementation
        • +
          +
        • Modify + initialization API and structures
          • +
        • Modify + Read / Write sequences: + separate transfer process + and SD Cards state management 
          • +
        • Adding + interrupt mode for Read / + Write operations
          • +
        • Update + the HAL_SD_IRQHandler + function by optimizing the + management of interrupt errors
          • +
        +
      • Refer to + the following example to + identify the changes: BSP + example and USB_Device/MSC_Standalone + application
        • +
      +
    • HAL NAND update
      • +
        +
      • Modify NAND_AddressTypeDef, + NAND_DeviceConfigTypeDef + and NAND_HandleTypeDef + structures fields
        • +
      • Add new HAL_NAND_ConfigDevice + API
        • +
      +
    • HAL DFSDM update
      • +
        +
      • Add + support of Multichannel + Delay feature
        • +
          +
        • Add HAL_DFSDM_ConfigMultiChannelDelay + API
          • +
        • The + following APIs are moved + to internal static + functions: HAL_DFSDM_ClockIn_SourceSelection, + HAL_DFSDM_ClockOut_SourceSelection, + HAL_DFSDM_DataInX_SourceSelection + (X=0,2,4,6), HAL_DFSDM_BitStreamClkDistribution_Config
          • +
        +
      +
    • HAL I2S update
      • +
        +
      • Add specific + + + + + callback API to manage I2S + full duplex end of transfer + process:
        • +
          +
        • HAL_I2S_TxCpltCallback() + and + HAL_I2S_RxCpltCallback() + API's will be replaced + with only + HAL_I2SEx_TxRxCpltCallback() + API. 
          • +
        +
      +
    +
  • HAL + + + + update
    • +
      +
    • Modifiy default HAL_Delay + implementation to guarantee + minimum delay 
      • +
    +
  • HAL + + + + Cortex update
    • +
      +
    • Move HAL_MPU_Disable() + and HAL_MPU_Enable() + + + + + from stm32f4xx_hal_cortex.h to + stm32f4xx_hal_cortex.c
      • +
    • Clear the + whole MPU control register + in HAL_MPU_Disable() + API
      • +
    +
  • HAL + + + + FLASH update
    • +
      +
    • IS_FLASH_ADDRESS() + macro update to support OTP + range
      • +
    • FLASH_Program_DoubleWord(): Replace + 64-bit accesses with 2 + double-words operations
      • +
    +
  • LL + + + + GPIO update
    • +
      +
    • Update + IS_GPIO_PIN() + macro implementation to be + more safe
      • +
    +
  • LL + + + + RCC update
    • +
      +
    • Update + IS_RCC_PLLQ_VALUE() + macro implementation: the + minimum accepted value is + 2 instead of 4
      • +
    • Rename + RCC_LPTIM1CLKSOURCE_PCLK + define to + RCC_LPTIM1CLKSOURCE_PCLK1
      • +
    • Fix + compilation issue w/ + __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() + and + __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() + macros for STM32F401xx devices
      • +
    • Add the + following is clock + enabled macros for STM32F401xx + devices
      • +
        +
      •  __HAL_RCC_SDIO_IS_CLK_ENABLED()
        • +
      • __HAL_RCC_SPI4_IS_CLK_ENABLED()
        • +
      • __HAL_RCC_TIM10_IS_CLK_ENABLED()
        • +
      +
    • Add the + following is clock + enabled macros for STM32F410xx + devices
      • +
        +
      •  __HAL_RCC_CRC_IS_CLK_ENABLED()
        • +
      • __HAL_RCC_RNG_IS_CLK_ENABLED()
        • +
      +
    • Update HAL_RCC_DeInit() + to reset the RCC clock + configuration to the default + reset state.
      • +
    • Remove macros + to configure BKPSRAM from + STM32F401xx devices 
      • +
    • Update to + refer to AHBPrescTable[] + and APBPrescTable[] + + + + + tables defined in + system_stm32f4xx.c file + instead of APBAHBPrescTable[] + + + + + table.
      • +
    +
  • HAL + + + + FMPI2C update
    • +
      +
    • Add + FMPI2C_FIRST_AND_NEXT_FRAME + define in Sequential + Transfer Options
      • +
    +
  • HAL + + + + ADC update
    • +
      +
    • HAL_ADCEx_InjectedConfigChannel(): update the + external trigger injected + condition
      • +
    +
  • HAL + + + + DMA update
    • +
      +
    • HAL_DMA_Init(): update to + check compatibility between + FIFO threshold level and size + of the memory burst 
      • +
    +
  • HAL + + + + QSPI update
    • +
      +
    • QSPI_HandleTypeDef structure: + Update transfer parameters on + uint32_t instead of uint16_t
      • +
    +
  • HAL + + + + UART/USART/IrDA/SMARTCARD update
    • +
      +
    • DMA Receive + process; the code has been + updated to clear the USART + OVR flag before + enabling DMA receive + request.
      • +
    • UART_SetConfig() update to + manage correctly USART6 + instance that is not available + on STM32F410Tx devices
      • +
    +
  • HAL + + + + CAN update
    • +
      +
    • Remove Lock + mechanism from HAL_CAN_Transmit_IT() + and HAL_CAN_Receive_IT() + + + + + processes
      • +
    +
  • HAL + + + + TIM update
    • +
      +
    • Add + __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() + macro to disable Master output + without check on TIM channel + state. 
      • +
    • Update HAL_TIMEx_ConfigBreakDeadTime() + to fix TIM BDTR register + corruption.
      • +
    +
  • HAL + + + + I2C update
    • +
      +
    • Update + HAL_I2C_Master_Transmit() + and HAL_I2C_Slave_Transmit() + to avoid sending extra + bytes at the end of the + transmit processes
      • +
    • Update + HAL_I2C_Mem_Read() + API to fix wrong check on + misused parameter �Size�
      • +
    • Update + I2C_MasterReceive_RXNE() + and I2C_MasterReceive_BTF() + static APIs to enhance Master + sequential reception process.
      • +
    +
  • HAL + + + + SPI update
    • +
      +
    • Add transfer + abort APIs and associated + callbacks in interrupt mode
      • +
        +
      • HAL_SPI_Abort()
        • +
      • HAL_SPI_Abort_IT()
        • +
      • HAL_SPI_AbortCpltCallback()
        • +
      +
    +
  • HAL + + + + I2S update
    • +
      +
    • Add specific + + + + + callback API to manage I2S + full duplex end of transfer + process:
      • +
        +
      • HAL_I2S_TxCpltCallback() + and HAL_I2S_RxCpltCallback() + API's will be replaced with + only + HAL_I2SEx_TxRxCpltCallback() + API. 
        • +
      +
    • Update I2S + Transmit/Receive polling + process to manage Overrun + and Underrun errors
      • +
    • Move + the I2S clock input + frequency calculation to + HAL RCC driver.
      • +
    • Update the + HAL I2SEx driver to keep only + full duplex feature.
      • +
    • HAL_I2S_Init() + API updated to
      • +
        +
      • Fix wrong + I2S clock calculation when + PCM mode is used.
        • +
      • Return + state HAL_I2S_ERROR_PRESCALER when + the I2S clock is wrongly configured
        • +
      +
    +
+
    +
  • HAL + + + + LTDC update
    • +
      +
    • Optimize HAL_LTDC_IRQHandler() + function by using direct + register read
      • +
    • Rename the + following API's
      • +
        +
      • HAL_LTDC_Relaod() by HAL_LTDC_Reload() 
        • +
      • HAL_LTDC_StructInitFromVideoConfig() by HAL_LTDCEx_StructInitFromVideoConfig()
        • +
      • HAL_LTDC_StructInitFromAdaptedCommandConfig() by HAL_LTDCEx_StructInitFromAdaptedCommandConfig()
        • +
      +
    • Add new + defines for LTDC layers + (LTDC_LAYER_1 / LTDC_LAYER_2)
      • +
    • Remove unused + asserts
      • +
    +
  • HAL + + + + USB PCD + update
    • +
      +
    • Flush all TX + FIFOs on USB Reset
      • +
    • Remove Lock + mechanism from HAL_PCD_EP_Transmit() + and HAL_PCD_EP_Receive() + + + + + API's
      • +
    +
+
    +
  • LL + + + + USB update
    • +
      +
    • Enable DMA + Burst mode for USB OTG HS
      • +
    • Fix SD card + detection issue
      • +
    +
  • LL + + + + SDMMC update
    • +
      +
    • Add new SDMMC_CmdSDEraseStartAdd, + SDMMC_CmdSDEraseEndAdd, + SDMMC_CmdOpCondition + and SDMMC_CmdSwitch + functions
      • +
    +
+

V1.6.0 + + + + / 04-November-2016

+

Main Changes

+
    +
  • Add support of STM32F413xx + and STM32F423xx + devices
    • +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • HAL + + + + CAN update
    • +
      +
    • Update to add + the support of 3 CAN management
      • +
    +
  • HAL + + + + CRYP update
    • +
      +
    • Update to add + the support of AES features
      • +
    +
  • HAL + + + + DFSDM update
    • +
      +
    • Add + definitions for new external + trigger filters
      • +
    • Add + definition for new Channels + 4, 5, 6 and 7
      • +
    • Add + functions and API for Filter + state configuration and management
      • +
    • Add new + functions: 
      • +
        +
      • HAL_DFSDM_BitstreamClock_Start()
        • +
      • HAL_DFSDM_BitstreamClock_Stop()
        • +
      • HAL_DFSDM_BitStreamClkDistribution_Config() 
        • +
      +
    +
  • HAL + + + + DMA
    • +
      +
    • Add the + support of DMA Channels from + 8 to 15
      • +
    • Update HAL_DMA_DeInit() + function with the check on + DMA stream instance
      • +
    +
  • HAL + + + + DSI update
    • +
+
    +
      +
    • Update HAL_DSI_ConfigHostTimeouts() + and HAL_DSI_Init() + + + + + functions to avoid scratch in + DSI_CCR register
      • +
    +
  • HAL + + + + FLASH update
    • +
      +
    • Enhance FLASH_WaitForLastOperation() + function implementation
      • +
    • Update + __HAL_FLASH_GET_FLAG() + macro implementation
      • +
    +
  • HAL + + + + GPIO update
    • +
      +
    • Add + specific alternate functions + definitions
      • +
    +
  • HAL + + + + I2C update
    • +
      +
    • Update I2C_DMAError() + function implementation to + ignore DMA FIFO error
      • +
    +
  • HAL + + + + I2S update
    • +
      +
    • Enhance + HAL_I2S_Init() + implementation to test on + PCM_SHORT and PCM_LONG + standards
      • +
    +
  • HAL + + + + IRDA update
    • +
      +
    • Add new + functions and call backs for + Transfer Abort
      • +
        +
      • HAL_IRDA_Abort()
        • +
      • HAL_IRDA_AbortTransmit()
        • +
      • HAL_IRDA_AbortReceive()
        • +
      • HAL_IRDA_Abort_IT()
        • +
      • HAL_IRDA_AbortTransmit_IT()
        • +
      • HAL_IRDA_AbortReceive_IT()
        • +
      • HAL_IRDA_AbortCpltCallback()
        • +
      • HAL_IRDA_AbortTransmitCpltCallback()
        • +
      +
    +
+
    +
      +
        +
      • HAL_IRDA_AbortReceiveCpltCallback()
        • +
      +
    +
  • HAL + + + + PCD update
    • +
+
    +
      +
    • Update HAL_PCD_GetRxCount() +  function implementation
      • +
    +
  • HAL + + + + RCC update
    • +
      +
    • Update + __HAL_RCC_HSE_CONFIG() + macro implementation
      • +
    • Update __HAL_RCC_LSE_CONFIG() + macro implementation
      • +
    +
  • HAL + + + + SMARTCARD update
    • +
+
    +
      +
    • Add new + functions and call backs for + Transfer Abort
      • +
        +
      • HAL_ SMARTCARD_Abort()
        • +
      • HAL_ SMARTCARD_AbortTransmit()
        • +
      • HAL_ SMARTCARD_AbortReceive()
        • +
      • HAL_ SMARTCARD_Abort_IT()
        • +
      • HAL_ SMARTCARD_AbortTransmit_IT()
        • +
      • HAL_ SMARTCARD_AbortReceive_IT()
        • +
      • HAL_ SMARTCARD_AbortCpltCallback()
        • +
      • HAL_ SMARTCARD_AbortTransmitCpltCallback()
        • +
      • HAL_ SMARTCARD_AbortReceiveCpltCallback()
        • +
      +
    +
  • HAL + + + + TIM update
    • +
      +
    • Update HAL_TIMEx_RemapConfig() + function to manage TIM + internal trigger remap: + LPTIM or TIM3_TRGO
      • +
    +
  • HAL + + + + UART update
    • +
      +
    • Add + Transfer abort functions and + callbacks
      • +
    +
  • HAL + + + + USART update
    • +
      +
    • Add + Transfer abort functions and + callbacks
      • +
    +
+

V1.5.2 + + + + / 22-September-2016

+

Main Changes

+
    +
  • HAL + + + + I2C update
    • +
      +
    • Fix wrong + behavior in consecutive + transfers in case of single + byte transmission + (Master/Memory Receive
      + interfaces)
      • +
    • Update + HAL_I2C_Master_Transmit_DMA() + / + HAL_I2C_Master_Receive_DMA()/ + HAL_I2C_Slave_Transmit_DMA()
      + and + HAL_I2C_Slave_Receive_DMA() to + manage addressing phase + through interruption instead + of polling
      • +
    • Add + a check on I2C handle + state at start of all I2C + API's to ensure that I2C is ready
      • +
    • Update I2C + API's (Polling, IT and DMA + interfaces) to manage I2C XferSize + and XferCount + handle parameters instead of + API size parameter to help + user to get information of + counter in case of + error. 
      • +
    • Update Abort + functionality to manage DMA + use case
      • +
    +
  • HAL + + + + FMPI2C update
    • +
      +
    • Update to + disable Own Address + before setting the new Own + Address + configuration:
      • +
        +
      • Update + HAL_FMPI2C_Init() + to disable FMPI2C_OARx_EN + bit before any + configuration in OARx + registers
        • +
      +
    +
  • HAL + + + + CAN update
    • +
      +
    • Update CAN + receive processes to set CAN + RxMsg + FIFONumber + parameter
      • +
    +
  • HAL + + + + UART update
    • +
      +
    • Update UART + + + + handle TxXferCount + and RxXferCount parameters + + + + + as volatile to avoid + eventual issue with High Speed + optimization  
      • +
    +
+

V1.5.1 + + + + / 01-July-2016

+

Main Changes

+
    +
  • HAL + + + + GPIO update
    • +
      +
    • HAL_GPIO_Init()/HAL_GPIO_DeInit() + API's: + update GPIO_GET_INDEX() + macro implementation to + support all GPIO's
      • +
    +
  • HAL + + + + SPI update
    • +
      +
    • Fix + regression issue: + retore HAL_SPI_DMAPause() + and HAL_SPI_DMAResume() API's +
      • +
    +
  • HAL + + + + RCC update
    • +
      +
    • Fix FSMC + macros compilation warnings + with STM32F412Rx devices
      • +
    +
  • HAL + + + + DMA update
    • +
      +
    • HAL_DMA_PollFortransfer() API clean + up
      +
      +
      • +
    +
  • HAL + + + + PPP update(PPP refers to + IRDA, UART, USART and SMARTCARD)
    • +
      +
    • Update + + + + HAL_PPP_IRQHandler() + to add a check on interrupt + source before managing the + error 
      • +
    +
+
    +
  • HAL + + + + QSPI update
    • +
      +
    • Implement + workaround to fix the + limitation pronounced + + + + in + the Errata + sheet 2.1.8 section: + In some specific cases, + DMA2 data corruption + occurs when managing AHB + and APB2 peripherals in a + concurrent way
      • +
    +
+

V1.5.0 + + + + / 06-May-2016

+

Main Changes

+
    +
  • Add support of STM32F412cx, + + + + + STM32F412rx, STM32F412vx and + STM32F412zx devices
    • +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • Add + new HAL driver for DFSDM peripheral
    • +
  • Enhance + + + + HAL delay and time base + implementation:
    • +
      +
    • Add new + drivers + stm32f4xx_hal_timebase_rtc_alarm_template.c + and + stm32f4xx_hal_timebase_rtc_wakeup_template.c + which override the native HAL + time base functions (defined + as weak) to either use the RTC + as time base tick source. For + more details about the usage + of these drivers, please refer + to HAL\HAL_TimeBase_RTC + examples and + + + + + FreeRTOS-based + + + + + applications
      • +
    +
  • The + + + + following changes done on the + HAL drivers require an update + on the application code based + on HAL V1.4.4
    • +
      +
    • HAL UART, + USART, IRDA, SMARTCARD, SPI, + I2C,FMPI2C, + + + + + QSPI (referenced + as PPP here + + + + + below) drivers
      • +
        +
      • Add PPP + error management during DMA + process. This requires the + following updates + on user application:
        • +
          +
        • Configure + and enable the PPP IRQ in + HAL_PPP_MspInit() + function
          • +
        • In stm32f4xx_it.c + + + + + file, PPP_IRQHandler() + function: add + + + + + a call to HAL_PPP_IRQHandler() + + + + + function
          • +
        • Add and + customize the Error + Callback API: HAL_PPP_ErrorCallback()
          • +
        +
      +
    • HAL I2C, FMPI2C (referenced + as PPP here + + + + + below) drivers:
      • +
        +
      • Update to + avoid waiting on STOPF/BTF/AF + + + + + flag under DMA ISR by using + the PPP + + + + end of transfer interrupt in + the DMA transfer process. This + + + + + requires the following + updates on user + application:
        • +
          +
        • Configure + and enable the PPP IRQ in + HAL_PPP_MspInit() + function
          • +
        • In stm32f4xx_it.c + + + + + file, PPP_IRQHandler() + function: add + + + + + a call to HAL_PPP_IRQHandler() + + + + + function
          • +
        +
      +
    • HAL I2C driver:
      • +
        +
      • I2C + transfer processes IT + update: NACK during + addressing phase is managed + through I2C Error + interrupt instead of + HAL state
        • +
      +
    +
+
    +
      +
    • HAL IWDG driver: + rework overall driver for + better implementation
      • +
        +
      • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() + + + + + and HAL_IWDG_GetState() APIs
        • +
      +
    • HAL WWDG driver: + rework overall driver for + better implementation
      • +
        +
      • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() + + + + + and HAL_WWDG_GetState() + + + + + APIs 
        • +
      • Update + the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, + uint32_t counter) +  function and API +  by removing the +  "counter" parameter
        • +
      +
    • HAL QSPI + driver:  Enhance + the DMA transmit process + by using PPP TC + interrupt instead of waiting + on TC flag under DMA + ISR. This requires the + following updates on user + application:
      • +
        +
      • Configure + and enable the QSPI IRQ + in HAL_QSPI_MspInit() + function
        • +
      • In stm32f4xx_it.c + + + + + file, QSPI_IRQHandler() + function: add + + + + a call to HAL_QSPI_IRQHandler() + + + + + function
        • +
      +
    • HAL CEC + driver:  Overall + driver rework with + compatibility break versus + previous HAL version
      • +
        +
      • Remove HAL + CEC polling Process + functions: HAL_CEC_Transmit() + and HAL_CEC_Receive()
        • +
      • Remove HAL + CEC receive interrupt + process function HAL_CEC_Receive_IT() + and enable the "receive" +  mode during the Init + phase
        • +
      • Rename HAL_CEC_GetReceivedFrameSize() + funtion + to HAL_CEC_GetLastReceivedFrameSize()
        • +
      • Add new HAL + APIs: HAL_CEC_SetDeviceAddress() + and HAL_CEC_ChangeRxBuffer()
        • +
      • Remove + the 'InitiatorAddress' + field from the CEC_InitTypeDef + structure and manage + it as a parameter in + the HAL_CEC_Transmit_IT() + function
        • +
      • Add new + parameter 'RxFrameSize' + in HAL_CEC_RxCpltCallback() + function
        • +
      • Move CEC Rx + buffer pointer from CEC_HandleTypeDef + structure to CEC_InitTypeDef + structure
        • +
      +
    +
+
    +
  • HAL + + + + RCC update
    • +
      +
    • Update HAL_RCC_ClockConfig() + function to adjust the SystemCoreClock
      • +
    • Rename macros + and Literals:
      • +
        +
      • RCC_PERIPHCLK_CK48 by RCC_PERIPHCLK_CLK48
        • +
      • IS_RCC_CK48CLKSOURCE by + + + + + IS_RCC_CLK48CLKSOURCE
        • +
      • RCC_CK48CLKSOURCE_PLLSAIP + + + + + by RCC_CLK48CLKSOURCE_PLLSAIP
        • +
      • RCC_SDIOCLKSOURCE_CK48 + + + + by RCC_SDIOCLKSOURCE_CLK48
        • +
      • RCC_CK48CLKSOURCE_PLLQ + + + + + by RCC_CLK48CLKSOURCE_PLLQ
        • +
      +
    • Update HAL_RCCEx_GetPeriphCLKConfig() + and HAL_RCCEx_PeriphCLKConfig() + + + + + functions to support TIM Prescaler + for STM32F411xx devices
      • +
    • HAL_RCCEx_PeriphCLKConfig() API: update + to fix the RTC clock + configuration issue
      • +
    +
  • HAL + + + + CEC update
    • +
      +
    • Overall + driver rework with break + of compatibility with HAL + V1.4.4
      • +
        +
      • Remove the + HAL CEC polling Process: HAL_CEC_Transmit() + and HAL_CEC_Receive()
        • +
      +
    +
+
    +
      +
        +
      • Remove the + HAL CEC receive interrupt + process (HAL_CEC_Receive_IT()) + + + + + and manage the "Receive" + mode enable within the Init + phase
        • +
      • Rename HAL_CEC_GetReceivedFrameSize() + function to HAL_CEC_GetLastReceivedFrameSize() + + + + + function
        • +
      • Add new HAL + APIs: HAL_CEC_SetDeviceAddress() + and HAL_CEC_ChangeRxBuffer()
        • +
      • Remove + the 'InitiatorAddress' + field from the CEC_InitTypeDef + structure and manage + it as a parameter in + the HAL_CEC_Transmit_IT() + function
        • +
      • Add new + parameter 'RxFrameSize' + in HAL_CEC_RxCpltCallback() + function
        • +
      • Move CEC Rx + buffer pointer from CEC_HandleTypeDef + structure to CEC_InitTypeDef + structure
        • +
      +
    • Update driver + to implement the new CEC state + machine:
      • +
        +
      • Add + new "rxState" field + + + + + in CEC_HandleTypeDef + structure to provide the CEC state + + + + + information related to Rx Operations
        • +
      • Rename + "state" field in CEC_HandleTypeDef + structure to "gstate": + + + + CEC state + + + + + information related to + global Handle management and + Tx Operations
        • +
      • Update CEC + process to manage the new + CEC states.
        • +
      • Update + __HAL_CEC_RESET_HANDLE_STATE() + macro to handle the new CEC + state parameters (gState, + rxState)
        • +
      +
    +
+
    +
  • HAL + + + + UART, USART, SMARTCARD and + IRDA (referenced + + + + as PPP here below) update
    • +
      +
    • Update + Polling management:
      • +
        +
      • The user + Timeout value must be + estimated for the overall + process duration: the + Timeout measurement is + cumulative
        • +
      +
    • Update DMA + process:
      • +
        +
      • Update the + management of PPP peripheral + errors during DMA process. + This requires the following + updates in user application:
        • +
          +
        • Configure + and enable the PPP IRQ in + HAL_PPP_MspInit() + function
          • +
        • In + stm32f4xx_it.c file, PPP_IRQHandler() + function: add a call to HAL_PPP_IRQHandler() + + + + + function
          • +
        • Add and + customize the Error + Callback API: HAL_PPP_ErrorCallback()
          • +
        +
      +
    +
  • HAL + + + + FMC update
    • +
      +
    • Update FMC_NORSRAM_Init() + to remove the Burst access + mode configuration
      • +
    • Update FMC_SDRAM_Timing_Init() + to fix initialization issue + when configuring 2 SDRAM banks
      • +
    +
  • HAL + + + + HCD update
    • +
      +
    • Update HCD_Port_IRQHandler() + to unmask disconnect IT only + when the port is disabled
      • +
    +
  • HAL + + + + I2C/FMPI2C + update
    • +
      +
    • Update Polling + + + + + management:
      • +
        +
      • The Timeout + value must be estimated for + the overall process + duration: the + Timeout measurement is + cumulative
        • +
      +
    • Add the + management of Abort + service: Abort DMA + transfer through interrupt
      • +
        +
      • In the case + of Master Abort IT transfer + usage:
        • +
          +
        • Add new + + + + user HAL_I2C_AbortCpltCallback() + to inform user of the end + of abort process
          • +
        • A new + abort state is defined in + the HAL_I2C_StateTypeDef structure
          • +
        +
      +
    • Add the + management of I2C peripheral + errors, ACK failure and STOP + condition detection during DMA + process. This requires the + following updates on user + application:
      • +
        +
      • Configure + and enable the I2C IRQ in + HAL_I2C_MspInit() + function
        • +
      • In + stm32f4xx_it.c file, I2C_IRQHandler() + function: add a call to + HAL_I2C_IRQHandler() + function
        • +
      • Add and + customize the Error Callback + API: HAL_I2C_ErrorCallback()
        • +
      • Refer to + the I2C_EEPROM or + I2C_TwoBoards_ComDMA project + examples usage of the API
        • +
      +
    • NACK error + during addressing phase is + returned through interrupt + instead of previously through + I2C transfer API's
      • +
    • I2C + addressing phase is updated to + be managed using interrupt + instead of polling (Only + for HAL I2C driver)
      • +
        +
      • Add new + static functions to manage + I2C SB, ADDR and ADD10 flags
        • +
      +
    +
  • HAL + + + + SPI update
    • +
+
    +
      +
    • Overall + driver optimization to improve + performance in + polling/interrupt mode to + reach maximum peripheral frequency
      • +
        +
      • Polling + mode:
        • +
          +
        • Replace + the use of SPI_WaitOnFlagUnitTimeout() + function by "if" statement + to check on RXNE/TXE flage + while transferring data
          • +
        +
      +
    +
+
    +
      +
        +
      •  Interrupt + + + + mode:
        • +
          +
        • Minimize + access on SPI registers
          • +
        +
      • All modes:
        • +
          +
        • Add the + USE_SPI_CRC switch to + minimize the number of + statements when CRC + calculation is disabled
          • +
        • Update timeout + + + + + management to check on + global processes
          • +
        • Update + error code management in + all processes
          • +
        +
      +
    • Update DMA + process:
      • +
        +
      • Add the + management of SPI peripheral + errors during DMA process. + This requires the following + updates in the user + application:
        • +
          +
        • Configure + and enable the SPI IRQ in + HAL_SPI_MspInit() + function
          • +
        • In + stm32f4xx_it.c file, SPI_IRQHandler() + function: add a call to HAL_SPI_IRQHandler() + + + + + function
          • +
        • Add and + customize the Error + Callback API: HAL_SPI_ErrorCallback()
          • +
        • Refer to + the following example + which describe the + changes: SPI_FullDuplex_ComDMA
          • +
        +
      +
    • Fix + regression in polling mode:
      • +
        +
      • Add + preparing data to transmit + in case of slave mode in HAL_SPI_TransmitReceive() + and HAL_SPI_Transmit()
        • +
      • Add to + manage properly the overrun + flag at the end of a HAL_SPI_TransmitReceive()
        • +
      +
    • Fix + regression in interrupt mode:
      • +
        +
      • Add a wait + on TXE flag in SPI_CloseTx_ISR() + and in SPI_CloseTxRx_ISR()
        • +
      • Add to + manage properly + the overrun flag in SPI_CloseRxTx_ISR() + and SPI_CloseRx_ISR()
        • +
      +
    +
+
    +
  • HAL + + + + DMA2D update
    • +
      +
    • Update the + HAL_DMA2D_DeInit() + function to:
      • +
        +
      • Abort + transfer in case of ongoing + DMA2D transfer
        • +
      • Reset DMA2D + control registers
        • +
      +
    • Update + HAL_DMA2D_Abort() + to disable DMA2D interrupts + after stopping transfer
      • +
    • Optimize + HAL_DMA2D_IRQHandler() + by reading status registers + only once
      • +
    • Update + HAL_DMA2D_ProgramLineEvent() + function to:
      • +
        +
      • Return HAL + error state in case of wrong + line value
        • +
      • Enable line + interrupt after setting the + line watermark configuration
        • +
      +
    • Add new + HAL_DMA2D_CLUTLoad() + and HAL_DMA2D_CLUTLoad_IT() functions + + + + + to start DMA2D CLUT loading
      • +
        +
      • HAL_DMA2D_CLUTLoading_Abort() + function to abort the DMA2D + CLUT loading
        • +
      • HAL_DMA2D_CLUTLoading_Suspend() + function to suspend the + DMA2D CLUT loading
        • +
      • HAL_DMA2D_CLUTLoading_Resume() + function to resume the DMA2D + CLUT loading
        • +
      +
    • Add new DMA2D + dead time management:
      • +
        +
      • HAL_DMA2D_EnableDeadTime() + function to enable DMA2D + dead time feature
        • +
      • HAL_DMA2D_DisableDeadTime() + function to disable DMA2D + dead time feature
        • +
      • HAL_DMA2D_ConfigDeadTime() + function to configure dead + time
        • +
      +
    • Update the + name of DMA2D Input/Output + color mode defines to be more + + + + clear for + user (DMA2D_INPUT_XXX for + input layers Colors, + DMA2D_OUTPUT_XXX for output + framebuffer Colors)
      • +
    +
+
    +
  • HAL + + + + LTDC update
    • +
+
    +
      +
    • Update HAL_LTDC_IRQHandler() + to manage the case of reload + interrupt
      • +
    • Add new + callback API HAL_LTDC_ReloadEventCallback()
      • +
    • Add HAL_LTDC_Reload() + to configure LTDC reload + feature
      • +
    • Add new No + Reload LTDC variant APIs
      • +
        +
      • HAL_LTDC_ConfigLayer_NoReload() to + configure the LTDC Layer + according to the specified + without reloading
        • +
      • HAL_LTDC_SetWindowSize_NoReload() to set + the LTDC window size without + reloading
        • +
      • HAL_LTDC_SetWindowPosition_NoReload() to set + the LTDC window position + without reloading
        • +
      • HAL_LTDC_SetPixelFormat_NoReload() to + reconfigure the pixel format + without reloading
        • +
      • HAL_LTDC_SetAlpha_NoReload() to + reconfigure the layer alpha + value without reloading
        • +
      • HAL_LTDC_SetAddress_NoReload() to + reconfigure the frame buffer + Address without reloading
        • +
      • HAL_LTDC_SetPitch_NoReload() to + reconfigure the pitch for + specific cases
        • +
      • HAL_LTDC_ConfigColorKeying_NoReload() to + configure the color keying + without reloading
        • +
      • HAL_LTDC_EnableColorKeying_NoReload() to enable + the color keying without + reloading
        • +
      • HAL_LTDC_DisableColorKeying_NoReload() to + disable the color keying + without reloading
        • +
      • HAL_LTDC_EnableCLUT_NoReload() to enable + the color lookup table + without reloading
        • +
      • HAL_LTDC_DisableCLUT_NoReload() to + disable the color lookup + table without reloading
        • +
      • Note: Variant + functions with �_NoReload� + post fix allows to set the + LTDC configuration/settings + without immediate reload. + This is useful in case when + the program requires to + modify several LTDC settings + (on one or both layers) then + applying (reload) these + settings in one shot by + calling the function �HAL_LTDC_Reload�
        • +
      +
    +
  • HAL + + + + RTC update 
    • +
      +
    • Add new + timeout implementation based + on cpu + cycles + for ALRAWF, ALRBWF + and WUTWF flags
      • +
    +
+
    +
  • HAL + + + + SAI update
    • +
      +
    • Update SAI + state in case of TIMEOUT error + within the HAL_SAI_Transmit() + / HAL_SAI_Receive()
      • +
    • Update HAL_SAI_IRQHandler:
      • +
        +
      • Add error + management in case DMA + errors through XferAbortCallback() + and HAL_DMA_Abort_IT()
        • +
      • Add error + management in case of IT
        • +
      +
    • Move SAI_BlockSynchroConfig() + and SAI_GetInputClock() + + + + + functions to + stm32f4xx_hal_sai.c/.h files + (extension files are kept + empty for projects + compatibility reason)
      • +
    +
+
    +
  • HAL + + + + DCMI update
    • +
      +
    • Rename DCMI_DMAConvCplt + to DCMI_DMAXferCplt
      • +
    • Update HAL_DCMI_Start_DMA() + function to Enable the + DCMI peripheral
      • +
    • Add new + timeout implementation based + on cpu + cycles for DCMI stop
      • +
    • Add HAL_DCMI_Suspend() + function to suspend DCMI + capture
      • +
    • Add HAL_DCMI_Resume() + function to resume capture + after DCMI suspend
      • +
    • Update lock + mechanism for DCMI process
      • +
    • Update HAL_DCMI_IRQHandler() + function to:
      • +
        +
      • Add error + management in case DMA + errors through XferAbortCallback() + and HAL_DMA_Abort_IT()
        • +
      • Optimize + code by using direct + register read
        • +
      +
    +
+
    +
  • HAL + + + + DMA + update
    • +
      +
    • Add new APIs + HAL_DMA_RegisterCallback() + and HAL_DMA_UnRegisterCallback + to register/unregister the + different callbacks identified + by the enum + typedef HAL_DMA_CallbackIDTypeDef
      • +
    • Add new API HAL_DMA_Abort_IT() + to abort DMA transfer under + interrupt context
      • +
        +
      • The new + registered Abort callback is + called when DMA transfer + abortion is completed
        • +
      +
    • Add the check + of compatibility between FIFO + threshold level and size of + the memory burst in the HAL_DMA_Init() + API
      • +
    • Add new Error + Codes: HAL_DMA_ERROR_PARAM, + HAL_DMA_ERROR_NO_XFER and + HAL_DMA_ERROR_NOT_SUPPORTED
      • +
    • Remove all + DMA states related to + MEM0/MEM1 in HAL_DMA_StateTypeDef
      • +
    +
  • HAL + + + + IWDG + update
    • +
      +
    • Overall + rework of the driver for a + more + efficient implementation
      • +
        +
      • Remove the + following APIs:
        • +
          +
        • HAL_IWDG_Start()
          • +
        • HAL_IWDG_MspInit()
          • +
        • HAL_IWDG_GetState()
          • +
        +
      • Update + implementation:
        • +
          +
        • HAL_IWDG_Init(): this + function insures the + configuration and the + start of the IWDG counter
          • +
        • HAL_IWDG_Refresh(): this + function insures the + reload of the IWDG counter
          • +
        +
      • Refer to + the following example to + identify the changes: IWDG_Example
        • +
      +
    +
  • HAL + + + + LPTIM + update
    • +
      +
    • Update HAL_LPTIM_TimeOut_Start_IT() + and HAL_LPTIM_Counter_Start_IT( + ) APIs to configure WakeUp + Timer EXTI interrupt to be + able to wakeup + MCU from low power mode by + pressing the EXTI line.
      • +
    • Update HAL_LPTIM_TimeOut_Stop_IT() + and HAL_LPTIM_Counter_Stop_IT( + ) APIs to disable WakeUp + Timer EXTI interrupt. 
      • +
    +
  • HAL + + + + NOR update
    • +
      +
    • Update + NOR_ADDR_SHIFT macro implementation
      • +
    +
  • HAL + + + + PCD update
    • +
      +
    • Update HAL_PCD_IRQHandler() + to get HCLK frequency before + setting TRDT value
      • +
    +
  • HAL + + + + QSPI + update
    • +
+
    +
      +
    • Update to + manage QSPI error management + during DMA process
      • +
    • Improve the + DMA transmit process by using + QSPI TC interrupt instead of + waiting loop on TC flag under + DMA ISR
      • +
    • These two + improvements require the + following updates on user + application:
      • +
        +
      • Configure + and enable the QSPI IRQ in HAL_QSPI_MspInit() + function
        • +
      • In + stm32f4xx_it.c file, QSPI_IRQHandler() + function: add a call to HAL_QSPI_IRQHandler() + + + + function
        • +
      • Add and + customize the Error Callback + API: HAL_QSPI_ErrorCallback()
        • +
      +
    • Add the + management of non-blocking + transfer abort service: HAL_QSPI_Abort_IT(). + + + + + In this case the user must:
      • +
        +
      • Add new + callback HAL_QSPI_AbortCpltCallback() + to inform user at the end of + abort process
        • +
      • A new value + of State in the HAL_QSPI_StateTypeDef + provides the current state + during the abort phase
        • +
      +
    • Polling + management update:
      • +
        +
      • The Timeout + value user must be estimated + for the overall process + duration: the + Timeout measurement is + cumulative. 
        • +
      +
    • Refer to the + following examples, which + describe the changes:
      • +
        +
      • QSPI_ReadWrite_DMA
        • +
      • QSPI_MemoryMapped
        • +
      • QSPI_ExecuteInPlace
        • +
      +
    +
+
    +
      +
    • Add two new + APIs for the QSPI fifo + threshold:
      • +
        +
      • HAL_QSPI_SetFifoThreshold(): + configure the FIFO threshold + of the QSPI
        • +
      • HAL_QSPI_GetFifoThreshold(): give the + current FIFO threshold
        • +
      +
    • Fix wrong + data size management in HAL_QSPI_Receive_DMA()
      • +
    +
+
    +
  • HAL + + + + ADC update
    • +
      +
    • Add new + __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() + macro for STM32F42x and + STM32F43x devices to + provide the possibility + to convert VrefInt + channel when both VrefInt + and Vbat + channels are selected.
      • +
    +
  • HAL + + + + SPDIFRX update
    • +
      +
    • Overall driver + update for wait on flag + management optimization 
      • +
    +
  • HAL + + + + WWDG update 
    • +
      +
    • Overall + rework of the driver for more + efficient implementation
      • +
        +
      • Remove the + following APIs:
        • +
          +
        • HAL_WWDG_Start()
          • +
        • HAL_WWDG_Start_IT()
          • +
        • HAL_WWDG_MspDeInit()
          • +
        • HAL_WWDG_GetState()
          • +
        +
      • Update + implementation:
        • +
          +
        • HAL_WWDG_Init()
          • +
            +
          • A new + + + + parameter in the Init + Structure: EWIMode
            • +
          +
        • HAL_WWDG_MspInit()
          • +
        • HAL_WWDG_Refresh() 
          • +
            +
          • This + function insures the + reload of the counter
            • +
          • The + "counter" parameter has + been removed
            • +
          +
        • HAL_WWDG_IRQHandler()
          • +
        • HAL_WWDG_EarlyWakeupCallback() is the + new prototype of HAL_WWDG_WakeUpCallback()
          • +
        +
      +
    • Refer to the + following example to identify + the changes: WWDG_Example
      • +
    +
+

V1.4.4 + + + + / 22-January-2016

+

Main Changes

+
    +
  • HAL + + + + Generic update
    • +
      +
    • stm32f4xx_hal_conf_template.h
      • +
        +
      • Optimize + HSE Startup Timeout value + from 5000ms to 100 ms
        • +
      • Add new + define LSE_STARTUP_TIMEOUT
        • +
      • Add new + define USE_SPI_CRC for code + cleanup when the CRC + calculation is disabled.
        • +
      +
    • Update HAL + drivers to support MISRA C + 2004 rule 10.6
      • +
    • Add new + template driver to + configure timebase + using TIMER :
      • +
        +
      • stm32f4xx_hal_timebase_tim_template.c
        • +
      +
    +
+
    +
  • HAL + + + + CAN update
    • +
      +
    • Update HAL_CAN_Transmit() + and HAL_CAN_Transmit_IT() + + + + + functions to unlock + process when all Mailboxes are + busy
      • +
    +
+
    +
  • HAL + + + + DSI update
    • +
      +
    • Update HAL_DSI_SetPHYTimings() + functions to use the correct + mask
      • +
    +
  • HAL + + + + UART update
    • +
      +
    • Several + update on HAL UART driver to + implement the new UART state + machine: 
      • +
        +
      • Add new + field in UART_HandleTypeDef + structure: "rxState", + + + + + UART state information + related to Rx Operations
        • +
      • Rename + "state" field in UART_HandleTypeDef + structure by "gstate": + + + + UART state information + related to global Handle + management and Tx Operations
        • +
      • Update UART + process to manage the new + UART states.
        • +
      • Update + __HAL_UART_RESET_HANDLE_STATE() + macro to handle the new UART + state parameters (gState, + rxState)
        • +
      +
    • Update + UART_BRR_SAMPLING16() and + UART_BRR_SAMPLING8() Macros to + fix wrong baudrate + calculation.
      • +
    +
+
    +
  • HAL + + + + IRDA update
    • +
      +
    • Several + update on HAL IRDA driver to + implement the new UART state + machine: 
      • +
        +
      • Add new + field in IRDA_HandleTypeDef + structure: "rxState", + + + + + IRDA state information + related to Rx Operations
        • +
      • Rename + "state" field in UART_HandleTypeDef + structure by "gstate": + + + + IRDA state information + related to global Handle + management and Tx Operations
        • +
      • Update IRDA + process to manage the new + UART states.
        • +
      • Update + __HAL_IRDA_RESET_HANDLE_STATE() + macro to handle the new IRDA + state parameters (gState, + rxState)
        • +
      +
    • Removal of + IRDA_TIMEOUT_VALUE define
      • +
    • Update IRDA_BRR() + Macro to fix wrong baudrate + calculation
      • +
    +
  • HAL + + + + SMARTCARD update
    • +
      +
    • Several + update on HAL SMARTCARD driver + to implement the new UART + state machine: 
      • +
        +
      • Add new + field in SMARTCARD_HandleTypeDef + structure: "rxState", + + + + + SMARTCARDstate + information related to Rx Operations
        • +
      • Rename + "state" field in UART_HandleTypeDef + structure by "gstate": + + + + SMARTCARDstate + information related to + global Handle management and + Tx Operations
        • +
      • Update SMARTCARD + + + + + process to manage the new + UART states.
        • +
      • Update + __HAL_SMARTCARD_RESET_HANDLE_STATE() + macro to handle the + new SMARTCARD state + parameters (gState, + rxState)
        • +
      +
    • Update + SMARTCARD_BRR() + macro to fix wrong baudrate + calculation
      • +
    +
+
    +
  • HAL  + RCC + update
    • +
      +
    • Add new + default define value for HSI + calibration + "RCC_HSICALIBRATION_DEFAULT"
      • +
    • Optimize + Internal oscillators and PLL + startup timeout 
      • +
    • Update to + avoid the disable for HSE/LSE + oscillators before setting the + new RCC HSE/LSE configuration + and add the following notes in + HAL_RCC_OscConfig() + API description:
      • +
    +
+

     + + + +       +     +     +     +       * + @note   Transitions LSE + Bypass to LSE On and LSE On to LSE + Bypass are not
+     + + + + +     +     +     +     +     +      + *         +     supported by this + API. User should request a + transition to LSE Off
+     + + + + +     +     +     +     +     +      + *         +     first and then LSE + On or LSE Bypass.
+     + + + + +     +     +     +     +     +      * + @note   Transition HSE + Bypass to HSE On and HSE On to HSE + Bypass are not
+     + + + + +     +     +     +     +     +      + *         +     supported by this + API. User should request a + transition to HSE Off
+     + + + + +     +     +     +         +      + *         +     first and then HSE + On or HSE Bypass.

+
    +
      +
    • Optimize + the HAL_RCC_ClockConfig() + API implementation.
      • +
    +
+
    +
  • HAL + + + + DMA2D update
    • +
      +
    • Update + HAL_DMA2D_Abort() + Function to end current DMA2D + transfer properly
      • +
    • Update + HAL_DMA2D_PollForTransfer() + function to add poll for + background CLUT loading (layer + 0 and layer 1).
      • +
    • Update + HAL_DMA2D_PollForTransfer() + to set the corresponding ErrorCode + in case of error occurrence
      • +
    • Update + HAL_DMA2D_ConfigCLUT() + function to fix wrong CLUT + size and color mode settings
      • +
    • Removal of + useless macro __HAL_DMA2D_DISABLE()
      • +
    • Update + HAL_DMA2D_Suspend() + to manage correctly the case + where no transfer is on going
      • +
    • Update + HAL_DMA2D_Resume() to + + + + + manage correctly the case + where no transfer is on going
      • +
    • Update + HAL_DMA2D_Start_IT() + to enable all required + interrupts before enabling the + transfer.
      • +
    • Add + HAL_DMA2D_CLUTLoad_IT() + Function to allow loading a + CLUT with interruption model.
      • +
    •  Update + HAL_DMA2D_IRQHandler() + to manage the following + cases :
      +
      +
      • +
        +
      • CLUT + transfer complete
        • +
      • CLUT access + error
        • +
      • Transfer + watermark reached
        • +
      +
    • Add new + Callback APIs:
      • +
        +
      •  HAL_DMA2D_LineEventCallback() + to signal a transfer + watermark reached event
        • +
      •  HAL_DMA2D_CLUTLoadingCpltCallback() + to signal a CLUT loading + complete event
        • +
      +
    +
+
    +
      +
    • Miscellaneous + Improvement:
      • +
        +
      • Add + "HAL_DMA2D_ERROR_CAE" new + define for CLUT Access error + management.
        • +
      • Add     ï¿½assert_param� + used for parameters check is + now done on the top of the + exported functions : before + locking the process using + __HAL_LOCK
        • +
      +
    +
+

 

+
    +
  • HAL + + + + I2C update
    • +
      +
    • Add support + of I2C repeated start feature:
      • +
        +
      • With the + following new API's
        • +
          +
        • HAL_I2C_Master_Sequential_Transmit_IT()
          • +
        • HAL_I2C_Master_Sequential_Receive_IT()
          • +
        • HAL_I2C_Master_Abort_IT()
          • +
        • HAL_I2C_Slave_Sequential_Transmit_IT()
          • +
        • HAL_I2C_Slave_Sequential_Receive_IT()
          • +
        • HAL_I2C_EnableListen_IT()
          • +
        • HAL_I2C_DisableListen_IT()
          • +
        +
      • Add new + user callbacks:
        • +
          +
        • HAL_I2C_ListenCpltCallback()
          • +
        • HAL_I2C_AddrCallback()
          • +
        +
      +
    • Update to + generate STOP condition when a + acknowledge failure error is detected
      • +
    • Several + update on HAL I2C driver to + implement the new I2C state + machine: 
      • +
        +
      • Add new API + to get the I2C mode: + HAL_I2C_GetMode()
        • +
      • Update I2C + process to manage the new + I2C states.
        • +
      +
    • Fix wrong behaviour + in single byte transmission 
      • +
    • Update I2C_WaitOnFlagUntilTimeout() to + + + + + manage the NACK feature.
      • +
    • Update  I2C + transmission process to + support the case data size + equal 0
      • +
    +
+
    +
  • HAL + + + + FMPI2C update
    • +
      +
    • Add support + of FMPI2C repeated start + feature:
      • +
        +
      • With the + following new API's
        • +
          +
        • HAL_FMPI2C_Master_Sequential_Transmit_IT()
          • +
        • HAL_FMPI2C_Master_Sequential_Receive_IT()
          • +
        • HAL_FMPI2C_Master_Abort_IT()
          • +
        • HAL_FMPI2C_Slave_Sequential_Transmit_IT()
          • +
        • HAL_FMPI2C_Slave_Sequential_Receive_IT()
          • +
        • HAL_FMPI2C_EnableListen_IT()
          • +
        • HAL_FMPI2C_DisableListen_IT()
          • +
        +
      • Add new + user callbacks:
        • +
          +
        • HAL_FMPI2C_ListenCpltCallback()
          • +
        • HAL_FMPI2C_AddrCallback()
          • +
        +
      +
    • Several + update on HAL I2C driver to + implement the new I2C state + machine: 
      • +
        +
      • Add new API + to get the FMPI2C mode: + HAL_FMPI2C_GetMode()
        • +
      • Update + FMPI2C process to manage the + new FMPI2C states.
        • +
      +
    +
+
    +
  • HAL + + + + SPI update
    • +
      +
    • Major Update + to improve performance in + polling/interrupt mode to + reach max frequency:
      • +
        +
      • Polling mode + + + + :
        • +
          +
        • Replace + use of SPI_WaitOnFlagUnitTimeout() + funnction + by "if" statement to check + on RXNE/TXE flage + while transferring data.
          • +
        • Use API + data pointer instead of + SPI handle data pointer.
          • +
        • Use a Goto + implementation instead of + "if..else" + statements.
          • +
        +
      +
    +
+
    +
      +
        +
      • Interrupt + mode
        • +
          +
        • Minimize + access on SPI registers.
          • +
        • Split the + SPI modes into dedicated + static functions to + minimize checking + statements under HAL_IRQHandler():
          • +
            +
          • 1lines/2lines + + + + modes
            • +
          • 8 bit/ + 16 bits data formats
            • +
          • CRC + calculation + enabled/disabled.
            • +
          +
        • Remove + waiting loop under ISR + when closing + + + +  the + communication.
          • +
        +
      • All + modes:  
        • +
          +
        • Adding + switch USE_SPI_CRC to + minimize number of + statements when CRC + calculation is disabled.
          • +
        • Update + Timeout management to + check on global process.
          • +
        • Update + Error code management in + all processes.
          • +
        +
      +
    • Add note to + the max frequencies reached in + all modes.
      • +
    • Add note + about Master Receive mode restrictions :
      • +
        +
      • Master + + + + Receive mode restriction:
        +       + (#) In Master + unidirectional receive-only + mode (MSTR =1, BIDIMODE=0, + RXONLY=0) or
        +           + + + + + bidirectional receive mode + (MSTR=1, BIDIMODE=1, + BIDIOE=0), to ensure that + the SPI
        +           + + + + does not initiate a new + transfer the following + procedure has to be + respected:
        +           + + + + (##) HAL_SPI_DeInit()
        +           + + + + (##) HAL_SPI_Init() + + + +
        • +
      +
    +
+
    +
  • HAL + + + + SAI update
    • +
      +
    • Update for + proper management of the + external synchronization input + selection
      • +
        +
      • update + of HAL_SAI_Init + () funciton
        • +
      • update + definition of SAI_Block_SyncExt + and SAI_Block_Synchronization + groups
        • +
      +
    • Update + SAI_SLOTACTIVE_X +  defines + values
      • +
    • Update HAL_SAI_Init() + function for proper companding + mode management
      • +
    • Update SAI_Transmit_ITxxBit() + functions to add the check on + transfer counter before + writing new data to SAIx_DR + registers
      • +
    • Update SAI_FillFifo() + function to avoid issue when + the number of data to transmit + is smaller than the FIFO size
      • +
    • Update HAL_SAI_EnableRxMuteMode() + function for proper mute + management
      • +
    • Update SAI_InitPCM() + function to support 24bits + configuration
      • +
    +
  • HAL + + + + ETH update
    • +
      +
    • Removal of + ETH MAC debug register defines
      • +
    +
  • HAL + + + + FLASH update
    • +
      +
    • Update FLASH_MassErase() + function to apply correctly + voltage range parameter
      • +
    +
  • HAL + + + + I2S update
    • +
      +
    • Update I2S_DMATxCplt() + and I2S_DMARxCplt() to manage + properly FullDuplex + mode without any risk of + missing data.
      • +
    +
  • LL + + + + FMC update
    • +
      +
    • Update the FMC_NORSRAM_Init() + function to use BurstAccessMode + field properly
      • +
    +
  • LL + + + + FSMC  + + + + update
    • +
      +
    • Update the FSMC_NORSRAM_Init() + function to use BurstAccessMode + field properly
      • +
    +
+


+
+

+

V1.4.4 + / 11-December-2015

+

Main Changes

+
    +
  • HAL + + + + Generic update
    • +
      +
    • Update HAL + weak empty callbacks to + prevent unused argument + compilation warnings with some + compilers by calling the + following line:
      • +
        +
      • UNUSED(hppp);
        • +
      +
    • STM32Fxxx_User_Manual.chm + + + + + files regenerated for HAL + V1.4.3
      • +
    +
  • HAL + + + + ETH update 
    • +
      +
    • Update HAL_ETH_Init() + function to add timeout on the + Software reset management
      • +
    +
+

V1.4.2 + + + + / 10-November-2015

+

Main Changes

+
    +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • One + + + + change done on the HAL CRYP + requires an update on the + application code based on HAL + V1.4.1
    • +
      +
    • Update HAL_CRYP_DESECB_Decrypt() + API to invert pPlainData + and pCypherData + parameters
      • +
    +
  • HAL + + + + generic + update
    • +
      +
    • Update HAL + weak empty callbacks to + prevent unused argument + compilation warnings with some + compilers by calling the + following line:
      • +
        +
      • UNUSED(hppp);
        • +
      +
    +
+
    +
  • HAL + + + + CORTEX update
    • +
      +
    • Remove + duplication for + __HAL_CORTEX_SYSTICKCLK_CONFIG() + macro
      • +
    +
+
    +
  • HAL + + + + HASH update
    • +
      +
    • Rename HAL_HASH_STATETypeDef + to HAL_HASH_StateTypeDef
      • +
    • Rename HAL_HASH_PhaseTypeDef + to HAL_HASH_PhaseTypeDef
      • +
    +
  • HAL + + + + RCC update
    • +
      +
    • Add new + macros __HAL_RCC_PPP_IS_CLK_ENABLED() + to check on Clock + enable/disable status
      • +
    • Update + __HAL_RCC_USB_OTG_FS_CLK_DISABLE() + macro to remove the disable + for the SYSCFG
      • +
    • Update HAL_RCC_MCOConfig() + API to use new defines for the + GPIO Speed
      • +
    • Generic + update to improve the + PLL VCO min + value(100MHz): PLLN, PLLI2S + and PLLSAI min value is 50 + instead of 192
      • +
    +
  • HAL + + + + FLASH update
    • +
      +
    • __HAL_FLASH_INSTRUCTION_CACHE_RESET() + macro: update to reset +  ICRST bit in + the ACR register after + setting it.
      • +
    • Update to + support until 15 FLASH wait + state (FLASH_LATENCY_15) for + STM32F446xx devices +
      • +
    +
+

�  + + + + + HAL CRYP update

+
    +
      +
    • Update HAL_CRYP_DESECB_Decrypt() + API to fix the inverted pPlainData + and pCypherData + parameters issue
      • +
    +
  • HAL + + + + I2S update
    • +
      +
    • Update + HAL_I2S_Init() + API to call + __HAL_RCC_I2S_CONFIG() macro + when external I2S clock is + selected
      • +
    +
  • HAL + + + + LTDC update
    • +
      +
    • Update HAL_LTDC_SetWindowPosition() + API to configure + Immediate reload register + instead of vertical blanking + reload register.
      • +
    +
  • HAL + + + + TIM update
    • +
      +
    • Update HAL_TIM_ConfigClockSource() + API to check only the + required parameters
      • +
    +
  • HAL + + + + NAND update
    • +
      +
    • Update + HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() + APIs to manage correctly the + NAND Page access
      • +
    +
  • HAL + + + + CAN update
    • +
      +
    • Update to use + "=" instead of "|=" to clear + flags in the MSR, TSR, RF0R + and RF1R registers
      • +
    +
  • HAL + + + + HCD update
    • +
      +
    • Fix typo in + __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() + macro implementation
      • +
    +
  • HAL + + + + PCD update
    • +
      +
    • Update HAL_PCD_IRQHandler() + API to avoid issue + when DMA mode enabled for + Status Phase IN stage
      • +
    +
  • LL + + + + FMC update
    • +
      +
    • Update the FMC_NORSRAM_Extended_Timing_Init() + API to remove the check + on CLKDIvison + and DataLatency + parameters
      • +
    • Update the FMC_NORSRAM_Init() + API to add a check on the PageSize + parameter for STM32F42/43xx + devices
      • +
    +
  • LL + + + + FSMC update
    • +
      +
    • Update the FSMC_NORSRAM_Extended_Timing_Init() + API to remove the check + on CLKDIvison + and DataLatency + parameters
      • +
    +
+

V1.4.1 + + + + / 09-October-2015

+

Main Changes

+
    +
  • HAL + + + + DSI update
    • +
      +
    • Update TCCR + register assigned value + in HAL_DSI_ConfigHostTimeouts() + function
      • +
    • Update WPCR + register assigned value + in HAL_DSI_Init(), + + + + + HAL_DSI_SetSlewRateAndDelayTuning(), + + + + + HAL_DSI_SetSlewRateAndDelayTuning(), + + + + + HAL_DSI_SetLowPowerRXFilter() + + + + + / HAL_DSI_SetSDD(), + + + + + HAL_DSI_SetLanePinsConfiguration(), + + + + + HAL_DSI_SetPHYTimings(), + + + + + HAL_DSI_ForceTXStopMode(), + + + + + HAL_DSI_ForceRXLowPower(), + + + + + HAL_DSI_ForceDataLanesInRX(), + + + + + HAL_DSI_SetPullDown() + + + + + and HAL_DSI_SetContentionDetectionOff() + + + + + functions
      • +
    • Update + DSI_HS_PM_ENABLE define value
      • +
    • Implement + workaround for the hardware + limitation: �The time to + activate the clock between HS + transmissions is not + calculated correctly�
      • +
    +
+

V1.4.0 + + + + / 14-August-2015

+

Main Changes

+
    +
  • Add + support of STM32F469xx, STM32F479xx, + STM32F410Cx, STM32F410Rx + and STM32F410Tx  + devices
    • +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • Add + new HAL drivers for DSI and LPTIM + + + + + peripherals
    • +
+
    +
  • HAL + + + + ADC update
    • +
      +
    • Rename + ADC_CLOCKPRESCALER_PCLK_DIV2 + define to + ADC_CLOCK_SYNC_PCLK_DIV2
      • +
    • Rename + ADC_CLOCKPRESCALER_PCLK_DIV4 + define to + ADC_CLOCK_SYNC_PCLK_DIV4
      • +
    • Rename + ADC_CLOCKPRESCALER_PCLK_DIV6 + define to + ADC_CLOCK_SYNC_PCLK_DIV6
      • +
    • Rename + ADC_CLOCKPRESCALER_PCLK_DIV8 + define to + ADC_CLOCK_SYNC_PCLK_DIV8
      • +
    +
  • HAL + + + + CORTEX update
    • +
      +
    • Add specific + API for MPU management
      • +
        +
      • add MPU_Region_InitTypeDef + structure
        • +
      • add new + function HAL_MPU_ConfigRegion()
        • +
      +
    +
  • HAL + + + + DMA update
    • +
      +
    • Overall driver + update for code optimization
      • +
        +
      • add StreamBaseAddress + and StreamIndex + new fields in the DMA_HandleTypeDef + structure
        • +
      • add DMA_Base_Registers + private structure
        • +
      • add static + function DMA_CalcBaseAndBitshift()
        • +
      • update HAL_DMA_Init() + function to use the new + added static function
        • +
      • update HAL_DMA_DeInit() + function to optimize clear + flag operations
        • +
      • update HAL_DMA_Start_IT() + function to optimize + interrupts enable
        • +
      • update HAL_DMA_PollForTransfer() + function to optimize check + on flags
        • +
      • update HAL_DMA_IRQHandler() + function to optimize + interrupt flag management
        • +
      +
    +
  • HAL + + + + FLASH update
    • +
      +
    • update HAL_FLASH_Program_IT() + function by removing the + pending flag clear
      • +
    • update HAL_FLASH_IRQHandler() + function to improve erase + operation procedure
      • +
    • update FLASH_WaitForLastOperation() + function by checking on end of + operation flag
      • +
    +
  • HAL + + + + GPIO update
    • +
      +
    • Rename + GPIO_SPEED_LOW define to + GPIO_SPEED_FREQ_LOW
      • +
    • Rename + GPIO_SPEED_MEDIUM define to + GPIO_SPEED_FREQ_MEDIUM
      • +
    • Rename + GPIO_SPEED_FAST define to + GPIO_SPEED_FREQ_HIGH
      • +
    • Rename + GPIO_SPEED_HIGH define to + GPIO_SPEED_FREQ_VERY_HIGH
      • +
    +
  • HAL + + + + I2S update
    • +
      +
    • Move + I2S_Clock_Source defines to + extension file to properly add + the support of STM32F410xx devices
      • +
    +
  • HAL + + + + LTDC update
    • +
      +
    • rename HAL_LTDC_LineEvenCallback() + function to HAL_LTDC_LineEventCallback()
      • +
    • add new + function HAL_LTDC_SetPitch()
      • +
    • add new + functions HAL_LTDC_StructInitFromVideoConfig() + and HAL_LTDC_StructInitFromAdaptedCommandConfig() + + + + + applicable only to STM32F469xx + and STM32F479xx devices
      • +
    +
  • HAL + + + + PWR update
    • +
      +
    • move + __HAL_PWR_VOLTAGESCALING_CONFIG() + macro to extension file
      • +
    • move + PWR_WAKEUP_PIN2 define to + extension file
      • +
    • add + PWR_WAKEUP_PIN3 define, + applicable only to STM32F10xx + devices
      • +
    • add new + functions HAL_PWREx_EnableWakeUpPinPolarityRisingEdge() + and HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(), + + + + + applicable only to STM32F469xx + and STM32F479xx devices
      • +
    +
+
    +
  • HAL + + + + RTC update
    • +
      +
    • Update HAL_RTCEx_SetWakeUpTimer() + and HAL_RTCEx_SetWakeUpTimer_IT() + + + + + functions to properly check on + the WUTWF flag
      • +
    +
  • HAL + + + + TIM update
    • +
      +
    • add new + defines TIM_SYSTEMBREAKINPUT_HARDFAULT,  + + + + TIM_SYSTEMBREAKINPUT_PVD + + + + + and + TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD, + applicable only to STM32F410xx + devices
      • +
    +
+

V1.3.2 + + + + / 26-June-2015

+

Main Changes

+
    +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • One + + + + changes + done on the HAL may require an + update on the application code + based on HAL V1.3.1
    • +
      +
    • HASH IT + process: update to call the HAL_HASH_InCpltCallback() + at the end of the complete + buffer instead of every each + 512 bits
      • +
    +
+
    +
  • HAL + + + + RCC update
    • +
      +
    • HAL_RCCEx_PeriphCLKConfig() updates:
      • +
        +
      • Update the + LSE check condition after + backup domain reset: + update to check LSE + ready flag when LSE + oscillator is already + enabled instead of check on + LSE oscillator only when LSE + is used as RTC clock source
        • +
      • Use the + right macro to check the + PLLI2SQ parameters +
        • +
      +
    +
+
    +
  • HAL + + + + RTC update
    • +
      +
    • __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() + macro: fix implementation + issue
      • +
    • __HAL_RTC_ALARM_GET_IT(), + + + + + __HAL_RTC_ALARM_CLEAR_FLAG(), + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(), + + + + + __HAL_RTC_TIMESTAMP_CLEAR_FLAG() + + + + and + __HAL_RTC_TAMPER_CLEAR_FLAG() + macros implementation changed: + remove unused cast
      • +
    • IS_RTC_TAMPER() + macro: update to use literal + instead of hardcoded + value 
      • +
    • Add new + parameter SecondFraction + in RTC_TimeTypeDef + structure
      • +
    • HAL_RTC_GetTime() API update + to support the new + parameter SecondFraction +
      • +
    +
  • HAL + + + + ADC update
    • +
      +
    • Add new + literal: + ADC_INJECTED_SOFTWARE_START to + be used as possible value for + the ExternalTrigInjecConvEdge + parameter in the ADC_InitTypeDef + structure to select the ADC + software trigger mode.
      • +
    +
  • HAL + + + + FLASH update
    • +
      +
    • FLASH_OB_GetRDP() API update + to return uint8_t instead of FlagStatus
      • +
    •  __HAL_FLASH_GET_LATENCY() + new macro add to get the flash + latency
      • +
    +
  • HAL + + + + SPI update
    • +
      +
    • Fix the wrong + definition of + HAL_SPI_ERROR_FLAG literal
      • +
    +
  • HAL + + + + I2S update
    • +
      +
    • HAL_I2S_Transmit() + API update to check on busy + flag only for I2S slave mode
      • +
    +
  • HAL + + + + CRC update
    • +
      +
    • __HAL_CRC_SET_IDR() + macro implementation change to + use WRITE_REG() instead of + MODIFY_REG()
      • +
    +
  • HAL + + + + DMA2D update
    • +
      +
    • HAL_DMA2D_ConfigLayer() + API update to use "=" instead + of "|=" to erase BGCOLR and + FGCOLR registers before + setting the new configuration
      • +
    +
  • HAL + + + + HASH update
    • +
      +
    • HAL_HASH_MODE_Start_IT() (MODE + + + + stands for MD5, SHA1, + SHA224 and SHA36) updates:
      • +
        +
      • Fix processing + + + + + fail for small input buffers
        • +
      • Update to + unlock the process and + call return + HAL_OK at the end of + HASH processing to avoid + incorrectly repeating software
        • +
      • Update to + properly manage the HashITCounter
        • +
      • Update to + call the HAL_HASH_InCpltCallback() + at the end of the complete + buffer instead of every each + 512 bits
        • +
      +
    • __HAL_HASH_GET_FLAG() + update to  check the + right register when the DINNE + flag  is selected
      • +
    • HAL_HASH_SHA1_Accumulate() + updates:
      • +
        +
      • Add + a call to the new + IS_HASH_SHA1_BUFFER_SIZE() + macro to check the size + parameter. 
        • +
      • Add the + following note in API description
        • +
      +
    +
+
+

 * + + + + + @note  + + + + + Input buffer + size in bytes must be a multiple + of 4 otherwise the digest + computation is corrupted.

+
+
    +
  • HAL + + + + RTC update
    • +
      +
    • Update to + define hardware + independent literals names:
      • +
        +
      • Rename + RTC_TAMPERPIN_PC13 by + + + +  RTC_TAMPERPIN_DEFAULT
        • +
      • Rename + RTC_TAMPERPIN_PA0 by + RTC_TAMPERPIN_POS1
        • +
      • Rename + RTC_TAMPERPIN_PI8 by + RTC_TAMPERPIN_POS1
        • +
      • Rename + RTC_TIMESTAMPPIN_PC13 by + RTC_TIMESTAMPPIN_DEFAULT
        • +
      • Rename + RTC_TIMESTAMPPIN_PA0 by + RTC_TIMESTAMPPIN_POS1
        • +
      • Rename + RTC_TIMESTAMPPIN_PI8 by + RTC_TIMESTAMPPIN_POS1
        • +
      +
    +
  • HAL + + + + ETH update
    • +
      +
    • Remove + duplicated IS_ETH_DUPLEX_MODE() + and IS_ETH_RX_MODE() macros
      • +
    • Remove + illegal space + ETH_MAC_READCONTROLLER_FLUSHING + macro
      • +
    • Update + ETH_MAC_READCONTROLLER_XXX + defined values (XXX can be + IDLE, READING_DATA and + READING_STATUS)
      • +
    +
  • HAL + + + + PCD update
    • +
      +
    • HAL_PCD_IRQHandler API: fix the + bad Configuration of + Turnaround Time
      • +
    +
  • HAL + + + + HCD update
    • +
      +
    • Update to use + local variable in USB + Host channel re-activation
      • +
    +
  • LL + + + + FMC update
    • +
      +
    • FMC_SDRAM_SendCommand() API: remove + the following line: return + HAL_ERROR;
      • +
    +
  • LL + + + + USB update
    • +
      +
    • USB_FlushTxFifo API: + update to flush all Tx FIFO
      • +
    • Update to use + local variable in USB + Host channel re-activation
      • +
    +
+

V1.3.1 + + + + / 25-Mars-2015

+

Main Changes

+
    +
  • HAL + + + + PWR update
    • +
      +
    • Fix + compilation issue with + STM32F417xx product: + update STM32F17xx + by STM32F417xx
      • +
    +
  • HAL + + + + SPI update
    • +
      +
    • Remove unused + variable to avoid warning with + TrueSTUDIO 
      • +
    +
  • HAL + + + + I2C update
    • +
      +
    • I2C + Polling/IT/DMA processes: move + the wait loop on busy + flag at the top of the + processes, to ensure that + software not perform any write + access to I2C_CR1 register + before hardware + clearing STOP bit and to + avoid + + + + + also the + waiting loop on BUSY flag + under I2C/DMA ISR.
      • +
    • Update busy + flag Timeout value
      • +
    • I2C Master + Receive Processes update to + disable ACK before generate + the STOP 
      • +
    +
  • HAL + + + + DAC update
    • +
      +
    • Fix V1.3.0 + regression issue with DAC + software trigger configuration
      • +
    +
+

V1.3.0 + + + + / 09-Mars-2015

+

Main Changes

+
    +
  • Add + support of STM32F446xx devices
    • +
  • General + + + + updates to fix known defects and + enhancements implementation
    • +
  • Add + new HAL drivers for CEC, + QSPI, FMPI2C and SPDIFRX + + + + peripherals
    • +
  • Two + + + + changes done on the HAL + requires an update on the + application code based on HAL + V1.2.0
    • +
      +
    • Overall SAI + driver rework to have + exhaustive support of the + peripheral features: details + are provided in HAL SAI update + + + + section below --> Compatibility + + + + + with previous version is impacted
      • +
    • CRYP driver + updated to support multi instance,so + user must ensure that the + new parameter Instance is + initalized + in his application(CRYPHandle.Instance + = CRYP) 
      • +
    +
+
    +
  • HAL + + + + Generic update
    • +
      +
    • stm32f4xx_hal_def.h
      • +
        +
      • Remove NULL + definition and add + include for stdio.h
        • +
      +
    • stm32_hal_legacy.h
      • +
        +
      • Update method + + + + to manage deference in + alias implementation between + all STM32 families
        • +
      +
    • stm32f4xx_hal_ppp.c
      • +
        +
      • HAL_PPP_Init(): update + to force the + HAL_PPP_STATE_RESET before + calling the HAL_PPP_MspInit()
        • +
      +
    +
+
    +
  • HAL + + + + RCC update
    • +
      +
    • Add new + function HAL_RCCEx_GetPeriphCLKFreq()
      • +
    • Move RCC_PLLInitTypeDef + structure to extension file + and add the new PLLR field + specific to STM32F446xx devices
      • +
    • Move the + following functions to + extension file and add a + __weak attribute in generic driver + + + + : this + update is related to new + system clock source (PLL/PLLR) + added and only available for + STM32F44xx devices
      • +
        +
      • HAL_RCC_OscConfig()
        • +
      • HAL_RCC_GetSysClockFreq()
        • +
      • HAL_RCC_GetOscConfig()
        • +
      +
    • Move the + following macro to extension + file as they have device + dependent implementation
      • +
        +
      • __HAL_RCC_PLL_CONFIG()
        • +
      • __HAL_RCC_PLLI2S_CONFIG()
        • +
      • __HAL_RCC_I2S_CONFIG()
        • +
      +
    • Add new + structure RCC_PLLI2SInitTypeDef + containing new PLLI2S + division factors used only w/ + STM32F446xx devices
      • +
    • Add new + structure RCC_PLLSAIInitTypeDef + containing new PLLSAI + division factors used only w/ + STM32F446xx devices
      • +
    • Add new RCC_PeriphCLKInitTypeDef + to support the peripheral + source clock selection for (I2S, + + + + SAI, SDIO, FMPI2C, CEC, + SPDIFRX and CLK48)
      • +
    • Update the HAL_RCCEx_PeriphCLKConfig() + and HAL_RCCEx_GetPeriphCLKConfig() + + + + + functions to support the + new peripherals Clock source + selection
      • +
    • Add __HAL_RCC_PLL_CONFIG() + macro (the number of parameter + and the implementation depend + on the device part number)
      • +
    • Add __HAL_RCC_PLLI2S_CONFIG() + macro(the number of parameter + and the implementation depend + on device part number)
      • +
    • Update __HAL_RCC_PLLSAI_CONFIG() + macro to support new PLLSAI + factors (PLLSAIM and + PLLSAIP)
      • +
    • Add new + macros for clock + enable/Disable for the + following peripherals (CEC, + + + + SPDIFRX, SAI2, QUADSPI)
      • +
    • Add the + following new macros for clock + source selection + + + + :
      • +
        +
      • __HAL_RCC_SAI1_CONFIG() + / + __HAL_RCC_GET_SAI1_SOURCE()
        • +
      • __HAL_RCC_SAI2_CONFIG() + / + __HAL_RCC_GET_SAI2_SOURCE()
        • +
      • __HAL_RCC_I2S1_CONFIG() + / + __HAL_RCC_GET_I2S1_SOURCE()
        • +
      • __HAL_RCC_I2S2_CONFIG() + / + __HAL_RCC_GET_I2S2_SOURCE()
        • +
      • __HAL_RCC_CEC_CONFIG() + / + __HAL_RCC__GET_CEC_SOURCE() +
        • +
      • __HAL_RCC_FMPI2C1_CONFIG() + / + __HAL_RCC_GET_FMPI2C1_SOURCE() +
        • +
      • __HAL_RCC_SDIO_CONFIG() + / + __HAL_RCC_GET_SDIO_SOURCE() +
        • +
      • __HAL_RCC_CLK48_CONFIG() + / + __HAL_RCC_GET_CLK48_SOURCE() +
        • +
      • __HAL_RCC_SPDIFRXCLK_CONFIG() + / + __HAL_RCC_GET_SPDIFRX_SOURCE()
        • +
      +
    • __HAL_RCC_PPP_CLK_ENABLE(): + + + + + Implement workaround to cover + RCC limitation regarding + peripheral enable delay
      • +
    • HAL_RCC_OscConfig() fix + issues: 
      • +
        +
      • Add a check + on LSERDY flag when + LSE_BYPASS is selected as + new state for LSE + oscillator.
        • +
      +
    • Add + new possible value RCC_PERIPHCLK_PLLI2S + + + + to be selected as PeriphClockSelection + parameter in the + + + + +  RCC_PeriphCLKInitTypeDef + structure to allow the + possibility to output the + PLLI2S on MCO without + activating the I2S or the SAI.
      • +
    • __HAL_RCC_HSE_CONFIG() +  macro: add + the comment below:
      • +
    +
+
+

 * + + + + + @note   Transition + HSE Bypass to HSE On and HSE + On to HSE Bypass are not + supported by this macro.
+  *         + + + + User should request a + transition to HSE Off first + and then HSE On or HSE Bypass.

+
+
    +
      +
    • __HAL_RCC_LSE_CONFIG()  macro: add + the comment below:
      • +
    +
+
+

  * + + + + + @note   Transition + LSE Bypass to LSE On and LSE + On to LSE Bypass are not + supported by this macro.
+   + *         + User should request a + transition to LSE Off first + and then LSE On or LSE Bypass.

+
+
    +
      +
    • Add the + following new macros for + PLL source and PLLM selection + + + + :
      • +
        +
      • __HAL_RCC_PLL_PLLSOURCE_CONFIG()
        • +
      • __HAL_RCC_PLL_PLLM_CONFIG()
        • +
      +
    • Macros + rename:
      • +
        +
      • HAL_RCC_OTGHS_FORCE_RESET() +by HAL_RCC_USB_OTG_HS_FORCE_RESET()
        • +
      • HAL_RCC_OTGHS_RELEASE_RESET() +by HAL_RCC_USB_OTG_HS_RELEASE_RESET()
        • +
      • HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() +by HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()
        • +
      • HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() +by HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()
        • +
      • HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() +by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
        • +
      • HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() +by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
        • +
      +
    • Add __HAL_RCC_SYSCLK_CONFIG() + new macro to configure the + system clock source (SYSCLK)
      • +
    • __HAL_RCC_GET_SYSCLK_SOURCE() + updates:
      • +
        +
      • Add new RCC + Literals:
        • +
          +
        • RCC_SYSCLKSOURCE_STATUS_HSI
          • +
        • RCC_SYSCLKSOURCE_STATUS_HSE
          • +
        • RCC_SYSCLKSOURCE_STATUS_PLLCLK
          • +
        • RCC_SYSCLKSOURCE_STATUS_PLLRCLK
          • +
        +
      •  Update + + + + macro description to refer + to the literals above +
        • +
      +
    +
  • HAL + + + + PWR update
    • +
      +
    • Add new + define PWR_WAKEUP_PIN2
      • +
    • Add new API + to Control/Get VOS bits + of CR register
      • +
        +
      • HAL_PWR_HAL_PWREx_ControlVoltageScaling()
        • +
      • HAL_PWREx_GetVoltageRange()
        • +
      +
    • __HAL_PWR_ + VOLTAGESCALING_CONFIG(): Implement + workaround to cover VOS + limitation delay when PLL is + enabled after setting the VOS + configuration
      • +
    +
  • HAL + + + + GPIO update
    • +
      +
    • Add the new + Alternate functions literals + related to remap for SPI, + + + + USART, I2C, SPDIFRX, CEC + and QSPI
      • +
    • HAL_GPIO_DeInit(): + + + + Update to check if GPIO + Pin x is already used in EXTI + mode on another GPIO Port + before De-Initialize the EXTI + registers
      • +
    +
  • HAL + + + + FLASH update
    • +
      +
    • __HAL_FLASH_INSTRUCTION_CACHE_RESET() + macro: update to reset +  ICRST bit in + the ACR register after + setting it.
      • +
    • __HAL_FLASH_DATA_CACHE_RESET() macro: + + + + + update to reset +  DCRST bit in the ACR + register after setting it.
      • +
    +
  • HAL + + + + ADC update
    • +
      +
    • Add new + literal: ADC_SOFTWARE_START to + be used as possible value for + the ExternalTrigConv + parameter in the ADC_InitTypeDef + structure to select the ADC + software trigger mode.
      • +
    • IS_ADC_CHANNEL() + macro update to don't assert + stop the ADC_CHANNEL_TEMPSENSOR + value
      • +
    • HAL_ADC_PollForConversion(): update to + manage particular case when + ADC configured in DMA mode and + ADC sequencer with several + ranks and polling for end of + each conversion
      • +
    • HAL_ADC_Start()/HAL_ADC_Start_IT() + /HAL_ADC_Start_DMA() + + + + + update:
      • +
        +
      • unlock the + process before starting the + ADC software conversion.
        • +
      • Optimize + the ADC stabilization delays
        • +
      +
    • __HAL_ADC_GET_IT_SOURCE() + update macro implementation
      • +
    • Add more + details in 'How to use this + driver' section
      • +
    +
  • HAL + + + + DAC update
    • +
      +
    • Add new macro + to check if the specified DAC + interrupt source is enabled or + disabled
      • +
        +
      • __HAL_DAC_GET_IT_SOURCE()
        • +
      +
    • HAL_DACEx_TriangleWaveGeneration() update to + use DAC CR bit mask definition
      • +
    • HAL_DACEx_NoiseWaveGeneration() update to + use DAC CR bit mask definition
      • +
    +
  • HAL + + + + CAN update
    • +
      +
    • CanTxMsgTypeDef structure: + update to use uint8_t Data[8] + + + + + instead of + uint32_t Data[8]
      • +
    • CanRxMsgTypeDef structure: + update to use uint8_t Data[8] + instead of + uint32_t Data[8]
      • +
    +
+
    +
  • HAL + + + + RTC update
    • +
      +
    • Update to + use CMSIS mask definition + instead of hardcoded values (EXTI_IMR_IM17, + EXTI_IMR_IM19..)
      • +
    +
  • HAL + + + + LTDC update
    • +
      +
    • LTDC_SetConfig() update to + allow the drawing + of partial bitmap in + active layer.
      • +
    +
  • HAL + + + + USART update
    • +
      +
    • HAL_USART_Init() fix USART + baud rate configuration + issue: USART baud rate is + twice Higher than expected
      • +
    +
  • HAL + + + + SMARTCARD update
    • +
      +
    • HAL_SMARTCARD_Transmit_IT() update to + force the disable for the ERR + interrupt to avoid the OVR + interrupt
      • +
    • HAL_SMARTCARD_IRQHandler() + update check condition + for transmission end
      • +
    • Clean up: + remove the following + literals that aren't used in + smartcard mode
      • +
        +
      • SMARTCARD_PARITY_NONE
        • +
      • SMARTCARD_WORDLENGTH_8B
        • +
      • SMARTCARD_STOPBITS_1
        • +
      • SMARTCADR_STOPBITS_2
        • +
      +
    +
  • HAL + + + + SPI update
    • +
      +
    • HAL_SPI_Transmit_DMA()/HAL_SPI_Receive_DMA()/HAL_SPI_TarnsmitReceive_DMA() + update to unlock + the process before + enabling the SPI peripheral
      • +
    • HAL_SPI_Transmit_DMA() update to + manage correctly the DMA RX + stream in SPI Full duplex mode
      • +
    • Section + SPI_Exported_Functions_Group2 update + to remove duplication in *.chm + UM
      • +
    +
  • HAL + + + + CRYP update
    • +
      +
    • Update to + manage multi instance:
      • +
        +
      • Add new + parameter Instance in the CRYP_HandleTypeDef + Handle structure.
        • +
      • Add new + parameter in all HAL CRYP + macros
        • +
          +
        • example: __HAL_CRYP_ENABLE() +  updated by + __HAL_CRYP_ENABLE(__HANDLE__)
          • +
        +
      +
    +
  • HAL + + + + DCMI update
    • +
      +
    • Add an + extension + driver stm32f4xx_hal_dcmi_ex.c/h + to manage the support of new + Black and White feature +
      • +
    • Add  __weak attribute + for HAL_DCMI_Init() + function and add a new + implementation in the + extension driver to manage the + black and white configuration + only available in the  + STM32F446xx devices. +
      • +
    • Move DCMI_InitTypeDef + structure to extension driver + and add the + following new fields + related to black and white + feature: ByteSelectMode, ByteSelectStart, LineSelectMode + and LineSelectStart
      • +
    +
  • HAL + + + + PCD update
    • +
      +
    • Add the + support of LPM feature
      • +
        +
      • add PCD_LPM_StateTypeDef + enum
        • +
      • update PCD_HandleTypeDef + structure to support the LPM + feature
        • +
      • add new + functions HAL_PCDEx_ActivateLPM(), + + + + + HAL_PCDEx_DeActivateLPM() + + + + + and HAL_PCDEx_LPM_Callback() + + + + + in the + stm32f4xx_hal_pcd_ex.h/.c + files
        • +
      +
    +
  • HAL + + + + TIM update
    • +
      +
    • Add  + TIM_TIM11_SPDIFRX + + + + define
      • +
    +
  • HAL + + + + SAI update
    • +
      +
    • Add + stm32f4xx_hal_sai_ex.h/.c + files for the SAI_BlockSynchroConfig() + and the SAI_GetInputClock() + + + + + management
      • +
    • Add new + defines HAL_SAI_ERROR_AFSDET, + HAL_SAI_ERROR_LFSDET, + HAL_SAI_ERROR_CNREADY, + HAL_SAI_ERROR_WCKCFG, + HAL_SAI_ERROR_TIMEOUT in the SAI_Error_Code + group
      • +
    • Add new + defines SAI_SYNCEXT_DISABLE, + SAI_SYNCEXT_IN_ENABLE, + SAI_SYNCEXT_OUTBLOCKA_ENABLE, + SAI_SYNCEXT_OUTBLOCKB_ENABLE + for the SAI External + synchronization
      • +
    • Add new + defines SAI_I2S_STANDARD, + SAI_I2S_MSBJUSTIFIED, + SAI_I2S_LSBJUSTIFIED, + SAI_PCM_LONG and SAI_PCM_SHORT + for the SAI Supported protocol
      • +
    • Add new + defines + SAI_PROTOCOL_DATASIZE_16BIT, + SAI_PROTOCOL_DATASIZE_16BITEXTENDED, + SAI_PROTOCOL_DATASIZE_24BIT + and + SAI_PROTOCOL_DATASIZE_32BIT + for SAI protocol data size
      • +
    • Add SAI + Callback prototype definition
      • +
    • Update SAI_InitTypeDef + structure by adding new + fields: SynchroExt, + Mckdiv, + MonoStereoMode, + CompandingMode, + TriState
      • +
    • Update SAI_HandleTypeDef + structure:
      • +
        +
      • remove + uint16_t *pTxBuffPtr, + *pRxBuffPtr, + TxXferSize, + RxXferSize, + TxXferCount + and RxXferCount + and replace them + respectively by uint8_t *pBuffPtr, + uint16_t XferSize and + + + + + uint16_t XferCount
        • +
      • add mutecallback + field
        • +
      • add struct + __SAI_HandleTypeDef + *hsai field
        • +
      +
    • Remove + SAI_CLKSOURCE_PLLR and + SAI_CLOCK_PLLSRC defines
      • +
    • Add + SAI_CLKSOURCE_NA define
      • +
    • Add + SAI_AUDIO_FREQUENCY_MCKDIV + define
      • +
    • Add + SAI_SPDIF_PROTOCOL define
      • +
    • Add + SAI_SYNCHRONOUS_EXT define
      • +
    • Add new + functions HAL_SAI_InitProtocol(), + + + + + HAL_SAI_Abort(), + + + + + HAL_SAI_EnableTxMuteMode(), + + + + + HAL_SAI_DisableTxMuteMode(), + + + + + HAL_SAI_EnableRxMuteMode(), + + + + + HAL_SAI_DisableRxMuteMode()
      • +
    • Update HAL_SAI_Transmit(), + + + + + HAL_SAI_Receive(), + + + + + HAL_SAI_Transmit_IT(), + + + + + HAL_SAI_Receive_IT(), + + + + + HAL_SAI_Transmit_DMA(), + + + + + HAL_SAI_Receive_DMA() + + + + + functions to use uint8_t *pData + instead of uint16_t *pData + --> This update is mainly + impacting the compatibility + with previous driver + version.
      • +
    +
  • HAL + + + + I2S update
    • +
      +
    • Split the + following + functions between Generic + and Extended API based on full + duplex management and add the + attribute __weak in the + Generic API
      • +
        +
      • HAL_I2S_Init(), + + + + + HAL_I2S_DMAPause(), HAL_I2S_DMAStop(), HAL_I2S_DMAResume(), HAL_I2S_IRQHandle() + + + + +
        • +
      +
    • Move the + following static functions + from generic to extension driver
      • +
        +
      •  I2S_DMARxCplt() + and I2S_DMATxCplt()
        • +
      +
    • Remove static + attribute from I2S_Transmit_IT() + and I2S_Receive_IT() functions
      • +
    • Move I2SxEXT() + macro to extension file
      • +
    • Add + I2S_CLOCK_PLLR and + I2S_CLOCK_PLLSRC defines for + I2S clock source
      • +
    • Add new + function I2S_GetInputClock()
      • +
    +
  • HAL + + + + LL FMC update
    • +
      +
    • Add WriteFifo + and PageSize + fields in the FMC_NORSRAM_InitTypeDef + structure
      • +
    • Add + FMC_PAGE_SIZE_NONE, + FMC_PAGE_SIZE_128, + FMC_PAGE_SIZE_256, + FMC_PAGE_SIZE_1024, + FMC_WRITE_FIFO_DISABLE, + FMC_WRITE_FIFO_ENABLE defines
      • +
    • Update FMC_NORSRAM_Init(), + + + + + FMC_NORSRAM_DeInit() + + + + + and FMC_NORSRAM_Extended_Timing_Init() functions
      • +
    +
  • HAL + + + + LL USB update
    • +
      +
    • Update USB_OTG_CfgTypeDef + structure to support LPM, lpm_enable + field added
      • +
    • Update USB_HostInit() + and USB_DevInit() + + + + + functions to support the VBUS + Sensing B activation
      • +
    +
+

V1.2.0 + + + + / 26-December-2014

+

Main Changes

+
    +
  • Maintenance + + + + release to fix known defects + and enhancements implementation
    • +
+
    +
  • Macros + + + + and literals renaming to + ensure compatibles across + STM32 series, + backward compatibility + maintained thanks to new added + file stm32_hal_legacy.h under + + + + /Inc/Legacy
    • +
  • Add + *.chm UM for all drivers, a UM + is provided for each superset RPN
    • +
  • Update + + + + drivers to be C++ compliant
    • +
  • Several + + + + update on source code + formatting, for better UM + generation (i.e. + Doxygen + tags updated)
    • +
  • Two + + + + changes done on the HAL + requires an update on the + application code based on HAL + V1.1.0
    • +
      +
    • LSI_VALUE constant has + been corrected in + stm32f4xx_hal_conf.h file, its + value changed from 40 KHz + to 32 KHz
      • +
    • UART, USART, + IRDA and SMARTCARD + (referenced as PPP + here below) drivers: + in DMA transmit process, the + code has been updated to avoid + waiting on TC flag under DMA + ISR, PPP TC interrupt + is used instead. Below the + update to be done on user + application:
      • +
        +
      • Configure + and enable the USART IRQ in + HAL_PPP_MspInit() + function
        • +
      • In + stm32f4xx_it.c file, PPP_IRQHandler() + function: add a call to HAL_PPP_IRQHandler() + + + + function
        • +
      +
    +
+
    +
  • HAL + + + + generic + update
    • +
+
    +
      +
    • stm32f4xx_hal_def.h
      • +
        +
      • Update NULL + definition to fix C++ + compilation issue
        • +
      • Add UNUSED() + macro
        • +
      • Add a new + define __NOINLINE to be used + for the no inline code + independent from tool chain
        • +
      +
    • stm32f4xx_hal_conf_template.h
      • +
        +
      • LSI_VALUE constant + has been corrected, + its value changed from 40 KHz + to 32 KHz
        • +
      +
    +
+
    +
      +
    • Update all + macros and literals naming to + be uper + case
      • +
    • ErrorCode parameter in + PPP_HandleTypeDef + structure updated + to uint32_t instead + of enum HAL_PPP_ErrorTypeDef
      • +
    • Remove the + + + + unused FLAG and IT assert macros
      • +
    +
  • HAL + + + + ADC update
    • +
      +
    • Fix temperature + + + + + sensor channel configuration + issue for STM32F427/437xx + + + + +  and STM32F429/439xx + + + + devices
      • +
    +
  • HAL + + + + DAC update
    • +
      +
    • HAL_DAC_ConfigChannel(): update the + access to the DAC peripheral + registers via the hdac + handle instance
      • +
    • HAL_DAC_IRQHandler(): update to + check on both DAC_FLAG_DMAUDR1 + and DAC_FLAG_DMAUDR2
      • +
    • HAL_DACEx_NoiseWaveGenerate(): update to + reset DAC CR register before + setting the new DAC + configuration
      • +
    • HAL_DACEx_TriangleWaveGenerate(): update to + reset DAC CR register before + setting the new DAC + configuration
      • +
    +
  • HAL + + + + CAN update
    • +
      +
    • Unlock the + CAN process when communication + error occurred
      • +
    +
  • HAL + + + + CORTEX update
    • +
      +
    • Add new macro + IS_NVIC_DEVICE_IRQ() + to check on negative values of + IRQn + parameter
      • +
    +
+

�  + + + + + HAL CRYP update

+
    +
      +
    • HAL_CRYP_DESECB_Decrypt_DMA(): fix the + inverted pPlainData + and pCypherData + parameters issue
      • +
    • CRYPEx_GCMCCM_SetInitVector(): remove + the IVSize + parameter as the key length + 192bits and 256bits are not + supported by this version
      • +
    • Add restriction for + + + + + the CCM Encrypt/Decrypt API's + that only DataType + equal to 8bits is supported
      • +
    • HAL_CRYPEx_AESGCM_Finish():
      • +
        +
      • Add restriction + + + + + that the implementation is + limited to 32bits inputs + data length  (Plain/Cyphertext, + + + + Header) compared with GCM stadards + specifications (800-38D)
        • +
      • Update Size + parameter on 32bits instead + of 16bits
        • +
      • Fix issue + with 16-bit Data Type: + update to use intrinsic __ROR() + instead of __REV16()
        • +
      +
    +
+

�  + + + + + HAL DCMI update

+
    +
      +
    • HAL_DCMI_ConfigCROP(): Invert + assert macros to check Y0 and + Ysize + parameters
      • +
    +
+

�  + + + + + HAL DMA update

+
    +
      +
    • HAL_DMA_Init(): Update to + + + + + clear the DBM bit in the + SxCR + register before setting the + new configuration
      • +
    • DMA_SetConfig(): + add to clear the DBM + bit in the SxCR + register
      • +
    +
+

�  + + + + + HAL FLASH update

+
    +
      +
    • Add "HAL_" + prefix in the defined values + for the FLASH error code
      • +
        +
      • Example: FLASH_ERROR_PGP + renamed by HAL_FLASH_ERROR_PGP
        • +
      +
    • Clear the + + + + Flash ErrorCode + in the FLASH_WaitForLastOperation() + function
      • +
    • Update FLASH_SetErrorCode() + function to use "|=" + operant to update the Flash ErrorCode + parameter in the FLASH handle
      • +
    • IS_FLASH_ADDRESS(): Update the + macro check using '<=' + condition instead of '<'
      • +
    • IS_OPTIONBYTE(): Update the + macro check using '<=' + condition instead of '<'
      • +
    • Add "FLASH_" + + + + + prefix in the defined values + of FLASH Type Program + parameter
      • +
        +
      • Example: TYPEPROGRAM_BYTE + renamed by FLASH_TYPEPROGRAM_BYTE
        • +
      +
    • Add "FLASH_" + + + + + prefix in the defined values + of FLASH Type Erase parameter
      • +
        +
      • Example: TYPEERASE_SECTORS + renamed by FLASH_TYPEERASE_SECTORS
        • +
      +
    • Add "FLASH_" + + + + + prefix in the defined values + of FLASH Voltage Range + parameter
      • +
        +
      • Example: VOLTAGE_RANGE_1 + renamed by FLASH_VOLTAGE_RANGE_1
        • +
      +
    • Add "OB_" + + + + + prefix in the defined values + of FLASH WRP State parameter
      • +
        +
      • Example: WRPSTATE_ENABLE + renamed by OB_WRPSTATE_ENABLE
        • +
      +
    • Add "OB_" + + + + + prefix in the defined values + of the FLASH PCROP State + parameter
      • +
        +
      • PCROPSTATE_DISABLE  + updated by OB_PCROP_STATE_DISABLE
        • +
      • PCROPSTATE_ENABLE +  updated by OB_PCROP_STATE_ENABLE
        • +
      +
    • Change + "OBEX" prefix by + "OPTIONBYTE" prefix in these + defines:
      • +
        +
      • OBEX_PCROP + + + + by OPTIONBYTE_PCROP 
        • +
      • OBEX_BOOTCONFIG + + + + by OPTIONBYTE_BOOTCONFIG
        • +
      +
    +
+

�  + + + + + HAL ETH update

+
    +
      +
    • Fix macros + naming typo
      • +
    +
+
    +
      +
        +
      • Update + __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() + by + __HAL_ETH_EXTI_SET_RISING_EDGE_TRIGGER()
        • +
      • Update + __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() +by __HAL_ETH_EXTI_SET_FALLING_EDGE_TRIGGER()
        • +
      +
    +
+

�  + + + + + HAL PWR update

+
    +
      +
    • Add new API + to manage SLEEPONEXIT and + SEVONPEND bits of SCR register
      • +
        +
      • HAL_PWR_DisableSleepOnExit()
        • +
      • HAL_PWR_EnableSleepOnExit()
        • +
      • HAL_PWR_EnableSEVOnPend()
        • +
      • HAL_PWR_DisableSEVOnPend()
        • +
      +
    • HAL_PWR_EnterSTOPMode()
      • +
        +
      • Update to + + + + clear the CORTEX SLEEPDEEP + bit of SCR register + before entering in sleep mode
        • +
      • Update + usage of __WFE() + in low power entry function: + if there is a pending event, + calling __WFE() will not + enter the CortexM4 core to + sleep mode. The solution is + to made the call below; the + first __WFE() + is always ignored and clears + the event if one was already + pending, the second is + always applied
        • +
      +
    +
+
+

__SEV()
+ __WFE()
+ __WFE()

+
+
    +
      +
    • Add + new PVD configuration modes
      • +
        +
      • PWR_PVD_MODE_NORMAL
        • +
      • PWR_PVD_MODE_EVENT_RISING 
        • +
      • PWR_PVD_MODE_EVENT_FALLING
        • +
      • PWR_PVD_MODE_EVENT_RISING_FALLING
        • +
      +
    • Add new + macros to manage PVD Trigger
      • +
        +
      • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()
        • +
      • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(
        • +
      • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()
        • +
      • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
        • +
      • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
        • +
      • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
        • +
      +
    • PVD macros:
      • +
        +
      • Remove the + __EXTILINE__ parameter
        • +
      • Update to + use prefix "__HAL_PWR_PVD_" + instead of  prefix + "__HAL_PVD"
        • +
      +
    +
+
    +
      +
    • Rename HAL_PWR_PVDConfig() + by HAL_PWR_ConfigPVD()
      • +
    • Rename HAL_PWREx_ActivateOverDrive() + by HAL_PWREx_EnableOverDrive() + + + + +
      • +
    • Rename HAL_PWREx_DeactivateOverDrive() + by HAL_PWREx_DisableOverDrive() + + + + +
      • +
    +
  • HAL + + + + GPIO update
    • +
      +
    • HAL_GPIO_Init()/HAL_GPIO_DeInit(): add a call + to the CMSIS assert macro + to check GPIO instance: + IS_GPIO_ALL_INSTANCE() 
      • +
    • HAL_GPIO_WritePin(): update to + write in BSRR register
      • +
    • Rename GPIO_GET_SOURCE() + by GET_GPIO_INDEX() and + + + + move this later to file  + stm32f4xx_hal_gpio_ex.h
      • +
    • Add new + define for alternate function + GPIO_AF5_SPI3 for + STM32F429xx/439xx and + STM32F427xx/437xx devices
      • +
    +
  • HAL + + + + HASH update
    • +
      +
    • HAL_HASH_MD5_Start_IT(): + + + + + fix input + address management issue
      • +
    +
  • HAL + + + + RCC update
    • +
      +
    • Rename the + following Macros
      • +
        +
      • __PPP_CLK_ENABLE()  + + + + + by + __HAL_RCC_PPP_CLK_ENABLE()
        • +
      • __PPP_CLK_DISABLE()  + + + + + by + __HAL_RCC_PPP_CLK_DISABLE()
        • +
      • __PPP_FORCE_RESET()  + + + + + by + __HAL_RCC_PPP_FORCE_RESET()
        • +
      • __PPP_RELEASE_RESET()  + + + + + by + __HAL_RCC_PPP_RELEASE_RESET()
        • +
      • __PPP_CLK_SLEEP_ENABLE() + by + __HAL_RCC_PPP_CLK_SLEEP_ENABLE()
        • +
      • __PPP_CLK_SLEEP_DISABLE() + by + __HAL_RCC_PPP_CLK_SLEEP_DISABLE()
        • +
      +
    • IS_RCC_PLLSAIN_VALUE() + macro: update the check + condition
      • +
    • Add + description of RCC known Limitations
      • +
    • Rename HAL_RCC_CCSCallback() + by HAL_RCC_CSSCallback()
      • +
    • HAL_RCC_OscConfig() fix + issues: 
      • +
        +
      • Remove the + disable of HSE + oscillator when + HSE_BYPASS is used as + system clock source or as + PPL clock source
        • +
      • Add a check + on HSERDY flag + when HSE_BYPASS is + selected as new state + for HSE oscillator.
        • +
      +
    • Rename + __HAL_RCC_I2SCLK() + by __HAL_RCC_I2S_Config()
      • +
    +
+

�  + + + + + HAL I2S update

+
    +
      +
    • HAL_I2S_Init(): add check + on I2S instance + using CMSIS macro IS_I2S_ALL_INSTANCE() 
      • +
    • HAL_I2S_IRQHandler() + update for compliancy w/ C++
      • +
    • Add use + of tmpreg + variable in __HAL_I2S_CLEAR_OVRFLAG() + and __HAL_I2S_CLEAR_UDRFLAG() + macro for compliancy with C++
      • +
    • HAL_I2S_GetError(): update to + return uint32_t instead of + HAL_I2S_ErrorTypeDef + enumeration
      • +
    +
+

�  + + + + + HAL I2C update

+
    +
      +
    • Update to + + + + + clear the POS bit in the + CR1 register at the end + of HAL_I2C_Master_Read_IT() + and HAL_I2C_Mem_Read_IT() + process
      • +
    • Rename + HAL_I2CEx_DigitalFilter_Config()  + + + + by + HAL_I2CEx_ConfigDigitalFilter() +
      • +
    • Rename + HAL_I2CEx_AnalogFilter_Config()  + + + + by + HAL_I2CEx_ConfigAnalogFilter() +
      • +
    • Add use + of tmpreg + variable in __HAL_I2C_CLEAR_ADDRFLAG() + and __HAL_I2C_CLEAR_STOPFLAG() + macro for compliancy with + C++
      • +
    +
  • HAL + + + + IrDA update
    • +
      +
    • DMA transmit + process; the code has been + updated to avoid waiting on TC + flag under DMA ISR, IrDA TC + interrupt is used instead. + Below the update to be done on + user application:
      • +
        +
      • Configure + and enable the USART IRQ in + HAL_IRDA_MspInit() + function
        • +
      • In + stm32f4xx_it.c file, UASRTx_IRQHandler() + function: add a call to HAL_IRDA_IRQHandler() + + + + function
        • +
      +
    • IT transmit + process; the code has been + updated to avoid waiting on TC + flag under IRDA ISR, IrDA TC + interrupt is used instead. No + impact on user application
      • +
    • Rename + Macros: add prefix "__HAL"
      • +
        +
      • __IRDA_ENABLE() + by __HAL_IRDA_ENABLE()
        • +
      • __IRDA_DISABLE() + by __HAL_IRDA_DISABLE()
        • +
      +
    • Add new user + macros to manage the sample + method feature
      • +
        +
      • __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE()
        • +
      • __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE()
        • +
      +
    • HAL_IRDA_Transmit_IT(): update to + remove the enable of the + parity error interrupt
      • +
    • Add use + of tmpreg + variable in __HAL_IRDA_CLEAR_PEFLAG() + macro for compliancy with + C++
      • +
    • HAL_IRDA_Transmit_DMA() update to + follow the + right procedure + "Transmission using DMA"  + in the reference manual
      • +
        +
      • Add clear + the TC flag in the SR + register before enabling the + DMA transmit + request
        • +
      +
    +
  • HAL + + + + IWDG update
    • +
      +
    • Rename the + defined IWDG keys: 
      • +
        +
      • KR_KEY_RELOAD + + + + by IWDG_KEY_RELOAD
        • +
      • KR_KEY_ENABLE + + + + by IWDG_KEY_ENABLE
        • +
      • KR_KEY_EWA + by + IWDG_KEY_WRITE_ACCESS_ENABLE
        • +
      • KR_KEY_DWA + by + IWDG_KEY_WRITE_ACCESS_DISABLE
        • +
      +
    •  Add new + macros + __HAL_IWDG_RESET_HANDLE_STATE() + and + __HAL_IWDG_CLEAR_FLAG() 
      • +
    • Update + __HAL_IWDG_ENABLE_WRITE_ACCESS() + and + __HAL_IWDG_DISABLE_WRITE_ACCESS() + as private macro
      • +
    +
+

�  + + + + + HAL SPI update

+
    +
      +
    • HAL_SPI_TransmitReceive_DMA() update to + remove the  DMA Tx Error + Callback initialization when + SPI RxOnly + mode is selected
      • +
    • Add use of UNUSED(tmpreg) + in __HAL_SPI_CLEAR_MODFFLAG(), + __HAL_SPI_CLEAR_OVRFLAG(), + __HAL_SPI_CLEAR_FREFLAG() to + fix "Unused variable" warning + with TrueSTUDIO.
      • +
    • Rename + Literals: remove "D" from + "DISABLED" and "ENABLED"
      • +
        +
      • SPI_TIMODE_DISABLED by + + + + + SPI_TIMODE_DISABLE
        • +
      • SPI_TIMODE_ENABLED by SPI_TIMODE_ENABLE
        • +
      • SPI_CRCCALCULATION_DISABLED + by + + + + +  SPI_CRCCALCULATION_DISABLE
        • +
      • SPI_CRCCALCULATION_ENABLED + by + + + + +  SPI_CRCCALCULATION_ENABLE
        • +
      +
    • Add use + of tmpreg + variable in __HAL_SPI_CLEAR_MODFFLAG(), + + + + + __HAL_SPI_CLEAR_FREFLAG() and + __HAL_SPI_CLEAR_OVRFLAG() + macros for compliancy + with C++
      • +
    +
+

�  + + + + + HAL SDMMC update

+
    +
      +
    • IS_SDIO_ALL_INSTANCE() +  macro moved to CMSIS + files
      • +
    +
  • HAL + + + + LTDC update
    • +
      +
    • HAL_LTDC_ConfigCLUT: optimize + the function when pixel format +is LTDC_PIXEL_FORMAT_AL44 
      • +
        +
      • Update the + size of color look up table + to 16 instead of 256 when + the pixel format + is LTDC_PIXEL_FORMAT_AL44 +
        • +
      +
    +
  • HAL + + + + NAND update
    • +
      +
    • Rename NAND + Address structure to NAND_AddressTypeDef + instead of NAND_AddressTypedef
      • +
    • Update the + used algorithm of these functions
      • +
        +
      • HAL_NAND_Read_Page()
        • +
      • HAL_NAND_Write_Page()
        • +
      • HAL_NAND_Read_SpareArea()
        • +
      • HAL_NAND_Write_SpareArea()
        • +
      +
    • HAL_NAND_Write_Page(): move + initialization of tickstart + before while loop
      • +
    • HAL_NAND_Erase_Block(): add whait + until NAND status is ready + before exiting this function
      • +
    +
  • HAL + + + + NOR update
    • +
      +
    • Rename NOR + Address structure to NOR_AddressTypeDef + instead of NOR_AddressTypedef
      • +
    • NOR Status + literals renamed
      • +
        +
      • NOR_SUCCESS + by HAL_NOR_STATUS_SUCCESS
        • +
      • NOR_ONGOING + by HAL_NOR_STATUS_ONGOING
        • +
      • NOR_ERROR + by HAL_NOR_STATUS_ERROR
        • +
      • NOR_TIMEOUT + by HAL_NOR_STATUS_TIMEOUT
        • +
      +
    • HAL_NOR_GetStatus() update to + fix Timeout issue + and exit from waiting + loop when timeout occurred
      • +
    +
  • HAL + + + + PCCARD update
    • +
      +
    • Rename PCCARD + Address structure to HAL_PCCARD_StatusTypeDef + instead of CF_StatusTypedef
      • +
    • PCCARD Status + literals renamed
      • +
        +
      • CF_SUCCESS + by HAL_PCCARD_STATUS_SUCCESS
        • +
      • CF_ONGOING + by HAL_PCCARD_STATUS_ONGOING
        • +
      • CF_ERROR + by HAL_PCCARD_STATUS_ERROR
        • +
      • CF_TIMEOUT + by HAL_PCCARD_STATUS_TIMEOUT
        • +
      +
    • Update "CF" + by "PCCARD" in functions, + literals + and macros
      • +
    +
  • HAL + + + + PCD update
    • +
      +
    • Rename functions
      • +
        +
      • HAL_PCD_ActiveRemoteWakeup() by HAL_PCD_ActivateRemoteWakeup()
        • +
      • HAL_PCD_DeActiveRemoteWakeup() by HAL_PCD_DeActivateRemoteWakeup()
        • +
      +
    • Rename literals
      • +
        +
      • USB_FS_EXTI_TRIGGER_RISING_EDGE + + + + + by + USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
        • +
      • USB_FS_EXTI_TRIGGER_FALLING_EDGE + + + + + by + USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
        • +
      • USB_FS_EXTI_TRIGGER_BOTH_EDGE() + by + USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
        • +
      • USB_HS_EXTI_TRIGGER_RISING_EDGE + + + + + by + USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 
        • +
      • USB_HS_EXTI_TRIGGER_FALLING_EDGE + + + + + by + USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
        • +
      • USB_HS_EXTI_TRIGGER_BOTH_EDGE + + + + + by + USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
        • +
      • USB_HS_EXTI_LINE_WAKEUP + + + + + by + USB_OTG_HS_EXTI_LINE_WAKEUP
        • +
      • USB_FS_EXTI_LINE_WAKEUP + + + + + by + USB_OTG_FS_EXTI_LINE_WAKEUP
        • +
      +
    • Rename USB + EXTI macros (FS, HS + + + + referenced as SUBBLOCK + here below)
      • +
        +
      • __HAL_USB_SUBBLOCK_EXTI_ENABLE_IT() +  by  + __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_IT()  
        • +
      • __HAL_USB_SUBBLOCK_EXTI_DISABLE_IT() + by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_DISABLE_IT()
        • +
      • __HAL_USB_SUBBLOCK_EXTI_GET_FLAG() + by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GET_FLAG() 
        • +
      • __HAL_USB_SUBBLOCK_EXTI_CLEAR_FLAG() + by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_CLEAR_FLAG()
        • +
      • __HAL_USB_SUBBLOCK_EXTI_SET_RISING_EGDE_TRIGGER() + by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_EDGE()
        • +
      • __HAL_USB_SUBBLOCK_EXTI_SET_FALLING_EGDE_TRIGGER() + by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
        • +
      • __HAL_USB_SUBBLOCK_EXTI_SET_FALLINGRISING_TRIGGER() + by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
        • +
      • __HAL_USB_SUBBLOCK_EXTI_GENERATE_SWIT()  + + + + + by __HAL_USB_OTG_SUBBLOCK_WAKEUP_EXTI_GENERATE_SWIT()                                       + + + + +
        • +
      +
    +
+
    +
  • HAL + + + + RNG update
    • +
      +
    • Add new functions
      • +
        +
      • HAL_RNG_GenerateRandomNumber(): to + generate a 32-bits random + number, + return + random value in argument and + return HAL status.
        • +
      • HAL_RNG_GenerateRandomNumber_IT(): to +  start generation of + the 32-bits random + number, user should call + the HAL_RNG_ReadLastRandomNumber() + + + + + function under the HAL_RNG_ReadyCallback() + + + + to get the generated random + value.
        • +
      • HAL_RNG_ReadLastRandomNumber(): to + return the last random value + stored in the RNG handle
        • +
      +
    • HAL_RNG_GetRandomNumber(): return + value update (obsolete), + replaced by HAL_RNG_GenerateRandomNumber()
      • +
    • HAL_RNG_GetRandomNumber_IT(): wrong + implementation (obsolete), + replaced by HAL_RNG_GenerateRandomNumber_IT()
      • +
    • __HAL_RNG_CLEAR_FLAG() + macro (obsolete), replaced by + new __HAL_RNG_CLEAR_IT() macro
      • +
    • Add new + define for RNG ready + interrupt:  RNG_IT_DRDY
      • +
    +
  • HAL + + + + RTC update
    • +
      +
    • HAL_RTC_GetTime() and HAL_RTC_GetDate(): + + + + + add the comment below
      • +
    +
+
+
+

  + + + + + * @note You must call HAL_RTC_GetDate() + after HAL_RTC_GetTime() + + + + + to unlock the values
+   + + + + + * in the higher-order + calendar shadow registers to + ensure consistency between + the time and date values.
+   + + + + + * Reading RTC current time + locks the values in calendar + shadow registers until + Current date is read. 

+
+
+
    +
      +
    • Rename + literals: add prefix "__HAL"
      • +
        +
      • FORMAT_BIN by HAL_FORMAT_BIN
        • +
      • FORMAT_BCD + by HAL_FORMAT_BCD
        • +
      +
    • Rename macros + (ALARM, WAKEUPTIMER and + TIMESTAMP referenced + as SUBBLOCK here + below)
      • +
        +
      • __HAL_RTC_EXTI_ENABLE_IT() + by  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_IT()
        • +
      • __HAL_RTC_EXTI_DISABLE_IT() + by  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_IT()
        • +
      • __HAL_RTC_EXTI_CLEAR_FLAG() + by  __HAL_RTC_SUBBLOCK_EXTI_CLEAR_FLAG()
        • +
      • __HAL_RTC_EXTI_GENERATE_SWIT() + by __HAL_RTC_SUBBLOCK_EXTI_GENERATE_SWIT()
        • +
      +
    • Add new + macros (ALARM, + WAKEUPTIMER and TAMPER_TIMESTAMP + + + + referenced as SUBBLOCK + here below)
      • +
        +
      • __HAL_RTC_SUBBLOCK_GET_IT_SOURCE() 
        • +
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_EVENT()
        • +
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_EVENT()
        • +
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_FALLING_EDGE()
        • +
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_FALLING_EDGE()
        • +
      • __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_EDGE()
        • +
      • __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_EDGE()
        • +
      •  __HAL_RTC_SUBBLOCK_EXTI_ENABLE_RISING_FALLING_EDGE()
        • +
      •  __HAL_RTC_SUBBLOCK_EXTI_DISABLE_RISING_FALLING_EDGE()
        • +
      •  __HAL_RTC_SUBBLOCK_EXTI_GET_FLAG()
        • +
      +
    +
  • HAL + + + + SAI update
    • +
      +
    • Update + SAI_STREOMODE by SAI_STEREOMODE
      • +
    • Update FIFO + status Level defines in upper + case
      • +
    • Rename + literals: remove "D" from + "DISABLED" and "ENABLED"
      • +
        +
      • SAI_OUTPUTDRIVE_DISABLED + + + + +  by + SAI_OUTPUTDRIVE_DISABLE
        • +
      • SAI_OUTPUTDRIVE_ENABLED + + + + +  by + SAI_OUTPUTDRIVE_ENABLE
        • +
      • SAI_MASTERDIVIDER_ENABLED  by + SAI_MASTERDIVIDER_ENABLE
        • +
      • SAI_MASTERDIVIDER_DISABLED  by + SAI_MASTERDIVIDER_DISABLE
        • +
      +
    +
+
    +
  • HAL + + + + SD update
    • +
      +
    • Rename + SD_CMD_SD_APP_STAUS by SD_CMD_SD_APP_STATUS
      • +
    • SD_PowerON() updated to + add 1ms required power up + waiting time before starting + the SD initialization sequence
      • +
    • SD_DMA_RxCplt()/SD_DMA_TxCplt(): + + + + + add a call to + HAL_DMA_Abort()
      • +
    • HAL_SD_ReadBlocks() update to + set the defined + DATA_BLOCK_SIZE as SDIO DataBlockSize + parameter
      • +
    • HAL_SD_ReadBlocks_DMA()/HAL_SD_WriteBlocks_DMA() + update to call the HAL_DMA_Start_IT() + + + + function with DMA Datalength + set to BlockSize/4  + + + + + as the DMA is + configured in word 
      • +
    +
  • HAL + + + + SMARTCARD update 
    • +
      +
    • DMA transmit + process; the code has been + updated to avoid waiting on TC + flag under DMA ISR, SMARTCARD + TC interrupt is used instead. + Below the update to be done on + user application:
      • +
        +
      • Configure + and enable the USART IRQ in + HAL_SAMRTCARD_MspInit() + function
        • +
      • In + stm32f4xx_it.c file, UASRTx_IRQHandler() + function: add a call to HAL_SMARTCARD_IRQHandler() + + + + + function
        • +
      +
    • IT transmit + process; the code has been + updated to avoid waiting on TC + flag under SMARTCARD + ISR, SMARTCARD TC + interrupt is used instead. No + impact on user application
      • +
    • Rename + macros: add prefix "__HAL"
      • +
        +
      • __SMARTCARD_ENABLE() + by __HAL_SMARTCARD_ENABLE()
        • +
      • __SMARTCARD_DISABLE() + by __HAL_SMARTCARD_DISABLE()
        • +
      • __SMARTCARD_ENABLE_IT() + by + __HAL_SMARTCARD_ENABLE_IT()
        • +
      • __SMARTCARD_DISABLE_IT() + by + __HAL_SMARTCARD_DISABLE_IT()
        • +
      • __SMARTCARD_DMA_REQUEST_ENABLE() + by + __HAL_SMARTCARD_DMA_REQUEST_ENABLE()
        • +
      • __SMARTCARD_DMA_REQUEST_DISABLE() + by + __HAL_SMARTCARD_DMA_REQUEST_DISABLE()
        • +
      +
    • Rename + literals: remove "D" from + "DISABLED" and "ENABLED"
      • +
        +
      • SMARTCARD_NACK_ENABLED by + + + + + SMARTCARD_NACK_ENABLE
        • +
      • SMARTCARD_NACK_DISABLED by SMARTCARD_NACK_DISABLE
        • +
      +
    • Add new user + macros to manage the sample + method feature
      • +
        +
      • __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE()
        • +
      • __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE()
        • +
      +
    • Add use + of tmpreg + variable in + __HAL_SMARTCARD_CLEAR_PEFLAG() + macro for compliancy with + C++
      • +
    • HAL_SMARTCARD_Transmit_DMA() update to + follow the + right procedure + "Transmission using DMA"  + in the reference manual
      • +
        +
      • Add clear + the TC flag in the SR + register before enabling the + DMA transmit + request
        • +
      +
    +
  • HAL + + + + TIM update
    • +
      +
    • Add + TIM_CHANNEL_ALL as possible + value for all Encoder + Start/Stop APIs Description
      • +
    • HAL_TIM_OC_ConfigChannel() remove call + to IS_TIM_FAST_STATE() assert + macro
      • +
    • HAL_TIM_PWM_ConfigChannel() add a call + to IS_TIM_FAST_STATE() assert + macro to check the OCFastMode + parameter
      • +
    • HAL_TIM_DMADelayPulseCplt() Update to + set the TIM Channel before to + call  HAL_TIM_PWM_PulseFinishedCallback()
      • +
    • HAL_TIM_DMACaptureCplt() update to + set the TIM Channel before to + call  HAL_TIM_IC_CaptureCallback()
      • +
    • TIM_ICx_ConfigChannel() update + to fix Timer CCMR1 register + corruption when setting ICFilter + parameter
      • +
    • HAL_TIM_DMABurst_WriteStop()/HAL_TIM_DMABurst_ReadStop() + update to abort the DMA + transfer for the specifc + TIM channel
      • +
    • Add new + function for TIM Slave + configuration in IT mode: + HAL_TIM_SlaveConfigSynchronization_IT() 
      • +
    • HAL_TIMEx_ConfigBreakDeadTime() add an + assert check on Break & DeadTime + parameters values
      • +
    • HAL_TIMEx_OCN_Start_IT() add the + enable of Break Interrupt for + all output modes
      • +
    • Add new + macros to ENABLE/DISABLE URS + bit in TIM CR1 register:
      • +
        +
      • __HAL_TIM_URS_ENABLE()
        • +
      • __HAL_TIM_URS_DISABLE()
        • +
      +
    • Add new macro + for TIM Edge modification: + __HAL_TIM_SET_CAPTUREPOLARITY()
      • +
    +
  • HAL + + + + UART update
    • +
      +
    • Add IS_LIN_WORD_LENGTH() + and + IS_LIN_OVERSAMPLING()  + macros: to check respectively + WordLength + and OverSampling + parameters in LIN mode
      • +
    • DMA transmit + process; the code has been + updated to avoid waiting on TC + flag under DMA ISR, UART TC + interrupt is used instead. + Below the update to be done on + user application:
      • +
        +
      • Configure + and enable the USART IRQ in + HAL_UART_MspInit() + function
        • +
      • In + stm32f4xx_it.c file, USARTx_IRQHandler() + function: add a call to HAL_UART_IRQHandler() + + + + function
        • +
      +
    • IT transmit + process; the code has been + updated to avoid waiting on TC + flag under UART ISR, UART + TC interrupt is used instead. + No impact on user application
      • +
    • Rename + macros:
      • +
        +
      • __HAL_UART_ONEBIT_ENABLE() + by + __HAL_UART_ONE_BIT_SAMPLE_ENABLE()
        • +
      • __HAL_UART_ONEBIT_DISABLE() + by + __HAL_UART_ONE_BIT_SAMPLE_DISABLE()
        • +
      +
    • Rename + literals:
      • +
        +
      • UART_WAKEUPMETHODE_IDLELINE by + + + + + UART_WAKEUPMETHOD_IDLELINE
        • +
      • UART_WAKEUPMETHODE_ADDRESSMARK by +UART_WAKEUPMETHOD_ADDRESSMARK
        • +
      +
    • Add use + of tmpreg + variable in __HAL_UART_CLEAR_PEFLAG() + macro for compliancy with + C++
      • +
    • HAL_UART_Transmit_DMA() update to + follow the right procedure + "Transmission using DMA" in + the reference manual
      • +
        +
      • Add clear + the TC flag in the SR + register before enabling the + DMA transmit + request
        • +
      +
    +
  • HAL + + + + USART update
    • +
      +
    • DMA transmit + process; the code has been + updated to avoid waiting on TC + flag under DMA ISR, USART TC + interrupt is used instead. + Below the update to be done on + user application:
      • +
        +
      • Configure + and enable the USART IRQ in + HAL_USART_MspInit() + function
        • +
      • In + stm32f4xx_it.c file, USARTx_IRQHandler() + function: add a call to HAL_USART_IRQHandler() + + + + + function
        • +
      +
    • IT transmit + process; the code has been + updated to avoid waiting on TC + flag under USART ISR, + USART TC interrupt is used + instead. No impact on user + application
      • +
    • HAL_USART_Init() update + to enable the USART + oversampling by 8 by default + in order to reach max USART + frequencies
      • +
    • USART_DMAReceiveCplt() update + to set the new USART state + after checking on the + old state
      • +
    • HAL_USART_Transmit_DMA()/HAL_USART_TransmitReceive_DMA() + update to + follow the + right procedure + "Transmission using DMA"  + in the reference manual
      • +
        +
      • Add clear + the TC flag in the SR + register before enabling the + DMA transmit + request
        • +
      +
    • Rename + macros:
      • +
        +
      • __USART_ENABLE() + by __HAL_USART_ENABLE()
        • +
      • __USART_DISABLE() + by __HAL_USART_DISABLE()
        • +
      • __USART_ENABLE_IT() + by __HAL_USART_ENABLE_IT()
        • +
      • __USART_DISABLE_IT() + by __HAL_USART_DISABLE_IT()
        • +
      +
    • Rename + literals: remove "D" from + "DISABLED" and "ENABLED"
      • +
        +
      • USART_CLOCK_DISABLED by + + + + + USART_CLOCK_DISABLE
        • +
      • USART_CLOCK_ENABLED by + + + + + USART_CLOCK_ENABLE
        • +
      • USARTNACK_ENABLED + + + + by USART_NACK_ENABLE
        • +
      • USARTNACK_DISABLED + + + + by USART_NACK_DISABLE
        • +
      +
    • Add new user + macros to manage the sample + method feature
      • +
        +
      • __HAL_USART_ONE_BIT_SAMPLE_ENABLE()
        • +
      • __HAL_USART_ONE_BIT_SAMPLE_DISABLE()
        • +
      +
    • Add use + of tmpreg + variable in __HAL_USART_CLEAR_PEFLAG() + macro for compliancy with + C++
      • +
    +
  • HAL + + + + WWDG update
    • +
      +
    • Add new + parameter in + __HAL_WWDG_ENABLE_IT() + macro
      • +
    • Add new + macros to manage WWDG IT & + correction:
      • +
        +
      • __HAL_WWDG_DISABLE()
        • +
      • __HAL_WWDG_DISABLE_IT()
        • +
      • __HAL_WWDG_GET_IT()
        • +
      • __HAL_WWDG_GET_IT_SOURCE()
        • +
      +
    +
+

V1.1.0 + + + + / 19-June-2014

+

Main Changes

+
    +
  • Add + support of STM32F411xE devices
    • +
+
    +
  • HAL + + + + generic + update
    • +
      +
    • Enhance HAL + delay and time base implementation
      • +
        +
      • Systick timer is + used by default as source of + time base, but user can + eventually implement his + proper time base source (a general + + + + purpose + timer for example or other + time source)
        • +
      • Functions + affecting time base + configurations are declared + as __Weak to make override + possible in case of other + implementations in user + file, for more details + please refer to HAL_TimeBase + example
        • +
      +
    • Fix flag + clear procedure: use atomic + write operation "=" instead of + ready-modify-write operation + "|=" or "&="
      • +
    • Fix on + Timeout management, Timeout + value set to 0 passed to API + automatically exits the + function after checking the + flag without any wait
      • +
    • Common update + for the following + communication peripherals: + SPI, UART, USART and IRDA
      • +
        +
      • Add DMA + circular mode support
        • +
      • Remove lock + from recursive process
        • +
      +
    • Add new macro + __HAL_RESET_HANDLE_STATE to + reset a given handle state
      • +
    • Add a new + attribute for functions + executed from internal SRAM + and depending from + Compiler implementation
      • +
    • When USE_RTOS + == 1 (in + stm32l0xx_hal_conf.h), the + __HAL_LOCK() + is not defined instead of + being defined empty
      • +
    • Miscellaneous + comments and formatting update
      • +
    • stm32f4xx_hal_conf_template.h
      • +
        +
      • Add a new + define for LSI default value + LSI_VALUE
        • +
      • Add a new + define for LSE default value + LSE_VALUE
        • +
      • Add a new + define for Tick interrupt + priority TICK_INT_PRIORITY + (needed for the enhanced + time base implementation)
        • +
      +
    • Important + + + + + Note: + aliases has been added for any + API naming change, to keep + compatibility with previous version
      • +
    +
  • HAL + + + + GPIO update
    • +
+
    +
      +
    • Add a new + macro __HAL_GPIO_EXTI_GENERATE_SWIT() + to manage the generation of + software interrupt on selected + EXTI line
      • +
    • HAL_GPIO_Init(): use + temporary variable when + modifying the registers, to + avoid unexpected transition in + the GPIO pin configuration
      • +
    • Remove + IS_GET_GPIO_PIN macro
      • +
    • Add a new + function HAL_GPIO_LockPin()
      • +
    • Private Macro + __HAL_GET_GPIO_SOURCE renamed + into GET_GPIO_SOURCE
      • +
    • Add the + support of STM32F411xx devices + + + + + : add the + new Alternate functions values + related to new remap added for + SPI, USART, I2C
      • +
    • Update the + following HAL GPIO macros + description: rename EXTI_Linex + by GPIO_PIN_x
      • +
        +
      • __HAL_GPIO_EXTI_CLEAR_IT()
        • +
      • __HAL_GPIO_EXTI_GET_IT()
        • +
      • __HAL_GPIO_EXTI_CLEAR_FLAG()
        • +
      • __HAL_GPIO_EXTI_GET_FLAG()
        • +
      +
    +
+

�  + + + + + HAL DMA update

+
    +
      +
    • Fix in HAL_DMA_PollForTransfer() + to:
      • +
        +
      • set DMA + error code in case of + HAL_ERROR status
        • +
      • set HAL + Unlock before DMA state update
        • +
      +
    +
+

�  + + + + + HAL DMA2D + update

+
    +
      +
    • Add + configuration of source + address in case of A8 or A4 + M2M_PFC DMA2D mode
      • +
    +
  • HAL + + + + FLASH update
    • +
+
    +
      +
    • Functions + reorganization update, + depending on the features + supported by each STM32F4 device
      • +
    • Add new + driver + (stm32f4xx_hal_flash_ramfunc.h/.c) + to manage function executed + from RAM, these functions are + available only for STM32F411xx + Devices
      • +
        +
      • FLASH_StopFlashInterfaceClk()  : + Stop the flash interface + while System Run
        • +
      • FLASH_StartFlashInterfaceClk() : Stop the + flash interface while System + Run
        • +
      • FLASH_EnableFlashSleepMode() : Enable + the flash sleep while System + Run
        • +
      • FLASH_DisableFlashSleepMode() :  + Disable the flash sleep + while System Run
        • +
      +
    +
+
    +
  • HAL + + + + PWR update
    • +
+
    +
      +
    • HAL_PWR_PVDConfig(): add clear + of the EXTI trigger before new + configuration
      • +
    • Fix in HAL_PWR_EnterSTANDBYMode() + to not clear Wakeup flag + (WUF), which need to be + cleared at application level + before to call this function
      • +
    • HAL_PWR_EnterSLEEPMode()
      • +
        +
      • Remove + disable and enable of SysTick + Timer
        • +
      • Update + usage of __WFE() + in low power entry function: + if there is a pending event, + calling __WFE() will not + enter the CortexM4 core to + sleep mode. The solution is + to made the call below; the + first __WFE() + is always ignored and clears + the event if one was already + pending, the second is + always applied
        • +
      +
    +
+
+

__SEV()
+ __WFE()
+ __WFE()

+
+
    +
      +
    • Add new macro + for software event generation + __HAL_PVD_EXTI_GENERATE_SWIT()
      • +
    • Remove the + following defines form Generic + driver and add them under + extension driver because they + are only used within extension + functions.
      • +
        +
      • CR_FPDS_BB: + used within HAL_PWREx_EnableFlashPowerDown() + function
        • +
      • CSR_BRE_BB: + used within HAL_PWREx_EnableBkUpReg() + function
        • +
      +
    • Add the + support of STM32F411xx devices + add the define STM32F411xE
      • +
        +
      • For + STM32F401xC, STM32F401xE and + STM32F411xE devices add the + following functions used to + enable or disable the low + voltage mode for regulators
        • +
      +
    +
+
    +
      +
        +
          +
        • HAL_PWREx_EnableMainRegulatorLowVoltage()
          • +
        • HAL_PWREx_DisableMainRegulatorLowVoltage()
          • +
        • HAL_PWREx_EnableLowRegulatorLowVoltage()
          • +
        • HAL_PWREx_DisableLowRegulatorLowVoltage()
          • +
        +
      +
    • For + STM32F42xxx/43xxx devices, add + a new function for Under + Driver management as the macro + already added for this mode is + not sufficient: HAL_PWREx_EnterUnderDriveSTOPMode()
      • +
    +
+
    +
  • HAL + + + + RCC update
    • +
      +
    • In HAL_RCC_ClockConfig() + function: update the AHB clock + divider before clock switch to + new source
      • +
    • Allow to + calibrate the HSI when it is + used as system clock source
      • +
    • Rename the + following macros
      • +
        +
      • __OTGFS_FORCE_RESET + + + + ()  by + __USB_OTG_FS_FORCE_RESET()
        • +
      • __OTGFS_RELEASE_RESET + + + + ()  by  +__USB_OTG_FS_RELEASE_RESET()
        • +
      • __OTGFS_CLK_SLEEP_ENABLE + + + + + ()  by  +__USB_OTG_FS_CLK_SLEEP_ENABLE()
        • +
      • __OTGFS_CLK_SLEEP_DISABLE + + + + + () by  __USB_OTG_FS_CLK_SLEEP_DISABLE()
        • +
      +
    +
+

 

+
    +
      +
    • Add new field + PLLI2SM in + RCC_PLLI2SInitTypeDef + structure, this division + factor is added for PLLI2S VCO + input clock only STM32F411xE + devices => the FW + compatibility is broken vs. + STM32F401xx devices
      • +
    • Update HAL_RCCEx_PeriphCLKConfig() + and  HAL_RCCEx_GetPeriphCLKConfig()  + + + + + functions to support the new + PLLI2SM
      • +
    • Add new + function to manage the new LSE + mode + + + + + : HAL_RCCEx_SelectLSEMode()
      • +
    • Reorganize + the macros depending from + Part number used and make them + more clear
      • +
    +
+

�  HAL + + + + UART update

+
    +
      +
    • Add new + macros to control CTS and RTS
      • +
    • Add specific + macros to manage the flags + cleared only by a software sequence
      • +
        +
      • __HAL_UART_CLEAR_PEFLAG()
        • +
      • __HAL_UART_CLEAR_FEFLAG()
        • +
      • __HAL_UART_CLEAR_NEFLAG()
        • +
      • __HAL_UART_CLEAR_OREFLAG()
        • +
      • __HAL_UART_CLEAR_IDLEFLAG()
        • +
      +
    • Add several + enhancements without affecting + the driver functionalities +
      • +
        +
      • Remove the + check on RXNE set after + reading the Data in the DR + register
        • +
      • Update the + transmit processes to use + TXE instead of TC
        • +
      • Update HAL_UART_Transmit_IT() + to enable UART_IT_TXE + instead of UART_IT_TC
        • +
      +
    +
+

�  + + + + + HAL USART + update

+
    +
      +
    • Add specific + macros to manage the flags + cleared only by a software sequence
      • +
        +
      • __HAL_USART_CLEAR_PEFLAG()
        • +
      • __HAL_USART_CLEAR_FEFLAG()
        • +
      • __HAL_USART_CLEAR_NEFLAG()
        • +
      • __HAL_USART_CLEAR_OREFLAG()
        • +
      • __HAL_USART_CLEAR_IDLEFLAG()
        • +
      +
    • Update HAL_USART_Transmit_IT() + to enable USART_IT_TXE + instead of USART_IT_TC
      • +
    +
+

�  + + + + + HAL IRDA update

+
    +
      +
    • Add specific + macros to manage the flags + cleared only by a software sequence
      • +
        +
      • __HAL_IRDA_CLEAR_PEFLAG()
        • +
      • __HAL_ + IRDA _CLEAR_FEFLAG()
        • +
      • __HAL_ + IRDA _CLEAR_NEFLAG()
        • +
      • __HAL_ + IRDA _CLEAR_OREFLAG()
        • +
      • __HAL_ + IRDA _CLEAR_IDLEFLAG()
        • +
      +
    • Add several + enhancements without affecting + the driver functionalities
      • +
    +
+
    +
      +
        +
      • Remove the + check on RXNE set after + reading the Data in the DR + register
        • +
      • Update HAL_IRDA_Transmit_IT() + to enable IRDA_IT_TXE + instead of IRDA_IT_TC
        • +
      +
    • Add the + following APIs used within DMA + process +
      • +
        +
      • HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef + *hirda);
        • +
      • HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef + *hirda);
        • +
      • HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef + *hirda); +
        • +
      • void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef + *hirda);
        • +
      • void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef + *hirda);
        • +
      +
    +
+

�  + + + + + HAL SMARTCARD + update

+
    +
      +
    • Add specific + macros to manage the flags + cleared only by a software sequence
      • +
        +
      • __HAL_SMARTCARD_CLEAR_PEFLAG()
        • +
      • __HAL_SMARTCARD_CLEAR_FEFLAG()
        • +
      • __HAL_SMARTCARD_CLEAR_NEFLAG()
        • +
      • __HAL_SMARTCARD_CLEAR_OREFLAG()
        • +
      • __HAL_SMARTCARD_CLEAR_IDLEFLAG()
        • +
      +
    • Add several + enhancements without affecting + the driver functionalities
      • +
        +
      • Add a new + state HAL_SMARTCARD_STATE_BUSY_TX_RX + and all processes has been + updated accordingly
        • +
      • Update HAL_SMARTCARD_Transmit_IT() + to enable SMARTCARD_IT_TXE + instead of SMARTCARD_IT_TC
        • +
      +
    +
+
    +
  • HAL + + + + SPI update
    • +
      +
    • Bugs fix
      • +
        +
      • SPI + interface is used in + synchronous polling mode: at + high clock rates like SPI prescaler + 2 and 4, calling
        + HAL_SPI_TransmitReceive() + returns with error + HAL_TIMEOUT         +
        • +
      • HAL_SPI_TransmitReceive_DMA() does not + clean up the TX DMA, so any + subsequent SPI calls return + the DMA error
        • +
      • HAL_SPI_Transmit_DMA() is failing + when data size is equal to 1 + byte +
        • +
      +
    • Add the + following APIs used within the + DMA process
      • +
    +
+
    +
      +
        +
      • HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef + *hspi);
        • +
      • HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef + *hspi);
        • +
      • HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef + *hspi);
        • +
      • void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef + *hspi);
        • +
      • void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef + *hspi);
        • +
      • void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef + *hspi);
        • +
      +
    +
+
    +
  • HAL + + + + RNG update
    • +
      +
        +
      • Add a + conditional define to make + this driver visible for all + STM32F4xx devices except + STM32F401xx and STM32F411xx + Devices.
        • +
      +
    +
  • HAL + + + + CRC update
    • +
      +
        +
      • These + macros are added to + read/write the CRC IDR + register: __HAL_CRC_SET_IDR() + and __HAL_CRC_GET_IDR()
        • +
      +
    +
+
    +
  • HAL + + + + DAC update
    • +
      +
    • Enhance the + DMA channel configuration when + used with DAC
      • +
    +
  • HAL + + + + TIM update
    • +
      +
    • HAL_TIM_IRQHandler(): update to + check the input capture + channel 3 and 4 in CCMR2 + instead of CCMR1
      • +
    • __HAL_TIM_PRESCALER() + updated to use '=' instead of + '|='
      • +
    • Add the + following macro in TIM HAL + driver
      • +
        +
      • __HAL_TIM_GetCompare() +
        • +
      • __HAL_TIM_GetCounter() +
        • +
      • __HAL_TIM_GetAutoreload() +
        • +
      • __HAL_TIM_GetClockDivision() +
        • +
      • __HAL_TIM_GetICPrescaler()
        • +
      +
    +
  • HAL + + + + SDMMC update
    • +
+
    +
      +
    • Use of CMSIS + constants instead of magic values
      • +
    • Miscellaneous + update in functions internal + coding
      • +
    +
  • HAL + + + + NAND update
    • +
      +
    • Fix + + + + issue of macros returning + wrong address for NAND blocks
      • +
    • Fix + + + + issue for read/write NAND + page/spare area
      • +
    +
  • HAL + + + + NOR update
    • +
      +
    • Add + + + + the NOR address bank macro + used within the API
      • +
    • Update + + + + NOR API implementation to + avoid the use of NOR address + bank hard coded
      • +
    +
  • HAL + + + + HCD update
    • +
      +
    • HCD_StateTypeDef structure + members renamed
      • +
    • These macro are renamed
      • +
        +
      • __HAL_GET_FLAG(__HANDLE__, + + + + + __INTERRUPT__)    + + + + by + __HAL_HCD_GET_FLAG(__HANDLE__, + __INTERRUPT__)
        • +
      • __HAL_CLEAR_FLAG(__HANDLE__, + + + + + __INTERRUPT__) by + __HAL_HCD_CLEAR_FLAG(__HANDLE__, + __INTERRUPT__) 
        • +
      • __HAL_IS_INVALID_INTERRUPT(__HANDLE__)  + + + + + by + __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)  +
        • +
      +
    +
  • HAL + + + + PCD update
    • +
      +
    • HAL_PCD_SetTxFiFo() and HAL_PCD_SetRxFiFo() + + + + + renamed into HAL_PCDEx_SetTxFiFo() + + + + + and HAL_PCDEx_SetRxFiFo() + + + + + and moved to the extension + files + stm32f4xx_hal_pcd_ex.h/.c
      • +
    • PCD_StateTypeDef structure + members renamed
      • +
    • Fix incorrect + masking of TxFIFOEmpty
      • +
    • stm32f4xx_ll_usb.c: + + + + fix issue in HS mode
      • +
    • New macros added
      • +
        +
      • __HAL_PCD_IS_PHY_SUSPENDED()
        • +
      • __HAL_USB_HS_EXTI_GENERATE_SWIT()
        • +
      • __HAL_USB_FS_EXTI_GENERATE_SWIT()
        • +
      +
    • These macro are renamed
      • +
        +
      • __HAL_GET_FLAG(__HANDLE__, + + + + + __INTERRUPT__)    + + + + by + __HAL_PCD_GET_FLAG(__HANDLE__, + __INTERRUPT__)
        • +
      • __HAL_CLEAR_FLAG(__HANDLE__, + + + + + __INTERRUPT__) by + __HAL_PCD_CLEAR_FLAG(__HANDLE__, + __INTERRUPT__) 
        • +
      • __HAL_IS_INVALID_INTERRUPT(__HANDLE__)  + + + + + by + __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)  +
        • +
      • __HAL_PCD_UNGATE_CLOCK(__HANDLE__) + + + + + by + __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)
        • +
      • __HAL_PCD_GATE_CLOCK(__HANDLE__) + + + + + by + __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)
        • +
      +
    +
  • HAL + + + + ETH update
    • +
      +
    • Update HAL_ETH_GetReceivedFrame_IT() + function to return HAL_ERROR + if the received packet is not + complete
      • +
    • Use HAL_Delay() + instead of counting loop
      • +
    •  __HAL_ETH_MAC_CLEAR_FLAG() + macro is removed: the MACSR + register is read only
      • +
    • Add the + following macros used to Wake + up the device from STOP mode + by Ethernet event + + + + :
      • +
        +
      • __HAL_ETH_EXTI_ENABLE_IT()
        • +
      • __HAL_ETH_EXTI_DISABLE_IT()
        • +
      • __HAL_ETH_EXTI_GET_FLAG()
        • +
      • __HAL_ETH_EXTI_CLEAR_FLAG()
        • +
      • __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER()
        • +
      • __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER()
        • +
      • __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER()
        • +
      +
    +
  • HAL + + + + WWDG update
    • +
      +
    • Update macro + parameters to use underscore: + __XXX__
      • +
    • Use of CMSIS + constants instead of magic values
      • +
    • Use + MODIFY_REG macro in HAL_WWDG_Init()
      • +
    • Add + IS_WWDG_ALL_INSTANCE in HAL_WWDG_Init() + and HAL_WWDG_DeInit()
      • +
    +
  • HAL + + + + IWDG update
    • +
      +
    • Use WRITE_REG + instead of SET_BIT for all + IWDG macros
      • +
    • __HAL_IWDG_CLEAR_FLAG + + + + + removed: no IWDG flag cleared + by access to SR register
      • +
    • Use + MODIFY_REG macro in HAL_IWDG_Init()
      • +
    • Add + IS_IWDG_ALL_INSTANCE in HAL_IWDG_Init()Add + + + + + the following macros used to + Wake
      • +
    +
+

V1.0.0 + + + + / 18-February-2014

+

Main Changes

+
    +
  • First + + + + official release
    • +
+

License

+

Redistribution + + + + + and use in source and binary + forms, with or without + modification, are permitted + provided that the following + conditions are met:

+
    +
  1. Redistributions + + + + of source code must retain the + above copyright notice, this + list of conditions and the + following disclaimer.
    2. +
  2. Redistributions + + + + in binary form must reproduce + the above copyright notice, this + list of conditions and the + following disclaimer in the + documentation and/or other + materials provided with the + distribution.
    3. +
  3. Neither + + + + the name of STMicroelectronics + nor the names of its + contributors may be used to + endorse or promote products + derived
    4. +
+

       + + + + + from this software without + specific prior written permission.
+
+ THIS + + + + + SOFTWARE IS PROVIDED BY THE + COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES + OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE + COPYRIGHT HOLDER OR CONTRIBUTORS + BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, + EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS + OF USE, DATA, OR PROFITS; OR + BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR + OTHERWISE) ARISING IN ANY WAY OUT + OF THE USE OF THIS SOFTWARE, EVEN + IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE.

+
+
+

For + + + + + complete documentation on STM32 + Microcontrollers visit www.st.com/STM32

+
+

 

+
+
+

+
+
+

 

+
+
+ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c index c8c7764e19..fc6c475ff3 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -50,11 +50,11 @@ * @{ */ /** - * @brief STM32F4xx HAL Driver version number V1.7.12 + * @brief STM32F4xx HAL Driver version number V1.7.13 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x0CU) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x0DU) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c index 945b11fa0f..af8ed59eb8 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c @@ -163,11 +163,11 @@ The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_ADC_RegisterCallback() + Use Functions HAL_ADC_RegisterCallback() to register an interrupt callback. [..] - Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: + Function HAL_ADC_RegisterCallback() allows to register following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback @@ -183,11 +183,11 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default + Use function HAL_ADC_UnRegisterCallback to reset a callback to the default weak function. [..] - @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ConvCpltCallback : ADC conversion complete callback @@ -203,27 +203,27 @@ (+) MspDeInitCallback : ADC Msp DeInit callback [..] - By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET + By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). + examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when + reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() + If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, + in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() - or @ref HAL_ADC_Init() function. + using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() + or HAL_ADC_Init() function. [..] When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or @@ -1752,7 +1752,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Enable the Temperature sensor and VREFINT channel*/ tmpADC_Common->CCR |= ADC_CCR_TSVREFE; - if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) + if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c index 86f6c7ceb0..3e03475802 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c @@ -131,9 +131,9 @@ The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_CAN_RegisterCallback() to register an interrupt callback. + Use Function HAL_CAN_RegisterCallback() to register an interrupt callback. - Function @ref HAL_CAN_RegisterCallback() allows to register following callbacks: + Function HAL_CAN_RegisterCallback() allows to register following callbacks: (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. @@ -152,9 +152,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_CAN_UnRegisterCallback() to reset a callback to the default + Use function HAL_CAN_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. @@ -173,13 +173,13 @@ (+) MspInitCallback : CAN MspInit. (+) MspDeInitCallback : CAN MspDeInit. - By default, after the @ref HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, + By default, after the HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, all callbacks are set to the corresponding weak functions: - example @ref HAL_CAN_ErrorCallback(). + example HAL_CAN_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() only when + reset to the legacy weak function in the HAL_CAN_Init()/ HAL_CAN_DeInit() only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() + if not, MspInit or MspDeInit are not null, the HAL_CAN_Init()/ HAL_CAN_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only. @@ -187,8 +187,8 @@ in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_CAN_RegisterCallback() before calling @ref HAL_CAN_DeInit() - or @ref HAL_CAN_Init() function. + using HAL_CAN_RegisterCallback() before calling HAL_CAN_DeInit() + or HAL_CAN_Init() function. When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -330,14 +330,14 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) } #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ - /* Exit from sleep mode */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); /* Get tick */ tickstart = HAL_GetTick(); - /* Check Sleep mode leave acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { @@ -351,14 +351,14 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) } } - /* Request initialisation */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); /* Get tick */ tickstart = HAL_GetTick(); - /* Wait initialisation acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { @@ -537,19 +537,19 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) * the configuration information for CAN module * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID - * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID - * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID - * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID - * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID - * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function @@ -680,19 +680,19 @@ HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Call * the configuration information for CAN module * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: - * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID - * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID - * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID - * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID - * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID - * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c index 7420907a69..c599bcfc4a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c @@ -47,10 +47,10 @@ The compilation define USE_HAL_CEC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback() + Use Functions HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback() to register an interrupt callback. - Function @ref HAL_CEC_RegisterCallback() allows to register following callbacks: + Function HAL_CEC_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : Tx Transfer completed callback. (+) ErrorCallback : callback for error detection. (+) MspInitCallback : CEC MspInit. @@ -59,11 +59,11 @@ and a pointer to the user callback function. For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks - @ref HAL_CEC_RegisterRxCpltCallback(). + HAL_CEC_RegisterRxCpltCallback(). - Use function @ref HAL_CEC_UnRegisterCallback() to reset a callback to the default + Use function HAL_CEC_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : Tx Transfer completed callback. @@ -72,15 +72,15 @@ (+) MspDeInitCallback : CEC MspDeInit. For callback HAL_CEC_RxCpltCallback use dedicated unregister callback : - @ref HAL_CEC_UnRegisterRxCpltCallback(). + HAL_CEC_UnRegisterRxCpltCallback(). - By default, after the @ref HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET + By default, after the HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET all callbacks are set to the corresponding weak functions : - examples @ref HAL_CEC_TxCpltCallback() , @ref HAL_CEC_RxCpltCallback(). + examples HAL_CEC_TxCpltCallback() , HAL_CEC_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the @ref HAL_CEC_Init()/ @ref HAL_CEC_DeInit() only when + reset to the legacy weak function in the HAL_CEC_Init()/ HAL_CEC_DeInit() only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the @ref HAL_CEC_Init() / @ref HAL_CEC_DeInit() + if not, MspInit or MspDeInit are not null, the HAL_CEC_Init() / HAL_CEC_DeInit() keep and use the user MspInit/MspDeInit functions (registered beforehand) Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only. @@ -88,8 +88,8 @@ in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_CEC_RegisterCallback() before calling @ref HAL_CEC_DeInit() - or @ref HAL_CEC_Init() function. + using HAL_CEC_RegisterCallback() before calling HAL_CEC_DeInit() + or HAL_CEC_Init() function. When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -696,7 +696,7 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec) HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size) { - /* if the IP isn't already busy and if there is no previous transmission + /* if the peripheral isn't already busy and if there is no previous transmission already pending due to arbitration lost */ if (hcec->gState == HAL_CEC_STATE_READY) { diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c index 18fc4bd6bd..652eeda37d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c @@ -69,8 +69,8 @@ */ /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * + * @brief Initialization and Configuration functions. + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -197,8 +197,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) */ /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions. - * + * @brief management functions. + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -285,8 +285,8 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t */ /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim =============================================================================== ##### Peripheral State functions ##### diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c index 6ad998b3a1..eeddffa431 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c @@ -141,7 +141,7 @@ The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback, + Use Functions HAL_DAC_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. @@ -156,7 +156,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default + Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. @@ -171,12 +171,12 @@ (+) All Callbacks This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET + By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init - and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit + reset to the legacy weak (surcharged) functions in the HAL_DAC_Init + and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -184,8 +184,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit - or @ref HAL_DAC_Init function. + using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit + or HAL_DAC_Init function. When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -522,7 +522,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpreg = 0U; /* Check the parameters */ @@ -895,23 +895,23 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) */ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) { - uint32_t tmp = 0U; + uint32_t result = 0; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); if (Channel == DAC_CHANNEL_1) { - tmp = hdac->Instance->DOR1; + result = hdac->Instance->DOR1; } #if defined(DAC_CHANNEL2_SUPPORT) else { - tmp = hdac->Instance->DOR2; + result = hdac->Instance->DOR2; } #endif /* DAC_CHANNEL2_SUPPORT */ /* Returns the DAC channel data output register value */ - return tmp; + return result; } /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c index 50ff2b85e2..4a05998fef 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c @@ -152,7 +152,6 @@ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) /* Return function status */ return HAL_OK; } - #endif /* DAC_CHANNEL2_SUPPORT */ /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c index f9257a1d59..fbb6839856 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c @@ -62,9 +62,9 @@ The compilation define USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use functions @ref HAL_DCMI_RegisterCallback() to register a user callback. + Use functions HAL_DCMI_RegisterCallback() to register a user callback. - Function @ref HAL_DCMI_RegisterCallback() allows to register following callbacks: + Function HAL_DCMI_RegisterCallback() allows to register following callbacks: (+) FrameEventCallback : DCMI Frame Event. (+) VsyncEventCallback : DCMI Vsync Event. (+) LineEventCallback : DCMI Line Event. @@ -74,9 +74,9 @@ This function takes as parameters the HAL peripheral handle, the callback ID and a pointer to the user callback function. - Use function @ref HAL_DCMI_UnRegisterCallback() to reset a callback to the default + Use function HAL_DCMI_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. This function allows to reset following callbacks: (+) FrameEventCallback : DCMI Frame Event. @@ -86,13 +86,13 @@ (+) MspInitCallback : DCMI MspInit. (+) MspDeInitCallback : DCMI MspDeInit. - By default, after the @ref HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET + By default, after the HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions: - examples @ref FrameEventCallback(), @ref HAL_DCMI_ErrorCallback(). + examples FrameEventCallback(), HAL_DCMI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_DCMI_Init - and @ref HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_DCMI_Init and @ref HAL_DCMI_DeInit + reset to the legacy weak (surcharged) functions in the HAL_DCMI_Init + and HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_DCMI_Init and HAL_DCMI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). Callbacks can be registered/unregistered in READY state only. @@ -100,8 +100,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_DCMI_RegisterCallback before calling @ref HAL_DCMI_DeInit - or @ref HAL_DCMI_Init function. + using HAL_DCMI_RegisterCallback before calling HAL_DCMI_DeInit + or HAL_DCMI_Init function. When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c index 576037023f..11e89a6431 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c @@ -200,12 +200,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } - /* Allocate lock resource */ - __HAL_UNLOCK(hdma); - /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); @@ -550,12 +550,12 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + return HAL_TIMEOUT; } } @@ -563,11 +563,11 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); } return HAL_OK; } @@ -658,12 +658,12 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + return HAL_TIMEOUT; } } @@ -708,12 +708,12 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /* Clear the half transfer and transfer complete flags */ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State= HAL_DMA_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + return HAL_ERROR; } } @@ -724,10 +724,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /* Clear the half transfer and transfer complete flags */ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + hdma->State = HAL_DMA_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hdma); - - hdma->State = HAL_DMA_STATE_READY; } else { @@ -863,12 +863,12 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + if(hdma->XferAbortCallback != NULL) { hdma->XferAbortCallback(hdma); @@ -905,11 +905,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Disable the transfer complete interrupt */ hdma->Instance->CR &= ~(DMA_IT_TC); - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); } if(hdma->XferCpltCallback != NULL) @@ -940,11 +940,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); } if(hdma->XferErrorCallback != NULL) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c index d76d29697d..f3582b643d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c @@ -94,9 +94,9 @@ [..] (#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback. + Use function HAL_DMA2D_RegisterCallback() to register a user callback. - (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks: + (#) Function HAL_DMA2D_RegisterCallback() allows to register following callbacks: (+) XferCpltCallback : callback for transfer complete. (+) XferErrorCallback : callback for transfer error. (+) LineEventCallback : callback for line event. @@ -106,9 +106,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default + (#) Use function HAL_DMA2D_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) XferCpltCallback : callback for transfer complete. @@ -118,13 +118,13 @@ (+) MspInitCallback : DMA2D MspInit. (+) MspDeInitCallback : DMA2D MspDeInit. - (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET + (#) By default, after the HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions: - examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback() + examples HAL_DMA2D_LineEventCallback(), HAL_DMA2D_CLUTLoadingCpltCallback() Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init - and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand) - If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit + reset to the legacy weak (surcharged) functions in the HAL_DMA2D_Init + and HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the HAL_DMA2D_Init and HAL_DMA2D_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). Exception as well for Transfer Completion and Transfer Error callbacks that are not defined @@ -135,8 +135,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit - or @ref HAL_DMA2D_Init function. + using HAL_DMA2D_RegisterCallback before calling HAL_DMA2D_DeInit + or HAL_DMA2D_Init function. When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c index 7cf3e092bf..099bf1ea25 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c @@ -276,6 +276,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT pExtiConfig->Mode |= EXTI_MODE_EVENT; } + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + /* 2] Get trigger for configurable lines : rising */ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) { @@ -284,10 +288,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT { pExtiConfig->Trigger = EXTI_TRIGGER_RISING; } - else - { - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - } /* Get falling configuration */ /* Check if configuration of selected line is enable */ @@ -304,16 +304,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regval = SYSCFG->EXTICR[linepos >> 2u]; pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); } - else - { - pExtiConfig->GPIOSel = 0x00u; - } - } - else - { - /* No Trigger selected */ - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - pExtiConfig->GPIOSel = 0x00u; } return HAL_OK; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c index edb8b150e8..5c72eaaba4 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c @@ -173,12 +173,12 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { /*Initialization of SectorError variable*/ *SectorError = 0xFFFFFFFFU; - if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { /*Mass erase to be done*/ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); @@ -195,7 +195,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); /* Erase by sector by sector to be done*/ - for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++) + for (index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++) { FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange); @@ -205,7 +205,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* If the erase operation is completed, disable the SER and SNB Bits */ CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); - if(status != HAL_OK) + if (status != HAL_OK) { /* In case of error, stop erase procedure and return the faulty sector*/ *SectorError = index; @@ -247,10 +247,10 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ - FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR); + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); - if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { /*Mass erase to be done*/ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; @@ -294,10 +294,10 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); /*Write protection configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + if ((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) { assert_param(IS_WRPSTATE(pOBInit->WRPState)); - if(pOBInit->WRPState == OB_WRPSTATE_ENABLE) + if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) { /*Enable of Write protection on the selected Sector*/ status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks); @@ -310,21 +310,21 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) } /*Read protection configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + if ((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) { status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); } /*USER configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + if ((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) { - status = FLASH_OB_UserConfig(pOBInit->USERConfig&OB_IWDG_SW, - pOBInit->USERConfig&OB_STOP_NO_RST, - pOBInit->USERConfig&OB_STDBY_NO_RST); + status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW, + pOBInit->USERConfig & OB_STOP_NO_RST, + pOBInit->USERConfig & OB_STDBY_NO_RST); } /*BOR Level configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + if ((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) { status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); } @@ -371,7 +371,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) * * @retval HAL Status */ -HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) +HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) { HAL_StatusTypeDef status = HAL_ERROR; @@ -379,11 +379,11 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO assert_param(IS_OBEX(pAdvOBInit->OptionType)); /*Program PCROP option byte*/ - if(((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) + if (((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) { /* Check the parameters */ assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState)); - if((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE) + if ((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE) { /*Enable of Write protection on the selected Sector*/ #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ @@ -411,7 +411,7 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /*Program BOOT config option byte*/ - if(((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG) + if (((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG) { status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig); } @@ -464,7 +464,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) uint8_t optiontmp = 0xFF; /* Mask SPRMOD bit */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); /* Update Option Byte */ *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp); @@ -489,7 +489,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) uint8_t optiontmp = 0xFF; /* Mask SPRMOD bit */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); /* Update Option Byte */ *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp); @@ -548,12 +548,12 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) /* if the previous operation is completed, proceed to erase all sectors */ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); - if(Banks == FLASH_BANK_BOTH) + if (Banks == FLASH_BANK_BOTH) { /* bank1 & bank2 will be erased*/ FLASH->CR |= FLASH_MER_BIT; } - else if(Banks == FLASH_BANK_1) + else if (Banks == FLASH_BANK_1) { /*Only bank1 will be erased*/ FLASH->CR |= FLASH_CR_MER1; @@ -563,7 +563,7 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) /*Only bank2 will be erased*/ FLASH->CR |= FLASH_CR_MER2; } - FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U); + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U); } /** @@ -591,15 +591,15 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) assert_param(IS_FLASH_SECTOR(Sector)); assert_param(IS_VOLTAGERANGE(VoltageRange)); - if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + if (VoltageRange == FLASH_VOLTAGE_RANGE_1) { - tmp_psize = FLASH_PSIZE_BYTE; + tmp_psize = FLASH_PSIZE_BYTE; } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + else if (VoltageRange == FLASH_VOLTAGE_RANGE_2) { tmp_psize = FLASH_PSIZE_HALF_WORD; } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + else if (VoltageRange == FLASH_VOLTAGE_RANGE_3) { tmp_psize = FLASH_PSIZE_WORD; } @@ -609,7 +609,7 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) } /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */ - if(Sector > FLASH_SECTOR_11) + if (Sector > FLASH_SECTOR_11) { Sector += 4U; } @@ -654,37 +654,37 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { - if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || - (WRPSector < OB_WRP_SECTOR_12)) + if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || + (WRPSector < OB_WRP_SECTOR_12)) { - if(WRPSector == OB_WRP_SECTOR_All) - { - /*Write protection on all sector of BANK1*/ - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~(WRPSector>>12)); - } - else - { - /*Write protection done on sectors of BANK1*/ - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector); - } + if (WRPSector == OB_WRP_SECTOR_All) + { + /*Write protection on all sector of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~(WRPSector >> 12)); + } + else + { + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector); + } } else { /*Write protection done on sectors of BANK2*/ - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12)); + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12)); } /*Write protection on all sector of BANK2*/ - if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) + if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) { /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12)); + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12)); } } @@ -725,37 +725,37 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { - if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || - (WRPSector < OB_WRP_SECTOR_12)) + if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || + (WRPSector < OB_WRP_SECTOR_12)) { - if(WRPSector == OB_WRP_SECTOR_All) - { - /*Write protection on all sector of BANK1*/ - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12); - } - else - { - /*Write protection done on sectors of BANK1*/ - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; - } + if (WRPSector == OB_WRP_SECTOR_All) + { + /*Write protection on all sector of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12); + } + else + { + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; + } } else { /*Write protection done on sectors of BANK2*/ - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12); + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12); } /*Write protection on all sector of BANK2*/ - if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) + if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) { /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12); + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12); } } @@ -785,7 +785,7 @@ static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig) /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { /* Set Dual Bank Boot */ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2); @@ -824,32 +824,32 @@ static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t Sec /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { - if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) + if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) { assert_param(IS_OB_PCROP(SectorBank1)); /*Write protection done on sectors of BANK1*/ - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1; + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1; } else { assert_param(IS_OB_PCROP(SectorBank2)); /*Write protection done on sectors of BANK2*/ - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; } /*Write protection on all sector of BANK2*/ - if(Banks == FLASH_BANK_BOTH) + if (Banks == FLASH_BANK_BOTH) { assert_param(IS_OB_PCROP(SectorBank2)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { /*Write protection done on sectors of BANK2*/ - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; } } @@ -889,32 +889,32 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t Se /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { - if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) + if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) { assert_param(IS_OB_PCROP(SectorBank1)); /*Write protection done on sectors of BANK1*/ - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~SectorBank1); + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~SectorBank1); } else { /*Write protection done on sectors of BANK2*/ assert_param(IS_OB_PCROP(SectorBank2)); - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); } /*Write protection on all sector of BANK2*/ - if(Banks == FLASH_BANK_BOTH) + if (Banks == FLASH_BANK_BOTH) { assert_param(IS_OB_PCROP(SectorBank2)); - /* Wait for last operation to be completed */ + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { /*Write protection done on sectors of BANK2*/ - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); } } @@ -959,7 +959,7 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) /* If the previous operation is completed, proceed to erase all sectors */ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U); + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U); } /** @@ -987,15 +987,15 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) assert_param(IS_FLASH_SECTOR(Sector)); assert_param(IS_VOLTAGERANGE(VoltageRange)); - if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + if (VoltageRange == FLASH_VOLTAGE_RANGE_1) { - tmp_psize = FLASH_PSIZE_BYTE; + tmp_psize = FLASH_PSIZE_BYTE; } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + else if (VoltageRange == FLASH_VOLTAGE_RANGE_2) { tmp_psize = FLASH_PSIZE_HALF_WORD; } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + else if (VoltageRange == FLASH_VOLTAGE_RANGE_3) { tmp_psize = FLASH_PSIZE_WORD; } @@ -1040,9 +1040,9 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector); + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector); } return status; @@ -1076,9 +1076,9 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; } return status; @@ -1108,9 +1108,9 @@ static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector) /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector; + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector; } return status; @@ -1136,9 +1136,9 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector) /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~Sector); + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~Sector); } return status; @@ -1169,9 +1169,9 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { - *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level; + *(__IO uint8_t *)OPTCR_BYTE1_ADDRESS = Level; } return status; @@ -1206,10 +1206,10 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F); + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F); /* Update User Option Byte */ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp))); @@ -1274,11 +1274,11 @@ static uint8_t FLASH_OB_GetRDP(void) { uint8_t readstatus = OB_RDP_LEVEL_0; - if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2)) + if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2) { readstatus = OB_RDP_LEVEL_2; } - else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0)) + else if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0) { readstatus = OB_RDP_LEVEL_0; } @@ -1311,7 +1311,7 @@ static uint8_t FLASH_OB_GetBOR(void) void FLASH_FlushCaches(void) { /* Flush instruction cache */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN)!= RESET) + if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) { /* Disable instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); @@ -1322,7 +1322,7 @@ void FLASH_FlushCaches(void) } /* Flush data cache */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c index 0f10310c73..f62aa27c16 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c @@ -19,7 +19,7 @@ (#) Declare a FMPI2C_HandleTypeDef handle structure, for example: FMPI2C_HandleTypeDef hfmpi2c; - (#)Initialize the FMPI2C low level resources by implementing the @ref HAL_FMPI2C_MspInit() API: + (#)Initialize the FMPI2C low level resources by implementing the HAL_FMPI2C_MspInit() API: (##) Enable the FMPI2Cx interface clock (##) FMPI2C pins configuration (+++) Enable the clock for the FMPI2C GPIOs @@ -28,7 +28,8 @@ (+++) Configure the FMPI2Cx interrupt priority (+++) Enable the NVIC FMPI2C IRQ Channel (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive stream (+++) Enable the DMAx interface clock using (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx stream @@ -39,49 +40,49 @@ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, Own Address2, Own Address2 Mask, General call and Nostretch mode in the hfmpi2c Init structure. - (#) Initialize the FMPI2C registers by calling the @ref HAL_FMPI2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_FMPI2C_MspInit(&hfmpi2c) API. + (#) Initialize the FMPI2C registers by calling the HAL_FMPI2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_FMPI2C_MspInit(&hfmpi2c) API. - (#) To check if target device is ready for communication, use the function @ref HAL_FMPI2C_IsDeviceReady() + (#) To check if target device is ready for communication, use the function HAL_FMPI2C_IsDeviceReady() (#) For FMPI2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= [..] - (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_FMPI2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using @ref HAL_FMPI2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_FMPI2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_FMPI2C_Slave_Receive() + (+) Transmit in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Receive() *** Polling mode IO MEM operation *** ===================================== [..] - (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_FMPI2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_FMPI2C_Mem_Read() + (+) Write an amount of data in blocking mode to a specific memory address using HAL_FMPI2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_FMPI2C_Mem_Read() *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Master_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_FMPI2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Master_Receive_IT() - (+) At reception end of transfer, @ref HAL_FMPI2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Slave_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Slave_Receive_IT() - (+) At reception end of transfer, @ref HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_FMPI2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_ErrorCallback() - (+) Abort a master FMPI2C process communication with Interrupt using @ref HAL_FMPI2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_FMPI2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_AbortCpltCallback() - (+) Discard a slave FMPI2C process communication using @ref __HAL_FMPI2C_GENERATE_NACK() macro. + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback() + (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT() + (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback() + (+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. @@ -92,120 +93,131 @@ when a direction change during transfer [..] (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through @ref FMPI2C_XFEROPTIONS and are listed below: + (+) Option field values are defined through FMPI2C_XFEROPTIONS and are listed below: (++) FMPI2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode (++) FMPI2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition (++) FMPI2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition, an then permit a call the same master sequential interface - several times (like @ref HAL_FMPI2C_Master_Seq_Transmit_IT() then @ref HAL_FMPI2C_Master_Seq_Transmit_IT() - or @ref HAL_FMPI2C_Master_Seq_Transmit_DMA() then @ref HAL_FMPI2C_Master_Seq_Transmit_DMA()) + several times (like HAL_FMPI2C_Master_Seq_Transmit_IT() then HAL_FMPI2C_Master_Seq_Transmit_IT() + or HAL_FMPI2C_Master_Seq_Transmit_DMA() then HAL_FMPI2C_Master_Seq_Transmit_DMA()) (++) FMPI2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer + and with new data to transfer if the direction change or manage only the new data to + transfer if no direction change and without a final stop condition in both cases (++) FMPI2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer + and with new data to transfer if the direction change or manage only the new data to + transfer if no direction change and with a final stop condition in both cases - (++) FMPI2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential - interface several times (link with option FMPI2C_FIRST_AND_NEXT_FRAME). - Usage can, transfer several bytes one by one using HAL_FMPI2C_Master_Seq_Transmit_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME) - or HAL_FMPI2C_Master_Seq_Receive_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME) - or HAL_FMPI2C_Master_Seq_Transmit_DMA(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME) - or HAL_FMPI2C_Master_Seq_Receive_DMA(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME). - Then usage of this option FMPI2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit + (++) FMPI2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option FMPI2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_FMPI2C_Master_Seq_Transmit_IT + or HAL_FMPI2C_Master_Seq_Receive_IT + or HAL_FMPI2C_Master_Seq_Transmit_DMA + or HAL_FMPI2C_Master_Seq_Receive_DMA + with option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME. + Then usage of this option FMPI2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit without stopping the communication and so generate a restart condition. - (++) FMPI2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential + (++) FMPI2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential interface. - Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_FMPI2C_Master_Seq_Transmit_IT(option FMPI2C_FIRST_FRAME then FMPI2C_OTHER_FRAME) - or HAL_FMPI2C_Master_Seq_Receive_IT(option FMPI2C_FIRST_FRAME then FMPI2C_OTHER_FRAME) - or HAL_FMPI2C_Master_Seq_Transmit_DMA(option FMPI2C_FIRST_FRAME then FMPI2C_OTHER_FRAME) - or HAL_FMPI2C_Master_Seq_Receive_DMA(option FMPI2C_FIRST_FRAME then FMPI2C_OTHER_FRAME). - Then usage of this option FMPI2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_FMPI2C_Master_Seq_Transmit_IT + or HAL_FMPI2C_Master_Seq_Receive_IT + or HAL_FMPI2C_Master_Seq_Transmit_DMA + or HAL_FMPI2C_Master_Seq_Receive_DMA + with option FMPI2C_FIRST_FRAME then FMPI2C_OTHER_FRAME. + Then usage of this option FMPI2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. (+) Different sequential FMPI2C interfaces are listed below: - (++) Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Master_Seq_Transmit_IT() - or using @ref HAL_FMPI2C_Master_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_FMPI2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MasterTxCpltCallback() - (++) Sequential receive in master FMPI2C mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Master_Seq_Receive_IT() - or using @ref HAL_FMPI2C_Master_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_FMPI2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA FMPI2C process communication with Interrupt using @ref HAL_FMPI2C_Master_Abort_IT() - (+++) End of abort process, @ref HAL_FMPI2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave FMPI2C mode using @ref HAL_FMPI2C_EnableListen_IT() @ref HAL_FMPI2C_DisableListen_IT() - (+++) When address slave FMPI2C match, @ref HAL_FMPI2C_AddrCallback() is executed and user can + (++) Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Seq_Transmit_IT() + or using HAL_FMPI2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback() + (++) Sequential receive in master FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Seq_Receive_IT() + or using HAL_FMPI2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT() + (+++) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave FMPI2C mode using HAL_FMPI2C_EnableListen_IT() HAL_FMPI2C_DisableListen_IT() + (+++) When address slave FMPI2C match, HAL_FMPI2C_AddrCallback() is executed and user can add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end @ref HAL_FMPI2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_ListenCpltCallback() - (++) Sequential transmit in slave FMPI2C mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Slave_Seq_Transmit_IT() - or using @ref HAL_FMPI2C_Slave_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveTxCpltCallback() - (++) Sequential receive in slave FMPI2C mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Slave_Seq_Receive_IT() - or using @ref HAL_FMPI2C_Slave_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveRxCpltCallback() - (++) In case of transfer Error, @ref HAL_FMPI2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_ErrorCallback() - (++) Discard a slave FMPI2C process communication using @ref __HAL_FMPI2C_GENERATE_NACK() macro. + (+++) At Listen mode end HAL_FMPI2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_ListenCpltCallback() + (++) Sequential transmit in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Seq_Transmit_IT() + or using HAL_FMPI2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback() + (++) Sequential receive in slave FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Seq_Receive_IT() + or using HAL_FMPI2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback() + (++) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** Interrupt mode IO MEM operation *** ======================================= [..] (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - @ref HAL_FMPI2C_Mem_Write_IT() - (+) At Memory end of write transfer, @ref HAL_FMPI2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MemTxCpltCallback() + HAL_FMPI2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - @ref HAL_FMPI2C_Mem_Read_IT() - (+) At Memory end of read transfer, @ref HAL_FMPI2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_FMPI2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_ErrorCallback() + HAL_FMPI2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_FMPI2C_Master_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_FMPI2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MasterTxCpltCallback() + HAL_FMPI2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_FMPI2C_Master_Receive_DMA() - (+) At reception end of transfer, @ref HAL_FMPI2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MasterRxCpltCallback() + HAL_FMPI2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_FMPI2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveTxCpltCallback() + HAL_FMPI2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_FMPI2C_Slave_Receive_DMA() - (+) At reception end of transfer, @ref HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_FMPI2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_ErrorCallback() - (+) Abort a master FMPI2C process communication with Interrupt using @ref HAL_FMPI2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_FMPI2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_AbortCpltCallback() - (+) Discard a slave FMPI2C process communication using @ref __HAL_FMPI2C_GENERATE_NACK() macro. + HAL_FMPI2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback() + (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT() + (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback() + (+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** DMA mode IO MEM operation *** ================================= [..] (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - @ref HAL_FMPI2C_Mem_Write_DMA() - (+) At Memory end of write transfer, @ref HAL_FMPI2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MemTxCpltCallback() + HAL_FMPI2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - @ref HAL_FMPI2C_Mem_Read_DMA() - (+) At Memory end of read transfer, @ref HAL_FMPI2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_FMPI2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_ErrorCallback() + HAL_FMPI2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback() *** FMPI2C HAL driver macros list *** @@ -213,23 +225,23 @@ [..] Below the list of most used macros in FMPI2C HAL driver. - (+) @ref __HAL_FMPI2C_ENABLE: Enable the FMPI2C peripheral - (+) @ref __HAL_FMPI2C_DISABLE: Disable the FMPI2C peripheral - (+) @ref __HAL_FMPI2C_GENERATE_NACK: Generate a Non-Acknowledge FMPI2C peripheral in Slave mode - (+) @ref __HAL_FMPI2C_GET_FLAG: Check whether the specified FMPI2C flag is set or not - (+) @ref __HAL_FMPI2C_CLEAR_FLAG: Clear the specified FMPI2C pending flag - (+) @ref __HAL_FMPI2C_ENABLE_IT: Enable the specified FMPI2C interrupt - (+) @ref __HAL_FMPI2C_DISABLE_IT: Disable the specified FMPI2C interrupt + (+) __HAL_FMPI2C_ENABLE: Enable the FMPI2C peripheral + (+) __HAL_FMPI2C_DISABLE: Disable the FMPI2C peripheral + (+) __HAL_FMPI2C_GENERATE_NACK: Generate a Non-Acknowledge FMPI2C peripheral in Slave mode + (+) __HAL_FMPI2C_GET_FLAG: Check whether the specified FMPI2C flag is set or not + (+) __HAL_FMPI2C_CLEAR_FLAG: Clear the specified FMPI2C pending flag + (+) __HAL_FMPI2C_ENABLE_IT: Enable the specified FMPI2C interrupt + (+) __HAL_FMPI2C_DISABLE_IT: Disable the specified FMPI2C interrupt *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_FMPI2C_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_FMPI2C_RegisterCallback() or @ref HAL_FMPI2C_RegisterAddrCallback() + Use Functions HAL_FMPI2C_RegisterCallback() or HAL_FMPI2C_RegisterAddrCallback() to register an interrupt callback. [..] - Function @ref HAL_FMPI2C_RegisterCallback() allows to register following callbacks: + Function HAL_FMPI2C_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. @@ -244,11 +256,11 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - For specific callback AddrCallback use dedicated register callbacks : @ref HAL_FMPI2C_RegisterAddrCallback(). + For specific callback AddrCallback use dedicated register callbacks : HAL_FMPI2C_RegisterAddrCallback(). [..] - Use function @ref HAL_FMPI2C_UnRegisterCallback to reset a callback to the default + Use function HAL_FMPI2C_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_FMPI2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_FMPI2C_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. @@ -263,24 +275,24 @@ (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. [..] - For callback AddrCallback use dedicated register callbacks : @ref HAL_FMPI2C_UnRegisterAddrCallback(). + For callback AddrCallback use dedicated register callbacks : HAL_FMPI2C_UnRegisterAddrCallback(). [..] - By default, after the @ref HAL_FMPI2C_Init() and when the state is @ref HAL_FMPI2C_STATE_RESET + By default, after the HAL_FMPI2C_Init() and when the state is HAL_FMPI2C_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_FMPI2C_MasterTxCpltCallback(), @ref HAL_FMPI2C_MasterRxCpltCallback(). + examples HAL_FMPI2C_MasterTxCpltCallback(), HAL_FMPI2C_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_FMPI2C_Init()/ @ref HAL_FMPI2C_DeInit() only when + reset to the legacy weak functions in the HAL_FMPI2C_Init()/ HAL_FMPI2C_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_FMPI2C_Init()/ @ref HAL_FMPI2C_DeInit() + If MspInit or MspDeInit are not null, the HAL_FMPI2C_Init()/ HAL_FMPI2C_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_FMPI2C_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_FMPI2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_FMPI2C_STATE_READY or @ref HAL_FMPI2C_STATE_RESET state, + in HAL_FMPI2C_STATE_READY or HAL_FMPI2C_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_FMPI2C_RegisterCallback() before calling @ref HAL_FMPI2C_DeInit() - or @ref HAL_FMPI2C_Init() function. + using HAL_FMPI2C_RegisterCallback() before calling HAL_FMPI2C_DeInit() + or HAL_FMPI2C_Init() function. [..] When the compilation flag USE_HAL_FMPI2C_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -337,28 +349,48 @@ #define FMPI2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ #define MAX_NBYTE_SIZE 255U -#define SlaveAddr_SHIFT 7U -#define SlaveAddr_MSK 0x06U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U /* Private define for @ref PreviousState usage */ -#define FMPI2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_FMPI2C_STATE_BUSY_TX | (uint32_t)HAL_FMPI2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_FMPI2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ -#define FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE)) /*!< Default Value */ -#define FMPI2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define FMPI2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define FMPI2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define FMPI2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -#define FMPI2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ -#define FMPI2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ +#define FMPI2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_FMPI2C_STATE_BUSY_TX | \ + (uint32_t)HAL_FMPI2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_FMPI2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE)) +/*!< Default Value */ +#define FMPI2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | \ + (uint32_t)HAL_FMPI2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define FMPI2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | \ + (uint32_t)HAL_FMPI2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define FMPI2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | \ + (uint32_t)HAL_FMPI2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define FMPI2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | \ + (uint32_t)HAL_FMPI2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define FMPI2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | \ + (uint32_t)HAL_FMPI2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define FMPI2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | \ + (uint32_t)HAL_FMPI2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ /* Private define to centralize the enable/disable of Interrupts */ -#define FMPI2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref FMPI2C_XFER_LISTEN_IT */ -#define FMPI2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref FMPI2C_XFER_LISTEN_IT */ -#define FMPI2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref FMPI2C_XFER_TX_IT and @ref FMPI2C_XFER_RX_IT */ - -#define FMPI2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */ -#define FMPI2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ -#define FMPI2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ +#define FMPI2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref FMPI2C_XFER_LISTEN_IT */ +#define FMPI2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref FMPI2C_XFER_LISTEN_IT */ +#define FMPI2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref FMPI2C_XFER_TX_IT + and @ref FMPI2C_XFER_RX_IT */ + +#define FMPI2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define FMPI2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define FMPI2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define FMPI2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -391,24 +423,34 @@ static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode); /* Private functions to handle IT transfer */ -static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); /* Private functions for FMPI2C transfer IRQ handler */ -static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources); /* Private functions to handle flags during polling transfer */ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, + uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest); @@ -422,7 +464,7 @@ static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c); /* Private function to handle start, restart or stop a transfer */ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request); + uint32_t Request); /* Private function to Convert Specific options */ static void FMPI2C_ConvertOtherXferOptions(FMPI2C_HandleTypeDef *hfmpi2c); @@ -560,7 +602,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c) hfmpi2c->Instance->OAR2 &= ~FMPI2C_DUALADDRESS_ENABLE; /* Configure FMPI2Cx: Dual mode and Own Address2 */ - hfmpi2c->Instance->OAR2 = (hfmpi2c->Init.DualAddressMode | hfmpi2c->Init.OwnAddress2 | (hfmpi2c->Init.OwnAddress2Masks << 8)); + hfmpi2c->Instance->OAR2 = (hfmpi2c->Init.DualAddressMode | hfmpi2c->Init.OwnAddress2 | \ + (hfmpi2c->Init.OwnAddress2Masks << 8)); /*---------------------------- FMPI2Cx CR1 Configuration ----------------------*/ /* Configure FMPI2Cx: Generalcall and NoStretch mode */ @@ -1066,8 +1109,8 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2 * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1098,12 +1141,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, + FMPI2C_GENERATE_START_WRITE); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_GENERATE_START_WRITE); } while (hfmpi2c->XferCount > 0U) @@ -1133,12 +1178,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_NO_STARTSTOP); } } } @@ -1181,8 +1228,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1213,12 +1260,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, + FMPI2C_GENERATE_START_READ); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_GENERATE_START_READ); } while (hfmpi2c->XferCount > 0U) @@ -1249,12 +1298,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_NO_STARTSTOP); } } } @@ -1295,7 +1346,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1432,7 +1484,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1607,7 +1660,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); return HAL_OK; @@ -1628,7 +1682,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; @@ -1676,7 +1731,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); return HAL_OK; @@ -1725,7 +1781,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT | FMPI2C_XFER_LISTEN_IT); return HAL_OK; @@ -1774,7 +1831,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uin /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_LISTEN_IT); return HAL_OK; @@ -1847,7 +1905,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, hfmpi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, + hfmpi2c->XferSize); } else { @@ -1907,7 +1966,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -1917,7 +1977,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } @@ -1991,7 +2052,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u hfmpi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, + hfmpi2c->XferSize); } else { @@ -2051,7 +2113,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2061,7 +2124,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } @@ -2119,7 +2183,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u hfmpi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, + hfmpi2c->XferSize); } else { @@ -2222,7 +2287,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui hfmpi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, + hfmpi2c->XferSize); } else { @@ -2375,12 +2441,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_NO_STARTSTOP); } } @@ -2475,12 +2543,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, + FMPI2C_GENERATE_START_READ); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_GENERATE_START_READ); } do @@ -2511,12 +2581,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t) hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t) hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_NO_STARTSTOP); } } } while (hfmpi2c->XferCount > 0U); @@ -2609,7 +2681,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ } /* Send Slave Address and Memory Address */ - if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) + != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2628,7 +2701,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); return HAL_OK; @@ -2720,7 +2794,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); return HAL_OK; @@ -2793,7 +2868,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 } /* Send Slave Address and Memory Address */ - if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) + != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2814,7 +2890,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 hfmpi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, + hfmpi2c->XferSize); } else { @@ -2958,7 +3035,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ hfmpi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, + hfmpi2c->XferSize); } else { @@ -3029,7 +3107,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) { uint32_t tickstart; @@ -3206,9 +3285,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2 xfermode = hfmpi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX) && (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX) && \ + (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = FMPI2C_NO_STARTSTOP; } @@ -3292,9 +3373,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi xfermode = hfmpi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX) && (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX) && \ + (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = FMPI2C_NO_STARTSTOP; } @@ -3325,7 +3408,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi hfmpi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, + hfmpi2c->XferSize); } else { @@ -3384,7 +3468,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -3394,7 +3479,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } @@ -3454,9 +3540,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c xfermode = hfmpi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) && (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) && \ + (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = FMPI2C_NO_STARTSTOP; } @@ -3540,9 +3628,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 xfermode = hfmpi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) && (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) && \ + (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = FMPI2C_NO_STARTSTOP; } @@ -3573,7 +3663,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 hfmpi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, + hfmpi2c->XferSize); } else { @@ -3632,7 +3723,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -3642,7 +3734,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } @@ -3863,7 +3956,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2 hfmpi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, + hfmpi2c->XferSize); } else { @@ -4139,7 +4233,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c hfmpi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, + (uint32_t)pData, hfmpi2c->XferSize); } else { @@ -4357,7 +4452,8 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) uint32_t tmperror; /* FMPI2C Bus error interrupt occurred ------------------------------------*/ - if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_BERR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) + if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_BERR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) { hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_BERR; @@ -4366,7 +4462,8 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) } /* FMPI2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_OVR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) + if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_OVR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) { hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_OVR; @@ -4375,7 +4472,8 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) } /* FMPI2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_ARLO) != RESET) && (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) + if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_ARLO) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) { hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_ARLO; @@ -4629,7 +4727,8 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c) * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) { uint16_t devaddress; uint32_t tmpITFlags = ITFlags; @@ -4637,7 +4736,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm /* Process Locked */ __HAL_LOCK(hfmpi2c); - if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); @@ -4650,7 +4750,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm /* Flush TX register */ FMPI2C_Flush_TXDR(hfmpi2c); } - else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_RXI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_RXI) != RESET)) { /* Remove RXNE flag on temporary variable as read done */ tmpITFlags &= ~FMPI2C_FLAG_RXNE; @@ -4664,7 +4765,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm hfmpi2c->XferSize--; hfmpi2c->XferCount--; } - else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)) { /* Write data to TXDR */ hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; @@ -4675,7 +4777,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm hfmpi2c->XferSize--; hfmpi2c->XferCount--; } - else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TCR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TCR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) { if ((hfmpi2c->XferCount != 0U) && (hfmpi2c->XferSize == 0U)) { @@ -4691,11 +4794,13 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm hfmpi2c->XferSize = hfmpi2c->XferCount; if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) { - FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, + hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP); } else { - FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); } } } @@ -4715,7 +4820,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm } } } - else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TC) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TC) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) { if (hfmpi2c->XferCount == 0U) { @@ -4746,7 +4852,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm /* Nothing to do */ } - if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) { /* Call FMPI2C Master complete process */ FMPI2C_ITMasterCplt(hfmpi2c, tmpITFlags); @@ -4766,7 +4873,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) { uint32_t tmpoptions = hfmpi2c->XferOptions; uint32_t tmpITFlags = ITFlags; @@ -4775,13 +4883,15 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp __HAL_LOCK(hfmpi2c); /* Check if STOPF is set */ - if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) { /* Call FMPI2C Slave complete process */ FMPI2C_ITSlaveCplt(hfmpi2c, tmpITFlags); } - if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { /* Check that FMPI2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -4789,8 +4899,9 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp /* So clear Flag NACKF only */ if (hfmpi2c->XferCount == 0U) { - /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ { /* Call FMPI2C Listen complete process */ FMPI2C_ITListenCplt(hfmpi2c, tmpITFlags); @@ -4829,7 +4940,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp } } } - else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_RXI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_RXI) != RESET)) { if (hfmpi2c->XferCount > 0U) { @@ -4855,11 +4967,12 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp { FMPI2C_ITAddrCplt(hfmpi2c, tmpITFlags); } - else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ - /* Check if all data have already been sent */ + /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hfmpi2c->XferCount > 0U) { @@ -4901,7 +5014,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) { uint16_t devaddress; uint32_t xfermode; @@ -4909,7 +5023,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf /* Process Locked */ __HAL_LOCK(hfmpi2c); - if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); @@ -4925,7 +5040,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf /* Flush TX register */ FMPI2C_Flush_TXDR(hfmpi2c); } - else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TCR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TCR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_FMPI2C_DISABLE_IT(hfmpi2c, FMPI2C_IT_TCI); @@ -4986,7 +5102,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf } } } - else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TC) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TC) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) { if (hfmpi2c->XferCount == 0U) { @@ -5012,7 +5129,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE); } } - else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) { /* Call FMPI2C Master complete process */ FMPI2C_ITMasterCplt(hfmpi2c, ITFlags); @@ -5036,7 +5154,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) { uint32_t tmpoptions = hfmpi2c->XferOptions; uint32_t treatdmanack = 0U; @@ -5046,13 +5165,15 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm __HAL_LOCK(hfmpi2c); /* Check if STOPF is set */ - if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) { /* Call FMPI2C Slave complete process */ FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags); } - if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { /* Check that FMPI2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5087,8 +5208,9 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm if (treatdmanack == 1U) { - /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ { /* Call FMPI2C Listen complete process */ FMPI2C_ITListenCplt(hfmpi2c, ITFlags); @@ -5149,7 +5271,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); } } - else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_ADDR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_ADDRI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_ADDR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_ADDRI) != RESET)) { FMPI2C_ITAddrCplt(hfmpi2c, ITFlags); } @@ -5176,8 +5299,9 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); @@ -5230,8 +5354,9 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE); @@ -5299,7 +5424,7 @@ static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) /* If 10bits addressing mode is selected */ if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT) { - if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) { slaveaddrcode = ownadd1code; hfmpi2c->AddrEventCount++; @@ -6026,7 +6151,8 @@ static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c) */ static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable DMA Request */ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN; @@ -6054,7 +6180,8 @@ static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, + hfmpi2c->XferSize) != HAL_OK) { /* Call the corresponding callback to inform upper layer of End of Transfer */ FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_DMA); @@ -6074,7 +6201,8 @@ static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) */ static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) { - FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hfmpi2c->XferOptions; if ((tmpoptions == FMPI2C_NEXT_FRAME) || (tmpoptions == FMPI2C_FIRST_FRAME)) @@ -6101,7 +6229,8 @@ static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) */ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { - FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable DMA Request */ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN; @@ -6129,7 +6258,8 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, + hfmpi2c->XferSize) != HAL_OK) { /* Call the corresponding callback to inform upper layer of End of Transfer */ FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_DMA); @@ -6149,7 +6279,8 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) */ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) { - FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hfmpi2c->XferOptions; if ((__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U) && \ @@ -6177,7 +6308,8 @@ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma) { uint32_t treatdmaerror = 0U; - FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); if (hfmpi2c->hdmatx != NULL) { @@ -6214,7 +6346,8 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma) */ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma) { - FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Reset AbortCpltCallback */ if (hfmpi2c->hdmatx != NULL) @@ -6270,7 +6403,8 @@ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfm * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET) { @@ -6307,7 +6441,8 @@ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) { @@ -6341,7 +6476,8 @@ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET) { @@ -6408,6 +6544,12 @@ static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2 { if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET) { + /* In case of Soft End condition, generate the STOP condition */ + if (FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE) + { + /* Generate Stop */ + hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP; + } /* Wait until STOP Flag is reset */ /* AutoEnd should be initiate after AF */ while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) @@ -6483,9 +6625,11 @@ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAdd /* update CR2 register */ MODIFY_REG(hfmpi2c->Instance->CR2, ((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | \ - (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | FMPI2C_CR2_START | FMPI2C_CR2_STOP)), \ - (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | - (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | \ + FMPI2C_CR2_START | FMPI2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | \ + (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request)); } /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c_ex.c index a6acc9e5cf..0a8f72ccf7 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c_ex.c @@ -5,7 +5,8 @@ * @brief FMPI2C Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of FMPI2C Extended peripheral: - * + Extended features functions + * + Filter Mode Functions + * + FastModePlus Functions * @verbatim ============================================================================== @@ -68,16 +69,15 @@ * @{ */ -/** @defgroup FMPI2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions +/** @defgroup FMPI2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions * @verbatim =============================================================================== - ##### Extended features functions ##### + ##### Filter Mode Functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure Noise Filters - (+) Configure Fast Mode Plus @endverbatim * @{ @@ -178,6 +178,23 @@ HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c return HAL_BUSY; } } +/** + * @} + */ + +/** @defgroup FMPI2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ /** * @brief Enable the FMPI2C fast mode plus driving capability. @@ -224,11 +241,9 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /* Disable fast mode plus driving capability for selected pin */ CLEAR_BIT(SYSCFG->CFGR, (uint32_t)ConfigFastModePlus); } - /** * @} */ - /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c index c2bc779c1b..578ecc5bfc 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c @@ -20,7 +20,7 @@ (#) Declare a FMPSMBUS_HandleTypeDef handle structure, for example: FMPSMBUS_HandleTypeDef hfmpsmbus; - (#)Initialize the FMPSMBUS low level resources by implementing the @ref HAL_FMPSMBUS_MspInit() API: + (#)Initialize the FMPSMBUS low level resources by implementing the HAL_FMPSMBUS_MspInit() API: (##) Enable the FMPSMBUSx interface clock (##) FMPSMBUS pins configuration (+++) Enable the clock for the FMPSMBUS GPIOs @@ -33,69 +33,69 @@ Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, Peripheral mode and Packet Error Check mode in the hfmpsmbus Init structure. - (#) Initialize the FMPSMBUS registers by calling the @ref HAL_FMPSMBUS_Init() API: + (#) Initialize the FMPSMBUS registers by calling the HAL_FMPSMBUS_Init() API: (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized @ref HAL_FMPSMBUS_MspInit(&hfmpsmbus) API. + by calling the customized HAL_FMPSMBUS_MspInit(&hfmpsmbus) API. - (#) To check if target device is ready for communication, use the function @ref HAL_FMPSMBUS_IsDeviceReady() + (#) To check if target device is ready for communication, use the function HAL_FMPSMBUS_IsDeviceReady() (#) For FMPSMBUS IO operations, only one mode of operations is available within this driver *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master/host FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Master_Transmit_IT() - (++) At transmission end of transfer @ref HAL_FMPSMBUS_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPSMBUS_MasterTxCpltCallback() - (+) Receive in master/host FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Master_Receive_IT() - (++) At reception end of transfer @ref HAL_FMPSMBUS_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPSMBUS_MasterRxCpltCallback() - (+) Abort a master/host FMPSMBUS process communication with Interrupt using @ref HAL_FMPSMBUS_Master_Abort_IT() + (+) Transmit in master/host FMPSMBUS mode an amount of data in non-blocking mode using HAL_FMPSMBUS_Master_Transmit_IT() + (++) At transmission end of transfer HAL_FMPSMBUS_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPSMBUS_MasterTxCpltCallback() + (+) Receive in master/host FMPSMBUS mode an amount of data in non-blocking mode using HAL_FMPSMBUS_Master_Receive_IT() + (++) At reception end of transfer HAL_FMPSMBUS_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPSMBUS_MasterRxCpltCallback() + (+) Abort a master/host FMPSMBUS process communication with Interrupt using HAL_FMPSMBUS_Master_Abort_IT() (++) The associated previous transfer callback is called at the end of abort process - (++) mean @ref HAL_FMPSMBUS_MasterTxCpltCallback() in case of previous state was master transmit - (++) mean @ref HAL_FMPSMBUS_MasterRxCpltCallback() in case of previous state was master receive + (++) mean HAL_FMPSMBUS_MasterTxCpltCallback() in case of previous state was master transmit + (++) mean HAL_FMPSMBUS_MasterRxCpltCallback() in case of previous state was master receive (+) Enable/disable the Address listen mode in slave/device or host/slave FMPSMBUS mode - using @ref HAL_FMPSMBUS_EnableListen_IT() @ref HAL_FMPSMBUS_DisableListen_IT() - (++) When address slave/device FMPSMBUS match, @ref HAL_FMPSMBUS_AddrCallback() is executed and user can + using HAL_FMPSMBUS_EnableListen_IT() HAL_FMPSMBUS_DisableListen_IT() + (++) When address slave/device FMPSMBUS match, HAL_FMPSMBUS_AddrCallback() is executed and user can add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). - (++) At Listen mode end @ref HAL_FMPSMBUS_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPSMBUS_ListenCpltCallback() - (+) Transmit in slave/device FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Slave_Transmit_IT() - (++) At transmission end of transfer @ref HAL_FMPSMBUS_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPSMBUS_SlaveTxCpltCallback() - (+) Receive in slave/device FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Slave_Receive_IT() - (++) At reception end of transfer @ref HAL_FMPSMBUS_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPSMBUS_SlaveRxCpltCallback() - (+) Enable/Disable the FMPSMBUS alert mode using @ref HAL_FMPSMBUS_EnableAlert_IT() @ref HAL_FMPSMBUS_DisableAlert_IT() - (++) When FMPSMBUS Alert is generated @ref HAL_FMPSMBUS_ErrorCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPSMBUS_ErrorCallback() - to check the Alert Error Code using function @ref HAL_FMPSMBUS_GetError() - (+) Get HAL state machine or error values using @ref HAL_FMPSMBUS_GetState() or @ref HAL_FMPSMBUS_GetError() - (+) In case of transfer Error, @ref HAL_FMPSMBUS_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_FMPSMBUS_ErrorCallback() - to check the Error Code using function @ref HAL_FMPSMBUS_GetError() + (++) At Listen mode end HAL_FMPSMBUS_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPSMBUS_ListenCpltCallback() + (+) Transmit in slave/device FMPSMBUS mode an amount of data in non-blocking mode using HAL_FMPSMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer HAL_FMPSMBUS_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPSMBUS_SlaveTxCpltCallback() + (+) Receive in slave/device FMPSMBUS mode an amount of data in non-blocking mode using HAL_FMPSMBUS_Slave_Receive_IT() + (++) At reception end of transfer HAL_FMPSMBUS_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPSMBUS_SlaveRxCpltCallback() + (+) Enable/Disable the FMPSMBUS alert mode using HAL_FMPSMBUS_EnableAlert_IT() HAL_FMPSMBUS_DisableAlert_IT() + (++) When FMPSMBUS Alert is generated HAL_FMPSMBUS_ErrorCallback() is executed and user can + add his own code by customization of function pointer HAL_FMPSMBUS_ErrorCallback() + to check the Alert Error Code using function HAL_FMPSMBUS_GetError() + (+) Get HAL state machine or error values using HAL_FMPSMBUS_GetState() or HAL_FMPSMBUS_GetError() + (+) In case of transfer Error, HAL_FMPSMBUS_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_FMPSMBUS_ErrorCallback() + to check the Error Code using function HAL_FMPSMBUS_GetError() *** FMPSMBUS HAL driver macros list *** ================================== [..] Below the list of most used macros in FMPSMBUS HAL driver. - (+) @ref __HAL_FMPSMBUS_ENABLE: Enable the FMPSMBUS peripheral - (+) @ref __HAL_FMPSMBUS_DISABLE: Disable the FMPSMBUS peripheral - (+) @ref __HAL_FMPSMBUS_GET_FLAG: Check whether the specified FMPSMBUS flag is set or not - (+) @ref __HAL_FMPSMBUS_CLEAR_FLAG: Clear the specified FMPSMBUS pending flag - (+) @ref __HAL_FMPSMBUS_ENABLE_IT: Enable the specified FMPSMBUS interrupt - (+) @ref __HAL_FMPSMBUS_DISABLE_IT: Disable the specified FMPSMBUS interrupt + (+) __HAL_FMPSMBUS_ENABLE: Enable the FMPSMBUS peripheral + (+) __HAL_FMPSMBUS_DISABLE: Disable the FMPSMBUS peripheral + (+) __HAL_FMPSMBUS_GET_FLAG: Check whether the specified FMPSMBUS flag is set or not + (+) __HAL_FMPSMBUS_CLEAR_FLAG: Clear the specified FMPSMBUS pending flag + (+) __HAL_FMPSMBUS_ENABLE_IT: Enable the specified FMPSMBUS interrupt + (+) __HAL_FMPSMBUS_DISABLE_IT: Disable the specified FMPSMBUS interrupt *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_FMPSMBUS_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_FMPSMBUS_RegisterCallback() or @ref HAL_FMPSMBUS_RegisterAddrCallback() + Use Functions HAL_FMPSMBUS_RegisterCallback() or HAL_FMPSMBUS_RegisterAddrCallback() to register an interrupt callback. [..] - Function @ref HAL_FMPSMBUS_RegisterCallback() allows to register following callbacks: + Function HAL_FMPSMBUS_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. @@ -107,11 +107,11 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - For specific callback AddrCallback use dedicated register callbacks : @ref HAL_FMPSMBUS_RegisterAddrCallback. + For specific callback AddrCallback use dedicated register callbacks : HAL_FMPSMBUS_RegisterAddrCallback. [..] - Use function @ref HAL_FMPSMBUS_UnRegisterCallback to reset a callback to the default + Use function HAL_FMPSMBUS_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_FMPSMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_FMPSMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. @@ -123,24 +123,24 @@ (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. [..] - For callback AddrCallback use dedicated register callbacks : @ref HAL_FMPSMBUS_UnRegisterAddrCallback. + For callback AddrCallback use dedicated register callbacks : HAL_FMPSMBUS_UnRegisterAddrCallback. [..] - By default, after the @ref HAL_FMPSMBUS_Init() and when the state is @ref HAL_FMPI2C_STATE_RESET + By default, after the HAL_FMPSMBUS_Init() and when the state is HAL_FMPI2C_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_FMPSMBUS_MasterTxCpltCallback(), @ref HAL_FMPSMBUS_MasterRxCpltCallback(). + examples HAL_FMPSMBUS_MasterTxCpltCallback(), HAL_FMPSMBUS_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_FMPSMBUS_Init()/ @ref HAL_FMPSMBUS_DeInit() only when + reset to the legacy weak functions in the HAL_FMPSMBUS_Init()/ HAL_FMPSMBUS_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_FMPSMBUS_Init()/ @ref HAL_FMPSMBUS_DeInit() + If MspInit or MspDeInit are not null, the HAL_FMPSMBUS_Init()/ HAL_FMPSMBUS_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_FMPI2C_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_FMPI2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_FMPI2C_STATE_READY or @ref HAL_FMPI2C_STATE_RESET state, + in HAL_FMPI2C_STATE_READY or HAL_FMPI2C_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_FMPSMBUS_RegisterCallback() before calling @ref HAL_FMPSMBUS_DeInit() - or @ref HAL_FMPSMBUS_Init() function. + using HAL_FMPSMBUS_RegisterCallback() before calling HAL_FMPSMBUS_DeInit() + or HAL_FMPSMBUS_Init() function. [..] When the compilation flag USE_HAL_FMPSMBUS_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -204,8 +204,8 @@ /** @addtogroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions * @{ */ -static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status, - uint32_t Timeout); +static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout); static void FMPSMBUS_Enable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); static void FMPSMBUS_Disable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); @@ -216,8 +216,8 @@ static void FMPSMBUS_ConvertOtherXferOptions(FMPSMBUS_HandleTypeDef *hfmpsmbus); static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); -static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request); +static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request); /** * @} */ @@ -365,15 +365,20 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus) /*---------------------------- FMPSMBUSx OAR2 Configuration -----------------------*/ /* Configure FMPSMBUSx: Dual mode and Own Address2 */ - hfmpsmbus->Instance->OAR2 = (hfmpsmbus->Init.DualAddressMode | hfmpsmbus->Init.OwnAddress2 | (hfmpsmbus->Init.OwnAddress2Masks << 8U)); + hfmpsmbus->Instance->OAR2 = (hfmpsmbus->Init.DualAddressMode | hfmpsmbus->Init.OwnAddress2 | \ + (hfmpsmbus->Init.OwnAddress2Masks << 8U)); /*---------------------------- FMPSMBUSx CR1 Configuration ------------------------*/ /* Configure FMPSMBUSx: Generalcall and NoStretch mode */ - hfmpsmbus->Instance->CR1 = (hfmpsmbus->Init.GeneralCallMode | hfmpsmbus->Init.NoStretchMode | hfmpsmbus->Init.PacketErrorCheckMode | hfmpsmbus->Init.PeripheralMode | hfmpsmbus->Init.AnalogFilter); + hfmpsmbus->Instance->CR1 = (hfmpsmbus->Init.GeneralCallMode | hfmpsmbus->Init.NoStretchMode | \ + hfmpsmbus->Init.PacketErrorCheckMode | hfmpsmbus->Init.PeripheralMode | \ + hfmpsmbus->Init.AnalogFilter); - /* Enable Slave Byte Control only in case of Packet Error Check is enabled and FMPSMBUS Peripheral is set in Slave mode */ - if ((hfmpsmbus->Init.PacketErrorCheckMode == FMPSMBUS_PEC_ENABLE) - && ((hfmpsmbus->Init.PeripheralMode == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || (hfmpsmbus->Init.PeripheralMode == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP))) + /* Enable Slave Byte Control only in case of Packet Error Check is enabled + and FMPSMBUS Peripheral is set in Slave mode */ + if ((hfmpsmbus->Init.PacketErrorCheckMode == FMPSMBUS_PEC_ENABLE) && \ + ((hfmpsmbus->Init.PeripheralMode == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \ + (hfmpsmbus->Init.PeripheralMode == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP))) { hfmpsmbus->Instance->CR1 |= FMPI2C_CR1_SBC; } @@ -582,8 +587,9 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, - pFMPSMBUS_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, + pFMPSMBUS_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -696,7 +702,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbu * @arg @ref HAL_FMPSMBUS_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -791,7 +798,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsm * @param pCallback pointer to the Address Match Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, pFMPSMBUS_AddrCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, + pFMPSMBUS_AddrCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -915,8 +923,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf * @param XferOptions Options of Transfer, value of @ref FMPSMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t tmp; @@ -956,7 +964,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE)) { FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, - FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_GENERATE_START_WRITE); + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_GENERATE_START_WRITE); } else { @@ -966,9 +975,11 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm /* Store current volatile XferOptions, misra rule */ tmp = hfmpsmbus->XferOptions; - if ((hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) && (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + if ((hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) && \ + (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, + FMPSMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -977,7 +988,9 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm FMPSMBUS_ConvertOtherXferOptions(hfmpsmbus); /* Handle Transfer */ - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_GENERATE_START_WRITE); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, + hfmpsmbus->XferOptions, + FMPSMBUS_GENERATE_START_WRITE); } /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ @@ -1058,7 +1071,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE)) { FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, - FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_GENERATE_START_READ); + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_GENERATE_START_READ); } else { @@ -1068,9 +1082,11 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb /* Store current volatile XferOptions, Misra rule */ tmp = hfmpsmbus->XferOptions; - if ((hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX) && (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + if ((hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX) && \ + (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, + FMPSMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -1079,7 +1095,9 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb FMPSMBUS_ConvertOtherXferOptions(hfmpsmbus); /* Handle Transfer */ - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_GENERATE_START_READ); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, + hfmpsmbus->XferOptions, + FMPSMBUS_GENERATE_START_READ); } } @@ -1223,12 +1241,14 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmb if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE)) { FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, - FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ - FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, + FMPSMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ @@ -1314,7 +1334,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbu /* This RELOAD bit will be reset for last BYTE to be receive in FMPSMBUS_Slave_ISR */ if (((FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) && (hfmpsmbus->XferSize == 2U)) || (hfmpsmbus->XferSize == 1U)) { - FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, + FMPSMBUS_NO_STARTSTOP); } else { @@ -1577,7 +1598,8 @@ void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) uint32_t tmpcr1value = READ_REG(hfmpsmbus->Instance->CR1); /* FMPSMBUS in mode Transmitter ---------------------------------------------------*/ - if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) && + if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | + FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TXIS) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || @@ -1601,7 +1623,8 @@ void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) } /* FMPSMBUS in mode Receiver ----------------------------------------------------*/ - if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) && + if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | + FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_RXNE) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || @@ -1721,7 +1744,8 @@ __weak void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus) * @param AddrMatchCode Address Match Code * @retval None */ -__weak void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) +__weak void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode) { /* Prevent unused argument(s) compilation warning */ UNUSED(hfmpsmbus); @@ -1968,13 +1992,15 @@ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE) { FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, MAX_NBYTE_SIZE, - (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), FMPSMBUS_NO_STARTSTOP); + (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), + FMPSMBUS_NO_STARTSTOP); hfmpsmbus->XferSize = MAX_NBYTE_SIZE; } else { hfmpsmbus->XferSize = hfmpsmbus->XferCount; - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, + FMPSMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) @@ -2226,7 +2252,9 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u else { /* Set Reload for next Bytes */ - FMPSMBUS_TransferConfig(hfmpsmbus, 0, 1, FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, 0, 1, + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_NO_STARTSTOP); /* Ack last Byte Read */ hfmpsmbus->Instance->CR2 &= ~FMPI2C_CR2_NACK; @@ -2238,14 +2266,16 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u { if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE) { - FMPSMBUS_TransferConfig(hfmpsmbus, 0, MAX_NBYTE_SIZE, (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), + FMPSMBUS_TransferConfig(hfmpsmbus, 0, MAX_NBYTE_SIZE, + (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), FMPSMBUS_NO_STARTSTOP); hfmpsmbus->XferSize = MAX_NBYTE_SIZE; } else { hfmpsmbus->XferSize = hfmpsmbus->XferCount; - FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, + FMPSMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) @@ -2490,7 +2520,8 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) uint32_t tmperror; /* FMPSMBUS Bus error interrupt occurred ------------------------------------*/ - if (((itflags & FMPSMBUS_FLAG_BERR) == FMPSMBUS_FLAG_BERR) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + if (((itflags & FMPSMBUS_FLAG_BERR) == FMPSMBUS_FLAG_BERR) && \ + ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) { hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_BERR; @@ -2499,7 +2530,8 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) } /* FMPSMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if (((itflags & FMPSMBUS_FLAG_OVR) == FMPSMBUS_FLAG_OVR) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + if (((itflags & FMPSMBUS_FLAG_OVR) == FMPSMBUS_FLAG_OVR) && \ + ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) { hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_OVR; @@ -2508,7 +2540,8 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) } /* FMPSMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ - if (((itflags & FMPSMBUS_FLAG_ARLO) == FMPSMBUS_FLAG_ARLO) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + if (((itflags & FMPSMBUS_FLAG_ARLO) == FMPSMBUS_FLAG_ARLO) && \ + ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) { hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ARLO; @@ -2517,7 +2550,8 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) } /* FMPSMBUS Timeout error interrupt occurred ---------------------------------------------*/ - if (((itflags & FMPSMBUS_FLAG_TIMEOUT) == FMPSMBUS_FLAG_TIMEOUT) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + if (((itflags & FMPSMBUS_FLAG_TIMEOUT) == FMPSMBUS_FLAG_TIMEOUT) && \ + ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) { hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_BUSTIMEOUT; @@ -2526,7 +2560,8 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) } /* FMPSMBUS Alert error interrupt occurred -----------------------------------------------*/ - if (((itflags & FMPSMBUS_FLAG_ALERT) == FMPSMBUS_FLAG_ALERT) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + if (((itflags & FMPSMBUS_FLAG_ALERT) == FMPSMBUS_FLAG_ALERT) && \ + ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) { hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ALERT; @@ -2535,7 +2570,8 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) } /* FMPSMBUS Packet Error Check error interrupt occurred ----------------------------------*/ - if (((itflags & FMPSMBUS_FLAG_PECERR) == FMPSMBUS_FLAG_PECERR) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + if (((itflags & FMPSMBUS_FLAG_PECERR) == FMPSMBUS_FLAG_PECERR) && \ + ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) { hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_PECERR; @@ -2583,8 +2619,8 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status, - uint32_t Timeout) +static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2633,8 +2669,8 @@ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef * @arg @ref FMPSMBUS_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request) +static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance)); @@ -2645,9 +2681,10 @@ static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t MODIFY_REG(hfmpsmbus->Instance->CR2, ((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | \ (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - FMPI2C_CR2_RD_WRN_Pos))) | \ - FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_PECBYTE)), \ + FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_PECBYTE)), \ (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | \ - (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request)); } /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus_ex.c index 119c76f9b2..e5147ca66a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus_ex.c @@ -63,15 +63,14 @@ * @{ */ -/** @defgroup FMPSMBUSEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * +/** @defgroup FMPSMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * @verbatim =============================================================================== - ##### Extended features functions ##### + ##### Fast Mode Plus Functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Configure Fast Mode Plus @endverbatim @@ -83,10 +82,10 @@ * @param ConfigFastModePlus Selects the pin. * This parameter can be one of the @ref FMPSMBUSEx_FastModePlus values * @note For FMPI2C1, fast mode plus driving capability can be enabled on all selected - * FMPI2C1 pins using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter or independently + * FMPI2C1 pins using FMPSMBUS_FASTMODEPLUS_FMPI2C1 parameter or independently * on each one of the following pins PB6, PB7, PB8 and PB9. * @note For remaining FMPI2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be enabled only by using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter. + * can be enabled only by using FMPSMBUS_FASTMODEPLUS_FMPI2C1 parameter. * @retval None */ void HAL_FMPSMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus) @@ -106,10 +105,10 @@ void HAL_FMPSMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus) * @param ConfigFastModePlus Selects the pin. * This parameter can be one of the @ref FMPSMBUSEx_FastModePlus values * @note For FMPI2C1, fast mode plus driving capability can be disabled on all selected - * FMPI2C1 pins using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter or independently + * FMPI2C1 pins using FMPSMBUS_FASTMODEPLUS_FMPI2C1 parameter or independently * on each one of the following pins PB6, PB7, PB8 and PB9. * @note For remaining FMPI2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be disabled only by using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter. + * can be disabled only by using FMPSMBUS_FASTMODEPLUS_FMPI2C1 parameter. * @retval None */ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus) @@ -124,6 +123,9 @@ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus) CLEAR_BIT(SYSCFG->CFGR, (uint32_t)ConfigFastModePlus); } +/** + * @} + */ /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c index c03bdd8c23..cc28b03844 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c @@ -172,7 +172,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) @@ -200,12 +199,15 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Configure the IO Output Type */ temp = GPIOx->OTYPER; temp &= ~(GPIO_OTYPER_OT_0 << position) ; - temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); GPIOx->OTYPER = temp; } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) { + /* Check the parameters */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); @@ -233,7 +235,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ - if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); @@ -246,7 +248,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Clear EXTI line configuration */ temp = EXTI->IMR; temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + if((GPIO_Init->Mode & EXTI_IT) != 0x00U) { temp |= iocurrent; } @@ -254,7 +256,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp = EXTI->EMR; temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) { temp |= iocurrent; } @@ -263,7 +265,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) { temp |= iocurrent; } @@ -271,7 +273,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp = EXTI->FTSR; temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) { temp |= iocurrent; } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c index 18f4e3bd4c..6ab4a3d37b 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c @@ -61,7 +61,6 @@ */ #ifdef HAL_HCD_MODULE_ENABLED - #if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** @defgroup HCD HCD @@ -495,7 +494,8 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t i, interrupt; + uint32_t i; + uint32_t interrupt; /* Ensure that we are in device mode */ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) @@ -537,14 +537,19 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) { + /* Flush USB Fifo */ + (void)USB_FlushTxFifo(USBx, 0x10U); + (void)USB_FlushRxFifo(USBx); + + /* Restore FS Clock */ + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + /* Handle Host Port Disconnect Interrupt */ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->DisconnectCallback(hhcd); #else HAL_HCD_Disconnect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - - (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); } } @@ -961,7 +966,8 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef * /** * @brief Unregister the USB HCD Host Channel Notify URB Change Callback - * USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * USB HCD Host Channel Notify URB Change Callback is redirected + * to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback * @param hhcd HCD handle * @retval HAL status */ @@ -1019,8 +1025,11 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) { __HAL_LOCK(hhcd); - __HAL_HCD_ENABLE(hhcd); + /* Enable port power */ (void)USB_DriveVbus(hhcd->Instance, 1U); + + /* Enable global interrupt */ + __HAL_HCD_ENABLE(hhcd); __HAL_UNLOCK(hhcd); return HAL_OK; @@ -1475,7 +1484,8 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { hhcd->hc[ch_num].ErrCnt = 0U; hhcd->hc[ch_num].urb_state = URB_ERROR; - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, + hhcd->hc[ch_num].urb_state); } else { @@ -1502,21 +1512,19 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) || (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)) { - if (hhcd->Init.dma_enable == 1U) + if (hhcd->Init.dma_enable == 0U) { - if (hhcd->hc[ch_num].xfer_len > 0U) - { - num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet; - - if ((num_packets & 1U) != 0U) - { - hhcd->hc[ch_num].toggle_out ^= 1U; - } - } + hhcd->hc[ch_num].toggle_out ^= 1U; } - else + + if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[ch_num].xfer_len > 0U)) { - hhcd->hc[ch_num].toggle_out ^= 1U; + num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet; + + if ((num_packets & 1U) != 0U) + { + hhcd->hc[ch_num].toggle_out ^= 1U; + } } } } @@ -1641,7 +1649,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - __IO uint32_t hprt0, hprt0_dup; + __IO uint32_t hprt0; + __IO uint32_t hprt0_dup; /* Handle Host Port Interrupts */ hprt0 = USBx_HPRT0; @@ -1661,7 +1670,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) HAL_HCD_Connect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } - hprt0_dup |= USB_OTG_HPRT_PCDET; + hprt0_dup |= USB_OTG_HPRT_PCDET; } /* Check whether Port Enable Changed */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c index cdf4ac7196..dfe5e62370 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c @@ -19,7 +19,7 @@ (#) Declare a I2C_HandleTypeDef handle structure, for example: I2C_HandleTypeDef hi2c; - (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: (##) Enable the I2Cx interface clock (##) I2C pins configuration (+++) Enable the clock for the I2C GPIOs @@ -39,48 +39,48 @@ (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. - (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit() API. + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit() API. - (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= [..] - (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() *** Polling mode IO MEM operation *** ===================================== [..] - (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() *** Interrupt mode or DMA mode IO sequential operation *** ========================================================== @@ -89,14 +89,14 @@ when a direction change during transfer [..] (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through @ref I2C_XferOptions_definition and are listed below: + (+) Option field values are defined through I2C_XferOptions_definition and are listed below: (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition, an then permit a call the same master sequential interface - several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() - or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) + several times (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address and with new data to transfer if the direction change or manage only the new data to transfer if no direction change and without a final stop condition in both cases @@ -120,85 +120,85 @@ Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. (+) Different sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() - or using @ref HAL_I2C_Master_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() - or using @ref HAL_I2C_Master_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Transmit_IT() + or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Receive_IT() + or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() - or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() - or using @ref HAL_I2C_Slave_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Transmit_IT() + or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Receive_IT() + or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** Interrupt mode IO MEM operation *** ======================================= [..] (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - @ref HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - @ref HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() *** DMA mode IO MEM operation *** ================================= [..] (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - @ref HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - @ref HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** I2C HAL driver macros list *** @@ -206,22 +206,22 @@ [..] Below the list of most used macros in I2C HAL driver. - (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) @ref __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not - (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() to register an interrupt callback. [..] - Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + Function HAL_I2C_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. @@ -236,11 +236,11 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). [..] - Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. @@ -255,24 +255,24 @@ (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. [..] - For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). [..] - By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() - or @ref HAL_I2C_Init() function. + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. [..] When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -1695,9 +1695,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->Devaddress = DevAddress; - /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); - /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1707,6 +1704,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Enable EVT, BUF and ERR interrupt */ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + return HAL_OK; } else @@ -1775,11 +1775,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->Devaddress = DevAddress; - /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1791,6 +1786,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Enable EVT, BUF and ERR interrupt */ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + return HAL_OK; } else @@ -2020,12 +2021,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t if (dmaxferstatus == HAL_OK) { - /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); - /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2038,6 +2033,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Enable DMA Request */ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); } else { @@ -2214,12 +2215,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D } else { - /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); - /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2229,6 +2224,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Enable EVT, BUF and ERR interrupt */ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); } return HAL_OK; @@ -3087,6 +3088,10 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; if (hi2c->XferSize > 0U) { @@ -3267,6 +3272,10 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; if (hi2c->XferSize > 0U) { @@ -4823,13 +4832,16 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* BTF set -------------------------------------------------------------*/ else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) { - if (CurrentMode == HAL_I2C_MODE_MASTER) + if (CurrentState == HAL_I2C_STATE_BUSY_TX) { I2C_MasterTransmit_BTF(hi2c); } else /* HAL_I2C_MODE_MEM */ { - I2C_MemoryTransmit_TXE_BTF(hi2c); + if (CurrentMode == HAL_I2C_MODE_MEM) + { + I2C_MemoryTransmit_TXE_BTF(hi2c); + } } } else @@ -5383,13 +5395,25 @@ static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) hi2c->PreviousState = I2C_STATE_NONE; hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MasterTxCpltCallback(hi2c); + hi2c->MasterTxCpltCallback(hi2c); #else - HAL_I2C_MasterTxCpltCallback(hi2c); + HAL_I2C_MasterTxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } } } } @@ -5442,6 +5466,8 @@ static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) { /* Generate Restart */ hi2c->Instance->CR1 |= I2C_CR1_START; + + hi2c->EventCount++; } else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) { @@ -6111,7 +6137,7 @@ static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags) else { /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); /* Process Unlocked */ __HAL_UNLOCK(hi2c); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c index 5febc391a8..332b6c2cae 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c @@ -303,12 +303,12 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ -#endif +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ -#endif +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ if (hi2s->MspInitCallback == NULL) @@ -368,7 +368,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) } #else i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S); -#endif +#endif /* I2S_APB1_APB2_FEATURE */ /* Compute the Real divider depending on the MCLK output state, with a floating point */ if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) @@ -603,7 +603,7 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call case HAL_I2S_TX_RX_COMPLETE_CB_ID : hi2s->TxRxCpltCallback = pCallback; break; -#endif +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ case HAL_I2S_TX_HALF_COMPLETE_CB_ID : hi2s->TxHalfCpltCallback = pCallback; @@ -617,7 +617,7 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID : hi2s->TxRxHalfCpltCallback = pCallback; break; -#endif +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ case HAL_I2S_ERROR_CB_ID : hi2s->ErrorCallback = pCallback; @@ -706,7 +706,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca case HAL_I2S_TX_RX_COMPLETE_CB_ID : hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ break; -#endif +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ case HAL_I2S_TX_HALF_COMPLETE_CB_ID : hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ @@ -720,7 +720,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID : hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ break; -#endif +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ case HAL_I2S_ERROR_CB_ID : hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c index 511a5bf826..29974d61b3 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c @@ -111,8 +111,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback. - Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks: + Use Function HAL_IRDA_RegisterCallback() to register a user callback. + Function HAL_IRDA_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -127,9 +127,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default + Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -144,13 +144,13 @@ (+) MspDeInitCallback : IRDA MspDeInit. [..] - By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET + By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback(). + examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init() - and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init() + and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -159,8 +159,8 @@ in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit() - or @ref HAL_IRDA_Init() function. + using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit() + or HAL_IRDA_Init() function. [..] When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or @@ -169,7 +169,7 @@ @endverbatim [..] - (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written + (@) Additional remark: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. Depending on the frame length defined by the M bit (8-bits or 9-bits), the possible IRDA frame formats are as listed in the following table: @@ -786,7 +786,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u hirda->ErrorCode = HAL_IRDA_ERROR_NONE; hirda->gState = HAL_IRDA_STATE_BUSY_TX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); hirda->TxXferSize = Size; @@ -871,7 +871,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui hirda->ErrorCode = HAL_IRDA_ERROR_NONE; hirda->RxState = HAL_IRDA_STATE_BUSY_RX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); hirda->RxXferSize = Size; @@ -1223,7 +1223,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) /* Clear the Overrun flag before resuming the Rx transfer */ __HAL_IRDA_CLEAR_OREFLAG(hirda); - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c index 6cbbc24ecf..5f376dac6c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c @@ -115,11 +115,13 @@ /* Status register needs up to 5 LSI clock periods divided by the clock prescaler to be updated. The number of LSI clock periods is upper-rounded to 6 for the timeout value calculation. - The timeout value is also calculated using the highest prescaler (256) and + The timeout value is calculated using the highest prescaler (256) and the LSI_VALUE constant. The value of this constant can be changed by the user to take into account possible LSI clock period variations. - The timeout value is multiplied by 1000 to be converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE) + The timeout value is multiplied by 1000 to be converted in milliseconds. + LSI startup time is also considered here by adding LSI_STARTUP_TIMEOUT + converted in milliseconds. */ +#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_RVU | IWDG_SR_PVU) /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c index e287795796..0ed761721e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c @@ -93,13 +93,13 @@ The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback. - @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, + Use Function HAL_LPTIM_RegisterCallback() to register a callback. + HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the + Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] These functions allow to register/unregister following callbacks: @@ -117,7 +117,7 @@ [..] By default, after the Init and when the state is HAL_LPTIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: - examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback(). + examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback(). [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak @@ -131,7 +131,7 @@ in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. + using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. [..] When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or @@ -233,7 +233,7 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) - || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); @@ -277,7 +277,7 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) tmpcfgr = hlptim->Instance->CFGR; if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) - || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); } @@ -308,7 +308,7 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Configure LPTIM external clock polarity and digital filter */ if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) - || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | hlptim->Init.UltraLowPowerClock.SampleTime); @@ -520,7 +520,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -656,7 +656,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the TIM state*/ + /* Change the LPTIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -743,7 +743,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -879,7 +879,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the TIM state*/ + /* Change the LPTIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -966,7 +966,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1102,7 +1102,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the TIM state*/ + /* Change the LPTIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -2183,39 +2183,48 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti switch (CallbackID) { case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + /* Legacy weak MspInit Callback */ + hlptim->MspInitCallback = HAL_LPTIM_MspInit; break; case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + /* Legacy weak Msp DeInit Callback */ + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; break; case HAL_LPTIM_COMPARE_MATCH_CB_ID : - hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare match Callback */ + /* Legacy weak Compare match Callback */ + hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; break; case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : - hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto-reload match Callback */ + /* Legacy weak Auto-reload match Callback */ + hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; break; case HAL_LPTIM_TRIGGER_CB_ID : - hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak External trigger event detection Callback */ + /* Legacy weak External trigger event detection Callback */ + hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; break; case HAL_LPTIM_COMPARE_WRITE_CB_ID : - hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare register write complete Callback */ + /* Legacy weak Compare register write complete Callback */ + hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; break; case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : - hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto-reload register write complete Callback */ + /* Legacy weak Auto-reload register write complete Callback */ + hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; break; case HAL_LPTIM_DIRECTION_UP_CB_ID : - hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Up-counting direction change Callback */ + /* Legacy weak Up-counting direction change Callback */ + hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; break; case HAL_LPTIM_DIRECTION_DOWN_CB_ID : - hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Down-counting direction change Callback */ + /* Legacy weak Down-counting direction change Callback */ + hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; break; default : @@ -2229,11 +2238,13 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti switch (CallbackID) { case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + /* Legacy weak MspInit Callback */ + hlptim->MspInitCallback = HAL_LPTIM_MspInit; break; case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + /* Legacy weak Msp DeInit Callback */ + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; break; default : @@ -2308,13 +2319,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) { /* Reset the LPTIM callback to the legacy weak callbacks */ - lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Compare match Callback */ - lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback */ - lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* External trigger event detection Callback */ - lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Compare register write complete Callback */ - lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */ - lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Up-counting direction change Callback */ - lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */ + lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; + lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; + lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; + lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; + lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; + lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; + lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; } #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c index 81e8348ee8..520efe12c4 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_mmc.c @@ -195,7 +195,7 @@ The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_MMC_RegisterCallback() to register a user callback, + Use Functions HAL_MMC_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -206,7 +206,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_MMC_UnRegisterCallback() to reset a callback to the default + Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -216,12 +216,12 @@ (+) MspDeInitCallback : MMC MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET + By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init - and @ref HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit + reset to the legacy weak (surcharged) functions in the HAL_MMC_Init + and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -229,8 +229,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit - or @ref HAL_MMC_Init function. + using HAL_MMC_RegisterCallback before calling HAL_MMC_DeInit + or HAL_MMC_Init function. When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c index 13aace25f3..aa9702eed3 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c @@ -224,7 +224,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->USB_Address = 0U; hpcd->State = HAL_PCD_STATE_READY; - #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) { @@ -721,7 +721,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, /** * @brief Unregister the USB PCD Iso OUT incomplete Callback - * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * USB PCD Iso OUT incomplete Callback is redirected + * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status */ @@ -795,7 +796,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, /** * @brief Unregister the USB PCD Iso IN incomplete Callback - * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * USB PCD Iso IN incomplete Callback is redirected + * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status */ @@ -1037,6 +1039,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) /* Disable USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); } + __HAL_UNLOCK(hpcd); return HAL_OK; @@ -1052,9 +1055,13 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t i, ep_intr, epint, epnum; - uint32_t fifoemptymsk, temp; USB_OTG_EPTypeDef *ep; + uint32_t i; + uint32_t ep_intr; + uint32_t epint; + uint32_t epnum; + uint32_t fifoemptymsk; + uint32_t temp; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) @@ -1651,19 +1658,16 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) { -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ __HAL_LOCK(hpcd); -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + if ((hpcd->Init.battery_charging_enable == 1U) && (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; } -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); @@ -1677,21 +1681,17 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) { -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ __HAL_LOCK(hpcd); (void)USB_DevDisconnect(hpcd->Instance); -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) if ((hpcd->Init.battery_charging_enable == 1U) && (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) { /* Disable USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); } -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ __HAL_UNLOCK(hpcd); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c index 51562ab8a1..7c7697c676 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c @@ -164,7 +164,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /* Enable DCD : Data Contact Detect */ USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; - /* Wait Detect flag or a timeout is happen*/ + /* Wait Detect flag or a timeout is happen */ while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U) { /* Check for the Timeout */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c index 0ca4380e65..688ce00b50 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c @@ -133,7 +133,7 @@ The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback, + Use Functions HAL_QSPI_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) ErrorCallback : callback when error occurs. (+) AbortCpltCallback : callback when abort is completed. @@ -150,7 +150,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default + Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) ErrorCallback : callback when error occurs. (+) AbortCpltCallback : callback when abort is completed. @@ -166,12 +166,12 @@ (+) MspDeInitCallback : QSPI MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET + By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init - and @ref HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit + reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init + and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -179,8 +179,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit - or @ref HAL_QSPI_Init function. + using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit + or HAL_QSPI_Init function. When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -258,6 +258,7 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma); static void QSPI_DMAError(DMA_HandleTypeDef *hdma); static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout); static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode); /* Exported functions --------------------------------------------------------*/ @@ -908,7 +909,7 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp hqspi->State = HAL_QSPI_STATE_BUSY; /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); if (status == HAL_OK) { @@ -964,6 +965,7 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp * @param pData : pointer to data buffer * @param Timeout : Timeout duration * @note This function is used only in Indirect Write Mode + * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) @@ -1542,15 +1544,46 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /* 4 Extra words (32-bits) are needed for read operation to guarantee the last data is transferred from DMA FIFO to RAM memory */ WRITE_REG(hqspi->Instance->DLR, (data_size - 1U + 16U)); + + /* Update direction mode bit */ + MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); + + /* Configure QSPI: CCR register with functional as indirect read */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Start the transfer by re-writing the address in AR register */ + WRITE_REG(hqspi->Instance->AR, addr_reg); + + /* Enable the DMA Channel */ + if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK) + { + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } #else /* Configure the direction of the DMA */ hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; -#endif + /* Update direction mode bit */ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); /* Enable the DMA Channel */ - if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK) + if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize)== HAL_OK) { /* Configure QSPI: CCR register with functional as indirect read */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); @@ -1576,6 +1609,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /* Process unlocked */ __HAL_UNLOCK(hqspi); } +#endif /* QSPI1_V2_1L */ } } else @@ -1710,7 +1744,6 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg) { HAL_StatusTypeDef status; - uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); @@ -1754,7 +1787,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); if (status == HAL_OK) { @@ -2673,6 +2706,31 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp return HAL_OK; } +/** + * @brief Wait for a flag state until timeout using CPU cycle. + * @param hqspi : QSPI handle + * @param Flag : Flag checked + * @param State : Value of the flag expected + * @param Timeout : Duration of the timeout + * @retval HAL status + */ +static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout) +{ + __IO uint32_t count = Timeout * (SystemCoreClock / 16U / 1000U); + do + { + if (count-- == 0U) + { + hqspi->State = HAL_QSPI_STATE_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; + return HAL_TIMEOUT; + } + } + while ((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State); + + return HAL_OK; +} + /** * @brief Configure the communication registers. * @param hqspi : QSPI handle @@ -2840,6 +2898,6 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin * @} */ -#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ +#endif /* defined(QUADSPI) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c index 47c313c89f..a9b233837d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c @@ -31,8 +31,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_RNG_RegisterCallback() to register a user callback. - Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks: + Use Function HAL_RNG_RegisterCallback() to register a user callback. + Function HAL_RNG_RegisterCallback() allows to register following callbacks: (+) ErrorCallback : RNG Error Callback. (+) MspInitCallback : RNG MspInit. (+) MspDeInitCallback : RNG MspDeInit. @@ -40,9 +40,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default + Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ErrorCallback : RNG Error Callback. @@ -51,16 +51,16 @@ [..] For specific callback ReadyDataCallback, use dedicated register callbacks: - respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback(). + respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback(). [..] - By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET + By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - example @ref HAL_RNG_ErrorCallback(). + example HAL_RNG_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init() - and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_RNG_Init() + and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -69,8 +69,8 @@ in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit() - or @ref HAL_RNG_Init() function. + using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit() + or HAL_RNG_Init() function. [..] When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or @@ -129,8 +129,8 @@ */ /** @addtogroup RNG_Exported_Functions_Group1 - * @brief Initialization and configuration functions - * + * @brief Initialization and configuration functions + * @verbatim =============================================================================== ##### Initialization and configuration functions ##### @@ -296,7 +296,8 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -515,8 +516,8 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng) */ /** @addtogroup RNG_Exported_Functions_Group2 - * @brief Peripheral Control functions - * + * @brief Peripheral Control functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -562,11 +563,15 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - return HAL_ERROR; + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } } } @@ -726,6 +731,8 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) /* Clear the clock error flag */ __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI); + + return; } /* Check RNG data ready interrupt occurred */ @@ -803,8 +810,8 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) /** @addtogroup RNG_Exported_Functions_Group3 - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -832,7 +839,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) * @brief Return the RNG handle error code. * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval RNG Error Code -*/ + */ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) { /* Return RNG Error Code */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c index c12879e307..00f9e4b03e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c @@ -108,10 +108,10 @@ [..] The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback. + Use Function HAL_RTC_RegisterCallback() to register an interrupt callback. [..] - Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks: + Function HAL_RTC_RegisterCallback() allows to register following callbacks: (+) AlarmAEventCallback : RTC Alarm A Event callback. (+) AlarmBEventCallback : RTC Alarm B Event callback. (+) TimeStampEventCallback : RTC TimeStamp Event callback. @@ -125,9 +125,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default + Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) AlarmAEventCallback : RTC Alarm A Event callback. @@ -140,13 +140,13 @@ (+) MspDeInitCallback : RTC MspDeInit callback. [..] - By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, + By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, all callbacks are set to the corresponding weak functions : - examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback(). + examples AlarmAEventCallback(), WakeUpTimerEventCallback(). Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function - in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null + in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() + If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) [..] @@ -155,8 +155,8 @@ in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit() - or @ref HAL_RTC_Init() function. + using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() + or HAL_RTC_Init() function. [..] When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or @@ -1765,9 +1765,8 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) */ void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) { - UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - SET_BIT(RTC->CR, RTC_CR_ADD1H); + SET_BIT(hrtc->Instance->CR, RTC_CR_ADD1H); __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } @@ -1779,9 +1778,8 @@ void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) */ void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) { - UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - SET_BIT(RTC->CR, RTC_CR_SUB1H); + SET_BIT(hrtc->Instance->CR, RTC_CR_SUB1H); __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } @@ -1793,9 +1791,8 @@ void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) */ void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) { - UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - SET_BIT(RTC->CR, RTC_CR_BKP); + SET_BIT(hrtc->Instance->CR, RTC_CR_BKP); __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } @@ -1806,9 +1803,8 @@ void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) */ void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) { - UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - CLEAR_BIT(RTC->CR, RTC_CR_BKP); + CLEAR_BIT(hrtc->Instance->CR, RTC_CR_BKP); __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } @@ -1819,8 +1815,7 @@ void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) */ uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) { - UNUSED(hrtc); - return READ_BIT(RTC->CR, RTC_CR_BKP); + return READ_BIT(hrtc->Instance->CR, RTC_CR_BKP); } /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c index a488bfa69d..994ba0c57f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c @@ -199,7 +199,7 @@ The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SD_RegisterCallback() to register a user callback, + Use Functions HAL_SD_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -210,7 +210,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default + Use function HAL_SD_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -220,12 +220,12 @@ (+) MspDeInitCallback : SD MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET + By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init - and @ref HAL_SD_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit + reset to the legacy weak (surcharged) functions in the HAL_SD_Init + and HAL_SD_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -233,8 +233,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit - or @ref HAL_SD_Init function. + using HAL_SD_RegisterCallback before calling HAL_SD_DeInit + or HAL_SD_Init function. When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c index 71a6c154c8..6746744c03 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c @@ -105,8 +105,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback. - Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: + Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback. + Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : Tx Complete Callback. (+) RxCpltCallback : Rx Complete Callback. (+) ErrorCallback : Error Callback. @@ -119,9 +119,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default + Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : Tx Complete Callback. @@ -134,13 +134,13 @@ (+) MspDeInitCallback : SMARTCARD MspDeInit. [..] - By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET + By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback(). + examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init() - and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init() + and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -149,8 +149,8 @@ in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit() - or @ref HAL_SMARTCARD_Init() function. + using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit() + or HAL_SMARTCARD_Init() function. [..] When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c index 15026b467e..09df379bc9 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smbus.c @@ -20,7 +20,7 @@ (#) Declare a SMBUS_HandleTypeDef handle structure, for example: SMBUS_HandleTypeDef hsmbus; - (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API: + (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: (##) Enable the SMBUSx interface clock (##) SMBUS pins configuration (+++) Enable the clock for the SMBUS GPIOs @@ -32,10 +32,10 @@ (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, Dual Addressing mode, Own Address2, General call and Nostretch mode in the hsmbus Init structure. - (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API. + (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_SMBUS_MspInit(&hsmbus) API. - (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady() + (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() (#) For SMBUS IO operations, only one mode of operations is available within this driver : @@ -44,35 +44,35 @@ =================================== [..] - (+) Transmit in master/host SMBUS mode an amount of data in non blocking mode using @ref HAL_SMBUS_Master_Transmit_IT() - (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback() - (+) Receive in master/host SMBUS mode an amount of data in non blocking mode using @ref HAL_SMBUS_Master_Receive_IT() - (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback() - (+) Abort a master/Host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT() - (++) End of abort process, @ref HAL_SMBUS_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_AbortCpltCallback() + (+) Transmit in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback() + (+) Receive in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback() + (+) Abort a master/Host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT() + (++) End of abort process, HAL_SMBUS_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_AbortCpltCallback() (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode - using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT() - (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can + using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT() + (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). - (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback() - (+) Transmit in slave/device SMBUS mode an amount of data in non blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT() - (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback() - (+) Receive in slave/device SMBUS mode an amount of data in non blocking mode using @ref HAL_SMBUS_Slave_Receive_IT() - (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback() - (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() and @ref HAL_SMBUS_DisableAlert_IT() - (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() - to check the Alert Error Code using function @ref HAL_SMBUS_GetError() - (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or HAL_SMBUS_GetError() - (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() - to check the Error Code using function @ref HAL_SMBUS_GetError() + (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback() + (+) Transmit in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback() + (+) Receive in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback() + (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() and HAL_SMBUS_DisableAlert_IT() + (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Alert Error Code using function HAL_SMBUS_GetError() + (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError() + (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Error Code using function HAL_SMBUS_GetError() *** SMBUS HAL driver macros list *** @@ -80,12 +80,12 @@ [..] Below the list of most used macros in SMBUS HAL driver. - (+) @ref __HAL_SMBUS_ENABLE : Enable the SMBUS peripheral - (+) @ref __HAL_SMBUS_DISABLE : Disable the SMBUS peripheral - (+) @ref __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not - (+) @ref __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag - (+) @ref __HAL_SMBUS_ENABLE_IT : Enable the specified SMBUS interrupt - (+) @ref __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt + (+) __HAL_SMBUS_ENABLE : Enable the SMBUS peripheral + (+) __HAL_SMBUS_DISABLE : Disable the SMBUS peripheral + (+) __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not + (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag + (+) __HAL_SMBUS_ENABLE_IT : Enable the specified SMBUS interrupt + (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt [..] (@) You can refer to the SMBUS HAL driver header file for more useful macros @@ -95,10 +95,10 @@ [..] The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterXXXCallback() + Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterXXXCallback() to register an interrupt callback. - Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks: + Function HAL_SMBUS_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. @@ -111,11 +111,11 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback(). + For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback(). [..] - Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default + Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. @@ -128,24 +128,24 @@ (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. [..] - For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback(). + For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback(). [..] - By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_SMBUS_STATE_RESET + By default, after the HAL_SMBUS_Init() and when the state is HAL_SMBUS_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback(). + examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when + reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() + If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_SMBUS_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_SMBUS_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_SMBUS_STATE_READY or @ref HAL_SMBUS_STATE_RESET state, + in HAL_SMBUS_STATE_READY or HAL_SMBUS_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit() - or @ref HAL_SMBUS_Init() function. + using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit() + or HAL_SMBUS_Init() function. [..] When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -359,7 +359,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx CR1 Configuration ----------------------*/ /* Configure SMBUSx: Generalcall , PEC , Peripheral mode and NoStretch mode */ - MODIFY_REG(hsmbus->Instance->CR1, (I2C_CR1_NOSTRETCH | I2C_CR1_ENGC | I2C_CR1_PEC | I2C_CR1_ENARP | I2C_CR1_SMBTYPE | I2C_CR1_SMBUS), (hsmbus->Init.NoStretchMode | hsmbus->Init.GeneralCallMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode)); + MODIFY_REG(hsmbus->Instance->CR1, (I2C_CR1_NOSTRETCH | I2C_CR1_ENGC | I2C_CR1_ENPEC | I2C_CR1_ENARP | I2C_CR1_SMBTYPE | I2C_CR1_SMBUS), (hsmbus->Init.NoStretchMode | hsmbus->Init.GeneralCallMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode)); /*---------------------------- SMBUSx OAR1 Configuration ---------------------*/ /* Configure SMBUSx: Own Address1 and addressing mode */ @@ -1706,7 +1706,7 @@ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ if (((sr1itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERR) != RESET)) { - hsmbus->ErrorCode |= SMBUS_FLAG_PECERR; + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; /* Clear PEC error flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); @@ -1963,7 +1963,7 @@ static HAL_StatusTypeDef SMBUS_MasterTransmit_TXE(SMBUS_HandleTypeDef *hsmbus) #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } } - else if ((CurrentState == HAL_SMBUS_STATE_BUSY_TX)) + else if (CurrentState == HAL_SMBUS_STATE_BUSY_TX) { if ((hsmbus->XferCount == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) == SMBUS_PEC_ENABLE) && ((hsmbus->XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || (hsmbus->XferOptions == SMBUS_LAST_FRAME_WITH_PEC))) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c index 85742889ad..8e53f3f9fd 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c @@ -1134,13 +1134,13 @@ error : HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { -#if (USE_SPI_CRC != 0U) - __IO uint32_t tmpreg = 0U; -#endif /* USE_SPI_CRC */ uint16_t initial_TxXferCount; uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; @@ -3156,12 +3156,15 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint32_t tmpreg = 0U; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC to flush Data Register */ - tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; /* To avoid GCC warning */ - UNUSED(tmpreg); + UNUSED(tmpreg8); /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); @@ -3311,12 +3314,15 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint32_t tmpreg = 0U; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC to flush Data Register */ - tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; /* To avoid GCC warning */ - UNUSED(tmpreg); + UNUSED(tmpreg8); SPI_CloseRx_ISR(hspi); } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c index 9f61754771..f3d46cdd34 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c @@ -103,14 +103,14 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_TIM_RegisterCallback() to register a callback. - @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] @@ -146,7 +146,7 @@ [..] By default, after the Init and when the state is HAL_TIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: - examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak @@ -160,7 +160,7 @@ all interrupt callbacks are set to the corresponding weak functions: in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. [..] When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or @@ -558,7 +558,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -874,6 +875,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -919,34 +921,38 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -962,6 +968,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -996,26 +1004,30 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1033,6 +1045,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1071,7 +1084,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1092,7 +1106,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1113,7 +1128,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1133,7 +1149,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1144,34 +1161,38 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1187,6 +1208,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1225,26 +1248,30 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1511,7 +1538,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1555,34 +1584,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1598,6 +1631,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1632,26 +1667,30 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1669,6 +1708,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1707,7 +1747,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1728,7 +1769,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1748,7 +1790,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1768,7 +1811,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1779,34 +1823,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } default: + status = HAL_ERROR; break; } - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1822,6 +1870,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1860,26 +1910,30 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2139,7 +2193,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); @@ -2188,27 +2244,32 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + if (status == HAL_OK) { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2224,6 +2285,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -2258,21 +2321,25 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2290,7 +2357,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); @@ -2322,6 +2391,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel return HAL_ERROR; } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + switch (Channel) { case TIM_CHANNEL_1: @@ -2334,7 +2406,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2354,7 +2427,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2374,7 +2448,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2394,7 +2469,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2405,12 +2481,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { @@ -2426,7 +2500,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2442,6 +2516,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); @@ -2484,18 +2560,22 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** * @} @@ -3548,7 +3628,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -3556,11 +3637,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); break; } @@ -3573,7 +3655,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -3581,15 +3664,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } - case TIM_CHANNEL_ALL: + default: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; @@ -3599,7 +3683,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -3613,27 +3698,27 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - default: + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + break; + } } /* Return function status */ @@ -3946,6 +4031,8 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); @@ -3997,12 +4084,13 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -4020,6 +4108,8 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); @@ -4076,7 +4166,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Set the IC3PSC value */ htim->Instance->CCMR2 |= sConfig->ICPrescaler; } - else + else if (Channel == TIM_CHANNEL_4) { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); @@ -4092,10 +4182,14 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } + else + { + status = HAL_ERROR; + } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -4115,6 +4209,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); @@ -4195,12 +4291,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -4225,6 +4322,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) { + HAL_StatusTypeDef status = HAL_OK; TIM_OC_InitTypeDef temp1; /* Check the parameters */ @@ -4255,6 +4353,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O TIM_OC1_SetConfig(htim->Instance, &temp1); break; } + case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); @@ -4262,60 +4361,67 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O TIM_OC2_SetConfig(htim->Instance, &temp1); break; } + default: + status = HAL_ERROR; break; } - switch (InputChannel) + if (status == HAL_OK) { - case TIM_CHANNEL_1: + switch (InputChannel) { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; - default: - break; + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; + } } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); - return HAL_OK; + return status; } else { @@ -4364,8 +4470,16 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { - return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); + HAL_StatusTypeDef status = HAL_OK; + + if (status == HAL_OK) + { + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + } + + + return status; } /** @@ -4411,6 +4525,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); @@ -4437,6 +4553,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint { /* nothing to do */ } + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: @@ -4450,7 +4567,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4468,7 +4585,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4486,7 +4603,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4504,7 +4621,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4522,7 +4639,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4540,7 +4657,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4558,7 +4675,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4566,16 +4683,20 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint break; } default: + status = HAL_ERROR; break; } - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -4586,6 +4707,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4628,17 +4751,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B break; } default: + status = HAL_ERROR; break; } - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -4682,8 +4809,15 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { - return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); + HAL_StatusTypeDef status = HAL_OK; + + if (status == HAL_OK) + { + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + } + + return status; } /** @@ -4729,6 +4863,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); @@ -4768,7 +4904,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4786,7 +4922,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4804,7 +4940,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4822,7 +4958,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4840,7 +4976,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4858,7 +4994,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4876,7 +5012,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4884,17 +5020,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 break; } default: + status = HAL_ERROR; break; } - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -4905,6 +5045,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4947,17 +5089,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu break; } default: + status = HAL_ERROR; break; } - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -5021,6 +5167,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); @@ -5062,76 +5210,80 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } - switch (Channel) + if (status == HAL_OK) { - case TIM_CHANNEL_1: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 1 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - break; - } - case TIM_CHANNEL_2: + switch (Channel) { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 2 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - else - { - /* Disable the OCREF clear feature for Channel 2 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - break; - } - case TIM_CHANNEL_3: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + case TIM_CHANNEL_1: { - /* Enable the OCREF clear feature for Channel 3 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; } - else + case TIM_CHANNEL_2: { - /* Disable the OCREF clear feature for Channel 3 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; } - break; - } - case TIM_CHANNEL_4: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + case TIM_CHANNEL_3: { - /* Enable the OCREF clear feature for Channel 4 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; } - else + case TIM_CHANNEL_4: { - /* Disable the OCREF clear feature for Channel 4 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; } - break; + default: + break; } - default: - break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -5143,6 +5295,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Process Locked */ @@ -5263,22 +5416,23 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo case TIM_CLOCKSOURCE_ITR1: case TIM_CLOCKSOURCE_ITR2: case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - break; - } + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } default: + status = HAL_ERROR; break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -5799,7 +5953,7 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } @@ -5865,14 +6019,14 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } else { /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; } /* Release Lock */ @@ -5928,116 +6082,143 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; case HAL_TIM_PERIOD_ELAPSED_CB_ID : - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; break; case HAL_TIM_TRIGGER_CB_ID : - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; break; case HAL_TIM_TRIGGER_HALF_CB_ID : - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; break; case HAL_TIM_IC_CAPTURE_CB_ID : - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; break; case HAL_TIM_ERROR_CB_ID : - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; break; case HAL_TIM_COMMUTATION_CB_ID : - htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; break; case HAL_TIM_COMMUTATION_HALF_CB_ID : - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; break; case HAL_TIM_BREAK_CB_ID : - htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; break; default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } @@ -6046,71 +6227,85 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } else { /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; } /* Release Lock */ @@ -6918,6 +7113,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; @@ -7014,16 +7210,18 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, case TIM_TS_ITR1: case TIM_TS_ITR2: case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - break; - } + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } default: + status = HAL_ERROR; break; } - return HAL_OK; + + return status; } /** @@ -7397,19 +7595,19 @@ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelStat void TIM_ResetCallback(TIM_HandleTypeDef *htim) { /* Reset the TIM callback to the legacy weak callbacks */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ - htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ - htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c index a0124f9318..bba44f15c6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c @@ -54,10 +54,13 @@ the commutation event). (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() - (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() - (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). @endverbatim ****************************************************************************** @@ -335,7 +338,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ @@ -367,7 +371,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the Peripheral */ @@ -418,7 +423,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ @@ -450,7 +456,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts event */ @@ -510,7 +517,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 } /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Set the DMA Input Capture 1 Callbacks */ @@ -557,7 +565,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); @@ -697,6 +706,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -736,34 +746,38 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann default: + status = HAL_ERROR; break; } - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -779,7 +793,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpccer; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -807,30 +823,34 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if (status == HAL_OK) { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -848,6 +868,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -886,7 +907,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -906,7 +928,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -926,7 +949,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -937,31 +961,35 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } default: + status = HAL_ERROR; break; } - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + if (status == HAL_OK) + { + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -977,6 +1005,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -1007,23 +1037,27 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1154,6 +1188,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1192,34 +1227,38 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan } default: + status = HAL_ERROR; break; } - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1235,6 +1274,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpccer; /* Check the parameters */ @@ -1264,30 +1304,34 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann } default: + status = HAL_ERROR; break; } - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if (status == HAL_OK) { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1305,6 +1349,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1343,7 +1388,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1363,7 +1409,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1383,7 +1430,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1394,31 +1442,35 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha } default: + status = HAL_ERROR; break; } - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + if (status == HAL_OK) + { + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1434,6 +1486,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -1464,23 +1518,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } default: + status = HAL_ERROR; break; } - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1529,7 +1587,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) @@ -1617,7 +1675,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c index a29865546a..5e53813c86 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c @@ -21,7 +21,7 @@ (##) Enable the USARTx interface clock. (##) UART pins configuration: (+++) Enable the clock for the UART GPIOs. - (+++) Configure these UART pins (TX as alternate function pull-up, RX as alternate function Input). + (+++) Configure the UART TX/RX pins as alternate function pull-up. (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() and HAL_UART_Receive_IT() APIs): (+++) Configure the USARTx interrupt priority. @@ -72,8 +72,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_UART_RegisterCallback() to register a user callback. - Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -88,9 +88,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -106,16 +106,16 @@ [..] For specific callback RxEventCallback, use dedicated registration/reset functions: - respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback(). + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). [..] - By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() - and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -124,8 +124,8 @@ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() - or @ref HAL_UART_Init() function. + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. [..] When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or @@ -299,7 +299,8 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); static void UART_SetConfig(UART_HandleTypeDef *huart); /** @@ -749,7 +750,8 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -1370,7 +1372,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - return(UART_Start_Receive_IT(huart, pData, Size)); + return (UART_Start_Receive_IT(huart, pData, Size)); } else { @@ -1435,7 +1437,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); return HAL_OK; } @@ -1473,7 +1475,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - return(UART_Start_Receive_DMA(huart, pData, Size)); + return (UART_Start_Receive_DMA(huart, pData, Size)); } else { @@ -1498,18 +1500,18 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) { /* Disable the UART DMA Tx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); } dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the UART DMA Rx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } /* Process Unlocked */ @@ -1532,7 +1534,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) if (huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); } if (huart->RxState == HAL_UART_STATE_BUSY_RX) @@ -1541,11 +1543,11 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) __HAL_UART_CLEAR_OREFLAG(huart); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Enable the UART DMA Rx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } /* Process Unlocked */ @@ -1573,7 +1575,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx stream */ if (huart->hdmatx != NULL) @@ -1587,7 +1589,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx stream */ if (huart->hdmarx != NULL) @@ -1615,7 +1617,8 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). * @retval HAL status */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout) +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) { uint8_t *pdata8bits; uint16_t *pdata16bits; @@ -1687,14 +1690,14 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p } else { - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) - { - *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); - } - else - { - *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); - } + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } pdata8bits++; } @@ -1766,7 +1769,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { __HAL_UART_CLEAR_IDLEFLAG(huart); - SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } else { @@ -1827,7 +1830,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { __HAL_UART_CLEAR_IDLEFLAG(huart); - SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } else { @@ -1858,23 +1861,23 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx stream: use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) @@ -1899,7 +1902,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx stream: use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) @@ -1947,16 +1950,16 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) @@ -1998,23 +2001,23 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) @@ -2059,19 +2062,19 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { uint32_t AbortCplt = 0x01U; /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised @@ -2109,7 +2112,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at UART level */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx stream : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) @@ -2132,7 +2135,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx stream : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) @@ -2194,16 +2197,16 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) @@ -2271,23 +2274,23 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) @@ -2371,7 +2374,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* If some errors occur */ - if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) @@ -2392,7 +2396,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* UART Over-Run interrupt occurred --------------------------------------*/ - if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) + if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) + || ((cr3its & USART_CR3_EIE) != RESET))) { huart->ErrorCode |= HAL_UART_ERROR_ORE; } @@ -2419,7 +2424,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx stream */ if (huart->hdmarx != NULL) @@ -2477,9 +2482,9 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Check current reception Mode : If Reception till IDLE event has been selected : */ - if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - &&((isrflags & USART_SR_IDLE) != 0U) - &&((cr1its & USART_SR_IDLE) != 0U)) + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_SR_IDLE) != 0U) + && ((cr1its & USART_SR_IDLE) != 0U)) { __HAL_UART_CLEAR_IDLEFLAG(huart); @@ -2491,8 +2496,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); - if ( (nb_remaining_rx_data > 0U) - &&(nb_remaining_rx_data < huart->RxXferSize)) + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; @@ -2501,18 +2506,18 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); @@ -2523,7 +2528,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); -#endif +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; } @@ -2533,27 +2538,27 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; - if ( (huart->RxXferCount > 0U) - &&(nb_rx_data > 0U) ) + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); -#endif +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; } @@ -2752,7 +2757,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Send break characters */ - SET_BIT(huart->Instance->CR1, USART_CR1_SBK); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_SBK); huart->gState = HAL_UART_STATE_READY; @@ -2779,7 +2784,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_RWU); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RWU); huart->gState = HAL_UART_STATE_READY; @@ -2806,7 +2811,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU); huart->gState = HAL_UART_STATE_READY; @@ -2984,10 +2989,10 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } /* DMA Circular mode */ @@ -3037,12 +3042,12 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) huart->RxXferCount = 0U; /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -3050,7 +3055,7 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } } @@ -3095,10 +3100,10 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize/2U); + huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize/2U); + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3161,7 +3166,8 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) @@ -3172,8 +3178,8 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; @@ -3267,14 +3273,14 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa __HAL_UNLOCK(huart); /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); return HAL_OK; } @@ -3287,7 +3293,7 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -3301,13 +3307,13 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } /* At end of Rx process, restore huart->RxState to Ready */ @@ -3606,8 +3612,18 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_IDLEFLAG(huart); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ @@ -3615,20 +3631,20 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else { - /* Standard reception API called */ + /* Standard reception API called */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + return HAL_OK; } return HAL_OK; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c index dfcb885127..aa6f021425 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c @@ -243,7 +243,8 @@ static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); /** * @} */ @@ -440,7 +441,8 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) * @param pCallback pointer to the Callback function * @retval HAL status + */ -HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -934,7 +936,8 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint8_t *prxdata8bits; uint16_t *prxdata16bits; @@ -1176,7 +1179,8 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx * @param Size Amount of data elements (u8 or u16) to be sent (same amount to be received). * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { if (husart->State == HAL_USART_STATE_READY) { @@ -1393,7 +1397,8 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { uint32_t *tmp; @@ -1576,7 +1581,7 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1642,7 +1647,7 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) { uint32_t AbortCplt = 0x01U; @@ -2295,7 +2300,8 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma) * @param Timeout Timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) @@ -2653,10 +2659,10 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { - pdata8bits = NULL; - pdata16bits = (uint16_t *) husart->pRxBuffPtr; - *pdata16bits = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); - husart->pRxBuffPtr += 2U; + pdata8bits = NULL; + pdata16bits = (uint16_t *) husart->pRxBuffPtr; + *pdata16bits = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); + husart->pRxBuffPtr += 2U; } else { diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c index 4ee3b346e3..e180e439ec 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c @@ -524,6 +524,11 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) ); + /* Reset register SQR3 */ + CLEAR_BIT(ADCx->SQR3, + ( ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 + | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1) + ); /* Reset register JSQR */ CLEAR_BIT(ADCx->JSQR, diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c index 821b281e8a..372e2f2723 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_crc.c @@ -26,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif/* USE_FULL_ASSERT */ /** @addtogroup STM32F4xx_LL_Driver * @{ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c index 7d7aeaaf82..8fcb2a1580 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c @@ -26,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F4xx_LL_Driver * @{ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c index cd44692400..780961d58c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_lptim.c @@ -28,7 +28,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F4xx_LL_Driver * @{ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c index d31a5ed28f..1b202c9606 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rng.c @@ -26,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F4xx_LL_Driver * @{ @@ -64,7 +64,7 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) { /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); -#if !defined (RCC_AHB2_SUPPORT) +#if !defined(RCC_AHB2_SUPPORT) /* Enable RNG reset state */ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RNG); @@ -76,7 +76,7 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) /* Release RNG from reset state */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); -#endif +#endif /* !RCC_AHB2_SUPPORT */ return (SUCCESS); } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c index c6fa695a18..14c3cfa5ca 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rtc.c @@ -87,18 +87,7 @@ #define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U)) -#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \ - || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \ - || ((__VALUE__) == LL_RTC_MONTH_MARCH) \ - || ((__VALUE__) == LL_RTC_MONTH_APRIL) \ - || ((__VALUE__) == LL_RTC_MONTH_MAY) \ - || ((__VALUE__) == LL_RTC_MONTH_JUNE) \ - || ((__VALUE__) == LL_RTC_MONTH_JULY) \ - || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \ - || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \ - || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \ - || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \ - || ((__VALUE__) == LL_RTC_MONTH_DECEMBER)) +#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U)) #define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) @@ -325,7 +314,7 @@ ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Time } /* Exit Initialization mode */ - LL_RTC_DisableInitMode(RTC); + LL_RTC_DisableInitMode(RTCx); /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) @@ -413,7 +402,7 @@ ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Date } /* Exit Initialization mode */ - LL_RTC_DisableInitMode(RTC); + LL_RTC_DisableInitMode(RTCx); /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_spi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_spi.c index dfbdabe3c7..2fde18057e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_spi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_spi.c @@ -27,7 +27,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F4xx_LL_Driver * @{ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c index fb1cfe78a8..089c5adebb 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_tim.c @@ -184,91 +184,91 @@ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); } -#endif +#endif /* TIM2 */ #if defined(TIM3) else if (TIMx == TIM3) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); } -#endif +#endif /* TIM3 */ #if defined(TIM4) else if (TIMx == TIM4) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); } -#endif +#endif /* TIM4 */ #if defined(TIM5) else if (TIMx == TIM5) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); } -#endif +#endif /* TIM5 */ #if defined(TIM6) else if (TIMx == TIM6) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); } -#endif +#endif /* TIM6 */ #if defined (TIM7) else if (TIMx == TIM7) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); } -#endif +#endif /* TIM7 */ #if defined(TIM8) else if (TIMx == TIM8) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); } -#endif +#endif /* TIM8 */ #if defined(TIM9) else if (TIMx == TIM9) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9); } -#endif +#endif /* TIM9 */ #if defined(TIM10) else if (TIMx == TIM10) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10); } -#endif +#endif /* TIM10 */ #if defined(TIM11) else if (TIMx == TIM11) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11); } -#endif +#endif /* TIM11 */ #if defined(TIM12) else if (TIMx == TIM12) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12); } -#endif +#endif /* TIM12 */ #if defined(TIM13) else if (TIMx == TIM13) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13); } -#endif +#endif /* TIM13 */ #if defined(TIM14) else if (TIMx == TIM14) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14); } -#endif +#endif /* TIM14 */ else { result = ERROR; @@ -296,7 +296,8 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) /** * @brief Configure the TIMx time base unit. * @param TIMx Timer Instance - * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure + * (TIMx time base unit configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable @@ -349,7 +350,8 @@ ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) /** * @brief Set the fields of the TIMx output channel configuration data * structure to their default values. - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure) + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure + * (the output channel configuration data structure) * @retval None */ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) @@ -373,7 +375,8 @@ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure) + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration + * data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized @@ -406,7 +409,8 @@ ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTy /** * @brief Set the fields of the TIMx input channel configuration data * structure to their default values. - * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure) + * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration + * data structure) * @retval None */ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) @@ -426,7 +430,8 @@ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 - * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure) + * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data + * structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized @@ -458,7 +463,8 @@ ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTy /** * @brief Fills each TIM_EncoderInitStruct field with its default value - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure) + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface + * configuration data structure) * @retval None */ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) @@ -478,7 +484,8 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct /** * @brief Configure the encoder interface of the timer instance. * @param TIMx Timer Instance - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface + * configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable @@ -542,7 +549,8 @@ ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *T /** * @brief Set the fields of the TIMx Hall sensor interface configuration data * structure to their default values. - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure) + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface + * configuration data structure) * @retval None */ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) @@ -569,7 +577,8 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used * when TIMx operates in Hall sensor interface mode. * @param TIMx Timer Instance - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor + * interface configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable @@ -649,7 +658,8 @@ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitType /** * @brief Set the fields of the Break and Dead Time configuration data structure * to their default values. - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) * @retval None */ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) @@ -672,7 +682,8 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @param TIMx Timer Instance - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: Break and Dead Time is initialized * - ERROR: not applicable diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c index d47e99cf85..150d8bbf62 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c @@ -64,41 +64,41 @@ #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ - || ((__VALUE__) == LL_USART_DIRECTION_RX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) + || ((__VALUE__) == LL_USART_DIRECTION_RX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ - || ((__VALUE__) == LL_USART_PARITY_EVEN) \ - || ((__VALUE__) == LL_USART_PARITY_ODD)) + || ((__VALUE__) == LL_USART_PARITY_EVEN) \ + || ((__VALUE__) == LL_USART_PARITY_ODD)) #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) + || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ - || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) + || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ - || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) + || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ - || ((__VALUE__) == LL_USART_PHASE_2EDGE)) + || ((__VALUE__) == LL_USART_PHASE_2EDGE)) #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ - || ((__VALUE__) == LL_USART_POLARITY_HIGH)) + || ((__VALUE__) == LL_USART_POLARITY_HIGH)) #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ - || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) + || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_1) \ - || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_2)) + || ((__VALUE__) == LL_USART_STOPBITS_1) \ + || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_2)) #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) + || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) /** * @} diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c index 78df37addf..cdd837da2d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c @@ -96,7 +96,8 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; } - /* Reset after a PHY select */ + + /* Reset after a PHY select */ ret = USB_CoreReset(USBx); } else /* FS interface (embedded Phy) */ @@ -247,21 +248,39 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) { + uint32_t ms = 0U; + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); if (mode == USB_HOST_MODE) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + + do + { + HAL_Delay(1U); + ms++; + } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U)); } else if (mode == USB_DEVICE_MODE) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + + do + { + HAL_Delay(1U); + ms++; + } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U)); } else { return HAL_ERROR; } - HAL_Delay(50U); + + if (ms == 50U) + { + return HAL_ERROR; + } return HAL_OK; } @@ -452,7 +471,7 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { - uint32_t count = 0U; + __IO uint32_t count = 0U; USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); @@ -474,7 +493,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { - uint32_t count = 0; + __IO uint32_t count = 0U; USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; @@ -736,7 +755,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & + (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); if (ep->type == EP_TYPE_ISOC) @@ -957,8 +978,9 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t *pSrc = (uint32_t *)src; - uint32_t count32b, i; + uint8_t *pSrc = src; + uint32_t count32b; + uint32_t i; if (dma == 0U) { @@ -967,6 +989,9 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, { USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); pSrc++; + pSrc++; + pSrc++; + pSrc++; } } @@ -983,14 +1008,34 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t *pDest = (uint32_t *)dest; + uint8_t *pDest = dest; + uint32_t pData; uint32_t i; - uint32_t count32b = ((uint32_t)len + 3U) / 4U; + uint32_t count32b = (uint32_t)len >> 2U; + uint16_t remaining_bytes = len % 4U; for (i = 0U; i < count32b; i++) { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); pDest++; + pDest++; + pDest++; + pDest++; + } + + /* When Number of data is not word aligned, read the remaining byte */ + if (remaining_bytes != 0U) + { + i = 0U; + __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); + + do + { + *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); + i++; + pDest++; + remaining_bytes--; + } while (remaining_bytes != 0U); } return ((void *)pDest); @@ -1222,7 +1267,9 @@ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t tmpreg, msk, emp; + uint32_t tmpreg; + uint32_t msk; + uint32_t emp; msk = USBx_DEVICE->DIEPMSK; emp = USBx_DEVICE->DIEPEMPMSK; @@ -1318,7 +1365,7 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uin */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { - uint32_t count = 0U; + __IO uint32_t count = 0U; /* Wait for AHB master IDLE state. */ do @@ -1407,11 +1454,6 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx_HC(i)->HCINTMSK = 0U; } - /* Enable VBUS driving */ - (void)USB_DriveVbus(USBx, 1U); - - HAL_Delay(200U); - /* Disable all interrupts. */ USBx->GINTMSK = 0U; @@ -1595,7 +1637,8 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, { HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t HCcharEpDir, HCcharLowSpeed; + uint32_t HCcharEpDir; + uint32_t HCcharLowSpeed; uint32_t HostCoreSpeed; /* Clear old interrupt conditions for this host channel. */ diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 161c32d747..ced59966f1 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -4,7 +4,7 @@ * STM32F1: 1.1.8 * STM32F2: 1.2.7 * STM32F3: 1.5.6 - * STM32F4: 1.7.12 + * STM32F4: 1.7.13 * STM32F7: 1.2.9 * STM32G0: 1.4.2 * STM32G4: 1.2.1