diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 3cd80cb04ab84..f6aaef2154322 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -611,7 +611,7 @@ X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
         // best of both worlds.
         if (U->getOpcode() == ISD::AND &&
             Imm->getAPIntValue().getBitWidth() == 64 &&
-            Imm->getAPIntValue().isIntN(32))
+            Imm->getAPIntValue().isSignedIntN(32))
           return false;
 
         // If this really a zext_inreg that can be represented with a movzx
diff --git a/llvm/test/CodeGen/X86/pr48458.ll b/llvm/test/CodeGen/X86/pr48458.ll
new file mode 100644
index 0000000000000..bca355961611b
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr48458.ll
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
+
+define i1 @foo(i64* %0) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %top
+; CHECK-NEXT:    movq (%rdi), %rax
+; CHECK-NEXT:    andq $-2147483648, %rax # imm = 0x80000000
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    retq
+top:
+  %1 = load i64, i64* %0, !range !0
+  %2 = icmp ult i64 %1, 2147483648
+  ret i1 %2
+}
+
+!0 = !{i64 0, i64 10000000000}