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Implement RegisterMapInterfaceINTEL execution mode #1774
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@MrSidims Could you please help me review this as well? The tricky part here is that:
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We usually add checks on the translation level, see Unroll vs DontUnroll masks as an example. I don't remember, if it's a case for FPGA extensions, since we were relying on clang to check correctness of attributes back then (probably we still have some checks here as well), but it seems to be a bad idea now not to add checks, since we no longer adding attributes to clang (with appropriate diagnostics). So I'd suggest to add checks here. |
@tiwaria1 please don't forget to add a test :) |
Added one. I did not run it locally though. Is there any automatic git CI testing that will run it for me on this PR? |
Yet here is, but I expect it to be broken right now due to LLVM upgrade to 17.0.0 . So I would suggest running tests locally (it won't faster the merge, since we would need to wait for the fixed CI, but still help with finding problems if any). To run test you should add |
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To incorporate changes from SPIR-V headers please update spirv-headers-tag.conf
I can only do that once the SPIRV-Headers PR is merged right? |
Ah, sorry, I've seen notification, that the PR got closed and assumed, that is was merged. |
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LGTM, just waiting for the headers be merged
Thanks!
Hey @MrSidims the headers change has been merged. Has the CI been fixed yet? |
@tiwaria1 please take a look at the test failure |
Having trouble building the translator locally, I did the following (llvm in-tree build steps):
and got the error:
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Not sure what's up with clang-format check, it says:
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I'll take a look at clang-format check, you may ignore it
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It was the missing entry in SPIRVNameMapEnum.h that was causing this. Fixed. |
What do I do about the clang-format error? Looks like it is some sort of script issue? |
…properties, fix RegisterMap sycl-post-link (#10406) Add defaults for template parameters for streaming_interface and register_map_interface in fpga_kernel_properties.hpp since current usage gets too verbose, and defaults are allowed and implementation defined. Register map interface also does not match SPIRV expected interface [spec](https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_kernel_attributes.asciidoc) and [implementation](KhronosGroup/SPIRV-LLVM-Translator#1774), so update sycl-post-link.
…properties, fix RegisterMap sycl-post-link (intel#10406) Add defaults for template parameters for streaming_interface and register_map_interface in fpga_kernel_properties.hpp since current usage gets too verbose, and defaults are allowed and implementation defined. Register map interface also does not match SPIRV expected interface [spec](https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_kernel_attributes.asciidoc) and [implementation](KhronosGroup/SPIRV-LLVM-Translator#1774), so update sycl-post-link.
This PR adds the new execution mode
RegisterMapInterfaceINTEL
, see the KhronosSPIRV spec here: KhronosGroup/SPIRV-Registry#176
This execution mode allows specifying a 'register' based interface for FPGA kernels.
The RegisterMapInterfaceINTEL execution mode is added with a 0/1 literal based on
the kernel metadata. When the metadata is:
The translator emits
RegisterMapInterfaceINTEL 0
, and when the metadata is:The translator emits
RegisterMapInterfaceINTEL 1
NOTE
FPGAKernelAttributesv2INTEL
which implicitly defines the capabilityFPGAKernelAttributesv2INTEL
.