Skip to content

Add support for SPI1 device #182

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
May 16, 2016
Merged

Add support for SPI1 device #182

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
2bb742a
Add support for SPI1 device to SPIClass
eriknyquist May 12, 2016
331b2f0
Clean up the SPI files
eriknyquist May 12, 2016
8dea7b4
Fix SPI clock divider calculation
May 16, 2016
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
69 changes: 38 additions & 31 deletions libraries/SPI/src/SPI.cpp
100644 → 100755
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -13,40 +13,43 @@

* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*
*/
#include "SPI.h"

SPIClass SPI;
SPIClass SPI(SPIDEV_1);
SPIClass SPI1(SPIDEV_0);

void SPIClass::setClockDivider(uint8_t clockDiv)
{
/* disable controller */
SPI1_M_REG_VAL(SPIEN) &= SPI_DISABLE;
SPI_M_REG_VAL(spi_addr, SPIEN) &= SPI_DISABLE;

/* Set SPI Clock Divider */
SPI1_M_REG_VAL(BAUDR) = clockDiv & SPI_CLOCK_MASK;
SPI_M_REG_VAL(spi_addr, BAUDR) = clockDiv & SPI_CLOCK_MASK;

/* re-enable controller */
SPI1_M_REG_VAL(SPIEN) |= SPI_ENABLE;
SPI_M_REG_VAL(spi_addr, SPIEN) |= SPI_ENABLE;
}

void SPIClass::setDataMode(uint8_t dataMode)
{
/* disable controller */
SPI1_M_REG_VAL(SPIEN) &= SPI_DISABLE;
SPI_M_REG_VAL(spi_addr, SPIEN) &= SPI_DISABLE;

/* Set frame size, bus mode and transfer mode */
SPI1_M_REG_VAL(CTRL0) = (SPI1_M_REG_VAL(CTRL0) & ~(SPI_MODE_MASK)) | ((dataMode << SPI_MODE_SHIFT) & SPI_MODE_MASK);
SPI_M_REG_VAL(spi_addr, CTRL0) = (SPI_M_REG_VAL(spi_addr, CTRL0)
& ~(SPI_MODE_MASK)) | ((dataMode << SPI_MODE_SHIFT) & SPI_MODE_MASK);

/* re-enable controller */
SPI1_M_REG_VAL(SPIEN) |= SPI_ENABLE;
SPI_M_REG_VAL(spi_addr, SPIEN) |= SPI_ENABLE;
}

void SPIClass::begin()
{
uint32_t flags = interrupt_lock(); // Protect from a scheduler and prevent transactionBegin
/* Protect from a scheduler and prevent transactionBegin*/
uint32_t flags = interrupt_lock();
if (!initialized) {
interruptMode = 0;
interruptMask[0] = 0;
Expand All @@ -58,31 +61,34 @@ void SPIClass::begin()
lsbFirst = false;
frameSize = SPI_8_BIT;

// Set SS to high so a connected chip will be "deselected" by default
// TODO - confirm that data register is updated even if pin is set as input
digitalWrite(SS, HIGH);
/* Set SS to high so a connected chip will be "deselected" by default.
* TODO - confirm that data register is updated even if pin is set as
* input. */
digitalWrite(ss_gpio, HIGH);

// When the SS pin is set as OUTPUT, it can be used as
// a general purpose output port (it doesn't influence
// SPI operations).
pinMode(SS, OUTPUT);
/* When the SS pin is set as OUTPUT, it can be used as
* a general purpose output port (it doesn't influence
* SPI operations). */
pinMode(ss_gpio, OUTPUT);

/* disable controller */
SPI1_M_REG_VAL(SPIEN) &= SPI_DISABLE;
SPI_M_REG_VAL(spi_addr, SPIEN) &= SPI_DISABLE;

/* Enable clock to peripheral */
MMIO_REG_VAL(PERIPH_CLK_GATE_CTRL) |= ENABLE_SPI_MASTER_1;
MMIO_REG_VAL(PERIPH_CLK_GATE_CTRL) |= enable_val;

/* Configure defaults for clock divider, frame size and data mode */
SPI1_M_REG_VAL(BAUDR) = SPI_CLOCK_DIV4;
SPI1_M_REG_VAL(CTRL0) = (frameSize << SPI_FSIZE_SHIFT) | (SPI_MODE0 << SPI_MODE_SHIFT);
SPI_M_REG_VAL(spi_addr, BAUDR) = SPI_CLOCK_DIV4;
SPI_M_REG_VAL(spi_addr, CTRL0) =
(frameSize << SPI_FSIZE_SHIFT) | (SPI_MODE0 << SPI_MODE_SHIFT);

/* Disable interrupts */
SPI1_M_REG_VAL(IMR) = SPI_DISABLE_INT;
/* Enable at least one slave device (mandatory, though SS signals are unused) */
SPI1_M_REG_VAL(SER) = 0x1;
SPI_M_REG_VAL(spi_addr, IMR) = SPI_DISABLE_INT;
/* Enable at least one slave device (mandatory, though
* SS signals are unused) */
SPI_M_REG_VAL(spi_addr, SER) = 0x1;
/* Enable controller */
SPI1_M_REG_VAL(SPIEN) |= SPI_ENABLE;
SPI_M_REG_VAL(spi_addr, SPIEN) |= SPI_ENABLE;

/* Set SoC pin mux configuration */
SET_PIN_MODE(g_APinDescription[MOSI].ulSocPin, SPI_MUX_MODE);
Expand All @@ -93,19 +99,20 @@ void SPIClass::begin()
g_APinDescription[SCK].ulPinMode = SPI_MUX_MODE;

}
initialized++; // reference count
initialized++; /* reference count */
interrupt_unlock(flags);
}

void SPIClass::end() {
uint32_t flags = interrupt_lock(); // Protect from a scheduler and prevent transactionBegin
// Decrease the reference counter
/* Protect from a scheduler and prevent transactionBegin */
uint32_t flags = interrupt_lock();
/* Decrease the reference counter */
if (initialized)
initialized--;
// If there are no more references disable SPI
/* If there are no more references disable SPI */
if (!initialized) {
SPI1_M_REG_VAL(SPIEN) &= SPI_DISABLE;
MMIO_REG_VAL(PERIPH_CLK_GATE_CTRL) &= DISABLE_SPI_MASTER_1;
SPI_M_REG_VAL(spi_addr, SPIEN) &= SPI_DISABLE;
MMIO_REG_VAL(PERIPH_CLK_GATE_CTRL) &= disable_val;
#ifdef SPI_TRANSACTION_MISMATCH_LED
inTransactionFlag = 0;
#endif
Expand Down Expand Up @@ -139,7 +146,7 @@ void SPIClass::usingInterrupt(uint8_t interruptNumber) {
}

void SPIClass::notUsingInterrupt(uint8_t interruptNumber) {
// Once in mode 8 we can't go back to 0 without a proper reference count
/* Once in mode 8 we can't go back to 0 without a proper reference count */
if (interruptMode == 8)
return;

Expand Down
Loading