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Fix relocs for linux-riscv64 AOT #112331

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Merged
merged 1 commit into from
Feb 10, 2025

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@am11 am11 commented Feb 10, 2025

With this delta, we successfully reach the hello-world milestone.

#106223

@ghost ghost added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Feb 10, 2025
@am11 am11 requested review from filipnavara and a team February 10, 2025 02:48
@dotnet-policy-service dotnet-policy-service bot added the community-contribution Indicates that the PR has been added by a community member label Feb 10, 2025
@am11 am11 added the arch-riscv Related to the RISC-V architecture label Feb 10, 2025
@am11 am11 mentioned this pull request Feb 10, 2025
@am11 am11 added area-NativeAOT-coreclr and removed area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI labels Feb 10, 2025
Comment on lines +3584 to +3601
GenTreeIntCon* con = op2->AsIntCon();

emitAttr attr = emitActualTypeSize(op2Type);
// TODO-CQ: Currently we cannot do this for all handles because of
// https://github.com/dotnet/runtime/issues/60712
if (con->ImmedValNeedsReloc(compiler))
{
attr = EA_SET_FLG(attr, EA_CNS_RELOC_FLG);
}

if (op2Type == TYP_BYREF)
{
attr = EA_SET_FLG(attr, EA_BYREF_FLG);
}

instGen_Set_Reg_To_Imm(attr, REG_RA, imm,
INS_FLAGS_DONT_CARE DEBUGARG(con->gtTargetHandle) DEBUGARG(con->gtFlags));
regSet.verifyRegUsed(REG_RA);
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Nit: looks like the CNS_INT case does the same (it's unused now). Can we just call genSetRegToConst?

void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTree* tree)
{
switch (tree->gtOper)
{
case GT_CNS_INT:
{
// relocatable values tend to come down as a CNS_INT of native int type
// so the line between these two opcodes is kind of blurry
GenTreeIntCon* con = tree->AsIntCon();
ssize_t cnsVal = con->IconValue();
emitAttr attr = emitActualTypeSize(targetType);
// TODO-RISCV64-CQ: Currently we cannot do this for all handles because of
// https://github.com/dotnet/runtime/issues/60712
if (con->ImmedValNeedsReloc(compiler))
{
attr = EA_SET_FLG(attr, EA_CNS_RELOC_FLG);
}
if (targetType == TYP_BYREF)
{
attr = EA_SET_FLG(attr, EA_BYREF_FLG);
}
instGen_Set_Reg_To_Imm(attr, targetReg, cnsVal,
INS_FLAGS_DONT_CARE DEBUGARG(con->gtTargetHandle) DEBUGARG(con->gtFlags));
regSet.verifyRegUsed(targetReg);
}
break;

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The difference is static_cast uint vs. int. If the value returned by op2->AsIntCon()->gtIconVal is negative, cond.IsUnsigned() is true, then cast to uint32_t will reinterpret it as a large positive number and cast to int32_t in else will keep it negative.

I can't tell if ignoring the signedness has any side-effects in this context.

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The relocatable constants should be pointer sized, so they will not be going through the EA_4BYTE case with the casts above.

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@jakobbotsch, instGen_Set_Reg_To_Imm(attr, REG_RA, imm, is called for both EA_4BYTE and EA_8BYTE right?

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Ah, yes. It seems like a RISCV64 version of genSetRegToConst would need to come with an extra argument about whether 32-bit constants should be sign or zero extended given that the full 64-bit register is expected to be used by callers afterwards.
So I agree it probably can't be used directly here.

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Yeah, let's leave it. Technically you could ABI-extend both sides (sign-extend from 32-bits up to full register, regardless of type's signedness), then the unsigned comparison on the whole register works correctly.

I hope to get to it this year, we've got plenty of unnecessary extension instructions, e.g. the register operand here is already ABI-extended in many cases.

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risc-vv commented Feb 10, 2025

13cfb9d is being scheduled for building and testing

GIT: 13cfb9d902564ec3ed85c2feb320bbe14ebd2d70
REPO: dotnet/runtime
BRANCH: main

Release-FX-tests FAILED

buildinfo.json
coreFX tests failed for unknown reason. Check buildinfo.json or gocd for more details.

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Handles can show up in a number of JIT nodes. It seems likely a similar fix will be needed in other places too.

@jakobbotsch jakobbotsch merged commit 2240175 into dotnet:main Feb 10, 2025
115 of 119 checks passed
@am11 am11 deleted the feature/nativeaot/riscv64-port branch February 10, 2025 13:02
grendello added a commit to grendello/runtime that referenced this pull request Feb 11, 2025
* main:
  Code clean up in AP for NonNull* (dotnet#112027)
  JIT: Invalidate LSRA's DFS tree if we aren't running new layout phase (dotnet#112364)
  Update dependencies from https://github.com/dotnet/source-build-reference-packages build 20250204.2 (dotnet#112339)
  Add doc on OS onboarding (dotnet#112026)
  Add `TypeName` APIs to simplify metadata lookup. (dotnet#111598)
  Internal monitor impl not using coop mutex causing deadlocks on Android. (dotnet#112358)
  Do not run NAOT arm64 OSX testing on all PRs (dotnet#112342)
  Special-case empty enumerables in AsyncEnumerable (dotnet#112321)
  Have mono handle ConvertToIntegerNative for Double and Single (dotnet#112206)
  Update dependencies from https://github.com/dotnet/arcade build 20250206.4 (dotnet#112338)
  System.Configuration.ConfigurationManager.Tests: use Assembly.Location to determine ThisApplicationPath. (dotnet#112231)
  Force write of local file header when "version needed to extract" changes (dotnet#112032)
  JIT: Don't reorder handler blocks (dotnet#112292)
  [RISC-V] Synthesize some floating constants inline (dotnet#111529)
  Enable `SA1000`: Spacing around keywords (dotnet#112302)
  Fix relocs for linux-riscv64 AOT (dotnet#112331)
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6 participants