[SYCL] Deny support of SPV_INTEL_usm_storage_classes for all targets … #1986
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NOTE: #1985 - need to be merged first |
…but FPGA Disable SPV_INTEL_usm_storage_classes by default since it adds new storage classes that represent global_device and global_host address spaces, which are not supported for all targets. With the extension disabled the storage classes will be lowered to CrossWorkgroup storage class that is mapped to just global address space. The extension is enabled only for FPGA with a flag 'enable-usm-address-spaces' passed to the driver. Signed-off-by: Dmitry Sidorov <[email protected]>
Signed-off-by: Dmitry Sidorov <[email protected]>
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AGindinson
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Jun 26, 2020
I was thinking I had it, thanks for pointing out! |
Signed-off-by: Dmitry Sidorov <[email protected]>
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@AGindinson I have added a positive test case in sycl-offload.c. Do you think it's necessary to add it in sycl-offload-intelfpga.cpp as well? I think the last test is more about aocx generation than about options. |
I agree, |
mdtoguchi
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Jun 26, 2020
Signed-off-by: Dmitry Sidorov <[email protected]>
AGindinson
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Jun 26, 2020
Signed-off-by: Dmitry Sidorov <[email protected]>
AGindinson
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Jun 29, 2020
jsji
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May 15, 2023
Currently, we always convert SPIR-V bultins to globals for forward translation and to functions for reverse translation. I have a use case where I want to keep them as globals for reverse translation, so I added this mode. Implementations for both cases already existed, I just consolidated them and added the option. Signed-off-by: Sarnie, Nick <[email protected]> Original commit: KhronosGroup/SPIRV-LLVM-Translator@730eaf0
jsji
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Currently, we always convert SPIR-V bultins to globals for forward translation and to functions for reverse translation. I have a use case where I want to keep them as globals for reverse translation, so I added this mode. Implementations for both cases already existed, I just consolidated them and added the option. Signed-off-by: Sarnie, Nick <[email protected]> Original commit: KhronosGroup/SPIRV-LLVM-Translator@730eaf0
jsji
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May 16, 2023
Currently, we always convert SPIR-V bultins to globals for forward translation and to functions for reverse translation. I have a use case where I want to keep them as globals for reverse translation, so I added this mode. Implementations for both cases already existed, I just consolidated them and added the option. Signed-off-by: Sarnie, Nick <[email protected]> Original commit: KhronosGroup/SPIRV-LLVM-Translator@730eaf0
jsji
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May 16, 2023
Currently, we always convert SPIR-V bultins to globals for forward translation and to functions for reverse translation. I have a use case where I want to keep them as globals for reverse translation, so I added this mode. Implementations for both cases already existed, I just consolidated them and added the option. Signed-off-by: Sarnie, Nick <[email protected]> Original commit: KhronosGroup/SPIRV-LLVM-Translator@730eaf0
jsji
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) Currently, we always convert SPIR-V bultins to globals for forward translation and to functions for reverse translation. I have a use case where I want to keep them as globals for reverse translation, so I added this mode. Implementations for both cases already existed, I just consolidated them and added the option. Signed-off-by: Sarnie, Nick <[email protected]> Original commit: KhronosGroup/SPIRV-LLVM-Translator@730eaf0
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jsji
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May 16, 2023
Currently, we always convert SPIR-V bultins to globals for forward translation and to functions for reverse translation. I have a use case where I want to keep them as globals for reverse translation, so I added this mode. Implementations for both cases already existed, I just consolidated them and added the option. Signed-off-by: Sarnie, Nick <[email protected]> Original commit: KhronosGroup/SPIRV-LLVM-Translator@730eaf0
This was referenced May 16, 2023
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…but FPGA
Disable SPV_INTEL_usm_storage_classes by default since it adds new
storage classes that represent global_device and global_host address
spaces, which are not supported for all targets. With the extension
disabled the storage classes will be lowered to CrossWorkgroup storage
class that is mapped to just global address space.
The extension is enabled only for FPGA with a flag 'enable-usm-address-spaces'
passed to the driver.
Signed-off-by: Dmitry Sidorov [email protected]