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[SYCL][FPGA] Adding a wrapper header for __builtin_intel_fpga_mem #2033
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@MrSidims any updates on this? Are you an approving reviewer? |
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LGTM with a few nits.
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For the future, it's recommended not to amend patches before pushing, so changes could be tracked from version to version.
Sounds good! Thank you @MrSidims . |
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Nice to see higher-level constructs for FPGA in SYCL, instead of ugly attributes or #pragma
! :-)
With this it is possible then to build higher-level libraries to wrap accessors and provide different behaviors and hiding explicit load/store.
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Thanks, the example is simpler.
But I have the feeling that the user-facing API could be streamlined and more obvious.
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@keryell Thank you for your comments. The code does indeed look better and the use model is more intuitive. |
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LGTM
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@jbrodman, could you take a look at the documentation for this extension, please? |
@mohammadfawaz looks like the PR as is is going nowhere, I suggest to split it to 2 PRs: implementation itself and the spec. Implementation PR can be approved (basically it's already approved) and merged right away. Spec can be merged later. |
…s around the Clang builtin __builtin_intel_fpga_mem
- Three of the parameters now accept a boolean only - Some simplifications to fpga_utils - dont_statically_coalesce is exposed as statically_coalesce instead.
Will create a separate PR for the spec alone.
Done. I removed the spec from this PR. Will open another one for the spec. |
Approved. @mohammadfawaz the only thing, that I want to ask you to change is the PR description. @bader usually uses it to create a commit message for a squashed commit during merging, hence I advise to replace "The .md file I added contains an example of how I see this being used. For now, this is only useful for global_ptrs." with a little extract from the spec itself (or just refer to the spec PR, when it's ready, but the first way is slightly preferable). |
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It no longer has a Scope (parent) parameter. It results in several changes including how to determine DIBuilder to use for debug info generation. The patch also fixes a bug of incorrect debug info assignment in case of recursion DebugInfo inst generation. Signed-off-by: Sidorov, Dmitry <[email protected]> Original commit: KhronosGroup/SPIRV-LLVM-Translator@01679ce
This patch adds a new wrapper header for the Clang builtin
__builtin_intel_fpga_mem
The SPIRV spec for this featuer is here: https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_memory_accesses.asciidoc
The Intel FPGA
lsu
class is implemented inCL/sycl/intel/fpga_lsu.hpp
whichis included in
CL/sycl/intel/fpga_extensions.hpp
.The class
cl::sycl::intel::lsu
allows users to explicitly request that theimplementation of a global memory access is configured in a certain way. The
class has two member functions,
load()
andstore()
which allow loading fromand storing to a
global_ptr
, respectively, and is templated on 4 optional paremeters.