Skip to content

[SYCL][FPGA] Adding a wrapper header for __builtin_intel_fpga_mem #2033

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 4 commits into from
Jul 22, 2020

Conversation

mohammadfawaz
Copy link
Contributor

@mohammadfawaz mohammadfawaz commented Jul 2, 2020

This patch adds a new wrapper header for the Clang builtin __builtin_intel_fpga_mem

The SPIRV spec for this featuer is here: https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_memory_accesses.asciidoc

The Intel FPGA lsu class is implemented in CL/sycl/intel/fpga_lsu.hpp which
is included in CL/sycl/intel/fpga_extensions.hpp.

The class cl::sycl::intel::lsu allows users to explicitly request that the
implementation of a global memory access is configured in a certain way. The
class has two member functions, load() and store() which allow loading from
and storing to a global_ptr, respectively, and is templated on 4 optional paremeters.

@mohammadfawaz mohammadfawaz requested review from jbrodman, mkinsner, MrSidims and a team as code owners July 2, 2020 18:25
@mohammadfawaz mohammadfawaz requested a review from rbegam July 2, 2020 18:25
@mohammadfawaz mohammadfawaz force-pushed the sycl branch 2 times, most recently from 1809dfe to 6bd4b76 Compare July 2, 2020 18:49
@mohammadfawaz
Copy link
Contributor Author

@MrSidims any updates on this? Are you an approving reviewer?

Copy link
Contributor

@MrSidims MrSidims left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM with a few nits.

MrSidims
MrSidims previously approved these changes Jul 4, 2020
Copy link
Contributor

@MrSidims MrSidims left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

For the future, it's recommended not to amend patches before pushing, so changes could be tracked from version to version.

@mohammadfawaz
Copy link
Contributor Author

For the future, it's recommended not to amend patches before pushing, so changes could be tracked from version to version.

Sounds good! Thank you @MrSidims .

Copy link
Contributor

@keryell keryell left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Nice to see higher-level constructs for FPGA in SYCL, instead of ugly attributes or #pragma! :-)

With this it is possible then to build higher-level libraries to wrap accessors and provide different behaviors and hiding explicit load/store.

Copy link
Contributor

@keryell keryell left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks, the example is simpler.
But I have the feeling that the user-facing API could be streamlined and more obvious.

@mohammadfawaz mohammadfawaz force-pushed the sycl branch 2 times, most recently from e56941d to 998b066 Compare July 9, 2020 02:04
@mohammadfawaz
Copy link
Contributor Author

@keryell Thank you for your comments. The code does indeed look better and the use model is more intuitive.

@MrSidims MrSidims self-requested a review July 9, 2020 13:45
MrSidims
MrSidims previously approved these changes Jul 9, 2020
rbegam
rbegam previously approved these changes Jul 9, 2020
Copy link
Contributor

@rbegam rbegam left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

@mohammadfawaz mohammadfawaz dismissed stale reviews from rbegam and MrSidims via a24a8ca July 10, 2020 02:18
@mohammadfawaz mohammadfawaz force-pushed the sycl branch 2 times, most recently from a24a8ca to 998b066 Compare July 10, 2020 02:33
MrSidims
MrSidims previously approved these changes Jul 14, 2020
@mohammadfawaz mohammadfawaz requested a review from bader July 14, 2020 18:34
@bader bader requested a review from rbegam July 14, 2020 18:38
@bader
Copy link
Contributor

bader commented Jul 14, 2020

@jbrodman, could you take a look at the documentation for this extension, please?

@mohammadfawaz
Copy link
Contributor Author

@jbrodman, could you take a look at the documentation for this extension, please?
@jbrodman @bader A gentle reminder to take a look at this at your convenience. Thanks!

rbegam
rbegam previously approved these changes Jul 20, 2020
@MrSidims
Copy link
Contributor

@mohammadfawaz looks like the PR as is is going nowhere, I suggest to split it to 2 PRs: implementation itself and the spec. Implementation PR can be approved (basically it's already approved) and merged right away. Spec can be merged later.

Mohammad Fawaz added 3 commits July 22, 2020 09:15
…s around

the Clang builtin __builtin_intel_fpga_mem
- Three of the parameters now accept a boolean only
- Some simplifications to fpga_utils
- dont_statically_coalesce is exposed as statically_coalesce instead.
Will create a separate PR for the spec alone.
@mohammadfawaz
Copy link
Contributor Author

@mohammadfawaz looks like the PR as is is going nowhere, I suggest to split it to 2 PRs: implementation itself and the spec. Implementation PR can be approved (basically it's already approved) and merged right away. Spec can be merged later.

Done. I removed the spec from this PR. Will open another one for the spec.

@MrSidims MrSidims requested review from MrSidims and rbegam July 22, 2020 13:45
MrSidims
MrSidims previously approved these changes Jul 22, 2020
@MrSidims
Copy link
Contributor

Approved. @mohammadfawaz the only thing, that I want to ask you to change is the PR description. @bader usually uses it to create a commit message for a squashed commit during merging, hence I advise to replace "The .md file I added contains an example of how I see this being used. For now, this is only useful for global_ptrs." with a little extract from the spec itself (or just refer to the spec PR, when it's ready, but the first way is slightly preferable).

@bader bader merged commit 74faa3f into intel:sycl Jul 22, 2020
jsji pushed a commit that referenced this pull request Jun 8, 2023
It no longer has a Scope (parent) parameter. It results in several changes including how to determine DIBuilder to use for debug info generation.

The patch also fixes a bug of incorrect debug info assignment in case of recursion DebugInfo inst generation.

Signed-off-by: Sidorov, Dmitry <[email protected]>

Original commit:
KhronosGroup/SPIRV-LLVM-Translator@01679ce
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

5 participants