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[SYCL][CUDA][libclc] Add atomic loads and stores with various memory orders and scopes #5191
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[SYCL][CUDA][libclc] Added atomic loads and stores with various memor…
t4c1 98aaa34
Merge branch 'sycl' into ptx_atomic_ldst
t4c1 be3b553
format and push/pop macros
t4c1 e400d17
removed redundant include and added tests for volatile intrinsics
t4c1 5c91b3d
removed tmp variable
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Original file line number | Diff line number | Diff line change |
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@@ -54,6 +54,8 @@ | |
#include "llvm/Support/X86TargetParser.h" | ||
#include <sstream> | ||
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#include <iostream> | ||
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using namespace clang; | ||
using namespace CodeGen; | ||
using namespace llvm; | ||
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@@ -17429,6 +17431,22 @@ CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID, const CallExpr *E) { | |
Ptr->getType()}), | ||
{Ptr, ConstantInt::get(Builder.getInt32Ty(), Align.getQuantity())}); | ||
}; | ||
auto MakeScopedLd = [&](unsigned IntrinsicID) { | ||
Value *Ptr = EmitScalarExpr(E->getArg(0)); | ||
auto tmp = Builder.CreateCall( | ||
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CGM.getIntrinsic(IntrinsicID, {Ptr->getType()->getPointerElementType(), | ||
Ptr->getType()}), | ||
{Ptr}); | ||
return tmp; | ||
}; | ||
auto MakeScopedSt = [&](unsigned IntrinsicID) { | ||
Value *Ptr = EmitScalarExpr(E->getArg(0)); | ||
return Builder.CreateCall( | ||
CGM.getIntrinsic( | ||
IntrinsicID, | ||
{Ptr->getType(), Ptr->getType()->getPointerElementType()}), | ||
{Ptr, EmitScalarExpr(E->getArg(1))}); | ||
}; | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. The pointer is in generic AS. We may want to |
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auto MakeScopedAtomic = [&](unsigned IntrinsicID) { | ||
Value *Ptr = EmitScalarExpr(E->getArg(0)); | ||
return Builder.CreateCall( | ||
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@@ -17444,6 +17462,85 @@ CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID, const CallExpr *E) { | |
{Ptr, EmitScalarExpr(E->getArg(1)), EmitScalarExpr(E->getArg(2))}); | ||
}; | ||
switch (BuiltinID) { | ||
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#define LD_VOLATILE_CASES(ADDR_SPACE) \ | ||
case NVPTX::BI__nvvm_volatile_ld##ADDR_SPACE##_i: \ | ||
case NVPTX::BI__nvvm_volatile_ld##ADDR_SPACE##_l: \ | ||
case NVPTX::BI__nvvm_volatile_ld##ADDR_SPACE##_ll: \ | ||
return MakeScopedLd(Intrinsic::nvvm_ld##ADDR_SPACE##_i_volatile); \ | ||
case NVPTX::BI__nvvm_volatile_ld##ADDR_SPACE##_f: \ | ||
case NVPTX::BI__nvvm_volatile_ld##ADDR_SPACE##_d: \ | ||
return MakeScopedLd(Intrinsic::nvvm_ld##ADDR_SPACE##_f_volatile); | ||
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#define LD_CASES(ORDER, SCOPE, ADDR_SPACE) \ | ||
case NVPTX::BI__nvvm##ORDER##SCOPE##_ld##ADDR_SPACE##_i: \ | ||
case NVPTX::BI__nvvm##ORDER##SCOPE##_ld##ADDR_SPACE##_l: \ | ||
case NVPTX::BI__nvvm##ORDER##SCOPE##_ld##ADDR_SPACE##_ll: \ | ||
return MakeScopedLd(Intrinsic::nvvm_ld##ADDR_SPACE##_i##ORDER##SCOPE); \ | ||
case NVPTX::BI__nvvm##ORDER##SCOPE##_ld##ADDR_SPACE##_f: \ | ||
case NVPTX::BI__nvvm##ORDER##SCOPE##_ld##ADDR_SPACE##_d: \ | ||
return MakeScopedLd(Intrinsic::nvvm_ld##ADDR_SPACE##_f##ORDER##SCOPE); | ||
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#define LD_CASES_AS(ORDER, SCOPE) \ | ||
LD_CASES(ORDER, SCOPE, _gen) \ | ||
LD_CASES(ORDER, SCOPE, _global) \ | ||
LD_CASES(ORDER, SCOPE, _shared) | ||
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#define LD_CASES_AS_SCOPES(ORDER) \ | ||
LD_CASES_AS(ORDER, ) \ | ||
LD_CASES_AS(ORDER, _cta) \ | ||
LD_CASES_AS(ORDER, _sys) | ||
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LD_CASES_AS_SCOPES() | ||
LD_CASES_AS_SCOPES(_acquire) | ||
LD_VOLATILE_CASES(_gen) | ||
LD_VOLATILE_CASES(_global) | ||
LD_VOLATILE_CASES(_shared) | ||
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#undef LD_VOLATILE_CASES | ||
#undef LD_CASES | ||
#undef LD_CASES_AS | ||
#undef LD_CASES_AS_SCOPES | ||
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#define ST_VOLATILE_CASES(ADDR_SPACE) \ | ||
case NVPTX::BI__nvvm_volatile_st##ADDR_SPACE##_i: \ | ||
case NVPTX::BI__nvvm_volatile_st##ADDR_SPACE##_l: \ | ||
case NVPTX::BI__nvvm_volatile_st##ADDR_SPACE##_ll: \ | ||
return MakeScopedSt(Intrinsic::nvvm_st##ADDR_SPACE##_i_volatile); \ | ||
case NVPTX::BI__nvvm_volatile_st##ADDR_SPACE##_f: \ | ||
case NVPTX::BI__nvvm_volatile_st##ADDR_SPACE##_d: \ | ||
return MakeScopedSt(Intrinsic::nvvm_st##ADDR_SPACE##_f_volatile); | ||
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#define ST_CASES(ORDER, SCOPE, ADDR_SPACE) \ | ||
case NVPTX::BI__nvvm##ORDER##SCOPE##_st##ADDR_SPACE##_i: \ | ||
case NVPTX::BI__nvvm##ORDER##SCOPE##_st##ADDR_SPACE##_l: \ | ||
case NVPTX::BI__nvvm##ORDER##SCOPE##_st##ADDR_SPACE##_ll: \ | ||
return MakeScopedSt(Intrinsic::nvvm_st##ADDR_SPACE##_i##ORDER##SCOPE); \ | ||
case NVPTX::BI__nvvm##ORDER##SCOPE##_st##ADDR_SPACE##_f: \ | ||
case NVPTX::BI__nvvm##ORDER##SCOPE##_st##ADDR_SPACE##_d: \ | ||
return MakeScopedSt(Intrinsic::nvvm_st##ADDR_SPACE##_f##ORDER##SCOPE); | ||
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#define ST_CASES_AS(ORDER, SCOPE) \ | ||
ST_CASES(ORDER, SCOPE, _gen) \ | ||
ST_CASES(ORDER, SCOPE, _global) \ | ||
ST_CASES(ORDER, SCOPE, _shared) | ||
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#define ST_CASES_AS_SCOPES(ORDER) \ | ||
ST_CASES_AS(ORDER, ) \ | ||
ST_CASES_AS(ORDER, _cta) \ | ||
ST_CASES_AS(ORDER, _sys) | ||
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ST_CASES_AS_SCOPES() | ||
ST_CASES_AS_SCOPES(_release) | ||
ST_VOLATILE_CASES(_gen) | ||
ST_VOLATILE_CASES(_global) | ||
ST_VOLATILE_CASES(_shared) | ||
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#undef ST_VOLATILE_CASES | ||
#undef ST_CASES | ||
#undef ST_CASES_AS | ||
#undef ST_CASES_AS_SCOPES | ||
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case NVPTX::BI__nvvm_atom_add_gen_i: | ||
case NVPTX::BI__nvvm_atom_add_gen_l: | ||
case NVPTX::BI__nvvm_atom_add_gen_ll: | ||
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I think it would make things a bit more orderly if builtins would be using
__nvvm_ld
/__nvvm_st
prefix and put modifiers as suffixes in the same order they are used in the PTX instructions the builtins translate into.E.g.
__nvvm_ld_shared_acquire_gpu_i()
->ld.shared.acquire.gpu.u32
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That would be nice to have, but I would argue that being consistent with other builtins is more important. I was looking especially at atomic read-modify-write operations I worked on before, where we have for example
__nvvm_atom_acq_rel_sys_min_shared_i
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OK. We can live with the order of modifiers matching that of
__nvvm_atom
.That said,
__nvvm_atom
does have the instruction mnemonicatom
in front and so should theseld
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My understanding is that these have
atom
at the start because they also haveatom
in the PTX, which is not true forld
andst
instructions.