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[CodeGen] [AMDGPU] Attempt DAGCombine for fmul with select to ldexp #111109

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Dec 9, 2024
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63 changes: 63 additions & 0 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -903,6 +903,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
ISD::FADD,
ISD::FSUB,
ISD::FDIV,
ISD::FMUL,
ISD::FMINNUM,
ISD::FMAXNUM,
ISD::FMINNUM_IEEE,
Expand Down Expand Up @@ -14595,6 +14596,66 @@ SDValue SITargetLowering::performFDivCombine(SDNode *N,
return SDValue();
}

SDValue SITargetLowering::performFMulCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
EVT VT = N->getValueType(0);
EVT ScalarVT = VT.getScalarType();
EVT IntVT = VT.changeElementType(MVT::i32);

SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);

// It is cheaper to realize i32 inline constants as compared against
// materializing f16 or f64 (or even non-inline f32) values,
// possible via ldexp usage, as shown below :
//
// Given : A = 2^a & B = 2^b ; where a and b are integers.
// fmul x, (select y, A, B) -> ldexp( x, (select i32 y, a, b) )
// fmul x, (select y, -A, -B) -> ldexp( (fneg x), (select i32 y, a, b) )
if ((ScalarVT == MVT::f64 || ScalarVT == MVT::f32 || ScalarVT == MVT::f16) &&
(RHS.hasOneUse() && RHS.getOpcode() == ISD::SELECT)) {
const ConstantFPSDNode *TrueNode = isConstOrConstSplatFP(RHS.getOperand(1));
if (!TrueNode)
return SDValue();
const ConstantFPSDNode *FalseNode =
isConstOrConstSplatFP(RHS.getOperand(2));
if (!FalseNode)
return SDValue();

if (TrueNode->isNegative() != FalseNode->isNegative())
return SDValue();

// For f32, only non-inline constants should be transformed.
const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
if (ScalarVT == MVT::f32 &&
TII->isInlineConstant(TrueNode->getValueAPF()) &&
TII->isInlineConstant(FalseNode->getValueAPF()))
return SDValue();

int TrueNodeExpVal = TrueNode->getValueAPF().getExactLog2Abs();
if (TrueNodeExpVal == INT_MIN)
return SDValue();
int FalseNodeExpVal = FalseNode->getValueAPF().getExactLog2Abs();
if (FalseNodeExpVal == INT_MIN)
return SDValue();

SDLoc SL(N);
SDValue SelectNode =
DAG.getNode(ISD::SELECT, SL, IntVT, RHS.getOperand(0),
DAG.getSignedConstant(TrueNodeExpVal, SL, IntVT),
DAG.getSignedConstant(FalseNodeExpVal, SL, IntVT));

LHS = TrueNode->isNegative()
? DAG.getNode(ISD::FNEG, SL, VT, LHS, LHS->getFlags())
: LHS;

return DAG.getNode(ISD::FLDEXP, SL, VT, LHS, SelectNode, N->getFlags());
}

return SDValue();
}

SDValue SITargetLowering::performFMACombine(SDNode *N,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
Expand Down Expand Up @@ -14881,6 +14942,8 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
return performFSubCombine(N, DCI);
case ISD::FDIV:
return performFDivCombine(N, DCI);
case ISD::FMUL:
return performFMulCombine(N, DCI);
case ISD::SETCC:
return performSetCCCombine(N, DCI);
case ISD::FMAXNUM:
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SIISelLowering.h
Original file line number Diff line number Diff line change
Expand Up @@ -218,6 +218,7 @@ class SITargetLowering final : public AMDGPUTargetLowering {
SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performFDivCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performFMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
Expand Down
60 changes: 30 additions & 30 deletions llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
Original file line number Diff line number Diff line change
Expand Up @@ -82,10 +82,10 @@ define float @test_pow_fast_f32__integral_y(float %x, i32 %y.i) {
; CHECK-NEXT: v_cvt_f32_i32_e32 v1, v1
; CHECK-NEXT: s_mov_b32 s4, 0x800000
; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; CHECK-NEXT: v_mov_b32_e32 v3, 0x4f800000
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_cvt_i32_f32_e32 v1, v1
; CHECK-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
; CHECK-NEXT: v_mul_f32_e64 v3, |v0|, v3
; CHECK-NEXT: v_lshlrev_b32_e32 v3, 5, v3
; CHECK-NEXT: v_ldexp_f32 v3, |v0|, v3
; CHECK-NEXT: v_log_f32_e32 v3, v3
; CHECK-NEXT: v_cvt_f32_i32_e32 v4, v1
; CHECK-NEXT: v_mov_b32_e32 v2, 0x42000000
Expand All @@ -98,10 +98,10 @@ define float @test_pow_fast_f32__integral_y(float %x, i32 %y.i) {
; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
; CHECK-NEXT: v_fma_f32 v2, v2, v4, v3
; CHECK-NEXT: v_exp_f32_e32 v2, v2
; CHECK-NEXT: v_mov_b32_e32 v3, 0x1f800000
; CHECK-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
; CHECK-NEXT: v_not_b32_e32 v3, 63
; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
; CHECK-NEXT: v_lshlrev_b32_e32 v1, 31, v1
; CHECK-NEXT: v_mul_f32_e32 v2, v2, v3
; CHECK-NEXT: v_ldexp_f32 v2, v2, v3
; CHECK-NEXT: v_and_or_b32 v0, v1, v0, v2
; CHECK-NEXT: s_setpc_b64 s[30:31]
%y = sitofp i32 %y.i to float
Expand Down Expand Up @@ -228,9 +228,9 @@ define float @test_powr_fast_f32(float %x, float %y) {
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s4, 0x800000
; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; CHECK-NEXT: v_mov_b32_e32 v3, 0x4f800000
; CHECK-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
; CHECK-NEXT: v_mul_f32_e32 v0, v0, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_lshlrev_b32_e32 v3, 5, v3
; CHECK-NEXT: v_ldexp_f32 v0, v0, v3
; CHECK-NEXT: v_log_f32_e32 v0, v0
; CHECK-NEXT: v_mov_b32_e32 v2, 0x42000000
; CHECK-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
Expand All @@ -242,9 +242,9 @@ define float @test_powr_fast_f32(float %x, float %y) {
; CHECK-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
; CHECK-NEXT: v_fma_f32 v0, v1, v0, v2
; CHECK-NEXT: v_exp_f32_e32 v0, v0
; CHECK-NEXT: v_mov_b32_e32 v1, 0x1f800000
; CHECK-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
; CHECK-NEXT: v_mul_f32_e32 v0, v0, v1
; CHECK-NEXT: v_not_b32_e32 v1, 63
; CHECK-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; CHECK-NEXT: v_ldexp_f32 v0, v0, v1
; CHECK-NEXT: s_setpc_b64 s[30:31]
%powr = tail call fast float @_Z4powrff(float %x, float %y)
ret float %powr
Expand Down Expand Up @@ -368,9 +368,9 @@ define float @test_pown_fast_f32(float %x, i32 %y) {
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s4, 0x800000
; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; CHECK-NEXT: v_mov_b32_e32 v3, 0x4f800000
; CHECK-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
; CHECK-NEXT: v_mul_f32_e64 v3, |v0|, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_lshlrev_b32_e32 v3, 5, v3
; CHECK-NEXT: v_ldexp_f32 v3, |v0|, v3
; CHECK-NEXT: v_log_f32_e32 v3, v3
; CHECK-NEXT: v_cvt_f32_i32_e32 v4, v1
; CHECK-NEXT: v_mov_b32_e32 v2, 0x42000000
Expand All @@ -383,10 +383,10 @@ define float @test_pown_fast_f32(float %x, i32 %y) {
; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
; CHECK-NEXT: v_fma_f32 v2, v2, v4, v3
; CHECK-NEXT: v_exp_f32_e32 v2, v2
; CHECK-NEXT: v_mov_b32_e32 v3, 0x1f800000
; CHECK-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
; CHECK-NEXT: v_not_b32_e32 v3, 63
; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
; CHECK-NEXT: v_lshlrev_b32_e32 v1, 31, v1
; CHECK-NEXT: v_mul_f32_e32 v2, v2, v3
; CHECK-NEXT: v_ldexp_f32 v2, v2, v3
; CHECK-NEXT: v_and_or_b32 v0, v1, v0, v2
; CHECK-NEXT: s_setpc_b64 s[30:31]
%call = tail call fast float @_Z4pownfi(float %x, i32 %y)
Expand Down Expand Up @@ -511,9 +511,9 @@ define float @test_pown_fast_f32_known_even(float %x, i32 %y.arg) {
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s4, 0x800000
; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; CHECK-NEXT: v_mov_b32_e32 v3, 0x4f800000
; CHECK-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
; CHECK-NEXT: v_mul_f32_e64 v0, |v0|, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_lshlrev_b32_e32 v3, 5, v3
; CHECK-NEXT: v_ldexp_f32 v0, |v0|, v3
; CHECK-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; CHECK-NEXT: v_log_f32_e32 v0, v0
; CHECK-NEXT: v_cvt_f32_i32_e32 v1, v1
Expand All @@ -527,9 +527,9 @@ define float @test_pown_fast_f32_known_even(float %x, i32 %y.arg) {
; CHECK-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
; CHECK-NEXT: v_fma_f32 v0, v0, v1, v2
; CHECK-NEXT: v_exp_f32_e32 v0, v0
; CHECK-NEXT: v_mov_b32_e32 v1, 0x1f800000
; CHECK-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
; CHECK-NEXT: v_mul_f32_e32 v0, v0, v1
; CHECK-NEXT: v_not_b32_e32 v1, 63
; CHECK-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; CHECK-NEXT: v_ldexp_f32 v0, v0, v1
; CHECK-NEXT: s_setpc_b64 s[30:31]
%y = shl i32 %y.arg, 1
%call = tail call fast float @_Z4pownfi(float %x, i32 %y)
Expand Down Expand Up @@ -651,9 +651,9 @@ define float @test_pown_fast_f32_known_odd(float %x, i32 %y.arg) {
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s4, 0x800000
; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; CHECK-NEXT: v_mov_b32_e32 v3, 0x4f800000
; CHECK-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
; CHECK-NEXT: v_mul_f32_e64 v3, |v0|, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_lshlrev_b32_e32 v3, 5, v3
; CHECK-NEXT: v_ldexp_f32 v3, |v0|, v3
; CHECK-NEXT: v_or_b32_e32 v1, 1, v1
; CHECK-NEXT: v_log_f32_e32 v3, v3
; CHECK-NEXT: v_cvt_f32_i32_e32 v1, v1
Expand All @@ -667,10 +667,10 @@ define float @test_pown_fast_f32_known_odd(float %x, i32 %y.arg) {
; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
; CHECK-NEXT: v_fma_f32 v1, v2, v1, v3
; CHECK-NEXT: v_exp_f32_e32 v1, v1
; CHECK-NEXT: v_mov_b32_e32 v2, 0x1f800000
; CHECK-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
; CHECK-NEXT: v_not_b32_e32 v2, 63
; CHECK-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; CHECK-NEXT: s_brev_b32 s4, -2
; CHECK-NEXT: v_mul_f32_e32 v1, v1, v2
; CHECK-NEXT: v_ldexp_f32 v1, v1, v2
; CHECK-NEXT: v_bfi_b32 v0, s4, v1, v0
; CHECK-NEXT: s_setpc_b64 s[30:31]
%y = or i32 %y.arg, 1
Expand Down
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