Skip to content

[SPIR-V] Disable Machine Sink pass in SPIR-V Backend #116060

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
Merged
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
11 changes: 11 additions & 0 deletions llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -102,6 +102,7 @@ class SPIRVPassConfig : public TargetPassConfig {
SPIRVTargetMachine &getSPIRVTargetMachine() const {
return getTM<SPIRVTargetMachine>();
}
void addMachineSSAOptimization() override;
void addIRPasses() override;
void addISelPrepare() override;

Expand Down Expand Up @@ -129,6 +130,16 @@ FunctionPass *SPIRVPassConfig::createTargetRegisterAllocator(bool) {
return nullptr;
}

// Disable passes that may break CFG.
void SPIRVPassConfig::addMachineSSAOptimization() {
// Some standard passes that optimize machine instructions in SSA form uses
// MI.isPHI() that doesn't account for OpPhi in SPIR-V and so are able to
// break the CFG (e.g., MachineSink).
disablePass(&MachineSinkingID);

TargetPassConfig::addMachineSSAOptimization();
}

// Disable passes that break from assuming no virtual registers exist.
void SPIRVPassConfig::addPostRegAlloc() {
// Do not work with vregs instead of physical regs.
Expand Down
Loading