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AMDGPU: Delete spills of undef values #119684

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Merged
merged 2 commits into from
Dec 17, 2024
Merged

AMDGPU: Delete spills of undef values #119684

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67b9d48
AMDGPU: Delete spills of undef values
arsenm Mar 28, 2022
13d828c
Move where undef sgpr spills are deleted
arsenm Dec 12, 2024
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7 changes: 7 additions & 0 deletions llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -422,6 +422,13 @@ bool SILowerSGPRSpills::run(MachineFunction &MF) {
if (!TII->isSGPRSpill(MI))
continue;

if (MI.getOperand(0).isUndef()) {
if (Indexes)
Indexes->removeMachineInstrFromMaps(MI);
MI.eraseFromParent();
continue;
}

int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex();
assert(MFI.getStackID(FI) == TargetStackID::SGPRSpill);

Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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Expand Up @@ -1956,6 +1956,9 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, int Index,
RegScavenger *RS, SlotIndexes *Indexes,
LiveIntervals *LIS, bool OnlyToVGPR,
bool SpillToPhysVGPRLane) const {
assert(!MI->getOperand(0).isUndef() &&
"undef spill should have been deleted earlier");

SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS);

ArrayRef<SpilledReg> VGPRSpills =
Expand Down Expand Up @@ -2377,6 +2380,11 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
case AMDGPU::SI_SPILL_WWM_AV32_SAVE: {
const MachineOperand *VData = TII->getNamedOperand(*MI,
AMDGPU::OpName::vdata);
if (VData->isUndef()) {
MI->eraseFromParent();
return true;
}

assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
MFI->getStackPtrOffsetReg());

Expand Down
42 changes: 42 additions & 0 deletions llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
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Expand Up @@ -54,3 +54,45 @@ body: |
SI_SPILL_S64_SAVE renamable $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s64) into %stack.0, align 4, addrspace 5)

...

---
name: sgpr_spill_s32_undef
tracksRegLiveness: true
machineFunctionInfo:
isEntryFunction: true
hasSpilledSGPRs: true
scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
stackPtrOffsetReg: '$sgpr32'
stack:
- { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
body: |
bb.0:
; CHECK-LABEL: name: sgpr_spill_s32_undef
; CHECK: body:
; CHECK-NEXT: bb.0:
; CHECK-NOT: {{.+}}
; CHECK: ...
SI_SPILL_S32_SAVE undef $sgpr8, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s32) into %stack.0, align 4, addrspace 5)

...

---
name: sgpr_spill_s64_undef
tracksRegLiveness: true
machineFunctionInfo:
isEntryFunction: true
hasSpilledSGPRs: true
scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
stackPtrOffsetReg: '$sgpr32'
stack:
- { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill }
body: |
bb.0:
; CHECK-LABEL: name: sgpr_spill_s64_undef
; CHECK: body:
; CHECK-NEXT: bb.0:
; CHECK-NOT: {{.+}}
; CHECK: ...
SI_SPILL_S64_SAVE undef $sgpr8_sgpr9, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store (s64) into %stack.0, align 4, addrspace 5)

...
34 changes: 34 additions & 0 deletions llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
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Expand Up @@ -71,3 +71,37 @@ body: |
; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: (store (s32) into %stack.0 + 4, addrspace 5)
SI_SPILL_A64_SAVE killed $agpr0_agpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5)
...

---
name: spill_a32_undef
tracksRegLiveness: true
stack:
- { id: 0, type: spill-slot, size: 4, alignment: 4 }
machineFunctionInfo:
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
stackPtrOffsetReg: '$sgpr32'
frameOffsetReg: '$sgpr33'
body: |
bb.0:
; CHECK-LABEL: name: spill_a32_undef
; CHECK: S_ENDPGM 0
SI_SPILL_A32_SAVE undef $agpr0, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)
S_ENDPGM 0
...

---
name: spill_a64_undef
tracksRegLiveness: true
stack:
- { id: 0, type: spill-slot, size: 8, alignment: 4 }
machineFunctionInfo:
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
stackPtrOffsetReg: '$sgpr32'
frameOffsetReg: '$sgpr33'
body: |
bb.0:
; CHECK-LABEL: name: spill_a64_undef
; CHECK: S_ENDPGM 0
SI_SPILL_A64_SAVE undef $agpr0_agpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5)
S_ENDPGM 0
...
34 changes: 34 additions & 0 deletions llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
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Expand Up @@ -153,3 +153,37 @@ body: |
; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0 + 12, addrspace 5)
SI_SPILL_V128_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.0, addrspace 5)
...

---
name: spill_v32_undef
tracksRegLiveness: true
stack:
- { id: 0, type: spill-slot, size: 4, alignment: 4 }
machineFunctionInfo:
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
stackPtrOffsetReg: '$sgpr32'
frameOffsetReg: '$sgpr33'
body: |
bb.0:
; CHECK-LABEL: name: spill_v32_undef
; CHECK: S_NOP 0, implicit undef $vgpr0
SI_SPILL_V32_SAVE undef $vgpr0, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5)
S_NOP 0, implicit undef $vgpr0
...

---
name: spill_v64_undef
tracksRegLiveness: true
stack:
- { id: 0, type: spill-slot, size: 8, alignment: 4 }
machineFunctionInfo:
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
stackPtrOffsetReg: '$sgpr32'
frameOffsetReg: '$sgpr33'
body: |
bb.0:
; CHECK-LABEL: name: spill_v64_undef
; CHECK: S_NOP 0, implicit undef $vgpr0_vgpr1
SI_SPILL_V64_SAVE undef $vgpr0_vgpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5)
S_NOP 0, implicit undef $vgpr0_vgpr1
...
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