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[Target] Use TableGen named argument syntax. NFC. #133418

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[Target] Use TableGen named argument syntax. NFC. #133418

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6 changes: 3 additions & 3 deletions llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
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Expand Up @@ -88,9 +88,9 @@ def SDT_AArch64RDSVL : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>;
def AArch64rdsvl : SDNode<"AArch64ISD::RDSVL", SDT_AArch64RDSVL>;

let Predicates = [HasSMEandIsNonStreamingSafe] in {
def RDSVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdsvl", /*streaming_sve=*/0b1>;
def ADDSPL_XXI : sve_int_arith_vl<0b1, "addspl", /*streaming_sve=*/0b1>;
def ADDSVL_XXI : sve_int_arith_vl<0b0, "addsvl", /*streaming_sve=*/0b1>;
def RDSVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdsvl", streaming_sve = 0b1>;
def ADDSPL_XXI : sve_int_arith_vl<0b1, "addspl", streaming_sve = 0b1>;
def ADDSVL_XXI : sve_int_arith_vl<0b0, "addsvl", streaming_sve = 0b1>;

def : Pat<(AArch64rdsvl (i32 simm6_32b:$imm)), (RDSVLI_XI simm6_32b:$imm)>;
}
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16 changes: 8 additions & 8 deletions llvm/lib/Target/AArch64/SMEInstrFormats.td
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Expand Up @@ -869,8 +869,8 @@ multiclass sme_mem_ld_v_ss<string mnemonic, bit is_col> {
}

multiclass sme_mem_ld_ss<string mnemonic> {
defm _H : sme_mem_ld_v_ss<mnemonic, /*is_col=*/0b0>;
defm _V : sme_mem_ld_v_ss<mnemonic, /*is_col=*/0b1>;
defm _H : sme_mem_ld_v_ss<mnemonic, is_col = 0b0>;
defm _V : sme_mem_ld_v_ss<mnemonic, is_col = 0b1>;
}

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -999,8 +999,8 @@ multiclass sme_mem_st_v_ss<string mnemonic, bit is_col> {
}

multiclass sme_mem_st_ss<string mnemonic> {
defm _H : sme_mem_st_v_ss<mnemonic, /*is_col=*/0b0>;
defm _V : sme_mem_st_v_ss<mnemonic, /*is_col=*/0b1>;
defm _H : sme_mem_st_v_ss<mnemonic, is_col = 0b0>;
defm _V : sme_mem_st_v_ss<mnemonic, is_col = 0b1>;
}

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -1256,8 +1256,8 @@ multiclass sme_vector_v_to_tile<string mnemonic, bit is_col> {
}

multiclass sme_vector_to_tile<string mnemonic> {
defm _H : sme_vector_v_to_tile<mnemonic, /*is_col=*/0b0>;
defm _V : sme_vector_v_to_tile<mnemonic, /*is_col=*/0b1>;
defm _H : sme_vector_v_to_tile<mnemonic, is_col = 0b0>;
defm _V : sme_vector_v_to_tile<mnemonic, is_col = 0b1>;
}

class sme_tile_to_vector_base<bit Q, bit V, bits<2> sz, dag outs, dag ins,
Expand Down Expand Up @@ -1423,8 +1423,8 @@ multiclass sme_tile_to_vector_v<string mnemonic, bit is_col> {
}

multiclass sme_tile_to_vector<string mnemonic> {
defm _H : sme_tile_to_vector_v<mnemonic, /*is_col=*/0b0>;
defm _V : sme_tile_to_vector_v<mnemonic, /*is_col=*/0b1>;
defm _H : sme_tile_to_vector_v<mnemonic, is_col = 0b0>;
defm _V : sme_tile_to_vector_v<mnemonic, is_col = 0b1>;
}

//===----------------------------------------------------------------------===//
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/BUFInstructions.td
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Expand Up @@ -947,10 +947,10 @@ defm BUFFER_LOAD_DWORDX2 : MUBUF_Pseudo_Loads <
"buffer_load_dwordx2", v2i32
>;
defm BUFFER_LOAD_DWORDX3 : MUBUF_Pseudo_Loads_Lds <
"buffer_load_dwordx3", v3i32, /*LDSPred=*/HasGFX950Insts
"buffer_load_dwordx3", v3i32, LDSPred = HasGFX950Insts
>;
defm BUFFER_LOAD_DWORDX4 : MUBUF_Pseudo_Loads_Lds <
"buffer_load_dwordx4", v4i32, /*LDSPred=*/HasGFX950Insts
"buffer_load_dwordx4", v4i32, LDSPred = HasGFX950Insts
>;

defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, atomic_load_8_global>;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/DSInstructions.td
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Expand Up @@ -1308,7 +1308,7 @@ multiclass DS_Real_gfx12<bits<8> op, string name = !tolower(NAME), bit needAlias
let DecoderNamespace = "GFX12" in
def _gfx12 :
Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX12,
name, /*hasGDS=*/false>;
name, hasGDS = false>;
if !and(needAlias, !ne(ps.Mnemonic, name)) then
def : AMDGPUMnemonicAlias<ps.Mnemonic, name>;
} // End AssemblerPredicate
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8 changes: 4 additions & 4 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
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Expand Up @@ -1214,7 +1214,7 @@ def FORMAT : CustomOperand<i8>;
let PrintInHex = 1 in
def DMask : NamedIntOperand<"dmask">;

def Dim : CustomOperand<i8, /*optional=*/1>;
def Dim : CustomOperand<i8, optional = 1>;

def dst_sel : SDWAOperand<"dst_sel", "SDWADstSel">;
def src0_sel : SDWAOperand<"src0_sel", "SDWASrc0Sel">;
Expand Down Expand Up @@ -2061,7 +2061,7 @@ class getInsVOP3OpSel <RegisterOperand Src0RC, RegisterOperand Src1RC,
dag ret = getInsVOP3Base<Src0RC, Src1RC,
Src2RC, NumSrcArgs,
HasClamp, 1/*HasModifiers*/, 1/*HasSrc2Mods*/, HasOMod,
Src0Mod, Src1Mod, Src2Mod, /*HasOpSel=*/1>.ret;
Src0Mod, Src1Mod, Src2Mod, HasOpSel = 1>.ret;
}

class getInsDPPBase <RegisterOperand OldRC, RegisterOperand Src0RC, RegisterOperand Src1RC,
Expand Down Expand Up @@ -2798,7 +2798,7 @@ def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i16, untyped]>;
def VOP_F16_F16_I32 : VOPProfile <[f16, f16, i32, untyped]>;
def VOP_I16_I16_I16 : VOPProfile <[i16, i16, i16, untyped]>;
def VOP_I16_I16_I16_ARITH : VOPProfile <[i16, i16, i16, untyped], /*EnableClamp=*/1>;
def VOP_I16_I16_I16_ARITH : VOPProfile <[i16, i16, i16, untyped], _EnableClamp = 1>;

def VOP_I16_I16_I16_I16 : VOPProfile <[i16, i16, i16, i16, untyped]>;
def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>;
Expand Down Expand Up @@ -2846,7 +2846,7 @@ def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
def VOP_I32_I32_I32_ARITH : VOPProfile <[i32, i32, i32, untyped], /*EnableClamp=*/1>;
def VOP_I32_I32_I32_ARITH : VOPProfile <[i32, i32, i32, untyped], _EnableClamp = 1>;
def VOP_V2F16_F32_F32 : VOPProfile <[v2f16, f32, f32, untyped]>;
def VOP_F32_F16_F16_F16 : VOPProfile <[f32, f16, f16, f16]>;
def VOP_V2BF16_F32_F32 : VOPProfile <[v2bf16, f32, f32, untyped]>;
Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.td
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Expand Up @@ -158,8 +158,8 @@ def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> {
let HWEncoding = VCC_LO.HWEncoding;
}

defm EXEC_LO : SIRegLoHi16<"exec_lo", 126, /*ArtificialHigh=*/1, /*isVGPR=*/0,
/*isAGPR=*/0, /*DwarfEncodings=*/[1, 1]>;
defm EXEC_LO : SIRegLoHi16<"exec_lo", 126, ArtificialHigh = 1, isVGPR = 0,
isAGPR = 0, DwarfEncodings = [1, 1]>;
defm EXEC_HI : SIRegLoHi16<"exec_hi", 127>;

def EXEC : RegisterWithSubRegs<"exec", [EXEC_LO, EXEC_HI]>, DwarfRegNum<[17, 1]> {
Expand Down Expand Up @@ -299,25 +299,25 @@ def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>;
// SGPR registers
foreach Index = 0...105 in {
defm SGPR#Index :
SIRegLoHi16 <"s"#Index, Index, /*ArtificialHigh=*/1,
/*isVGPR=*/0, /*isAGPR=*/0, /*DwarfEncodings=*/
SIRegLoHi16 <"s"#Index, Index, ArtificialHigh = 1,
isVGPR = 0, isAGPR = 0, DwarfEncodings =
[!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024)),
!if(!le(Index, 63), !add(Index, 32), !add(Index, 1024))]>;
}

// VGPR registers
foreach Index = 0...255 in {
defm VGPR#Index :
SIRegLoHi16 <"v"#Index, Index, /*ArtificialHigh=*/ 0,
/*isVGPR=*/ 1, /*isAGPR=*/ 0, /*DwarfEncodings=*/
SIRegLoHi16 <"v"#Index, Index, ArtificialHigh = 0,
isVGPR = 1, isAGPR = 0, DwarfEncodings =
[!add(Index, 2560), !add(Index, 1536)]>;
}

// AccVGPR registers
foreach Index = 0...255 in {
defm AGPR#Index :
SIRegLoHi16 <"a"#Index, Index, /*ArtificialHigh=*/ 1,
/*isVGPR=*/ 0, /*isAGPR=*/ 1, /*DwarfEncodings=*/
SIRegLoHi16 <"a"#Index, Index, ArtificialHigh = 1,
isVGPR = 0, isAGPR = 1, DwarfEncodings =
[!add(Index, 3072), !add(Index, 2048)]>;
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SMInstructions.td
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Expand Up @@ -932,7 +932,7 @@ multiclass SMRD_Pattern <string Instr, ValueType vt, bit immci = true> {
// XNACK is enabled and the load wasn't naturally aligned. The constrained sload variant.
if !gt(vt.Size, 32) then {
let OtherPredicates = [HasXNACKEnabled], AddedComplexity = 101 in
defm: SMRD_Patterns <Instr, vt, smrd_load, /*immci=*/false, /*suffix=*/"_ec">;
defm: SMRD_Patterns <Instr, vt, smrd_load, immci = false, suffix = "_ec">;
}

// XNACK is disabled.
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/VOP1Instructions.td
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Expand Up @@ -767,15 +767,15 @@ def VOP_SWAP_I16 : VOPProfile_True16<VOP_I16_I16> {
}

let SubtargetPredicate = isGFX11Plus in {
def V_SWAP_B16 : VOP1_Pseudo<"v_swap_b16", VOP_SWAP_I16, [], /* VOP1Only= */true> {
def V_SWAP_B16 : VOP1_Pseudo<"v_swap_b16", VOP_SWAP_I16, [], VOP1Only = true> {
let Constraints = "$vdst = $src1, $vdst1 = $src0";
let DisableEncoding = "$vdst1, $src1";
let SchedRW = [Write64Bit, Write64Bit];
let True16Predicate = UseRealTrue16Insts;
}
// Restrict src0 to be VGPR
def V_PERMLANE64_B32 : VOP1_Pseudo<"v_permlane64_b32", VOP_MOVRELS,
[], /*VOP1Only=*/ 1>;
[], VOP1Only = 1>;
defm V_MOV_B16 : VOP1Inst_t16<"v_mov_b16", VOP_I16_I16>;
defm V_NOT_B16 : VOP1Inst_t16<"v_not_b16", VOP_I16_I16>;
defm V_CVT_I32_I16 : VOP1Inst_t16<"v_cvt_i32_i16", VOP_I32_I16>;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/VOP2Instructions.td
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Expand Up @@ -604,7 +604,7 @@ def VOP_DOT_ACC_I32_I32 : VOP_DOT_ACC<i32, i32> {
}

// Write out to vcc or arbitrary SGPR.
def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], /*EnableClamp=*/1> {
def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], _EnableClamp = 1> {
let Asm32 = "$vdst, vcc, $src0, $src1";
let AsmVOP3Base = "$vdst, $sdst, $src0, $src1$clamp";
let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
Expand All @@ -630,7 +630,7 @@ def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped], /*EnableClamp=*/

// Write out to vcc or arbitrary SGPR and read in from vcc or
// arbitrary SGPR.
def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], /*EnableClamp=*/1> {
def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1], _EnableClamp = 1> {
let HasSrc2Mods = 0;
let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/VOP3PInstructions.td
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Expand Up @@ -890,7 +890,7 @@ class MAIInst<string OpName, VOPProfile P, SDPatternOperator node, bit Scaled =
//
// FIXME: Usual syntax for op_sel is quite hostile here.
class ScaledMAIInst<string OpName, MAIInst BaseInst, SDPatternOperator node> :
MAIInst<OpName, BaseInst.Pfl, node, /*Scaled=*/true> {
MAIInst<OpName, BaseInst.Pfl, node, Scaled = true> {
// Append operands from V_MFMA_LD_SCALE_B32, but we need to rename them.
let InOperandList = !con(BaseInst.InOperandList,
(ins VSrc_b32:$scale_src0,
Expand Down Expand Up @@ -2046,11 +2046,11 @@ multiclass VOP3PX_Real_ScaledMFMA<bits<7> op> {
DecoderNamespace = "GFX940",
AsmString = Name # PS_ACD.AsmOperands, Constraints = "" in {
def _gfx940_acd : VOP3P_Real<PS_ACD, SIEncodingFamily.GFX940>,
VOP3PXe <op, PS_ACD.Pfl, /*acc_cd=*/1>,
VOP3PXe <op, PS_ACD.Pfl, acc_cd = 1>,
MFMA_F8F6F4_WithSizeTable_Helper<PS_ACD, F8F8Name#"_gfx940_acd">;

def _gfx940_vcd : VOP3P_Real<PS_VCD, SIEncodingFamily.GFX940>,
VOP3PXe <op, PS_VCD.Pfl, /*acc_cd=*/0>,
VOP3PXe <op, PS_VCD.Pfl, acc_cd = 0>,
MFMA_F8F6F4_WithSizeTable_Helper<PS_VCD, F8F8Name#"_gfx940_vcd">;
}
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMInstrCDE.td
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Expand Up @@ -52,7 +52,7 @@ def imm_13b : BitWidthImm<13>;
class CDE_Instr<bit acc, dag oops, dag iops, string asm, string cstr>
: Thumb2XI<oops, !con((ins p_imm:$coproc), iops),
AddrModeNone, /*sz=*/4, NoItinerary,
asm, cstr, /*pattern=*/[]>,
asm, cstr, pattern = []>,
Sched<[]> {
bits<3> coproc;

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/M68k/M68kRegisterInfo.td
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Expand Up @@ -70,8 +70,8 @@ defm SP : MxAddressRegister<7, "sp", ["usp", "ssp", "isp", "a7"]>;

// Floating Point Registers
class MxFPRegister<int INDEX, string REG_NAME, list<string> ALTNAMES = []>
: MxReg<REG_NAME, INDEX, /*SUBREGS=*/[], /*SUBIDX=*/[],
/*DWREGS=*/[!add(18,INDEX)], ALTNAMES>;
: MxReg<REG_NAME, INDEX, SUBREGS = [], SUBIDX = [],
DWREGS = [!add(18,INDEX)], ALTNAMES>;

foreach i = {0-7} in
def FP#i : MxFPRegister<i, "fp"#i>;
Expand Down
26 changes: 13 additions & 13 deletions llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
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Expand Up @@ -819,8 +819,8 @@ defm SUB_i1 : ADD_SUB_i1<sub>;

// int16, int32, and int64 signed addition. Since nvptx is 2's complement, we
// also use these for unsigned arithmetic.
defm ADD : I3<"add.s", add, /*commutative=*/ true>;
defm SUB : I3<"sub.s", sub, /*commutative=*/ false>;
defm ADD : I3<"add.s", add, commutative = true>;
defm SUB : I3<"sub.s", sub, commutative = false>;

def ADD16x2 : I16x2<"add.s", add>;

Expand All @@ -832,18 +832,18 @@ defm SUBCC : ADD_SUB_INT_CARRY<"sub.cc", subc>;
defm ADDCCC : ADD_SUB_INT_CARRY<"addc.cc", adde>;
defm SUBCCC : ADD_SUB_INT_CARRY<"subc.cc", sube>;

defm MULT : I3<"mul.lo.s", mul, /*commutative=*/ true>;
defm MULT : I3<"mul.lo.s", mul, commutative = true>;

defm MULTHS : I3<"mul.hi.s", mulhs, /*commutative=*/ true>;
defm MULTHU : I3<"mul.hi.u", mulhu, /*commutative=*/ true>;
defm MULTHS : I3<"mul.hi.s", mulhs, commutative = true>;
defm MULTHU : I3<"mul.hi.u", mulhu, commutative = true>;

defm SDIV : I3<"div.s", sdiv, /*commutative=*/ false>;
defm UDIV : I3<"div.u", udiv, /*commutative=*/ false>;
defm SDIV : I3<"div.s", sdiv, commutative = false>;
defm UDIV : I3<"div.u", udiv, commutative = false>;

// The ri versions of rem.s and rem.u won't be selected; DAGCombiner::visitSREM
// will lower it.
defm SREM : I3<"rem.s", srem, /*commutative=*/ false>;
defm UREM : I3<"rem.u", urem, /*commutative=*/ false>;
defm SREM : I3<"rem.s", srem, commutative = false>;
defm UREM : I3<"rem.u", urem, commutative = false>;

// Integer absolute value. NumBits should be one minus the bit width of RC.
// This idiom implements the algorithm at
Expand All @@ -858,10 +858,10 @@ defm ABS_32 : ABS<i32, Int32Regs, ".s32">;
defm ABS_64 : ABS<i64, Int64Regs, ".s64">;

// Integer min/max.
defm SMAX : I3<"max.s", smax, /*commutative=*/ true>;
defm UMAX : I3<"max.u", umax, /*commutative=*/ true>;
defm SMIN : I3<"min.s", smin, /*commutative=*/ true>;
defm UMIN : I3<"min.u", umin, /*commutative=*/ true>;
defm SMAX : I3<"max.s", smax, commutative = true>;
defm UMAX : I3<"max.u", umax, commutative = true>;
defm SMIN : I3<"min.s", smin, commutative = true>;
defm UMIN : I3<"min.u", umin, commutative = true>;

def SMAX16x2 : I16x2<"max.s", smax>;
def UMAX16x2 : I16x2<"max.u", umax>;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoV.td
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Expand Up @@ -1699,10 +1699,10 @@ def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VR:$vd_wb),
let Predicates = [HasVInstructions] in {
// Vector Slide Instructions
let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
defm VSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110, /*slidesUp=*/true>;
defm VSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110, slidesUp = true>;
defm VSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110>;
} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
defm VSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111, /*slidesUp=*/false>;
defm VSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111, slidesUp = false>;
let ElementsDependOn = EltDepsVL in
defm VSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111>;
} // Predicates = [HasVInstructions]
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
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Expand Up @@ -1003,9 +1003,9 @@ foreach mx = ["M8", "M4", "M2"] in {
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = SiFiveP600VSlideXComplex<mx>.latency in {
let ReleaseAtCycles = [SiFiveP600VSlideXComplex<mx, /*isUp=*/true>.cycles] in
let ReleaseAtCycles = [SiFiveP600VSlideXComplex<mx, isUp = true>.cycles] in
defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFiveP600VEXQ1], mx, IsWorstCase>;
let ReleaseAtCycles = [SiFiveP600VSlideXComplex<mx, /*isUp=*/false>.cycles] in
let ReleaseAtCycles = [SiFiveP600VSlideXComplex<mx, isUp = false>.cycles] in
defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFiveP600VEXQ1], mx, IsWorstCase>;
}
}
Expand Down
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