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[Clang] Partially fix m68k alignments #144740

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[Clang] Partially fix m68k alignments #144740

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1 change: 1 addition & 0 deletions clang/lib/Basic/Targets/M68k.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -56,6 +56,7 @@ M68kTargetInfo::M68kTargetInfo(const llvm::Triple &Triple,
SizeType = UnsignedInt;
PtrDiffType = SignedInt;
IntPtrType = SignedInt;
IntAlign = LongAlign = PointerAlign = 16;
}

bool M68kTargetInfo::setCPU(const std::string &Name) {
Expand Down
52 changes: 51 additions & 1 deletion clang/test/CodeGen/bitfield-access-pad.c
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
// RUN: %clang_cc1 -triple=hexagon-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT-T %s

// Big endian
// RUN: %clang_cc1 -triple=m68k-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT-T %s
// RUN: %clang_cc1 -triple=m68k-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT-M68K %s
// RUN: %clang_cc1 -triple=mips-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT-T %s

// And now a few with -fno-bitfield-type-align. Precisely how this behaves is
Expand All @@ -45,6 +45,7 @@ struct P1 {
// CHECK-LABEL: LLVMType:%struct.P1 =
// LAYOUT-T-SAME: type { i8, i8, [2 x i8] }
// LAYOUT-ARM64-T-SAME: type { i8, i8 }
// LAYOUT-M68K-SAME: type { i8, i8 }
// LAYOUT-NT-SAME: type { i8, i8 }
// LAYOUT-STRICT-NT-SAME: type { i8, i8 }
// LAYOUT-DWN32-SAME: type { i8, [3 x i8], i8, [3 x i8] }
Expand All @@ -60,6 +61,9 @@ struct P1 {

// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:1
//
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:1

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:4
Expand All @@ -75,6 +79,7 @@ struct P2 {
// CHECK-LABEL: LLVMType:%struct.P2 =
// LAYOUT-T-SAME: type { i8, i8, i8, i8 }
// LAYOUT-ARM64-T-SAME: type { i8, i8, i8, i8 }
// LAYOUT-M68K-SAME: type { i8, i8, i8, i8 }
// LAYOUT-NT-SAME: type { i8, i8 }
// LAYOUT-STRICT-NT-SAME: type { i8, i8 }
// LAYOUT-DWN32-SAME: type { i8, [3 x i8], i8, [3 x i8] }
Expand All @@ -90,6 +95,9 @@ struct P2 {

// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:2
//
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:2

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:4
Expand All @@ -105,6 +113,7 @@ struct P3 {
// CHECK-LABEL: LLVMType:%struct.P3 =
// LAYOUT-T-SAME: type { i8, [3 x i8], i8, [3 x i8] }
// LAYOUT-ARM64-T-SAME: type { i8, [3 x i8], i8, [3 x i8] }
// LAYOUT-M68K-SAME: type { i8, i8, i8, i8 }
// LAYOUT-NT-SAME: type { i8, i8 }
// LAYOUT-STRICT-NT-SAME: type { i8, i8 }
// LAYOUT-DWN32-SAME: type { i8, [3 x i8], i8, [3 x i8] }
Expand All @@ -120,6 +129,9 @@ struct P3 {

// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:4
//
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:2

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:4
Expand All @@ -134,6 +146,7 @@ struct P4 {
// CHECK-LABEL: LLVMType:%struct.P4 =
// LAYOUT-T-SAME: type { i8, [3 x i8], i8, [3 x i8] }
// LAYOUT-ARM64-T-SAME: type { i8, [3 x i8], i8, [3 x i8] }
// LAYOUT-M68K-SAME: type { i8, i8, i8, i8 }
// LAYOUT-NT-SAME: type { i8, i8 }
// LAYOUT-STRICT-NT-SAME: type { i8, i8 }
// LAYOUT-DWN32-SAME: type { i8, [3 x i8], i8, [3 x i8] }
Expand All @@ -149,6 +162,9 @@ struct P4 {

// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:4
//
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:2

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:4
Expand All @@ -162,6 +178,7 @@ struct P5 {
// CHECK-LABEL: LLVMType:%struct.P5 =
// LAYOUT-T-SAME: type { i8, [3 x i8], i8, [3 x i8] }
// LAYOUT-ARM64-T-SAME: type { i8, [3 x i8], i8, [3 x i8] }
// LAYOUT-M68K-SAME: type { i8, i8, i8, i8 }
// LAYOUT-NT-SAME: type { i8, i8 }
// LAYOUT-STRICT-NT-SAME: type { i8, i8 }
// LAYOUT-DWN32-SAME: type { i8, [3 x i8], i8, [3 x i8] }
Expand All @@ -177,6 +194,9 @@ struct P5 {

// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:4
//
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:2

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:4
Expand All @@ -192,6 +212,7 @@ struct P6 {
// CHECK-LABEL: LLVMType:%struct.P6 =
// LAYOUT-T-SAME: type { i8, [3 x i8], i8, [3 x i8] }
// LAYOUT-ARM64-T-SAME: type { i8, [3 x i8], i8, [3 x i8] }
// LAYOUT-M68K-SAME: type { i8, i8, i8, i8 }
// LAYOUT-NT-SAME: type { i8, i8 }
// LAYOUT-STRICT-NT-SAME: type { i8, i8 }
// LAYOUT-DWN32-SAME: type { i8, [3 x i8], i8, [3 x i8] }
Expand All @@ -207,6 +228,9 @@ struct P6 {

// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:4
//
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:2

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:4
Expand All @@ -220,6 +244,7 @@ struct P7 {
// CHECK-LABEL: LLVMType:%struct.P7 =
// LAYOUT-T-SAME: type { i8, i8, i8, i8 }
// LAYOUT-ARM64-T-SAME: type { i8, i8, i8, i8 }
// LAYOUT-M68K-SAME: type { i8, i8, i8, i8 }
// LAYOUT-NT-SAME: type { i8, i8 }
// LAYOUT-STRICT-NT-SAME: type { i8, i8 }
// LAYOUT-DWN32-SAME: type { i8, [3 x i8], i8, [3 x i8] }
Expand All @@ -235,6 +260,9 @@ struct P7 {

// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:2
//
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:2

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:4
Expand All @@ -250,6 +278,7 @@ struct __attribute__ ((aligned (2))) P7_align {
// CHECK-LABEL: LLVMType:%struct.P7_align =
// LAYOUT-T-SAME: type { i8, i8, i8, i8 }
// LAYOUT-ARM64-T-SAME: type { i8, i8, i8, i8 }
// LAYOUT-M68K-SAME: type { i8, i8, i8, i8 }
// LAYOUT-NT-SAME: type { i8, i8 }
// LAYOUT-STRICT-NT-SAME: type { i8, i8 }
// LAYOUT-DWN32-SAME: type { i8, [3 x i8], i8, [3 x i8] }
Expand All @@ -265,6 +294,9 @@ struct __attribute__ ((aligned (2))) P7_align {

// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:2
//
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:2

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:8 StorageOffset:4
Expand All @@ -278,6 +310,7 @@ struct P8 {
// CHECK-LABEL: LLVMType:%struct.P8 =
// LAYOUT-T-SAME: type { i8, i8, i8, i8 }
// LAYOUT-ARM64-T-SAME: type { i8, i8, i8, i8 }
// LAYOUT-M68K-SAME: type { i8, i8, i8, i8 }
// LAYOUT-NT-SAME: type { i16 }
// LAYOUT-STRICT-NT-SAME: type { i16 }
// LAYOUT-DWN32-SAME: type { i8, [3 x i8], i8, [3 x i8] }
Expand All @@ -293,6 +326,9 @@ struct P8 {

// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:8 StorageOffset:2
//
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:8 StorageOffset:2

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:8 StorageOffset:4
Expand All @@ -306,6 +342,7 @@ struct P9 {
// CHECK-LABEL: LLVMType:%struct.P9 =
// LAYOUT-T-SAME: type { i8, i8, [2 x i8] }
// LAYOUT-ARM64-T-SAME: type { i8, i8 }
// LAYOUT-M68K-SAME: type { i8, i8 }
// LAYOUT-NT-SAME: type { i16 }
// LAYOUT-STRICT-NT-SAME: type { i16 }
// LAYOUT-DWN32-SAME: type { i8, [3 x i8], i8, [3 x i8] }
Expand All @@ -321,6 +358,9 @@ struct P9 {

// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:8 StorageOffset:1
//
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:8 StorageOffset:1

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:8 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:8 StorageOffset:4
Expand All @@ -335,6 +375,7 @@ struct __attribute__((aligned(4))) P10 {
// CHECK-LABEL: LLVMType:%struct.P10 =
// LAYOUT-T-SAME: type { i32 }
// LAYOUT-ARM64-T-SAME: type { i32 }
// LAYOUT-M68K-SAME: type { i32 }
// LAYOUT-NT-SAME: type { i32 }
// LAYOUT-STRICT-NT-SAME: type { i32 }
// LAYOUT-DWN32-SAME: type { i32 }
Expand All @@ -354,6 +395,10 @@ struct __attribute__((aligned(4))) P10 {
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:32 StorageOffset:0
//
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:32 StorageOffset:0

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:32 StorageOffset:0
Expand All @@ -369,6 +414,7 @@ struct __attribute__((aligned(4))) P11 {
// CHECK-LABEL: LLVMType:%struct.P11 =
// LAYOUT-T-SAME: type { i32 }
// LAYOUT-ARM64-T-SAME: type { i32 }
// LAYOUT-M68K-SAME: type { i32 }
// LAYOUT-NT-SAME: type { i32 }
// LAYOUT-STRICT-NT-SAME: type { i32 }
// LAYOUT-DWN32-SAME: type { i32 }
Expand All @@ -388,6 +434,10 @@ struct __attribute__((aligned(4))) P11 {
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-ARM64-T-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:10 IsSigned:0 StorageSize:32 StorageOffset:0
//
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:10 IsSigned:0 StorageSize:32 StorageOffset:0

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:7 IsSigned:0 StorageSize:32 StorageOffset:0
Expand Down
22 changes: 21 additions & 1 deletion clang/test/CodeGenCXX/bitfield-access-empty.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@

// Big endian
// RUN: %clang_cc1 -triple=lanai-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s
// RUN: %clang_cc1 -triple=m68k-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s
// RUN: %clang_cc1 -triple=m68k-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT-M68K %s
// RUN: %clang_cc1 -triple=mips-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s
// RUN: %clang_cc1 -triple=mips64-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s
// RUN: %clang_cc1 -triple=sparc-elf %s -emit-llvm -o /dev/null -fdump-record-layouts-simple | FileCheck --check-prefixes CHECK,LAYOUT %s
Expand All @@ -51,13 +51,17 @@ struct P1 {
// CHECK-LABEL: LLVMType:%struct.P1 =
// LAYOUT-SAME: type { i16, i16 }
// LAYOUT-DWN32-SAME: type { i16, i16 }
// LAYOUT-DWN32-M68K: type { i16, i16 }
// CHECK-NEXT: NonVirtualBaseLLVMType:%struct.P1 =
// CHECK: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:16 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:16 StorageOffset:2

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:16 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:16 StorageOffset:2

// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:16 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:16 StorageOffset:2
// CHECK-NEXT: ]>

struct P2 {
Expand All @@ -68,13 +72,17 @@ struct P2 {
// CHECK-LABEL: LLVMType:%struct.P2 =
// LAYOUT-SAME: type { i16, i16 }
// LAYOUT-DWN32-SAME: type { i16, i16 }
// LAYOUT-M68K-SAME: type { i16, i16 }
// CHECK-NEXT: NonVirtualBaseLLVMType:%struct.P2 =
// CHECK: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:15 IsSigned:0 StorageSize:16 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:15 IsSigned:0 StorageSize:16 StorageOffset:2

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:15 IsSigned:0 StorageSize:16 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:15 IsSigned:0 StorageSize:16 StorageOffset:2

// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:15 IsSigned:0 StorageSize:16 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:15 IsSigned:0 StorageSize:16 StorageOffset:2
// CHECK-NEXT: ]>

struct P3 {
Expand All @@ -85,13 +93,17 @@ struct P3 {
// CHECK-LABEL: LLVMType:%struct.P3 =
// LAYOUT-SAME: type { i16, [2 x i8], i16, [2 x i8] }
// LAYOUT-DWN32-SAME: type <{ i16, i8, i16 }>
// LAYOUT-M68K-SAME: type <{ i16, i8, i16, i8 }>
// CHECK-NEXT: NonVirtualBaseLLVMType:%struct.P3 =
// CHECK: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:16 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:16 StorageOffset:4

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:16 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:16 StorageOffset:3

// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:16 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:16 StorageOffset:3
// CHECK-NEXT: ]>

struct P4 {
Expand Down Expand Up @@ -121,13 +133,17 @@ struct P6 {
// CHECK-LABEL: LLVMType:%struct.P6 =
// LAYOUT-SAME: type { i32, i32 }
// LAYOUT-DWN32-SAME: type { i32, i32 }
// LAYOUT-M68K-SAME: type { i32, i32 }
// CHECK-NEXT: NonVirtualBaseLLVMType:%struct.P6 =
// CHECK: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:32 StorageOffset:0

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:32 StorageOffset:0

// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:32 StorageOffset:0
// CHECK-NEXT: ]>

struct P7 {
Expand All @@ -139,11 +155,15 @@ struct P7 {
// CHECK-LABEL: LLVMType:%struct.P7 =
// LAYOUT-SAME: type { i32, i32 }
// LAYOUT-DWN32-SAME: type { i32, i32 }
// LAYOUT-M68K-SAME: type { i32, i32 }
// CHECK-NEXT: NonVirtualBaseLLVMType:%struct.P7 =
// CHECK: BitFields:[
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:32 StorageOffset:0

// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-DWN32-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:32 StorageOffset:0

// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:16 IsSigned:0 StorageSize:32 StorageOffset:0
// LAYOUT-M68K-NEXT: <CGBitFieldInfo Offset:{{[0-9]+}} Size:8 IsSigned:0 StorageSize:32 StorageOffset:0
// CHECK-NEXT: ]>
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