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[Sparc] Change register spelling to lowercase (NFC) #65464

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Merged
merged 1 commit into from
Sep 7, 2023
Merged

[Sparc] Change register spelling to lowercase (NFC) #65464

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42 changes: 7 additions & 35 deletions llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1261,44 +1261,16 @@ SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,

case AsmToken::Percent: {
Parser.Lex(); // Eat the '%'.
MCRegister RegNo;
MCRegister Reg;
unsigned RegKind;
if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
StringRef name = Parser.getTok().getString();
if (matchRegisterName(Parser.getTok(), Reg, RegKind)) {
StringRef Name = Parser.getTok().getString();
Parser.Lex(); // Eat the identifier token.
E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
switch (RegNo) {
default:
Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
break;
case Sparc::PSR:
Op = SparcOperand::CreateToken("%psr", S);
break;
case Sparc::FSR:
Op = SparcOperand::CreateToken("%fsr", S);
break;
case Sparc::FQ:
Op = SparcOperand::CreateToken("%fq", S);
break;
case Sparc::CPSR:
Op = SparcOperand::CreateToken("%csr", S);
break;
case Sparc::CPQ:
Op = SparcOperand::CreateToken("%cq", S);
break;
case Sparc::WIM:
Op = SparcOperand::CreateToken("%wim", S);
break;
case Sparc::TBR:
Op = SparcOperand::CreateToken("%tbr", S);
break;
case Sparc::ICC:
if (name == "xcc")
Op = SparcOperand::CreateToken("%xcc", S);
else
Op = SparcOperand::CreateToken("%icc", S);
break;
}
if (Reg == Sparc::ICC && Name == "xcc")
Op = SparcOperand::CreateToken("%xcc", S);
else
Op = SparcOperand::CreateReg(Reg, RegKind, S, E);
break;
}
if (matchSparcAsmModifiers(EVal, E)) {
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
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Expand Up @@ -39,12 +39,12 @@ bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const {
}

void SparcInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const {
OS << '%' << StringRef(getRegisterName(Reg)).lower();
OS << '%' << getRegisterName(Reg);
}

void SparcInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg,
unsigned AltIdx) const {
OS << '%' << StringRef(getRegisterName(Reg, AltIdx)).lower();
OS << '%' << getRegisterName(Reg, AltIdx);
}

void SparcInstPrinter::printInst(const MCInst *MI, uint64_t Address,
Expand Down
5 changes: 5 additions & 0 deletions llvm/lib/Target/Sparc/Sparc.td
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Expand Up @@ -81,6 +81,10 @@ def SparcAsmParser : AsmParser {
bit ShouldEmitMatchRegisterName = 0;
}

def SparcAsmParserVariant : AsmParserVariant {
let RegisterPrefix = "%";
}

//===----------------------------------------------------------------------===//
// SPARC processors supported.
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -179,6 +183,7 @@ def Sparc : Target {
// Pull in Instruction Info:
let InstructionSet = SparcInstrInfo;
let AssemblyParsers = [SparcAsmParser];
let AssemblyParserVariants = [SparcAsmParserVariant];
let AssemblyWriters = [SparcAsmWriter];
let AllowRegisterRenaming = 1;
}
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