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[mlir][spirv][doc] Remove duplicate syntax formats #73386

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Nov 27, 2023
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[mlir][spirv][doc] Remove duplicate syntax formats #73386

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177 changes: 30 additions & 147 deletions mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -88,18 +88,11 @@ def SPIRV_FAddOp : SPIRV_ArithmeticBinaryOp<"FAdd", SPIRV_Float, [Commutative]>
let description = [{
Result Type must be a scalar or vector of floating-point type.

The types of Operand 1 and Operand 2 both must be the same as Result
The types of Operand 1 and Operand 2 both must be the same as Result
Type.

Results are computed per component.
Results are computed per component.

<!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
fadd-op ::= ssa-id `=` `spirv.FAdd` ssa-use, ssa-use
`:` float-scalar-vector-type
```
#### Example:

```mlir
Expand All @@ -117,20 +110,12 @@ def SPIRV_FDivOp : SPIRV_ArithmeticBinaryOp<"FDiv", SPIRV_Float, []> {
let description = [{
Result Type must be a scalar or vector of floating-point type.

The types of Operand 1 and Operand 2 both must be the same as Result
The types of Operand 1 and Operand 2 both must be the same as Result
Type.

Results are computed per component. The resulting value is undefined
Results are computed per component. The resulting value is undefined
if Operand 2 is 0.

<!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
fdiv-op ::= ssa-id `=` `spirv.FDiv` ssa-use, ssa-use
`:` float-scalar-vector-type
```

#### Example:

```mlir
Expand All @@ -150,21 +135,14 @@ def SPIRV_FModOp : SPIRV_ArithmeticBinaryOp<"FMod", SPIRV_Float, []> {
let description = [{
Result Type must be a scalar or vector of floating-point type.

The types of Operand 1 and Operand 2 both must be the same as Result
The types of Operand 1 and Operand 2 both must be the same as Result
Type.

Results are computed per component. The resulting value is undefined
Results are computed per component. The resulting value is undefined
if Operand 2 is 0. Otherwise, the result is the remainder r of Operand
1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the
sign of Operand 2.

<!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
fmod-op ::= ssa-id `=` `spirv.FMod` ssa-use, ssa-use
`:` float-scalar-vector-type
```
#### Example:

```mlir
Expand All @@ -182,19 +160,10 @@ def SPIRV_FMulOp : SPIRV_ArithmeticBinaryOp<"FMul", SPIRV_Float, [Commutative]>
let description = [{
Result Type must be a scalar or vector of floating-point type.

The types of Operand 1 and Operand 2 both must be the same as Result
The types of Operand 1 and Operand 2 both must be the same as Result
Type.

Results are computed per component.

<!-- End of AutoGen section -->

```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
fmul-op ::= `spirv.FMul` ssa-use, ssa-use
`:` float-scalar-vector-type
```
Results are computed per component.

#### Example:

Expand All @@ -218,17 +187,9 @@ def SPIRV_FNegateOp : SPIRV_ArithmeticUnaryOp<"FNegate", SPIRV_Float, []> {
let description = [{
Result Type must be a scalar or vector of floating-point type.

The type of Operand must be the same as Result Type.

Results are computed per component.

<!-- End of AutoGen section -->
The type of Operand must be the same as Result Type.

```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
fmul-op ::= `spirv.FNegate` ssa-use `:` float-scalar-vector-type
```
Results are computed per component.

#### Example:

Expand All @@ -249,22 +210,14 @@ def SPIRV_FRemOp : SPIRV_ArithmeticBinaryOp<"FRem", SPIRV_Float, []> {
let description = [{
Result Type must be a scalar or vector of floating-point type.

The types of Operand 1 and Operand 2 both must be the same as Result
The types of Operand 1 and Operand 2 both must be the same as Result
Type.

Results are computed per component. The resulting value is undefined
Results are computed per component. The resulting value is undefined
if Operand 2 is 0. Otherwise, the result is the remainder r of Operand
1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the
sign of Operand 1.

<!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
frem-op ::= ssa-id `=` `spirv.FRemOp` ssa-use, ssa-use
`:` float-scalar-vector-type
```

#### Example:

```mlir
Expand All @@ -282,18 +235,10 @@ def SPIRV_FSubOp : SPIRV_ArithmeticBinaryOp<"FSub", SPIRV_Float, []> {
let description = [{
Result Type must be a scalar or vector of floating-point type.

The types of Operand 1 and Operand 2 both must be the same as Result
The types of Operand 1 and Operand 2 both must be the same as Result
Type.

Results are computed per component.

<!-- End of AutoGen section -->
```
float-scalar-vector-type ::= float-type |
`vector<` integer-literal `x` float-type `>`
fsub-op ::= ssa-id `=` `spirv.FRemOp` ssa-use, ssa-use
`:` float-scalar-vector-type
```
Results are computed per component.

#### Example:

Expand All @@ -314,23 +259,15 @@ def SPIRV_IAddOp : SPIRV_ArithmeticBinaryOp<"IAdd",
let description = [{
Result Type must be a scalar or vector of integer type.

The type of Operand 1 and Operand 2 must be a scalar or vector of
The type of Operand 1 and Operand 2 must be a scalar or vector of
integer type. They must have the same number of components as Result
Type. They must have the same component width as Result Type.

The resulting value will equal the low-order N bits of the correct
result R, where N is the component width and R is computed with enough
precision to avoid overflow and underflow.

Results are computed per component.

<!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
iadd-op ::= ssa-id `=` `spirv.IAdd` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
Results are computed per component.

#### Example:

Expand Down Expand Up @@ -391,23 +328,15 @@ def SPIRV_IMulOp : SPIRV_ArithmeticBinaryOp<"IMul",
let description = [{
Result Type must be a scalar or vector of integer type.

The type of Operand 1 and Operand 2 must be a scalar or vector of
The type of Operand 1 and Operand 2 must be a scalar or vector of
integer type. They must have the same number of components as Result
Type. They must have the same component width as Result Type.

The resulting value will equal the low-order N bits of the correct
result R, where N is the component width and R is computed with enough
precision to avoid overflow and underflow.

Results are computed per component.

<!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
imul-op ::= ssa-id `=` `spirv.IMul` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
Results are computed per component.

#### Example:

Expand All @@ -431,23 +360,15 @@ def SPIRV_ISubOp : SPIRV_ArithmeticBinaryOp<"ISub",
let description = [{
Result Type must be a scalar or vector of integer type.

The type of Operand 1 and Operand 2 must be a scalar or vector of
The type of Operand 1 and Operand 2 must be a scalar or vector of
integer type. They must have the same number of components as Result
Type. They must have the same component width as Result Type.

The resulting value will equal the low-order N bits of the correct
result R, where N is the component width and R is computed with enough
precision to avoid overflow and underflow.

Results are computed per component.

<!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
isub-op ::= `spirv.ISub` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
Results are computed per component.

#### Example:

Expand Down Expand Up @@ -511,21 +432,13 @@ def SPIRV_SDivOp : SPIRV_ArithmeticBinaryOp<"SDiv",
let description = [{
Result Type must be a scalar or vector of integer type.

The type of Operand 1 and Operand 2 must be a scalar or vector of
The type of Operand 1 and Operand 2 must be a scalar or vector of
integer type. They must have the same number of components as Result
Type. They must have the same component width as Result Type.

Results are computed per component. The resulting value is undefined
Results are computed per component. The resulting value is undefined
if Operand 2 is 0.

<!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
sdiv-op ::= ssa-id `=` `spirv.SDiv` ssa-use, ssa-use
`:` integer-scalar-vector-type
```

#### Example:

```mlir
Expand All @@ -549,22 +462,15 @@ def SPIRV_SModOp : SPIRV_ArithmeticBinaryOp<"SMod",
let description = [{
Result Type must be a scalar or vector of integer type.

The type of Operand 1 and Operand 2 must be a scalar or vector of
The type of Operand 1 and Operand 2 must be a scalar or vector of
integer type. They must have the same number of components as Result
Type. They must have the same component width as Result Type.

Results are computed per component. The resulting value is undefined
Results are computed per component. The resulting value is undefined
if Operand 2 is 0. Otherwise, the result is the remainder r of Operand
1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the
sign of Operand 2.

<!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
smod-op ::= ssa-id `=` `spirv.SMod` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
#### Example:

```mlir
Expand Down Expand Up @@ -649,22 +555,15 @@ def SPIRV_SRemOp : SPIRV_ArithmeticBinaryOp<"SRem",
let description = [{
Result Type must be a scalar or vector of integer type.

The type of Operand 1 and Operand 2 must be a scalar or vector of
The type of Operand 1 and Operand 2 must be a scalar or vector of
integer type. They must have the same number of components as Result
Type. They must have the same component width as Result Type.

Results are computed per component. The resulting value is undefined
Results are computed per component. The resulting value is undefined
if Operand 2 is 0. Otherwise, the result is the remainder r of Operand
1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the
sign of Operand 1.

<!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
srem-op ::= ssa-id `=` `spirv.SRem` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
#### Example:

```mlir
Expand All @@ -686,25 +585,17 @@ def SPIRV_UDivOp : SPIRV_ArithmeticBinaryOp<"UDiv",
Result Type must be a scalar or vector of integer type, whose Signedness
operand is 0.

The types of Operand 1 and Operand 2 both must be the same as Result
The types of Operand 1 and Operand 2 both must be the same as Result
Type.

Results are computed per component. The resulting value is undefined
Results are computed per component. The resulting value is undefined
if Operand 2 is 0.

<!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
udiv-op ::= ssa-id `=` `spirv.UDiv` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
#### Example:

```mlir
%4 = spirv.UDiv %0, %1 : i32
%5 = spirv.UDiv %2, %3 : vector<4xi32>

```
}];
}
Expand Down Expand Up @@ -789,25 +680,17 @@ def SPIRV_UModOp : SPIRV_ArithmeticBinaryOp<"UMod",
Result Type must be a scalar or vector of integer type, whose Signedness
operand is 0.

The types of Operand 1 and Operand 2 both must be the same as Result
The types of Operand 1 and Operand 2 both must be the same as Result
Type.

Results are computed per component. The resulting value is undefined
Results are computed per component. The resulting value is undefined
if Operand 2 is 0.

<!-- End of AutoGen section -->
```
integer-scalar-vector-type ::= integer-type |
`vector<` integer-literal `x` integer-type `>`
umod-op ::= ssa-id `=` `spirv.UMod` ssa-use, ssa-use
`:` integer-scalar-vector-type
```
#### Example:

```mlir
%4 = spirv.UMod %0, %1 : i32
%5 = spirv.UMod %2, %3 : vector<4xi32>

```
}];

Expand Down
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