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[CodeGen] Fix generating permute bytes from register pair when the initial values are undefined #74437

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Jan 16, 2024
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6 changes: 4 additions & 2 deletions llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2360,8 +2360,10 @@ SDValue NVPTXTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
SDValue V2 = Op.getOperand(1);
uint32_t Selector = 0;
for (auto I : llvm::enumerate(SVN->getMask()))
Selector |= (I.value() << (I.index() * 4));
for (auto I : llvm::enumerate(SVN->getMask())) {
if (I.value() != -1) // -1 is a placeholder for undef.
Selector |= (I.value() << (I.index() * 4));
}

SDLoc DL(Op);
return DAG.getNode(NVPTXISD::PRMT, DL, MVT::v4i8, V1, V2,
Expand Down
18 changes: 18 additions & 0 deletions llvm/test/CodeGen/NVPTX/shuffle-vec-undef-init.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,18 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-FOUND

define void @kernel_func(ptr %in.vec, ptr %out.vec0) nounwind {
entry:
%wide.vec = load <32 x i8>, ptr %in.vec, align 64
%vec0 = shufflevector <32 x i8> %wide.vec, <32 x i8> undef, <4 x i32> <i32 0, i32 8, i32 16, i32 24>
store <4 x i8> %vec0, ptr %out.vec0, align 64
ret void

; CHECK-FOUND: prmt.b32 {{.*}} 16384;
; CHECK-FOUND: prmt.b32 {{.*}} 64;
; CHECK-FOUND: prmt.b32 {{.*}} 30224;

; CHECK: @kernel_func
; CHECK-NOT: prmt.b32 {{.*}} -1;
; CHECK: -- End function
}