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[RISCV][TTI] Cost a subvector extract at a register boundary with exact vlen #82405

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Merged
merged 3 commits into from
Feb 21, 2024
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[RISCV][TTI] Cost a subvector extract at a register boundary with exact vlen #82405

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5b3e543
[RISCV][TTI] Cost a subvector extract at a register boundary with exa…
preames Feb 20, 2024
2c525a8
Fix a bug with insufficiently aligned extracts
preames Feb 21, 2024
962163f
Update llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
preames Feb 21, 2024
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16 changes: 16 additions & 0 deletions llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -436,6 +436,22 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
if (Index == 0)
return TTI::TCC_Free;

// If we're extracting a subvector of at most m1 size at a sub-register
// boundary - which unfortunately we need exact vlen to identify - this is
// a subregister extract at worst and thus won't require a vslidedown.
// TODO: Extend for aligned m2, m4 subvector extracts
// TODO: Extend for misalgined (but contained) extracts
// TODO: Extend for scalable subvector types
if (std::pair<InstructionCost, MVT> SubLT = getTypeLegalizationCost(SubTp);
SubLT.second.isValid() && SubLT.second.isFixedLengthVector()) {
const unsigned MinVLen = ST->getRealMinVLen();
const unsigned MaxVLen = ST->getRealMaxVLen();
if (MinVLen == MaxVLen &&
SubLT.second.getScalarSizeInBits() * Index % MinVLen == 0 &&
SubLT.second.getSizeInBits() <= MinVLen)
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For extending it to m2+, checking that the extract is LMUL aligned is the same as checking that the index is a multiple of the number of elements, so you could do something like:

Suggested change
SubLT.second.getSizeInBits() <= MinVLen)
SubLT.second.getVectorNumElements() % Index == 0)

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For extending it to m2+, checking that the extract is LMUL aligned is the same as checking that the index is a multiple of the number of elements, so you could do something like:

I'll explore this in a follow up after auditing the testing for the >= m2 case.

return TTI::TCC_Free;
}

// Example sequence:
// vsetivli zero, 4, e8, mf2, tu, ma (ignored)
// vslidedown.vi v8, v9, 2
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