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Merged
merged 1 commit into from
Dec 13, 2022
Merged

[beta] Adjust miri to still be optional #3

merged 1 commit into from
Dec 13, 2022

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lukas-code
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@Mark-Simulacrum
Adjust miri to still be optional
565b8ec 
We don't distribute a miri build for beta/stable so it needs to be kept
optional. In the future it likely makes sense to switch the miri
*artifacts* to always be built, but the rustup component to not be
included -- this will avoid some of this pain.
@pietroalbini pietroalbini merged commit cfccd7e into pietroalbini:pa-beta-1.67.0 Dec 13, 2022
@lukas-code lukas-code deleted the beta-next branch December 13, 2022 11:37
pietroalbini pushed a commit that referenced this pull request Jul 17, 2025
@Kobzol
Rollup merge of rust-lang#143881 - orlp:once-state-repr, r=tgross35
70301da 
Use zero for initialized Once state

By re-labeling which integer represents which internal state for `Once` we can ensure that the initialized state is the all-zero state. This is beneficial because some CPU architectures (such as Arm) have specialized instructions to specifically branch on non-zero, and checking for the initialized state is by far the most important operation.

As an example, take this:

```rust
use std::sync::atomic::{AtomicU32, Ordering};

const INIT: u32 = 3;

#[inline(never)]
#[cold]
pub fn slow(state: &AtomicU32) {
    state.store(INIT, Ordering::Release);
}

pub fn ensure_init(state: &AtomicU32) {
    if state.load(Ordering::Acquire) != INIT {
        slow(state)
    }
}
```

If `INIT` is 3 (as is currently the state for `Once`), we see the following assembly on `aarch64-apple-darwin`:

```asm
example::ensure_init::h332061368366e313:
        ldapr   w8, [x0]
        cmp     w8, #3
        b.ne    LBB1_2
        ret
LBB1_2:
        b       example::slow::ha042bd6a4f33724e
```

By changing the `INIT` state to zero we get the following:

```asm
example::ensure_init::h332061368366e313:
        ldapr   w8, [x0]
        cbnz    w8, LBB1_2
        ret
LBB1_2:
        b       example::slow::ha042bd6a4f33724e
```

So this PR saves 1 instruction every time a `LazyLock` gets accessed on platforms such as these.
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3 participants
@lukas-code @pietroalbini @Mark-Simulacrum