NVIC's IPR registers are broken on ARMv6-M

[hannobraun]

The IPR registers are modelled as an array of byte-sized registers. I believe this is fine on ARMv7-M, as the ARMv7-M Architecture Reference Manual (link requires registration), section B.3.4.9 states:

The registers are byte, aligned halfword, and word accessible.

However, the situation is different on ARMv6-M. The ARMv6-M Architecture Reference Manual (link requires registration), section B3.4.7 states:

Subject to standard PPB usage constraints, see General rules for PPB register accesses on page B3-260.

Which states (section B3.1.1):

The PPB address space only supports aligned word accesses. Byte and halfword access is UNPREDICTABLE.

This aligns with my own observation, that setting interrupt priority on an ARM Cortex-M0+ via NVIC::set_priority doesn't seem to have any effect.

I think the right way to fix this is to model the ipr field as an array of 32-bit registers, which should be compatible with both architectures. I should be able to put together a pull request by tomorrow, or next week at the latest.