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Merged
merged 4 commits into from
Mar 30, 2021
Merged

Update STM32MP1 HAL and CMSIS drivers #1340

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e2c9709
[MP1] Update STM32MP1xx HAL Drivers to v1.4.0
fpistm Mar 29, 2021
264693b
[MP1] Update STM32MP1xx CMSIS Drivers to v1.4.0
fpistm Mar 29, 2021
86f1b5f
[MP1] Update wrapped files
fpistm Mar 29, 2021
5704416
[MP1] Remove CMSISdevice patch
fpistm Mar 29, 2021
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26 changes: 0 additions & 26 deletions CI/utils/patch/CMSIS/MP1/0001-MP1-Review-HAL-default-configuration.patch
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12 changes: 6 additions & 6 deletions cores/arduino/stm32/stm32_def_build.h
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Original file line number Diff line number Diff line change
Expand Up @@ -381,17 +381,17 @@
#elif defined(STM32L562xx)
#define CMSIS_STARTUP_FILE "startup_stm32l562xx.s"
#elif defined(STM32MP151Axx)
#define CMSIS_STARTUP_FILE "startup_stm32mp151a_cm4 .s"
#define CMSIS_STARTUP_FILE "startup_stm32mp151axx_cm4 .s"
#elif defined(STM32MP151Cxx)
#define CMSIS_STARTUP_FILE "startup_stm32mp151c_cm4.s"
#define CMSIS_STARTUP_FILE "startup_stm32mp151cxx_cm4.s"
#elif defined(STM32MP153Axx)
#define CMSIS_STARTUP_FILE "startup_stm32mp153a_cm4.s"
#define CMSIS_STARTUP_FILE "startup_stm32mp153axx_cm4.s"
#elif defined(STM32MP153Cxx)
#define CMSIS_STARTUP_FILE "startup_stm32mp153c_cm4.s"
#define CMSIS_STARTUP_FILE "startup_stm32mp153cxx_cm4.s"
#elif defined(STM32MP157Axx)
#define CMSIS_STARTUP_FILE "startup_stm32mp157a_cm4.s"
#define CMSIS_STARTUP_FILE "startup_stm32mp157axx_cm4.s"
#elif defined(STM32MP157Cxx)
#define CMSIS_STARTUP_FILE "startup_stm32mp157c_cm4.s"
#define CMSIS_STARTUP_FILE "startup_stm32mp157cxx_cm4.s"
#elif defined(STM32MP15xx)
#define CMSIS_STARTUP_FILE "startup_stm32mp15xx.s"
#elif defined(STM32WB30xx)
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26 changes: 11 additions & 15 deletions system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1088,14 +1088,11 @@ typedef struct
__IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */
uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */
__IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
__IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */
__IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */
__IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */
__IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
__IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */
__IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */
__IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */
__IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */
__IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */
__IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */
__IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */
__IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */
__IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */
__IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */
Expand Down Expand Up @@ -2414,17 +2411,16 @@ typedef struct
/**
* @brief RNG
*/

typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
__IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */
__IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
__IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */
__IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */
} RNG_TypeDef;

/**
Expand Down
26 changes: 11 additions & 15 deletions system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1054,14 +1054,11 @@ typedef struct
__IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */
uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */
__IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
__IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */
__IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */
__IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */
__IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
__IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */
__IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */
__IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */
__IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */
__IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */
__IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */
__IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */
__IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */
__IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */
__IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */
Expand Down Expand Up @@ -2380,17 +2377,16 @@ typedef struct
/**
* @brief RNG
*/

typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
__IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */
__IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
__IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */
__IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */
} RNG_TypeDef;

/**
Expand Down
26 changes: 11 additions & 15 deletions system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1088,14 +1088,11 @@ typedef struct
__IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */
uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */
__IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
__IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */
__IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */
__IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */
__IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
__IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */
__IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */
__IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */
__IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */
__IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */
__IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */
__IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */
__IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */
__IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */
__IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */
Expand Down Expand Up @@ -2462,17 +2459,16 @@ typedef struct
/**
* @brief RNG
*/

typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
__IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */
__IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
__IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */
__IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */
} RNG_TypeDef;

/**
Expand Down
26 changes: 11 additions & 15 deletions system/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1054,14 +1054,11 @@ typedef struct
__IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */
uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */
__IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
__IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */
__IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */
__IO uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x84 - 0x8C */
__IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
__IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */
__IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */
__IO uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x94 - 0x9C */
__IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */
__IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */
__IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */
__IO uint32_t RESERVED7[7]; /*!< Reserved, Address offset: 0xA4 - 0xBC */
__IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */
__IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */
__IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */
Expand Down Expand Up @@ -2428,17 +2425,16 @@ typedef struct
/**
* @brief RNG
*/

typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
__IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */
__IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
__IO uint32_t RESERVED1[249]; /*!< Reserved Address offset: 0x0C - 0x3EC */
__IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */
} RNG_TypeDef;

/**
Expand Down
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