Update STM32L5 HAL and CMSIS drivers

cores/arduino/stm32/LL/stm32yyxx_ll.h

@@ -28,6 +28,7 @@
 #include "stm32yyxx_ll_hrtim.h"
 #include "stm32yyxx_ll_hsem.h"
 #include "stm32yyxx_ll_i2c.h"
+#include "stm32yyxx_ll_icache.h"
 #include "stm32yyxx_ll_ipcc.h"
 #include "stm32yyxx_ll_iwdg.h"
 #include "stm32yyxx_ll_lptim.h"

cores/arduino/stm32/LL/stm32yyxx_ll_icache.h

@@ -0,0 +1,12 @@
+#ifndef _STM32YYXX_LL_ICACHE_H_
+#define _STM32YYXX_LL_ICACHE_H_
+/* LL raised several warnings, ignore them */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#pragma GCC diagnostic ignored "-Wstrict-aliasing"
+
+#ifdef STM32L5xx
+  #include "stm32l5xx_ll_icache.h"
+#endif
+#pragma GCC diagnostic pop
+#endif /* _STM32YYXX_LL_ICACHE_H_ */

libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c

@@ -1,3 +1,6 @@
 #ifdef STM32L0xx
   #include "stm32l0xx_hal_smbus_ex.c"
 #endif
+#ifdef STM32L5xx
+  #include "stm32l5xx_hal_smbus_ex.c"
+#endif

libraries/SrcWrapper/src/LL/stm32yyxx_ll_icache.c

@@ -0,0 +1,3 @@
+#ifdef STM32L5xx
+  #include "stm32l5xx_ll_icache.c"
+#endif

system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l552xx.h

@@ -164,8 +164,8 @@ typedef enum
   HASH_IRQn                 = 96,     /*!< HASH global interrupt                                             */
   LPTIM3_IRQn               = 98,     /*!< LPTIM3 global interrupt                                           */
   SPI3_IRQn                 = 99,     /*!< SPI3 global interrupt                                             */
-  I2C4_EV_IRQn              = 100,    /*!< I2C4 Event interrupt                                              */
-  I2C4_ER_IRQn              = 101,    /*!< I2C4 Error interrupt                                              */
+  I2C4_ER_IRQn              = 100,    /*!< I2C4 Error interrupt                                              */
+  I2C4_EV_IRQn              = 101,    /*!< I2C4 Event interrupt                                              */
   DFSDM1_FLT0_IRQn          = 102,    /*!< DFSDM1 Filter 0 global interrupt                                  */
   DFSDM1_FLT1_IRQn          = 103,    /*!< DFSDM1 Filter 1 global interrupt                                  */
   DFSDM1_FLT2_IRQn          = 104,    /*!< DFSDM1 Filter 2 global interrupt                                  */
@@ -1022,7 +1022,9 @@ typedef struct
   __IO uint32_t SMISR;       /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */
   __IO uint32_t SCR;         /*!< TAMP status clear register,               Address offset: 0x3C */
   __IO uint32_t COUNTR;      /*!< TAMP monotonic counter register,          Address offset: 0x40 */
-       uint32_t RESERVED1[47];/*!< Reserved,                                Address offset: 0x54 -- 0xFC */
+       uint32_t RESERVED1[3];/*!< Reserved,                                 Address offset: 0x44 -- 0x4C */
+  __IO uint32_t CFGR;        /*!< TAMP configuration register,              Address offset: 0x50 */
+       uint32_t RESERVED2[43];/*!< Reserved,                                Address offset: 0x54 -- 0xFC */
   __IO uint32_t BKP0R;       /*!< TAMP backup register 0,                   Address offset: 0x100 */
   __IO uint32_t BKP1R;       /*!< TAMP backup register 1,                   Address offset: 0x104 */
   __IO uint32_t BKP2R;       /*!< TAMP backup register 2,                   Address offset: 0x108 */
@@ -13974,9 +13976,20 @@ typedef struct
 #define TAMP_SCR_CITAMP8F            TAMP_SCR_CITAMP8F_Msk
 
 /********************  Bits definition for TAMP_COUNTR register  ***************/
-#define TAMP_COUNTR_Pos               (16U)
-#define TAMP_COUNTR_Msk               (0xFFFFUL << TAMP_COUNTR_Pos)            /*!< 0xFFFF0000 */
-#define TAMP_COUNTR                   TAMP_COUNTR_Msk
+#define TAMP_COUNTR_Pos              (16U)
+#define TAMP_COUNTR_Msk              (0xFFFFUL << TAMP_COUNTR_Pos)            /*!< 0xFFFF0000 */
+#define TAMP_COUNTR                  TAMP_COUNTR_Msk
+
+/********************  Bits definition for TAMP_CFGR register  *****************/
+#define TAMP_CFGR_TMONEN_Pos         (1U)
+#define TAMP_CFGR_TMONEN_Msk         (0x1UL << TAMP_CFGR_TMONEN_Pos)           /*!< 0x00000002 */
+#define TAMP_CFGR_TMONEN             TAMP_CFGR_TMONEN_Msk
+#define TAMP_CFGR_VMONEN_Pos         (2U)
+#define TAMP_CFGR_VMONEN_Msk         (0x1UL << TAMP_CFGR_VMONEN_Pos)           /*!< 0x00000004 */
+#define TAMP_CFGR_VMONEN             TAMP_CFGR_VMONEN_Msk
+#define TAMP_CFGR_WUTMONEN_Pos       (3U)
+#define TAMP_CFGR_WUTMONEN_Msk       (0x1UL << TAMP_CFGR_WUTMONEN_Pos)         /*!< 0x00000008 */
+#define TAMP_CFGR_WUTMONEN           TAMP_CFGR_WUTMONEN_Msk
 
 /********************  Bits definition for TAMP_BKP0R register  ***************/
 #define TAMP_BKP0R_Pos               (0U)

system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l562xx.h

@@ -166,8 +166,8 @@ typedef enum
   PKA_IRQn                  = 97,     /*!< PKA global interrupt                                              */
   LPTIM3_IRQn               = 98,     /*!< LPTIM3 global interrupt                                           */
   SPI3_IRQn                 = 99,     /*!< SPI3 global interrupt                                             */
-  I2C4_EV_IRQn              = 100,    /*!< I2C4 Event interrupt                                              */
-  I2C4_ER_IRQn              = 101,    /*!< I2C4 Error interrupt                                              */
+  I2C4_ER_IRQn              = 100,    /*!< I2C4 Error interrupt                                              */
+  I2C4_EV_IRQn              = 101,    /*!< I2C4 Event interrupt                                              */
   DFSDM1_FLT0_IRQn          = 102,    /*!< DFSDM1 Filter 0 global interrupt                                  */
   DFSDM1_FLT1_IRQn          = 103,    /*!< DFSDM1 Filter 1 global interrupt                                  */
   DFSDM1_FLT2_IRQn          = 104,    /*!< DFSDM1 Filter 2 global interrupt                                  */
@@ -1096,7 +1096,9 @@ typedef struct
   __IO uint32_t SMISR;       /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */
   __IO uint32_t SCR;         /*!< TAMP status clear register,               Address offset: 0x3C */
   __IO uint32_t COUNTR;      /*!< TAMP monotonic counter register,          Address offset: 0x40 */
-       uint32_t RESERVED1[47];/*!< Reserved,                                Address offset: 0x54 -- 0xFC */
+       uint32_t RESERVED1[3];/*!< Reserved,                                 Address offset: 0x44 -- 0x4C */
+  __IO uint32_t CFGR;        /*!< TAMP configuration register,              Address offset: 0x50 */
+       uint32_t RESERVED2[43];/*!< Reserved,                                Address offset: 0x54 -- 0xFC */
   __IO uint32_t BKP0R;       /*!< TAMP backup register 0,                   Address offset: 0x100 */
   __IO uint32_t BKP1R;       /*!< TAMP backup register 1,                   Address offset: 0x104 */
   __IO uint32_t BKP2R;       /*!< TAMP backup register 2,                   Address offset: 0x108 */
@@ -14713,9 +14715,20 @@ typedef struct
 #define TAMP_SCR_CITAMP8F            TAMP_SCR_CITAMP8F_Msk
 
 /********************  Bits definition for TAMP_COUNTR register  ***************/
-#define TAMP_COUNTR_Pos               (16U)
-#define TAMP_COUNTR_Msk               (0xFFFFUL << TAMP_COUNTR_Pos)            /*!< 0xFFFF0000 */
-#define TAMP_COUNTR                   TAMP_COUNTR_Msk
+#define TAMP_COUNTR_Pos              (16U)
+#define TAMP_COUNTR_Msk              (0xFFFFUL << TAMP_COUNTR_Pos)            /*!< 0xFFFF0000 */
+#define TAMP_COUNTR                  TAMP_COUNTR_Msk
+
+/********************  Bits definition for TAMP_CFGR register  *****************/
+#define TAMP_CFGR_TMONEN_Pos         (1U)
+#define TAMP_CFGR_TMONEN_Msk         (0x1UL << TAMP_CFGR_TMONEN_Pos)           /*!< 0x00000002 */
+#define TAMP_CFGR_TMONEN             TAMP_CFGR_TMONEN_Msk
+#define TAMP_CFGR_VMONEN_Pos         (2U)
+#define TAMP_CFGR_VMONEN_Msk         (0x1UL << TAMP_CFGR_VMONEN_Pos)           /*!< 0x00000004 */
+#define TAMP_CFGR_VMONEN             TAMP_CFGR_VMONEN_Msk
+#define TAMP_CFGR_WUTMONEN_Pos       (3U)
+#define TAMP_CFGR_WUTMONEN_Msk       (0x1UL << TAMP_CFGR_WUTMONEN_Pos)         /*!< 0x00000008 */
+#define TAMP_CFGR_WUTMONEN           TAMP_CFGR_WUTMONEN_Msk
 
 /********************  Bits definition for TAMP_BKP0R register  ***************/
 #define TAMP_BKP0R_Pos               (0U)

system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l5xx.h

@@ -79,7 +79,7 @@
   */
 #define __STM32L5_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
 #define __STM32L5_CMSIS_VERSION_SUB1   (0x00U) /*!< [23:16] sub1 version */
-#define __STM32L5_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
+#define __STM32L5_CMSIS_VERSION_SUB2   (0x04U) /*!< [15:8]  sub2 version */
 #define __STM32L5_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32L5_CMSIS_VERSION        ((__STM32L5_CMSIS_VERSION_MAIN << 24U)\
                                        |(__STM32L5_CMSIS_VERSION_SUB1 << 16U)\

system/Drivers/CMSIS/Device/ST/STM32L5xx/README.md

@@ -31,7 +31,8 @@ CMSIS Device L5 | CMSIS Core | Was delivered in the full MCU package
 --------------- | ---------- | -------------------------------------
 Tag v1.0.0 | Tag v5.4.0_cm33 | Tag v1.1.0
 Tag v1.0.2 | Tag v5.4.0_cm33 | Tag v1.2.0
-Tag v1.0.3 | Tag v5.6.0_cm33 | Tag v1.3.0 (and following, if any, till next tag)
+Tag v1.0.3 | Tag v5.6.0_cm33 | Tag v1.3.0
+Tag v1.0.4 | Tag v5.6.0_cm33 | Tag v1.4.0 (and following, if any, till next tag)
 
 The full **STM32CubeL5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeL5).
 

system/Drivers/CMSIS/Device/ST/STM32L5xx/Release_Notes.html

@@ -11,24 +11,22 @@
       span.underline{text-decoration: underline;}
       div.column{display: inline-block; vertical-align: top; width: 50%;}
   </style>
-  <link rel="stylesheet" href="_htmresc/mini-st.css" />
+  <link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
   <!--[if lt IE 9]>
     <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
   <![endif]-->
+  <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
 </head>
 <body>
 <div class="row">
 <div class="col-sm-12 col-lg-4">
-<div class="card fluid">
-<div class="sectione dark">
 <center>
-<h1 id="release-notes-for-stm32l5xx-cmsis"><small>Release Notes for</small> <strong>STM32L5xx CMSIS</strong></h1>
+<h1 id="release-notes-for">Release Notes for</h1>
+<h1 id="stm32l5xx-cmsis"><mark>STM32L5xx CMSIS</mark></h1>
 <p>Copyright © 2019 STMicroelectronics<br />
 </p>
-<a href="https://www.st.com" class="logo"><img src="./_htmresc/st_logo.png" alt="ST logo" /></a>
+<a href="https://www.st.com" class="logo"><img src="./_htmresc/st_logo_2020.png" alt="ST logo" /></a>
 </center>
-</div>
-</div>
 <h1 id="license">License</h1>
 <p>This software component is licensed by ST under Apache-2.0 license, the "License"; You may not use this component except in compliance with the License. You may obtain a copy of the License at:</p>
 <p><a href="https://opensource.org/licenses/Apache-2.0">Apache License v2.0</a></p>
@@ -48,11 +46,44 @@ <h1 id="purpose">Purpose</h1>
 <div class="col-sm-12 col-lg-8">
 <h1 id="update-history">Update History</h1>
 <div class="collapse">
-<input type="checkbox" id="collapse-section4" checked aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.0.3 / 26-June-2020</strong></label>
+<input type="checkbox" id="collapse-section5" checked aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.0.4 / 10-February-2021</strong></label>
 <div>
 <h2 id="main-changes">Main Changes</h2>
-<p><strong>Fourth release</strong></p>
+<p><strong>Maintenance release</strong></p>
 <h2 id="contents">Contents</h2>
+<p>Maintenance release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
+<ul>
+<li>stm32l552xx.h and stm32l562xx.h updates
+<ul>
+<li>Add TAMP_CFGR configuration register and definitions for TMONEN, VMONEN and WUTMONEN monitoring functions</li>
+<li>Fix I2C4_EV_IRQn and I2C4_ER_IRQn order in IRQn_Type</li>
+</ul></li>
+</ul>
+<h2 id="notes">Notes</h2>
+<p>Reminder:</p>
+<ul>
+<li>When TrustZone is enabled in the system (Flash option bit TZEN=1)
+<ul>
+<li>template device partition_stm32l552xx.h or partition_stm32l562xx.h file must be copied and optionally updated in user application secure project to configure the system (SAU, interrupts, core).</li>
+<li>default Security Attribute Unit (SAU) configuration in the partition_stm32l552xx.h and partition_stm32l562xx.h:
+<ul>
+<li>SAU region 0: 0x0C03E000-0x0C03FFFF (Secure, Non-Secure Callable)</li>
+<li>SAU region 1: 0x08040000-0x0807FFFF (Non-Secure FLASH Bank2 (256 Kbytes))</li>
+<li>SAU region 2: 0x20018000-0x2003FFFF (Non-Secure RAM (2nd half SRAM1 + SRAM2 (160 Kbytes)))</li>
+<li>SAU region 3: 0x40000000-0x4FFFFFFF (Non-Secure Peripheral mapped memory)</li>
+<li>SAU region 4: 0x60000000-0x9FFFFFFF (Non-Secure external memories)</li>
+<li>SAU region 5: 0x0BF90000-0x0BFA8FFF (Non-Secure System memory)</li>
+</ul></li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.0.3 / 26-June-2020</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<p><strong>Fourth release</strong></p>
+<h2 id="contents-1">Contents</h2>
 <p>Fourth release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
 <ul>
 <li>stm32l552xx.h and stm32l562xx.h updates
@@ -68,7 +99,7 @@ <h2 id="contents">Contents</h2>
 <li>Add README.md and License.md files for GitHub publication</li>
 <li>Misspelled words corrections in driver descriptions</li>
 </ul>
-<h2 id="notes">Notes</h2>
+<h2 id="notes-1">Notes</h2>
 <p>Reminder:</p>
 <ul>
 <li>When TrustZone is enabled in the system (Flash option bit TZEN=1)
@@ -90,9 +121,9 @@ <h2 id="notes">Notes</h2>
 <div class="collapse">
 <input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.0.2 / 12-February-2020</strong></label>
 <div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
 <p><strong>Third release</strong></p>
-<h2 id="contents-1">Contents</h2>
+<h2 id="contents-2">Contents</h2>
 <p>Third official release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
 <ul>
 <li>stm32l552xx.h and stm32l562xx.h updates
@@ -102,7 +133,7 @@ <h2 id="contents-1">Contents</h2>
 <li>Align DBGMCU_APB2FZR register and bits definitions with RM0438</li>
 </ul></li>
 </ul>
-<h2 id="notes-1">Notes</h2>
+<h2 id="notes-2">Notes</h2>
 <p>Reminder:</p>
 <ul>
 <li>When TrustZone is enabled in the system (Flash option bit TZEN=1)
@@ -124,17 +155,17 @@ <h2 id="notes-1">Notes</h2>
 <div class="collapse">
 <input type="checkbox" id="collapse-section2" unchecked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.0.1 / 22-January-2020</strong></label>
 <div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
 <p><strong>Second release</strong></p>
-<h2 id="contents-2">Contents</h2>
+<h2 id="contents-3">Contents</h2>
 <p>Second official release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
 <ul>
 <li>Templates system_stm32l5xx.c, system_stm32l5xx_s.c and system_stm32l5xx_ns.c
 <ul>
 <li>Add vector table relocation capability with conditional USER_VECT_TAB_ADDRESS</li>
 </ul></li>
 </ul>
-<h2 id="notes-2">Notes</h2>
+<h2 id="notes-3">Notes</h2>
 <p>Reminder:</p>
 <ul>
 <li>When TrustZone is enabled in the system (Flash option bit TZEN=1)
@@ -156,9 +187,9 @@ <h2 id="notes-2">Notes</h2>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1" unchecked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 13-December-2019</strong></label>
 <div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
 <p><strong>First release</strong></p>
-<h2 id="contents-3">Contents</h2>
+<h2 id="contents-4">Contents</h2>
 <p>First official release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
 <ul>
 <li>Templates
@@ -176,7 +207,7 @@ <h2 id="contents-3">Contents</h2>
 <li>Linker files for 256 and 512 Kbytes Flash device configurations</li>
 </ul></li>
 </ul>
-<h2 id="notes-3">Notes</h2>
+<h2 id="notes-4">Notes</h2>
 <p>When TrustZone is enabled in the system (Flash option bit TZEN=1), template device partition_stm32l552xx.h or partition_stm32l562xx.h file must be copied and optionally updated in user application secure project to configure the system (SAU, interrupts, core)</p>
 </div>
 </div>