stm32duino · fpistm · Aug 10, 2021 · Aug 10, 2021 · Aug 10, 2021 · Aug 10, 2021
diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c
@@ -14,5 +14,7 @@
   #include "stm32l5xx_hal_smbus_ex.c"
 #elif STM32WBxx
   #include "stm32wbxx_hal_smbus_ex.c"
+#elif STM32WLxx
+  #include "stm32wlxx_hal_smbus_ex.c"
 #endif
 #pragma GCC diagnostic pop
diff --git a/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl54xx.h b/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl54xx.h
@@ -14,13 +14,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2020(-2021) STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under Apache License, Version 2.0,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/Apache-2.0
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -206,7 +205,7 @@ typedef enum
 #define __VTOR_PRESENT            1U /*!< Vector Table Register supported               */
 #define __NVIC_PRIO_BITS          4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */
 #define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             0U /*!< FPU present                                   */
+#define __FPU_PRESENT             0U /*!< FPU not present                                   */
 
 #include "core_cm4.h"                /* Cortex-M4 processor and core peripherals */
 
@@ -481,7 +480,7 @@ typedef struct
 } GPIO_TypeDef;
 
 /**
-  * @brief Global TrustZone Controller
+  * @brief Global Security Controller
   */
 typedef struct{
   __IO uint32_t CR;             /*!< TZSC control register,                             Address offset: 0x00       */
@@ -1188,6 +1187,15 @@ typedef struct
   * @{
   */
 
+/** @addtogroup Hardware_Constant_Definition
+  * @{
+  */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+  * @}
+  */
+
 /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -4001,7 +4009,7 @@ typedef struct
 
 /******************************************************************************/
 /*                                                                            */
-/*                        Global TrustZone Control                            */
+/*                        Global Security Control                            */
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for registers x = 0  ********************/

diff --git a/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h b/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h
@@ -14,13 +14,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2020(-2021) STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under Apache License, Version 2.0,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/Apache-2.0
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -206,7 +205,7 @@ typedef enum
 #define __VTOR_PRESENT            1U /*!< Vector Table Register supported               */
 #define __NVIC_PRIO_BITS          4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */
 #define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             0U /*!< FPU present                                   */
+#define __FPU_PRESENT             0U /*!< FPU not present                                   */
 
 #include "core_cm4.h"                /* Cortex-M4 processor and core peripherals */
 
@@ -481,7 +480,7 @@ typedef struct
 } GPIO_TypeDef;
 
 /**
-  * @brief Global TrustZone Controller
+  * @brief Global Security Controller
   */
 typedef struct{
   __IO uint32_t CR;             /*!< TZSC control register,                             Address offset: 0x00       */
@@ -1188,6 +1187,15 @@ typedef struct
   * @{
   */
 
+/** @addtogroup Hardware_Constant_Definition
+  * @{
+  */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+  * @}
+  */
+
 /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -4001,7 +4009,7 @@ typedef struct
 
 /******************************************************************************/
 /*                                                                            */
-/*                        Global TrustZone Control                            */
+/*                        Global Security Control                            */
 /*                                                                            */
 /******************************************************************************/
 /*******************  Bits definition for registers x = 0  ********************/

diff --git a/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle4xx.h b/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle4xx.h
@@ -14,13 +14,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2020(-2021) STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under Apache License, Version 2.0,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/Apache-2.0
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -140,7 +139,7 @@ typedef enum
 #define __VTOR_PRESENT            1U /*!< Vector Table Register supported               */
 #define __NVIC_PRIO_BITS          4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */
 #define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             0U /*!< FPU present                                   */
+#define __FPU_PRESENT             0U /*!< FPU not present                                   */
 
 #include "core_cm4.h"                /* Cortex-M4 processor and core peripherals */
 
@@ -1006,6 +1005,15 @@ typedef struct
   * @{
   */
 
+/** @addtogroup Hardware_Constant_Definition
+  * @{
+  */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+  * @}
+  */
+
 /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */

diff --git a/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h b/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h
@@ -14,13 +14,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2020(-2021) STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under Apache License, Version 2.0,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/Apache-2.0
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -140,7 +139,7 @@ typedef enum
 #define __VTOR_PRESENT            1U /*!< Vector Table Register supported               */
 #define __NVIC_PRIO_BITS          4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */
 #define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             0U /*!< FPU present                                   */
+#define __FPU_PRESENT             0U /*!< FPU not present                                   */
 
 #include "core_cm4.h"                /* Cortex-M4 processor and core peripherals */
 
@@ -1006,6 +1005,15 @@ typedef struct
   * @{
   */
 
+/** @addtogroup Hardware_Constant_Definition
+  * @{
+  */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+  * @}
+  */
+
 /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */

diff --git a/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h b/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h
@@ -8,21 +8,20 @@
   *          is using in the C source code, usually in main.c. This file contains:
   *           - Configuration section that allows to select:
   *              - The STM32WLxx device used in the target application
-  *              - To use or not the peripheral�s drivers in application code(i.e.
-  *                code will be based on direct access to peripheral�s registers
+  *              - To use or not the peripheral’s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral’s registers
   *                rather than drivers API), this option is controlled by
   *                "#define USE_HAL_DRIVER"
   *
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2020(-2021) STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under Apache License, Version 2.0,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/Apache-2.0
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -80,7 +79,7 @@
   * @brief CMSIS Device version number
   */
 #define __STM32WLxx_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define __STM32WLxx_CMSIS_VERSION_SUB1   (0x00U) /*!< [23:16] sub1 version */
+#define __STM32WLxx_CMSIS_VERSION_SUB1   (0x01U) /*!< [23:16] sub1 version */
 #define __STM32WLxx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32WLxx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32WLxx_CMSIS_DEVICE_VERSION        ((__STM32WLxx_CMSIS_VERSION_MAIN << 24)\
@@ -157,9 +156,105 @@ typedef enum
 #define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
 
 #if defined(CORE_CM0PLUS)
+/* Use of interrupt control for register exclusive access (privileged mode only) */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT) \
+  do {                           \
+    uint32_t primask;            \
+    primask = __get_PRIMASK();   \
+    __set_PRIMASK(1);            \
+    SET_BIT((REG), (BIT));       \
+    __set_PRIMASK(primask);      \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT) \
+  do {                             \
+    uint32_t primask;              \
+    primask = __get_PRIMASK();     \
+    __set_PRIMASK(1);              \
+    CLEAR_BIT((REG), (BIT));       \
+    __set_PRIMASK(primask);        \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
+  do {                                            \
+    uint32_t primask;                             \
+    primask = __get_PRIMASK();                    \
+    __set_PRIMASK(1);                             \
+    MODIFY_REG((REG), (CLEARMSK), (SETMASK));     \
+    __set_PRIMASK(primask);                       \
+  } while(0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT)   ATOMIC_SET_BIT(REG, BIT)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)
+
 #else
+/* Use of CMSIS compiler intrinsics for register exclusive access */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT)                             \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT)                           \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \
+  do {                                                                     \
+    uint32_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \
+  } while(0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT)                            \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT)                          \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \
+  do {                                                                     \
+    uint16_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \
+  } while(0)
+
 #define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
-#endif
+#endif /* CORE_CM0PLUS */
+
 /**
   * @}
   */

diff --git a/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h b/system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2020(-2021) STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under Apache License, Version 2.0,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/Apache-2.0
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */