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Pull requests: Xilinx/llvm-aie
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[AIE2P] Fix scheduling model to add missing ItinRegClass pairs
#521
opened Jul 9, 2025 by
khallouh
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[aie][aie2p] Global Isel : trunc vector when size(src)/size(dst) = 4
#496
opened Jun 20, 2025 by
newling
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[AIE2P] Add SingletonCopyEdges dag mutator in pre-scheduler
#469
opened May 14, 2025 by
khallouh
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[AIE2P] Support all 64-bit-destination G_BUILD_VECTOR in legalizer
#467
opened May 13, 2025 by
khallouh
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[AIE2p] Use multi-slot pseudo for const COPY with unique def
#454
opened May 2, 2025 by
krishnamtibrewala
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[AIE2P] Allow more address chaining and add a profitability check heuristic
#451
opened Apr 28, 2025 by
khallouh
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[DRAFT][AIEX] Improve pre-sched decisions for Post-SWP candidates
#429
opened Apr 8, 2025 by
andcarminati
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Draft
Avoid broadcast/extract when implementing memset
#416
opened Mar 31, 2025 by
martien-de-jong
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[AIEX] Enhance combiner to support post-inc-load requiring moving multiple instructions
#369
opened Feb 24, 2025 by
krishnamtibrewala
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Improvements in resource conflict detection related to slots
#305
opened Jan 23, 2025 by
martien-de-jong
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Draft
[WIP] Reclaim size regression for aligning fallthrough-only blocks
#303
opened Jan 23, 2025 by
abhinay-anubola
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